To improve the technical depth and reproducibility of this repository, we should benchmark each Verilog module on two FPGA families- one beginner-friendly and one industry-grade to report LUT, FF, DSP, BRAM usage, and achievable frequency.
This will allow users to understand resource consumption in real environments and compare modules meaningfully instead of relying only on theoretical complexity.
Target FPGA Devices
-
Lattice iCE40 UP5K
Example part: iCE40UP5K-ES
Toolchain: Yosys + nextpnr-ice40
LUT primitive: LUT4
-
Xilinx Artix-7 XC7A35T
Example part: XC7A35T-1CPG236C
Toolchain: Vivado (2023.x)
LUT primitive: LUT6
These devices represent a useful contrast between open-source hobbyist FPGAs and industry-standard mid-range FPGAs.
Benchmarking Tasks
-
Create a standard top.v wrapper for each module.
-
Write reproducible synthesis scripts:
- synth_ice40.sh (Yosys + nextpnr)
- synth_vivado.tcl (Vivado)
-
Run synthesis and implementation on both devices.
-
Collect and record:
- LUTs
- FFs
- DSPs
- BRAMs
- Post-route maximum frequency
-
Add results to a new file: BENCHMARKS.md.
Acceptance Criteria
- Scripts build successfully on both flows.
- Benchmark results are consistent and reproducible.
- All modules have entries for both FPGA targets.
- BENCHMARKS.md is added and linked from the main README.
Notes
LUT counts vary across FPGA architectures, so results will be explicitly tied to device + toolchain version to maintain scientific validity. Relative comparison between modules matters more than the absolute numbers.
To improve the technical depth and reproducibility of this repository, we should benchmark each Verilog module on two FPGA families- one beginner-friendly and one industry-grade to report LUT, FF, DSP, BRAM usage, and achievable frequency.
This will allow users to understand resource consumption in real environments and compare modules meaningfully instead of relying only on theoretical complexity.
Target FPGA Devices
Lattice iCE40 UP5K
Example part: iCE40UP5K-ES
Toolchain: Yosys + nextpnr-ice40
LUT primitive: LUT4
Xilinx Artix-7 XC7A35T
Example part: XC7A35T-1CPG236C
Toolchain: Vivado (2023.x)
LUT primitive: LUT6
These devices represent a useful contrast between open-source hobbyist FPGAs and industry-standard mid-range FPGAs.
Benchmarking Tasks
Create a standard top.v wrapper for each module.
Write reproducible synthesis scripts:
Run synthesis and implementation on both devices.
Collect and record:
Add results to a new file: BENCHMARKS.md.
Acceptance Criteria
Notes
LUT counts vary across FPGA architectures, so results will be explicitly tied to device + toolchain version to maintain scientific validity. Relative comparison between modules matters more than the absolute numbers.