LVS report missing

[Dario-CP]

Describe the bug
I am trying OpenRAM for the first time, and I am unable to succesfully generate a memory. I started trying to generate a 4KB memory, but it was very slow on my machine, so I am now trying with a 1Kb one. However, for both cases I get an error caused by the LVS report not being found.

This is the log:

(.venv) dario@localhost:~/OpenRAM$ python3 sram_compiler.py /home/dario/OpenRAM/macros/sram_configs/sky130_sram_0_125kbyte_1rw1r_16x64_8.py
OpenRAM: Nix devShell (venv on PATH: /home/dario/OpenRAM/compiler/.venv)
|==============================================================================|
|=========                      OpenRAM v1.2.49                       =========|
|=========                                                            =========|
|=========               VLSI Design and Automation Lab               =========|
|=========        Computer Science and Engineering Department         =========|
|=========            University of California Santa Cruz             =========|
|=========                                                            =========|
|=========          Usage help: openram-user-group@ucsc.edu           =========|
|=========        Development help: openram-dev-group@ucsc.edu        =========|
|=========                See LICENSE for license info                =========|
|==============================================================================|
** Start: 06/02/2026 10:36:26
Technology: sky130
Total size: 1024 bits
Word size: 16
Words: 64
Banks: 1
Write size: 8
RW ports: 1
R-only ports: 1
W-only ports: 0
DRC/LVS/PEX is only run on the top-level design to save run-time (inline_lvsdrc=True to do inline checking).
Characterization is disabled (using analytical delay models) (analytical_delay=False to simulate).
Only generating nominal corner timing.
Words per row: None
Output files are: 
/home/dario/OpenRAM/macro/sky130_sram_0.12kbytes_1rw1r_16x64_8/sky130_sram_0.12kbytes_1rw1r_16x64_8.lvs
/home/dario/OpenRAM/macro/sky130_sram_0.12kbytes_1rw1r_16x64_8/sky130_sram_0.12kbytes_1rw1r_16x64_8.sp
/home/dario/OpenRAM/macro/sky130_sram_0.12kbytes_1rw1r_16x64_8/sky130_sram_0.12kbytes_1rw1r_16x64_8.v
/home/dario/OpenRAM/macro/sky130_sram_0.12kbytes_1rw1r_16x64_8/sky130_sram_0.12kbytes_1rw1r_16x64_8.lib
/home/dario/OpenRAM/macro/sky130_sram_0.12kbytes_1rw1r_16x64_8/sky130_sram_0.12kbytes_1rw1r_16x64_8.py
/home/dario/OpenRAM/macro/sky130_sram_0.12kbytes_1rw1r_16x64_8/sky130_sram_0.12kbytes_1rw1r_16x64_8.html
/home/dario/OpenRAM/macro/sky130_sram_0.12kbytes_1rw1r_16x64_8/sky130_sram_0.12kbytes_1rw1r_16x64_8.log
/home/dario/OpenRAM/macro/sky130_sram_0.12kbytes_1rw1r_16x64_8/sky130_sram_0.12kbytes_1rw1r_16x64_8.lef
/home/dario/OpenRAM/macro/sky130_sram_0.12kbytes_1rw1r_16x64_8/sky130_sram_0.12kbytes_1rw1r_16x64_8.gds
** Submodules: 2.9 seconds
** Placement: 0.0 seconds
** Routing: 288.6 seconds
ERROR: file magic.py: line 326: Unable to load LVS results from /tmp/openram_dario_19123_temp/sky130_sram_0.12kbytes_1rw1r_16x64_8.lvs.report
Traceback (most recent call last):
  File "/home/dario/OpenRAM/compiler/verify/magic.py", line 324, in run_lvs
    f = open(resultsfile, "r")
FileNotFoundError: [Errno 2] No such file or directory: '/tmp/openram_dario_19123_temp/sky130_sram_0.12kbytes_1rw1r_16x64_8.lvs.report'

During handling of the above exception, another exception occurred:

Traceback (most recent call last):
  File "/home/dario/OpenRAM/sram_compiler.py", line 73, in <module>
    s = sram()
  File "/home/dario/OpenRAM/compiler/sram.py", line 58, in __init__
    self.s.create_layout()
    ~~~~~~~~~~~~~~~~~~~~^^
  File "/home/dario/OpenRAM/compiler/modules/sram_1bank.py", line 239, in create_layout
    self.DRC_LVS(final_verification=OPTS.route_supplies, force_check=OPTS.check_lvsdrc)
    ~~~~~~~~~~~~^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
  File "/home/dario/OpenRAM/compiler/base/hierarchy_design.py", line 71, in DRC_LVS
    self.lvs_errors = verify.run_lvs(self.cell_name, tempgds, tempspice, final_verification=final_verification)
                      ~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
  File "/home/dario/OpenRAM/compiler/verify/magic.py", line 326, in run_lvs
    debug.error("Unable to load LVS results from {}".format(resultsfile), 1)
    ~~~~~~~~~~~^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
  File "/home/dario/OpenRAM/compiler/debug.py", line 48, in error
    assert return_value == 0
           ^^^^^^^^^^^^^^^^^
AssertionError

Version
v1.2.49 (commit e16d9eb)

To Reproduce
I am using SKY130, and this is the memory configuration used:

word_size = 16
num_words = 64
human_byte_size = "{:.2f}kbytes".format((word_size * num_words)/1024/8)
write_size = 8
num_rw_ports = 1
num_r_ports = 1
num_w_ports = 0
num_spare_rows = 2
num_spare_cols = 1
ports_human = '1rw1r'

num_threads = 4

import os
exec(open(os.path.join(os.path.dirname(__file__), 'sky130_sram_common.py')).read())

[Dario-CP]

I also get the error with the release version 1.2.48, so I assume I am doing something wrong. I think it may be the use of a decimal point in human_byte_size, which makes the output files have a decimal point, and may be messing with the LVS tool parser.

[Dario-CP]

The issue was the decimal point. By fixing that, it works. However, I had to implement a change in compiler/verify/run_script.py, or else I get this error:

ERROR: file magic.py: line 245: Unable to find the total error line in Magic output.
Traceback (most recent call last):
  File "/home/dario/OpenRAM/sram_compiler.py", line 73, in <module>
    s = sram()
  File "/home/dario/OpenRAM/compiler/sram.py", line 58, in __init__
    self.s.create_layout()
    ~~~~~~~~~~~~~~~~~~~~^^
  File "/home/dario/OpenRAM/compiler/modules/sram_1bank.py", line 239, in create_layout
    self.DRC_LVS(final_verification=OPTS.route_supplies, force_check=OPTS.check_lvsdrc)
    ~~~~~~~~~~~~^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
  File "/home/dario/OpenRAM/compiler/base/hierarchy_design.py", line 70, in DRC_LVS
    self.drc_errors = verify.run_drc(self.cell_name, tempgds, tempspice, extract=True, final_verification=final_verification)
                      ~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
  File "/home/dario/OpenRAM/compiler/verify/magic.py", line 245, in run_drc
    debug.error("Unable to find the total error line in Magic output.", 1)
    ~~~~~~~~~~~^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
  File "/home/dario/OpenRAM/compiler/debug.py", line 48, in error
    assert return_value == 0
           ^^^^^^^^^^^^^^^^^
AssertionError

This is the change:

The script was being launched from the temp directory, so Nix could not find the repo's flake.nix. I am not sure if this is a good fix, since I am not familiar with the repo, but it seems to work.

[jcirimel]

Thanks for the issue I'll see if I can reproduce this. I have my temp directory set at $OPENRAM_HOME/output, so I might have missed this bug because nix can still find the flake.nix by looking up a couple directories. I think adding the repo_root to the path like you did is a sensible solution.

[Dario-CP]

Thanks for your answer @jcirimel ! I am having troubles with LVS, and do not manage to get a result with no mismatches. Reading the previous issues, I thought the problem might be caused by the magic version, so I tried different older versions with no success. Since I am not familiar with OpenRAM, I really don't know how to approach this.

I am trying to compile this small true dual port memory (I forgot to change ports_human, so the output files have 1rw1r in the name):

word_size = 16
num_words = 64
human_byte_size = "{:.0f}kbits".format((word_size * num_words)/1024)

write_size = 8

num_rw_ports = 2
num_r_ports = 0
num_w_ports = 0

num_spare_rows = 2
num_spare_cols = 1
ports_human = '1rw1r'

num_threads = 4
inline_lvsdrc=True

import os
exec(open(os.path.join(os.path.dirname(__file__), 'sky130_sram_common.py')).read())

And this is the error I got:

ERROR: file magic.py: line 385: sky130_sram_1kbits_1rw1r_16x64_8_bitcell_array	LVS mismatch (results in /tmp/openram_dario_8205_temp/sky130_sram_1kbits_1rw1r_16x64_8_bitcell_array.lvs.report)
ERROR: file hierarchy_design.py: line 79: LVS failed for sky130_sram_1kbits_1rw1r_16x64_8_bitcell_array with 2 errors(s)

Here are the LVS-related reports I got:
lvs_reports.zip

I also tried with different size and port configurations and the LVS keeps failing.
Thanks a lot in advance.