diff --git a/.abc.config b/.abc.config index b41d346..fb9a74b 100644 --- a/.abc.config +++ b/.abc.config @@ -1,11 +1,11 @@ # SPDX-FileCopyrightText: 2026 Accemic Technologies GmbH # SPDX-License-Identifier: ISC # -# abc-flow project configuration for CEDARtools.TraceEncoder. +# abc-flow project configuration for CEDARtools.TraceEncoder (CTTE). # # Pins the Vivado version used for simulation and implementation (2022.1). # Update these together when the project moves to a new tool version. sim_backend=verilator vivado_sim=2022.1 -vivado_impl=2022.1 \ No newline at end of file +vivado_impl=2022.1 diff --git a/.editorconfig b/.editorconfig index 3429dcb..49748ba 100644 --- a/.editorconfig +++ b/.editorconfig @@ -1,5 +1,20 @@ # SPDX-FileCopyrightText: 2026 Accemic Technologies GmbH # SPDX-License-Identifier: ISC +# +# Canonical whitespace conventions for this repository. +# +# Indentation is by TAB, rendered four columns wide, for everything that is +# written by hand in a hardware-design idiom: SystemVerilog, shell, Make, +# constraints. That is what the sources have always used and what the +# per-file vim / Emacs modelines declare, so the two can never disagree. +# Alignment *within* a line (port lists, comment columns) uses spaces, so a +# file reads the same at any tab width. +# +# Languages whose ecosystems mandate spaces keep spaces: Python (PEP 8), +# YAML (tabs are illegal), JSON, and the prose formats. +# +# Generated files (rtl/pkg/ct_cs_cpuif*.sv, tests/lib/ct_cs_cpuif_wb_helper.sv) +# follow their generator's style — never reformat them, rerun `make rdl`. root = true @@ -8,20 +23,65 @@ charset = utf-8 end_of_line = lf insert_final_newline = true trim_trailing_whitespace = true -indent_style = space -indent_size = 2 +indent_style = tab +tab_width = 4 +indent_size = 4 [*.{sv,svh,v,vh}] -indent_size = 2 +indent_style = tab +tab_width = 4 -[*.rdl] -indent_size = 2 +[*.{sh,bash}] +indent_style = tab +tab_width = 4 [Makefile] indent_style = tab +tab_width = 4 -[*.{md,markdown}] -trim_trailing_whitespace = false +[*.{xdc,f}] +indent_style = tab +tab_width = 4 + +[*.abc] +indent_style = space +indent_size = 4 + +[*.py] +indent_style = space +indent_size = 4 + +[*.{tcl,rdl}] +indent_style = space +indent_size = 4 [*.{yml,yaml}] +indent_style = space +indent_size = 2 + +[*.json] +indent_style = space +indent_size = 2 + +[*.adoc] +indent_style = space +indent_size = 2 + +# Markdown keeps trailing whitespace: two trailing spaces are a hard line +# break, and stripping them silently reflows the rendered text. +[*.{md,markdown}] +indent_style = space indent_size = 2 +trim_trailing_whitespace = false + +# Verbatim third-party text — never reformatted. +[LICENSES/**] +insert_final_newline = false +trim_trailing_whitespace = false + +[third_party/**] +indent_style = unset +indent_size = unset +tab_width = unset +trim_trailing_whitespace = false +insert_final_newline = false diff --git a/.github/CODEOWNERS b/.github/CODEOWNERS index 9ea70b5..0dbd79b 100644 --- a/.github/CODEOWNERS +++ b/.github/CODEOWNERS @@ -4,15 +4,15 @@ # GitHub CODEOWNERS — review routing. # Human-readable maintainer list lives in MAINTAINERS.md. # -# Owners: @accemic (company profile) and @albertschulz (main developer). +# Owners: @accemic (company profile), @albertschulz and @accemic-weiss (maintainers). # Default — every change needs a maintainer review. -* @accemic @albertschulz +* @accemic @albertschulz @accemic-weiss # Legal / CI surface — extra care. -/LICENSE.md @accemic @albertschulz -/LICENSES/ @accemic @albertschulz -/.github/workflows/ @accemic @albertschulz -/.github/CODEOWNERS @accemic @albertschulz -/CITATION.cff @accemic @albertschulz -/.abc.config @accemic @albertschulz +/LICENSE.md @accemic @albertschulz @accemic-weiss +/LICENSES/ @accemic @albertschulz @accemic-weiss +/.github/workflows/ @accemic @albertschulz @accemic-weiss +/.github/CODEOWNERS @accemic @albertschulz @accemic-weiss +/CITATION.cff @accemic @albertschulz @accemic-weiss +/.abc.config @accemic @albertschulz @accemic-weiss diff --git a/.github/ISSUE_TEMPLATE/bug_report.md b/.github/ISSUE_TEMPLATE/bug_report.md index 0c49abe..0136d4d 100644 --- a/.github/ISSUE_TEMPLATE/bug_report.md +++ b/.github/ISSUE_TEMPLATE/bug_report.md @@ -23,7 +23,7 @@ SPDX-License-Identifier: CC-BY-4.0 ## Environment -- CEDARtools.TraceEncoder commit / version: +- CTTE commit / version: - Vivado version: - `abc` version: - PeakRDL version (if RDL-related): diff --git a/.github/PULL_REQUEST_TEMPLATE.md b/.github/PULL_REQUEST_TEMPLATE.md index 5016f95..2a00ce5 100644 --- a/.github/PULL_REQUEST_TEMPLATE.md +++ b/.github/PULL_REQUEST_TEMPLATE.md @@ -16,7 +16,7 @@ SPDX-License-Identifier: CC-BY-4.0 - [ ] If `rdl/ct_cs_cpuif.rdl` changed, `make rdl` was re-run and the regenerated `rtl/pkg/ct_cs_cpuif*.sv` + `tests/lib/ct_cs_cpuif_wb_helper.sv` are committed in the same PR (likewise `make rdl-soc` → - `examples/tgc5b_soc/pkg/ct_soc_regs*.sv`) + `examples/kv260/common/tgc5b/pkg/ct_soc_regs*.sv`) - [ ] CLA agreed (see [CONTRIBUTING.md](../CONTRIBUTING.md)) ## Notes for reviewers diff --git a/.github/actions/setup-formal/action.yml b/.github/actions/setup-formal/action.yml new file mode 100644 index 0000000..db7a9fa --- /dev/null +++ b/.github/actions/setup-formal/action.yml @@ -0,0 +1,84 @@ +# SPDX-FileCopyrightText: 2026 Accemic Technologies GmbH +# SPDX-License-Identifier: ISC + +name: Set up the formal toolchain +description: >- + Install the pinned YosysHQ OSS CAD Suite and sv2v, and export + OSS_CAD_SUITE / SV2V_HOME so formal/common/env.sh picks them up. + Both are public tarballs -- the formal gates need no EDA licence. + +inputs: + oss-cad-suite-version: + description: OSS CAD Suite release tag (a date, e.g. 2026-08-02) + required: false + # The build formal/README.md records its results against. Bump it + # deliberately and re-read that README's timing table -- solver versions + # move proof times, and an unbounded proof that starts timing out looks + # exactly like a property regression. + default: "2026-08-02" + sv2v-version: + description: sv2v release tag + required: false + default: "v0.0.13" + +runs: + using: composite + steps: + - name: Cache the formal toolchain + id: cache + uses: actions/cache@v4 + with: + path: | + ~/.local/oss-cad-suite + ~/.local/sv2v + key: formal-${{ runner.os }}-oss${{ inputs.oss-cad-suite-version }}-sv2v${{ inputs.sv2v-version }} + + - name: Download OSS CAD Suite ${{ inputs.oss-cad-suite-version }} + if: steps.cache.outputs.cache-hit != 'true' + shell: bash + run: | + set -euo pipefail + ver='${{ inputs.oss-cad-suite-version }}' + # Asset name is the tag with the dashes removed: 2026-08-02 -> 20260802. + stamp="${ver//-/}" + url="https://github.com/YosysHQ/oss-cad-suite-build/releases/download/${ver}/oss-cad-suite-linux-x64-${stamp}.tgz" + echo "fetching $url" + curl -fsSL "$url" -o /tmp/oss-cad-suite.tgz + mkdir -p "$HOME/.local" + # The tarball unpacks to a top-level oss-cad-suite/ directory. + tar -xzf /tmp/oss-cad-suite.tgz -C "$HOME/.local" + + - name: Download sv2v ${{ inputs.sv2v-version }} + if: steps.cache.outputs.cache-hit != 'true' + shell: bash + run: | + set -euo pipefail + ver='${{ inputs.sv2v-version }}' + url="https://github.com/zachjs/sv2v/releases/download/${ver}/sv2v-Linux.zip" + echo "fetching $url" + curl -fsSL "$url" -o /tmp/sv2v.zip + rm -rf /tmp/sv2v-unzip && mkdir -p /tmp/sv2v-unzip + unzip -q /tmp/sv2v.zip -d /tmp/sv2v-unzip + mkdir -p "$HOME/.local/sv2v" + # The zip holds sv2v-Linux/sv2v; SV2V_HOME must be the directory + # CONTAINING the binary, which is what formal/common/env.sh probes for. + find /tmp/sv2v-unzip -name sv2v -type f -exec cp {} "$HOME/.local/sv2v/sv2v" \; + chmod +x "$HOME/.local/sv2v/sv2v" + + - name: Export the toolchain locations + shell: bash + run: | + set -euo pipefail + echo "OSS_CAD_SUITE=$HOME/.local/oss-cad-suite" >> "$GITHUB_ENV" + echo "SV2V_HOME=$HOME/.local/sv2v" >> "$GITHUB_ENV" + + - name: Prove the toolchain runs + shell: bash + run: | + set -euo pipefail + # A formal job that starts without a working solver reports property + # failures about an encoder nobody checked. Fail here instead. + export PATH="$HOME/.local/oss-cad-suite/bin:$HOME/.local/sv2v:$PATH" + yosys -V + sby --help >/dev/null + sv2v --version diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml index 4d008e9..fe049ad 100644 --- a/.github/workflows/ci.yml +++ b/.github/workflows/ci.yml @@ -1,41 +1,113 @@ # SPDX-FileCopyrightText: 2026 Accemic Technologies GmbH # SPDX-License-Identifier: ISC +# +# What runs here is what a hosted runner can honestly run. Two things +# deliberately do NOT: the 51-gate XSIM battery (scripts/run_gates.sh) needs +# Vivado, and hardware verdicts need a KV260 board. See CONTRIBUTING.md, +# "Continuous integration". name: ci on: push: branches: [main] + # No branch filter: a PR against any base runs this. A plain push to a + # feature branch runs nothing -- dispatch the workflow on that branch + # (`gh workflow run ci.yml --ref `) or open the PR. pull_request: - branches: [main] + workflow_dispatch: + +permissions: + contents: read + +env: + # Pinned, not `releases/latest`: the old form scraped the GitHub API + # unauthenticated (60 requests/hour shared across all hosted runners) and + # silently followed whatever Verible released that morning, so the lint + # verdict was not reproducible. Bump deliberately. + VERIBLE_VERSION: v0.0-4148-g1ea007ec jobs: lint: - name: SystemVerilog lint (verible) + name: Lint + static guards runs-on: ubuntu-latest steps: - uses: actions/checkout@v4 - - name: Install Verible + + - name: Install Verible ${{ env.VERIBLE_VERSION }} + env: + GH_TOKEN: ${{ github.token }} run: | - url=$(curl -fsSL https://api.github.com/repos/chipsalliance/verible/releases/latest \ - | grep -oE '"browser_download_url": *"[^"]*linux-static-x86_64\.tar\.gz"' \ - | sed -E 's/.*"(https[^"]*)"/\1/' | head -1) - test -n "$url" - curl -fsSL "$url" -o verible.tar.gz + set -euo pipefail + asset="verible-${VERIBLE_VERSION}-linux-static-x86_64.tar.gz" + url="https://github.com/chipsalliance/verible/releases/download/${VERIBLE_VERSION}/${asset}" + curl -fsSL -H "Authorization: Bearer $GH_TOKEN" "$url" -o verible.tar.gz mkdir -p "$HOME/verible" tar -xzf verible.tar.gz -C "$HOME/verible" --strip-components=1 echo "$HOME/verible/bin" >> "$GITHUB_PATH" - - name: Run make lint + + - name: make lint run: make lint + publication-checks: + name: Publication guards + runs-on: ubuntu-latest + steps: + - uses: actions/checkout@v4 + # No lab addresses or credentials in a tracked file, English-only prose, + # every path a tutorial names resolves, the vendored-CVA6 delta list + # matches what fetch.sh does, and the mbv CTRL map agrees with its RTL. + # These used to hang off an internal CI driver and had therefore never + # run on a public CI at all. + - name: make check-publication + run: make check-publication + + dashboard-tests: + name: Dashboard self-tests + runs-on: ubuntu-latest + steps: + - uses: actions/checkout@v4 + - uses: actions/setup-node@v4 + with: + node-version: "20" + # test_demo_decode.py takes a real decode verdict and refuses to run + # without the decoder -- a decode check without its decoder would be a + # false green. Same pin, same hard failure as in the sim job. + - name: Provision the reference decoder (CTTD) + run: python3 scripts/fetch_cttd.py + - name: Run the dashboard self-tests + run: | + set -euo pipefail + cd examples/dashboard + rc=0 + for t in test_*.py; do + echo "== $t" + python3 "$t" || rc=1 + done + # The *.py glob never covered this one, so it had never run anywhere. + echo "== test_addr64.mjs" + node test_addr64.mjs || rc=1 + exit $rc + + reuse: + name: REUSE / SPDX compliance + runs-on: ubuntu-latest + steps: + - uses: actions/checkout@v4 + # v6 runs reuse 6.x (REUSE spec 3.3), the tool version `reuse lint` is + # run with locally; the reuse 4.x behind v4 did not match REUSE.toml + # paths with a `*` in a middle directory segment and reported 44 files + # as uncovered that 6.x covers. + - uses: fsfe/reuse-action@v6 + sim: name: Simulation (Verilator) runs-on: ubuntu-latest + timeout-minutes: 90 env: - # Pinned Verilator, built from source. Ubuntu's apt ships 5.020, which - # rejects the standards-compliant binary $fopen modes ("wb") the dump - # testbenches use — binary-mode $fopen needs a newer Verilator. Bump this - # deliberately, the same way .abc.config pins the Vivado version. + # Ubuntu's apt ships 5.020, which rejects the standards-compliant binary + # $fopen modes ("wb") the dump testbenches use. Bump deliberately, the + # same way .abc.config pins the Vivado version. VERILATOR_VERSION: v5.042 steps: - uses: actions/checkout@v4 @@ -50,6 +122,7 @@ jobs: - name: Build Verilator ${{ env.VERILATOR_VERSION }} if: steps.verilator-cache.outputs.cache-hit != 'true' run: | + set -euo pipefail sudo apt-get update sudo apt-get install -y git autoconf g++ flex bison make help2man \ libfl-dev libfl2 perl python3 @@ -61,8 +134,9 @@ jobs: make -j"$(nproc)" make install - - name: Set up sim toolchain + - name: Set up the sim toolchain run: | + set -euo pipefail sudo apt-get update # tclsh evaluates the .abc dependency files; libfl2 is Verilator's # runtime dependency (needed on a cache hit too, when the build above @@ -72,17 +146,47 @@ jobs: - name: Install abc (abc-flow) run: | + set -euo pipefail git clone --depth 1 https://github.com/accemic/abc-flow.git "$HOME/abc-flow" echo "$HOME/abc-flow/abc" >> "$GITHUB_PATH" - - name: Run make sim + # The decode verdict of every sim-* target is taken by CTTD, the pinned + # reference decoder. It is not committed; scripts/cttd.pin names the + # public GitHub release it is fetched from and the sha256 per platform. + # A runner that cannot obtain exactly that build has no verdict to + # offer, so this step is a hard failure: a simulation that decoded + # nothing must never look like a green one. (Before the pin pointed at + # a public host this step was allowed to fail and the run said so in + # its summary; that fallback is gone with the reason for it.) + - name: Provision the reference decoder (CTTD) + run: python3 scripts/fetch_cttd.py + + - name: make sim run: | verilator --version abc -h >/dev/null make sim - # The worked integrations under examples/ (TGC5B SoC + its KV260 devmem - # flow). Same toolchain as `make sim` — the program artifacts are - # committed, so no RISC-V toolchain is needed here. - - name: Run make sim-examples + - name: make sim-examples run: make sim-examples + + - name: Decoder regression corpus + run: bash scripts/run_corpus_regression.sh + + # decode_and_check.sh writes bld/.decode_skipped only under + # CT_DECODE_OPTIONAL=1, which this workflow never sets; the check stays + # so a future change that sets it cannot pass as a full verdict. + - name: Summarise + if: always() + run: | + { + if [ -f bld/.decode_skipped ]; then + echo "### Simulation ran, decode verdict NOT taken" + echo + echo '```' + sort -u bld/.decode_skipped + echo '```' + else + echo "### Simulation and decode verdict both taken" + fi + } >> "$GITHUB_STEP_SUMMARY" diff --git a/.github/workflows/formal.yml b/.github/workflows/formal.yml new file mode 100644 index 0000000..72a2d63 --- /dev/null +++ b/.github/workflows/formal.yml @@ -0,0 +1,147 @@ +# SPDX-FileCopyrightText: 2026 Accemic Technologies GmbH +# SPDX-License-Identifier: ISC +# +# The SymbiYosys property gates of the emission core. Licence-free (OSS CAD +# Suite + sv2v), no decoder, no hardware -- so unlike the XSIM gate battery +# and the board campaign, this one really can run on a hosted runner. +# +# Split into two jobs because of wall clock, not because of scope. sby runs +# the tasks of one .sby CONCURRENTLY and they contend, so a target costs one +# wall clock for all of its tasks (formal/README.md records mseo_mdo at +# ~3200 s per task that way, and a livecover attempt that ran 1:29:35 without +# concluding). A hosted job is capped at 6 h, so a PR gets the targets that +# are measurably quick and the rest runs nightly. +# +# Measured on this tree, 2026-08-21, oss-cad-suite 2026-08-02: +# ovf_injector prove 58 s, cover 3 s -> PR tier +# msg_gen cover 92 s, bmc 287 s -> PR tier +# CAVEAT: that bmc figure is a run that ABORTED at step +# 20 on the stale-mirror defect described below. The +# complete 50 steps cost 401 s on the Windows +# workstation and 581 s with two other sby runs on the +# same box (2026-08-24), so budget for more than the +# table says -- still far inside the 6 h job cap. +# nexus_formatter still in yosys AST derivation after 11 min for a +# SINGLE task on an idle machine -> nightly only +# nexus_formatter was in the PR tier in the first draft of this file. That was +# wrong and it was wrong for an instructive reason: it had been tiered by the +# DEPTHS in its .sby (bmc 40, cover 25, prove 15), which say nothing about +# elaboration cost. +# +# RED=1 (the mutation counter-proofs) is deliberately NOT wired in: two of the +# run_red.sh scripts do `git worktree add` at hardcoded SHAs into a directory +# outside the repository root, which a shallow actions/checkout cannot serve. +# Run those by hand on a full clone -- see formal/README.md. +# +# RESOLVED 2026-08-24; this was KNOWN RED from the first run of this workflow +# on 2026-08-21. `msg_gen bmc` failed with a counterexample at step 20 on +# A_msg4_slot_pays (P-MSG-4). The cause was neither the RTL nor the property's +# timing: formal/msg_gen/wrapper.sv enumerated seven of the RTL's EIGHT +# drain-hold arms, so a cycle in which the RTL legitimately drained an +# accumulated ICNT read as a free emission slot. The eighth arm +# (cf_sync_icnt_overflow_hold) entered the RTL on 2026-08-12 with ee25d098f85, +# which touched rtl/ only -- the mirror was complete when written on +# 2026-08-02 and silently stopped being so nine days before this workflow +# first ran and showed it. Keeping the job red rather than waiving it was the +# right call: the criterion was intact, the wrapper was not. +# +# Fixed by completing the mirror, plus two additions so the next arm cannot +# cost the same detour: A_consume_decomposition (the hold set derived from +# consume_etip's own definition instead of counted -- a ninth arm turns THAT +# assertion red, by name) and A_msg4_no_idle_beat (the debt claim with no hold +# enumeration at all). Measured on the pinned toolchain: bmc PASS at depth 50, +# cover PASS with 8/8 witnesses -- including the new C_freeslot_reached, +# without which completing a hold list could buy a green run by emptying the +# property. Mutation counter-proof: formal/msg_gen/run_red_p4.sh. +# Reproduce with: +# TARGETS=msg_gen bash scripts/run_formal.sh + +name: formal + +on: + push: + branches: [main] + pull_request: + workflow_dispatch: + inputs: + targets: + description: "Space-separated formal targets (default: the full set)" + required: false + default: "" + schedule: + # 02:30 UTC nightly -- the full set, including the multi-hour targets. + - cron: "30 2 * * *" + +permissions: + contents: read + +jobs: + # Fast tier: bounded depths and the cheap solvers. Runs on every PR. + formal-fast: + name: "formal: ${{ matrix.target }}" + if: github.event_name == 'push' || github.event_name == 'pull_request' + runs-on: ubuntu-latest + timeout-minutes: 60 + strategy: + fail-fast: false + matrix: + target: [ovf_injector, msg_gen] + steps: + - uses: actions/checkout@v4 + - uses: ./.github/actions/setup-formal + - name: Run ${{ matrix.target }} + run: TARGETS='${{ matrix.target }}' FORMAL_TIMEOUT=2400 bash scripts/run_formal.sh + - name: Upload solver logs + if: failure() + uses: actions/upload-artifact@v4 + with: + name: formal-fast-${{ matrix.target }} + path: | + formal/${{ matrix.target }}/${{ matrix.target }}_*/ + formal/${{ matrix.target }}/build/ + retention-days: 7 + if-no-files-found: ignore + + # Full tier: everything, including preproc_sync (12 tasks) and mseo_mdo. + # Nightly and on demand only. + formal-full: + name: "formal-full: ${{ matrix.target }}" + if: github.event_name == 'schedule' || github.event_name == 'workflow_dispatch' + runs-on: ubuntu-latest + timeout-minutes: 350 + strategy: + fail-fast: false + matrix: + target: + - ovf_injector + - preproc_sync + - msg_gen + - mseo_mdo + - nexus_formatter + - composer_slots + - nexus_formatter_xlen64 + steps: + - uses: actions/checkout@v4 + with: + # nexus_formatter_xlen64 copies the tracked sources into bld/ via + # `git ls-files`, so it needs a real checkout, not an export. + fetch-depth: 1 + - uses: ./.github/actions/setup-formal + - name: Run ${{ matrix.target }} + run: | + want='${{ github.event.inputs.targets }}' + if [ -n "$want" ] && ! printf '%s ' $want | grep -qw '${{ matrix.target }}'; then + echo "::notice::${{ matrix.target }} not in the requested set ($want) -- skipped" + exit 0 + fi + TARGETS='${{ matrix.target }}' FORMAL_TIMEOUT=18000 bash scripts/run_formal.sh + - name: Upload solver logs + if: failure() + uses: actions/upload-artifact@v4 + with: + name: formal-full-${{ matrix.target }} + path: | + formal/${{ matrix.target }}/${{ matrix.target }}_*/ + formal/${{ matrix.target }}/build/ + retention-days: 14 + if-no-files-found: ignore diff --git a/.github/workflows/reuse.yml b/.github/workflows/reuse.yml deleted file mode 100644 index e5d4ecf..0000000 --- a/.github/workflows/reuse.yml +++ /dev/null @@ -1,19 +0,0 @@ -# SPDX-FileCopyrightText: 2026 Accemic Technologies GmbH -# SPDX-License-Identifier: ISC - -name: reuse - -on: - push: - branches: [main] - pull_request: - branches: [main] - -jobs: - reuse: - name: REUSE / SPDX compliance - runs-on: ubuntu-latest - steps: - - uses: actions/checkout@v4 - - name: REUSE compliance check - uses: fsfe/reuse-action@v4 diff --git a/.gitignore b/.gitignore index bebcb7e..90e02d8 100644 --- a/.gitignore +++ b/.gitignore @@ -8,6 +8,7 @@ bld/ *.jou *.log *.str +*.pb .Xil/ vivado_*.backup.* vivado_pid*.str @@ -16,6 +17,16 @@ webtalk*.log webtalk*.jou .cxl.*.log +# Gate verdicts are evidence, not build output: they are versioned on +# purpose (verification/evidence/README.md -- P7 audit B-5). The transcripts they +# were extracted from stay in bld/ and are regenerated by re-running the +# command each file names. +!verification/evidence/**/*.log +# Same reasoning for the synthesis reports a documented resource figure +# rests on: the number in the manual is only checkable if the report it +# was read from is in the tree (P4 final audit B-1). +!verification/evidence/**/*.rpt + # Editor / IDE *.swp *.swo @@ -30,6 +41,11 @@ Thumbs.db # Private / local-only notes — never published with the public release .private/ +# Internal engineering working area: coverage campaign reports, waiver store, +# generated gcovr HTML, reference-manual working copy. The published +# documentation is doc/ (AsciiDoc); docs/ stays local. +docs/ + # Python (PeakRDL toolchain) __pycache__/ *.pyc @@ -39,3 +55,49 @@ __pycache__/ # NOTE: the generated SV (rtl/pkg/ct_cs_cpuif*.sv, # tests/lib/ct_cs_cpuif_wb_helper.sv) is intentionally committed, not ignored. +dfx_runtime.txt +# Fetched decoder binaries (scripts/fetch_cttd.py); the pin is the truth. +bin/cttd-* +bin/*.part +# Vivado-generated IP output of the example board flows (the .tcl sources +# are committed; their generated ip/ trees and journals are build products). +examples/kv260/*/fpga/ip/ +examples/kv260/*/fpga/proj*/ +examples/kv260/*/fpga/pkg/ +examples/kv260/*/fpga/*.jou +examples/kv260/*/fpga/*.log +examples/kv260/*/fpga/.Xil/ + +# fetched reference cores (examples/kv260/third_party/fetch.sh; pinned, never vendored) +/examples/kv260/third_party/cva6_ref/ +/examples/kv260/third_party/rocket_ref_repo/ +# rocket_ref/ IS committed since 2026-08-19 (maintainer decision). Unlike CVA6 there +# is no fetch path for it: the Verilog is GENERATED, and the recipe needs +# four patches that are not in this repository plus a Linux sbt/FIRRTL +# toolchain. Leaving it out meant two of the ten examples could not be built +# by anyone who did not already have the file -- while the build matrix said +# "builds with one command". Vendoring it costs 17.6 MB and makes the matrix +# true. Licences: BSD-3-Clause (Regents), Apache-2.0 (SiFive), MIT +# (vivado-risc-v), chisel-jtag -- all permissive, all redistributable, texts +# alongside the file. +# per-flow report drops (the "no .rpt in git" rule from examples/README.md) +examples/kv260/*/fpga/reports/ +examples/kv260/*/fpga/*.rpt + +# Board-gate working directories. Every gate under examples/kv260/*/board/ +# defaults its --out next to its own script (board_run_duo, board_run_mbv, +# board_run_cva6_linux ...), and a run drops the generated board sequence, +# the raw ring words and the decoded pcout there -- session material, not +# evidence. Without this a reviewer who follows the tutorial ends up with a +# dirty `git status` and no way to tell their own run's leftovers from the +# repository. The gates' PASS/FAIL verdicts live in the terminal and in the +# handoff documents, not in these directories. +examples/kv260/*/board/board_run_*/ + +# Software build outputs of the KV260 examples (payloads, listings, pcinfo). +# These are gigabyte-scale and reproducible from sw/build_payload_*.sh; the +# one artifact that is deliberately shipped is the pinned demo pcinfo under +# examples/dashboard/demo/. +examples/kv260/*/sw/out/ +examples/kv260/*/sw/out_*/ +examples/kv260/*/sw/out64*/ diff --git a/.rules.verible_lint b/.rules.verible_lint index 3a85d09..2cb2c39 100644 --- a/.rules.verible_lint +++ b/.rules.verible_lint @@ -1,12 +1,20 @@ +# Opt-in lint rule set (scripts/lint.sh runs with --ruleset=none, so only the +# rules listed here are active). Per-directory overrides are picked up by +# --rules_config_search: see rtl/pkg/ and formal/. +# +# Deliberately NOT enabled: +# plusarg-assignment Verible rejects every $test$plusargs. The testbenches +# use it for BOOLEAN feature flags, which is exactly what +# it is for; the two places that read a VALUE correctly +# use $value$plusargs. The rule cannot tell the two apart +# and would flag 47 correct uses. +always-comb-blocking +always-ff-non-blocking=catch_modifying_assignments:on;waive_for_locals:on +module-begin-block +parameter-name-style=localparam_style:ALL_CAPS;parameter_style:ALL_CAPS +module-filename -+module-parameter -+module-begin-block ++module-parameter +mismatched-labels +invalid-system-task-function +forbid-consecutive-null-statements -+plusarg-assignment +void-cast diff --git a/CITATION.cff b/CITATION.cff index 1286528..1f88e89 100644 --- a/CITATION.cff +++ b/CITATION.cff @@ -1,7 +1,7 @@ # SPDX-FileCopyrightText: 2026 Accemic Technologies GmbH # SPDX-License-Identifier: ISC cff-version: 1.2.0 -title: "CEDARtools.TraceEncoder — RISC-V N-Trace Encoder IP" +title: "CEDARtools.TraceEncoder — trace encoder IP for RISC-V cores" message: >- If you use this software in academic or research work, please cite it using the metadata in this file. @@ -12,14 +12,17 @@ authors: repository-code: "https://github.com/accemic/TraceEncoder" url: "https://www.accemic.com" abstract: >- - CEDARtools.TraceEncoder is an open-source SystemVerilog implementation of a RISC-V - N-Trace encoder. It ingests a core's instruction-trace port (TIP), - compresses the execution stream into N-Trace messages, and emits them - on an ATB or AXI-Stream output. The IP is dual-licensed under - CERN-OHL-S-2.0 or an Accemic commercial license. + CEDARtools.TraceEncoder (CTTE, formerly C-Trace) is an open-source + SystemVerilog trace encoder for RISC-V cores. It ingests a core's + instruction-trace port (TIP) and compresses the execution stream either + into N-Trace messages per the IEEE-ISTO 5001-2012 (Nexus) standard or + into E-Trace te_inst packets, emitting them on an ATB or AXI-Stream + output. The IP is dual-licensed under CERN-OHL-S-2.0 or an Accemic + commercial license. keywords: - RISC-V - N-Trace + - E-Trace - tracing - hardware - SystemVerilog @@ -27,4 +30,5 @@ keywords: - FPGA license: CERN-OHL-S-2.0 license-url: "https://github.com/accemic/TraceEncoder/blob/main/LICENSE.md" -version: "0.1.0" +version: "1.0.0" +date-released: "2026-08-28" diff --git a/CONTRIBUTING.md b/CONTRIBUTING.md index e8d200e..dde7161 100644 --- a/CONTRIBUTING.md +++ b/CONTRIBUTING.md @@ -6,7 +6,17 @@ SPDX-License-Identifier: CC-BY-4.0 # Contributing to CEDARtools.TraceEncoder Thanks for your interest in contributing. This document describes the -expectations for changes to CEDARtools.TraceEncoder. +expectations for changes to CEDARtools.TraceEncoder (CTTE). The earlier +short name *C-Trace* is retired from prose but deliberately kept where +renaming would break something outside this repository: the `ct_*` identifier +prefix (the IP's public API), the published demo bundles `*_ctrace_kv260` and +the board artifacts `ctrace_resmem.dtso` / `ctrace-pl-ddr` / +`ctrace-dashboard.service`, the Vivado block design `mbv_ctrace_soc` baked +into committed bitstreams, and the recorded captures and evidence files under +`examples/dashboard/demo/` and `verification/`, which are raw data with +published checksums. (The sibling repositories have all been renamed too — +`scripts/check_public_links.py`, part of `make check-publication`, fails on a +link to one of the retired names.) ## Quick checklist @@ -16,10 +26,51 @@ expectations for changes to CEDARtools.TraceEncoder. - [ ] `make sim` passes for any module you touched. - [ ] If you changed `rdl/ct_cs_cpuif.rdl`, you re-ran `make rdl` and committed the regenerated SV in the same commit; likewise - `make rdl-soc` for `examples/tgc5b_soc/rdl/ct_soc.rdl`. + `make rdl-soc` for `examples/kv260/common/tgc5b/rdl/ct_soc.rdl`. - [ ] Commit messages explain *why*, not just *what*. - [ ] You've signed the CLA (see [License & CLA](#license--cla)). +## Which checks apply to which change + +The checklist above is the floor. Which *further* gate has to be green +depends on what you touched, and that mapping is not obvious from the +directory names, so here it is: + +| You changed | What has to be green as well | +|---|---| +| RTL of the encoder pipeline | `make sim`, and the simulation gate battery `scripts/run_gates.sh` (overflow/robustness gates, the compression byte-identity legs, the feature gates) | +| a register description (`rdl/*.rdl`) | `make rdl` re-run and the regenerated files under `rtl/pkg/` committed in the *same* commit — they are never hand-edited | +| a feature switch (`rtl/pkg/ct_pkg.sv`, an RDL reset or offset, the TCODE-58 CAPS map) | `scripts/check_feature_flags.py`, the drift guard that holds those three representations of one switch to each other (part of `make lint`) | +| the emission core — the state machine that forms the output | the SymbiYosys property gates `scripts/run_formal.sh`, including the `RED=1` mutation counter-proof where the property has one ([`formal/README.md`](formal/README.md)) | +| the byte format on the wire, or the pinned decoder | the decoder regression corpus `scripts/run_corpus_regression.sh`: archived campaign captures under `verification/corpus/` must keep decoding to their recorded verdicts. Turning an old green capture red needs a commit message saying why the old verdict was wrong | +| anything that carries a claim about *hardware* behaviour (robustness, overflow recovery) | a run on a real KV260 board. A green simulation is evidence about the model, not about the hardware — and this repository no longer carries the lab campaign driver, so that evidence is produced outside it and quoted into `verification/evidence/` | +| a diagram under `doc/images/` | edit the **`.drawio.png` itself** — open it in draw.io, it *is* the source. Re-export with `drawio -x -f png -e -s 2 -b 0 -o .drawio.png .drawio` and delete any temporary `.drawio` you exported from; `scripts/check_drawio_embedded.py` (part of `make lint`) fails on a sibling `.drawio` or on an image that lost its embedded source | +| documentation under `doc/` | the conformance and limitation lists ([`doc/trace-format.adoc`](doc/trace-format.adoc), [`doc/release-notes.adoc`](doc/release-notes.adoc)) re-read against the RTL you changed. Resource numbers quoted in `doc/` are additionally checked against the reports under `verification/evidence/` by `scripts/check_doc_evidence.py` (part of `make lint`) | + +### Continuous integration + +CI runs on GitHub Actions ([`.github/workflows/`](.github/workflows/)). What +runs where, and why the split exists: + +| Workflow / job | What it runs | Tools | +|---|---|---| +| `ci` → `lint` | `make lint`: 14 drift guards, the 6 publication guards below, and Verible over every `*.sv` | Python 3.8+, Verible | +| `ci` → `publication-checks` | `make check-publication` on its own (it is also part of `make lint`): no lab internals, English-only, tutorial paths resolve, no private host or retired repository name and every README link resolves, vendored-CVA6 delta list matches, mbv CTRL map consistent | Python only | +| `ci` → `dashboard-tests` | the dashboard's stdlib-only self-tests | Python, Node | +| `ci` → `sim` | `make sim` + `make sim-examples` | Verilator, `abc`; the decode verdict additionally needs CTTD | +| `ci` → `reuse` | REUSE / SPDX compliance | — | +| `formal` | `scripts/run_formal.sh`: the SymbiYosys property gates. A fast subset per PR, the full set nightly | OSS CAD Suite + sv2v, no EDA licence | + +Two things deliberately do **not** run on a hosted runner, because they cannot: + +- **The gate battery** `scripts/run_gates.sh` (51 gates listed in + `scripts/gates.list`) needs Vivado XSIM. `make sim` is the + simulator-agnostic subset that CI does run. +- **Hardware verdicts** need a real KV260 board. + +You do not need all of them locally — CI runs what it can — but a PR that is +red in the check its change belongs to will come back. + ## Development setup The required tools and the high-level commands are listed once, in the @@ -60,8 +111,8 @@ Make use `#` lines. Files that cannot carry a header are recorded in their upstream copyright and license, and are left byte-identical — their SPDX metadata goes into a REUSE `.license` sidecar instead of an in-file header. The one such file today is the MINRES TGC5B core, -`examples/tgc5b_soc/cpu/TGC5B_AXI4L_H2E.sv` (see -[`examples/tgc5b_soc/cpu/README.md`](examples/tgc5b_soc/cpu/README.md)). +`examples/kv260/common/tgc5b/cpu/TGC5B_AXI4L_H2E.sv` (see +[`examples/kv260/common/tgc5b/cpu/README.md`](examples/kv260/common/tgc5b/cpu/README.md)). Do not modify it and do not submit patches against it — they belong upstream at MINRES. Adding new vendored third-party code needs a maintainer decision first. @@ -83,7 +134,7 @@ valid SPDX header. ## License & CLA -CEDARtools.TraceEncoder is licensed per artifact type (see [`LICENSE.md`](LICENSE.md)): +CTTE is licensed per artifact type (see [`LICENSE.md`](LICENSE.md)): the **hardware IP** is dual-licensed under **CERN-OHL-S-2.0** or a **commercial license** from Accemic Technologies GmbH, **software** is **ISC**, and **documentation** is **CC-BY-4.0**. diff --git a/LICENSE.md b/LICENSE.md index 9162bbd..4245ca5 100644 --- a/LICENSE.md +++ b/LICENSE.md @@ -5,7 +5,7 @@ SPDX-License-Identifier: CC-BY-4.0 # Licensing -CEDARtools.TraceEncoder — RISC-V N-Trace Encoder IP +CEDARtools.TraceEncoder — RISC-V Trace Encoder IP Copyright (C) 2026 Accemic Technologies GmbH This repository is licensed **per artifact type**. Which license applies @@ -24,8 +24,9 @@ The full text of every license used is in [`LICENSES/`](LICENSES/). | **Hardware IP** | RTL (`.sv`), register description (`.rdl`), timing/placement constraints (`.xdc`), and the SystemVerilog/`.abc` verification testbenches | **`CERN-OHL-S-2.0 OR LicenseRef-Accemic-Commercial`** (dual) | | **Software** | Build, tooling and CI — shell/Python scripts, `Makefile`, GitHub workflows, config and metadata | **`ISC`** | | **Documentation** | Markdown, AsciiDoc, and documentation images | **`CC-BY-4.0`** | -| **Third-party IP** | MINRES TGC5B core vendored for the example SoC (`examples/tgc5b_soc/cpu/`) | **`CERN-OHL-S-2.0 OR LicenseRef-MINRES-Commercial`** (dual — licensed by MINRES) | -| **Vendored** | `bin/NexRv` reference decoder (derived from the IAR Systems NexRv tool) | **`ISC`** | +| **Pre-built demo apps** | The ready-to-load KV260 apps under `examples/kv260//fpga/prebuilt/` — bitstream, device-tree overlay, `shell.json`, manifest — built from the Hardware IP and the example SoCs (declared in [`REUSE.toml`](REUSE.toml)) | **`CERN-OHL-S-2.0 OR LicenseRef-Accemic-Commercial`** (dual); the third-party cores compiled into a bitstream keep their own licenses, stated in that example's README | +| **Third-party IP** | MINRES TGC5B core vendored for the example SoC (`examples/kv260/common/tgc5b/cpu/`) | **`CERN-OHL-S-2.0 OR LicenseRef-MINRES-Commercial`** (dual — licensed by MINRES) | +| **Fetched tool** | CTTD (CEDARtools.TraceDecoder) reference decoder — not committed; `scripts/fetch_cttd.py` downloads the pinned build into the gitignored `bin/` (see below) | **`ISC`** (upstream NexRv reference decoder of the RISC-V Nexus Trace TG, extended by Accemic) | ## Hardware IP — dual license @@ -49,13 +50,20 @@ SPDX-License-Identifier: CERN-OHL-S-2.0 OR LicenseRef-Accemic-Commercial ## Third-party IP — MINRES TGC5B core -`examples/tgc5b_soc/cpu/TGC5B_AXI4L_H2E.sv` is **not** Accemic's work. It +`examples/kv260/common/tgc5b/cpu/TGC5B_AXI4L_H2E.sv` is **not** Accemic's work. It is the MINRES **TGC5B** RISC-V core, `Copyright 2020-2022 MINRES Technologies GmbH`, vendored so the integration example builds and simulates against a real core. MINRES has permitted its publication under the same dual-license model -this repository uses for its own hardware IP: +this repository uses for its own hardware IP. The permission is on +record — Eyck Jentzsch, Managing Director of MINRES Technologies GmbH, by +e-mail of **2026-08-03**, in reply to an explicit request naming this +repository's `LICENSE.md`; the parties, the date and the scope are in +[`legal/minres-tgc5b-license-grant-20260803.md`](legal/minres-tgc5b-license-grant-20260803.md). +The correspondence itself is MINRES' text and not Accemic's to publish; +Accemic holds it and produces it for licensees and licence auditors on +request (). ``` SPDX-License-Identifier: CERN-OHL-S-2.0 OR LicenseRef-MINRES-Commercial @@ -92,13 +100,17 @@ under **Creative Commons Attribution 4.0 International (CC-BY-4.0)** — you may share and adapt them with attribution. Full text: [`LICENSES/CC-BY-4.0.txt`](LICENSES/CC-BY-4.0.txt). -## Vendored — NexRv +## Fetched tool — CTTD -`bin/NexRv` is a reference decoder built from the CEDARtools.TraceEncoder port at -[accemic/NexRv-for-C-Trace](https://github.com/accemic/NexRv-for-C-Trace), -derived from the IAR Systems NexRv tool, copyright IAR Systems AB and -Accemic Technologies GmbH, licensed under **ISC**. It is recorded in -[`REUSE.toml`](REUSE.toml). +The reference decoder **CTTD (CEDARtools.TraceDecoder)** is not part of this +repository's tree: `scripts/fetch_cttd.py` downloads the build pinned in +`scripts/cttd.pin` (sha256 per platform, `base_url` naming the CTTD +repository) into the gitignored `bin/`. CTTD is +derived from the RISC-V Nexus Trace Task Group's reference decoder NexRv +(copyright IAR Systems AB, **ISC**) and extended by Accemic Technologies GmbH +(E-Trace front end, DAQ, multi-target decode, CTXP export); its licence text +and notices travel with the CTTD repository. Nothing of it is redistributed +from here, so it carries no `REUSE.toml` entry in this repository. ## Commercial licensing @@ -106,10 +118,17 @@ Organizations that cannot comply with the copyleft obligations of CERN-OHL-S-2.0 for the hardware IP may obtain a commercial license from Accemic Technologies GmbH. Inquiries: [sales@accemic.com](mailto:sales@accemic.com). -That license covers the **CEDARtools.TraceEncoder IP** — everything in -`rtl/`, `rdl/`, `tests/` and the Accemic-authored parts of `examples/`. -It does **not** cover the vendored MINRES TGC5B core, which carries its -own dual license from MINRES. The two are independent: +That license covers the **CEDARtools.TraceEncoder IP**, and the IP is +defined by its licence expression, not by its directory: it is exactly the +set of files whose SPDX header reads +`CERN-OHL-S-2.0 OR LicenseRef-Accemic-Commercial` — the RTL, the register +description, the testbenches, the formal properties, the reference vectors +and the Accemic-authored hardware parts of `examples/`. Files under the +same directories that carry a different expression (`ISC` build and board +scripts, `CC-BY-4.0` documentation) are already permissive and need no +commercial license. The commercial arm does **not** cover the vendored +MINRES TGC5B core, which carries its own dual license from MINRES. The two +are independent: | You want to ship | Encoder | TGC5B core | License(s) needed | |---|---|---|---| diff --git a/LICENSES/Apache-2.0.txt b/LICENSES/Apache-2.0.txt new file mode 100644 index 0000000..137069b --- /dev/null +++ b/LICENSES/Apache-2.0.txt @@ -0,0 +1,73 @@ +Apache License +Version 2.0, January 2004 +http://www.apache.org/licenses/ + +TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION + +1. Definitions. + +"License" shall mean the terms and conditions for use, reproduction, and distribution as defined by Sections 1 through 9 of this document. + +"Licensor" shall mean the copyright owner or entity authorized by the copyright owner that is granting the License. + +"Legal Entity" shall mean the union of the acting entity and all other entities that control, are controlled by, or are under common control with that entity. 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Commercial licenses allow integration without the copyleft obligations of CERN-OHL-S-2.0. diff --git a/LICENSES/LicenseRef-Accemic-Trademark.txt b/LICENSES/LicenseRef-Accemic-Trademark.txt new file mode 100644 index 0000000..c2b54dc --- /dev/null +++ b/LICENSES/LicenseRef-Accemic-Trademark.txt @@ -0,0 +1,58 @@ +Accemic Trade Mark Permission +============================= + +This permission covers the Accemic word marks, the CEDARtools(R) mark and the +Accemic figurative marks (logos) as distributed in this repository. It is a +TRADE MARK permission, not a copyright licence, and it exists because the two +must not be confused. + +WHY THIS FILE EXISTS + +Everything else in this repository is offered under an open-source licence, +and those licences deliberately permit modification. A trade mark is the one +thing that must not be modified: its entire purpose is to tell a reader who +stands behind a thing. A permissive copyright licence on a logo would allow +anyone to alter it and keep calling it ours -- which is precisely what trade +mark law prevents, and what this repository's TRADEMARKS.md relies on. + +Open-source projects that ship their own marks handle this the same way; the +Linux Foundation, Mozilla and the Rust Foundation each separate the code +licence from the mark permission for this reason. + +WHAT YOU MAY DO + + * Reproduce the mark UNALTERED to identify Accemic, Accemic products or + Accemic technology -- for example in documentation, a paper, a slide, a + comparison, a press article, or a user interface built on this software + that says truthfully where the software comes from. + * Scale it proportionally and place it on a background that keeps it + legible. That is not a modification. + +WHAT YOU MAY NOT DO + + * Modify the mark: no re-drawing, re-colouring, re-proportioning, adding to + or removing from it, and no derivative marks based on it. + * Use it as a badge of origin for anything that is not Accemic's -- on your + own product, your fork, your distribution, your service, or your company. + * Use it in a way that suggests Accemic endorses, sponsors or certifies you + or your work, when it does not. + * Register it, or anything confusingly similar to it, anywhere. + +FORKS + +You may keep the mark in an unmodified copy of this repository, because there +it still identifies the origin truthfully. If you modify the software and +distribute it, remove the marks from your distribution -- the open-source +licences give you every right to the code, and none to the name. That is not +a restriction on the code; it is the ordinary condition of every open-source +project that has a name worth protecting. + +QUESTIONS + +Anything this text does not answer -- co-branding, a use you are unsure about, +a permission beyond the above -- is decided case by case. Ask: +info@accemic.com. + +Nothing here narrows any right you have under applicable trade mark law, +including nominative fair use: naming us in order to refer to us needs no +permission from anyone. diff --git a/LICENSES/LicenseRef-MINRES-Commercial.txt b/LICENSES/LicenseRef-MINRES-Commercial.txt index 81eb10d..dfc1c35 100644 --- a/LICENSES/LicenseRef-MINRES-Commercial.txt +++ b/LICENSES/LicenseRef-MINRES-Commercial.txt @@ -8,7 +8,7 @@ Scope It applies to the third-party core vendored in this repository: - examples/tgc5b_soc/cpu/TGC5B_AXI4L_H2E.sv + examples/kv260/common/tgc5b/cpu/TGC5B_AXI4L_H2E.sv Copyright 2020-2022 MINRES Technologies GmbH Core config TGC5B_AXI4L_H2E Config hash ecababb8345510fc9133035ddf2a3116ca7a57bf diff --git a/LICENSES/MIT.txt b/LICENSES/MIT.txt new file mode 100644 index 0000000..d817195 --- /dev/null +++ b/LICENSES/MIT.txt @@ -0,0 +1,18 @@ +MIT License + +Copyright (c) + +Permission is hereby granted, free of charge, to any person obtaining a copy of this software and +associated documentation files (the "Software"), to deal in the Software without restriction, including +without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the +following conditions: + +The above copyright notice and this permission notice shall be included in all copies or substantial +portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT +LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO +EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER +IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE +USE OR OTHER DEALINGS IN THE SOFTWARE. diff --git a/LICENSES/SHL-2.0.txt b/LICENSES/SHL-2.0.txt new file mode 100644 index 0000000..9218b47 --- /dev/null +++ b/LICENSES/SHL-2.0.txt @@ -0,0 +1,22 @@ +# Solderpad Hardware Licence Version 2.0 + +This licence (the “Licence”) operates as a wraparound licence to the Apache License Version 2.0 (the “Apache License”) and grants to You the rights, and imposes the obligations, set out in the Apache License (which can be found here: http://apache.org/licenses/LICENSE-2.0), with the following extensions. It must be read in conjunction with the Apache License. Section 1 below modifies definitions in the Apache License, and section 2 below replaces sections 2 of the Apache License. You may, at your option, choose to treat any Work released under this License as released under the Apache License (thus ignoring all sections written below entirely). Words in italics indicate changes rom the Apache License, but are indicative and not to be taken into account in interpretation. + +1. The definitions set out in the Apache License are modified as follows: + +Copyright any reference to ‘copyright’ (whether capitalised or not) includes ‘Rights’ (as defined below). + +Contribution also includes any design, as well as any work of authorship. + +Derivative Works shall not include works that remain reversibly separable from, or merely link (or bind by name) or physically connect to or interoperate with the interfaces of the Work and Derivative Works thereof. + +Object form shall mean any form resulting from mechanical transformation or translation of a Source form or the application of a Source form to physical material, including but not limited to compiled object code, generated documentation, the instantiation of a hardware design or physical object and conversions to other media types, including intermediate forms such as bytecodes, FPGA bitstreams, moulds, artwork and semiconductor topographies (mask works). + +Rights means copyright and any similar right including design right (whether registered or unregistered), semiconductor topography (mask) rights and database rights (but excluding Patents and Trademarks). + +Source form shall mean the preferred form for making modifications, including but not limited to source code, net lists, board layouts, CAD files, documentation source, and configuration files. +Work also includes a design or work of authorship, whether in Source form or other Object form. + +2. Grant of Licence + +2.1 Subject to the terms and conditions of this License, each Contributor hereby grants to You a perpetual, worldwide, non-exclusive, no-charge, royalty-free, irrevocable license under the Rights to reproduce, prepare Derivative Works of, make, adapt, repair, publicly display, publicly perform, sublicense, and distribute the Work and such Derivative Works in Source or Object form and do anything in relation to the Work as if the Rights did not exist. diff --git a/MAINTAINERS.md b/MAINTAINERS.md index 2e842fb..7883764 100644 --- a/MAINTAINERS.md +++ b/MAINTAINERS.md @@ -5,16 +5,18 @@ SPDX-License-Identifier: CC-BY-4.0 # Maintainers -This file lists the people who maintain CEDARtools.TraceEncoder. Maintainers have +This file lists the people who maintain CEDARtools.TraceEncoder (CTTE). +Maintainers have write access, review and merge PRs, and steer the project's direction. For machine-readable review routing, see [`.github/CODEOWNERS`](.github/CODEOWNERS). ## Active maintainers -| Name | GitHub | Contact | Focus | -|----------------|------------|----------------------------------|------------------------| -| Albert Schulz | [@albertschulz](https://github.com/albertschulz) | | Architecture, RTL, RDL | +| Name | GitHub | Contact | Focus | +|------------------|------------|----------------------------------|----------------------------------| +| Albert Schulz | [@albertschulz](https://github.com/albertschulz) | | Architecture, RTL, RDL | +| Alexander Weiss | [@accemic-weiss](https://github.com/accemic-weiss) | | Encoder core, verification, tooling | ## Becoming a maintainer diff --git a/Makefile b/Makefile index 436ee83..3330bf8 100644 --- a/Makefile +++ b/Makefile @@ -1,7 +1,7 @@ # SPDX-FileCopyrightText: 2026 Accemic Technologies GmbH # SPDX-License-Identifier: ISC # -# CEDARtools.TraceEncoder top-level Makefile. +# CEDARtools.TraceEncoder (CTTE) top-level Makefile. .DEFAULT_GOAL := help SHELL := /bin/bash @@ -14,7 +14,80 @@ SHELL := /bin/bash ABC_COV ?= COV_DIR := bld/coverage -.PHONY: help rdl rdl-soc rdl-html sim sim-basic sim-interrupts sim-stress sim-periodic-sync sim-exceptions sim-data-basic sim-overrun-recovery sim-hsi-csr-cap sim-combined sim-tgc5b-soc sim-tgc5b-ps sim-examples impl-tgc5b-soc coverage lint clean +# Windows/MSYS2: the Verilator binary reports its data directory as an +# MSYS-internal POSIX path (/ucrt64/share/verilator) that the Windows process +# itself cannot open, so every `abc -sim` aborts with "Cannot find +# verilated_std.sv". Derive a native path from the binary location instead. +# On Linux this stays empty and Verilator's built-in default applies. +ifeq ($(OS),Windows_NT) +VERILATOR_ROOT ?= $(shell d=$$(command -v verilator 2>/dev/null); \ + [ -n "$$d" ] && cd "$$(dirname "$$d")/../share/verilator" 2>/dev/null && pwd -W 2>/dev/null) +export VERILATOR_ROOT +endif + +# ------------------------------------------------------------ toolchain ---- +# Every sim target below runs `abc`, and abc is a Python program whose shebang +# is `#!/usr/bin/env python3`. This Makefile ASSUMED that name resolves to an +# interpreter. On Windows it usually does not: `python3` and `python` on PATH +# are the Microsoft Store stubs, which print an installation hint and run +# nothing. `make sim` then reported 19 FAIL out of 19 on a healthy tree +# (measured 2026-08-12) -- and the hint that says why scrolls past inside the +# per-test output, so the summary a reader keeps is "the encoder is broken". +# +# scripts/ct_env.sh already heals all three spellings (bld/pyshim wrappers, +# ct_need_python) and locates the abc driver (ct_need_abc). Two halves use it: +# +# $(ABC) establishes the toolchain IN THE RECIPE that needs it. Every +# recipe line is its own shell, so this has to happen per line; +# $(ABC) is the single definition they all spell out. +# CT_ENV_OK a parse-time PROBE, whose only consumer is the ct-tools gate +# below. It reports; it does not repair. +# +# The probe deliberately does NOT export a repaired PATH back into make, which +# was the first version of this block and is wrong on Windows: make here is a +# NATIVE program whose PATH is `C:\...;C:\...`, while the PATH bash reports is +# `/c/...:/c/...`. Exporting the latter made make's own CreateProcess lookup +# fail -- measured 2026-08-13, `make help` died with +# process_begin: CreateProcess(NULL, awk ...) failed +# on a host where awk is right there. A fix that breaks a working target is +# not a fix. +# +# `bash -c` explicitly: ct_env.sh needs bash (BASH_SOURCE, local) and $(shell) +# is not guaranteed to use one -- on a host whose /bin/sh is dash, an implicit +# shell would fail HERE and report a toolchain problem on a healthy machine. +# stderr is kept (bld/ct_env.log) instead of printed: the diagnosis belongs to +# the target that needs the tool, not to `make help`. +CT_ENV_LOG := bld/ct_env.log +CT_ENV_OK := $(shell mkdir -p bld 2>/dev/null; \ + bash -c '. "$(CURDIR)/scripts/ct_env.sh" && ct_need_abc' \ + >/dev/null 2>$(CT_ENV_LOG) && echo ok) +ABC := . "$(CURDIR)/scripts/ct_env.sh" && ct_need_abc && abc + +# The same disease, one layer over: the twelve `check-*` drift guards each +# carried their own copy of +# +# PY=""; for c in py python3 python; do command -v "$$c" ... done; \ +# "$${PY:-python}" scripts/check_.py +# +# which tests PRESENCE, not function, and falls back to bare `python`. On +# Windows both `python3` and `python` on PATH are the Microsoft Store stub: +# present, and it runs nothing. Measured 2026-08-13 on this host with `py` +# taken off PATH: +# +# make check-xsim +# Python was not found; run without arguments to install ... +# make: *** [Makefile:476: check-xsim] Error 49 +# +# (the stub answers in the host locale -- the line above is the English wording +# of the message this host actually printed) +# +# "Error 49" from a drift guard reads as DRIFT -- a verdict about an RTL/doc +# consistency nobody checked. ct_need_python (scripts/ct_env.sh) probes the +# FUNCTION (`-c ""`), heals all three spellings via bld/pyshim, and dies with +# 78 when there is no interpreter at all. One definition, twelve users. +PY := . "$(CURDIR)/scripts/ct_env.sh" && ct_need_python && python3 + +.PHONY: rdl-soc rdl-kv260 rdl-html sim-tgc5b-soc sim-examples help rdl ct-tools sim sim-basic sim-interrupts sim-stress sim-periodic-sync sim-exceptions sim-sync-quota-bytes sim-sync-quota-msgs sim-data-basic sim-data-split sim-addr-compress sim-data-sync sim-df-workload sim-df-workload-full sim-df-drop sim-trig-regs sim-te-sync-req sim-overrun-recovery sim-hsi-csr-cap sim-combined coverage lint check-flags check-discovery check-profile-deps check-core-xlen check-xsim check-negative-legs check-micro-csr check-swwel-census check-publication check-drawio check-doc-evidence check-evidence-stamp check-sim-fmt check-orphan-gates check-sva-channel check-rdl-encode doc-check clean bld-bootstrap bld-refresh ## help: List available targets. help: @@ -30,16 +103,47 @@ help: rdl: @scripts/gen_rdl.sh +# ct-tools (internal, no help entry): the gate in front of every simulation +# target. It does not run a tool, it refuses to start when the toolchain above +# could not be established -- and it refuses in the one wording that keeps the +# two cases apart: +# +# "a test failed" -> the encoder or the testbench is wrong +# "TOOL / nothing ran" -> this machine cannot run the test at all +# +# The exit code is 78 (CT_E_TOOL, scripts/ct_env.sh), the code +# scripts/run_gates.sh reports as `TOOL ` and `make bld-bootstrap` +# already returns. make itself always exits 2 for a failed recipe, so the 78 +# is carried by make's own "Error 78" line plus the TOOL: message -- not +# silently, and never as a pass: the recipe FAILS, it does not skip. +ct-tools: +ifeq ($(CT_ENV_OK),) + @echo "TOOL: the simulation toolchain could not be established -- nothing was run." + @echo " This is NOT a test failure. scripts/ct_env.sh reports:" + @sed 's/^/ /' $(CT_ENV_LOG) 2>/dev/null || echo " (no $(CT_ENV_LOG))" + @echo " Fix the tool, or set CT_PYTHON_BIN / CT_ABC_BIN, then re-run." + @exit 78 +endif + ## rdl-soc: Regenerate the example SoC peripheral regblock from its rdl/ct_soc.rdl -## (via scripts/gen_rdl_soc.sh) -> examples/tgc5b_soc/pkg/ct_soc_regs*.sv. +## (via scripts/gen_rdl_soc.sh) -> examples/kv260/common/tgc5b/pkg/ct_soc_regs*.sv. ## Same pinned toolchain as `rdl`. Commit RDL + regenerated SV together. rdl-soc: @scripts/gen_rdl_soc.sh +## rdl-kv260: Regenerate the unified KV260 example-SoC CTRL block from +## examples/kv260/common/rdl/ct_kv260_ctrl.rdl via +## examples/kv260/common/rdl/gen_rdl_kv260.sh -> +## examples/kv260/common/ct_kv260_ctrl_regs*.sv. Same pinned +## toolchain as `rdl`. Commit RDL + regenerated SV together. +rdl-kv260: + @examples/kv260/common/rdl/gen_rdl_kv260.sh + ## rdl-html: Render the browsable HTML register reference (via ## scripts/gen_rdl_html.sh) -> bld/rdl-html/: the KV260 example-SoC -## app map (absolute devmem addresses, encoder CSRs included) and the -## bare encoder CSR map. Same pinned toolchain as `rdl`. +## app map (absolute devmem addresses, encoder CSRs included), the +## bare encoder CSR map, and the unified KV260 CTRL window +## (examples/kv260/common/rdl/). Same pinned toolchain as `rdl`. rdl-html: @scripts/gen_rdl_html.sh @@ -50,17 +154,18 @@ rdl-html: ## `make sim`. The run exits non-zero iff a normal test FAILs or an ## XFAIL test unexpectedly passes (XPASS — fix landed; promote it out ## of SIM_XFAIL). Run one test with its own `make sim-`. -SIM_ALL := basic interrupts stress periodic-sync exceptions data-basic overrun-recovery hsi-csr-cap combined -# overrun-recovery: known-failing — the soft-overflow desync drops the trailing -# Program Trace Disabled correlation message (--disabled check). Under -# investigation; remove from SIM_XFAIL once the encoder fix lands (an XPASS here -# will flag that for you). -SIM_XFAIL := overrun-recovery -# The worked integrations under examples/ — run by `make sim-examples`, kept out -# of SIM_ALL so `make sim` stays the encoder's own regression suite. -SIM_EXAMPLES := tgc5b-soc tgc5b-ps - -sim: +SIM_ALL := basic interrupts stress periodic-sync exceptions sync-quota-bytes sync-quota-msgs data-basic data-split addr-compress data-sync df-workload df-workload-full df-drop trig-regs te-sync-req overrun-recovery hsi-csr-cap combined +# Empty: every test in SIM_ALL is expected to pass. Add a name here (with a +# comment naming the defect it gates) only while an encoder fix is pending — +# the test then runs and is reported as XFAIL instead of failing the suite. +SIM_XFAIL := + +# The worked integrations under examples/ -- run by `make sim-examples`, kept +# out of SIM_ALL so `make sim` stays the encoder's own regression suite. +SIM_EXAMPLES := tgc5b-soc ddr-sink-window axis-wp-shim tgc5b2-axis-soc ctte-smoke rvcfi-units rvcfi-e2e + +sim: ct-tools + @rm -f bld/.decode_skipped @overall=0; declare -A st; xfail=" $(SIM_XFAIL) "; \ declare -A dir=( \ [basic]=instruction/01_basic \ @@ -68,7 +173,17 @@ sim: [stress]=instruction/03_stress \ [periodic-sync]=instruction/04_periodic_sync \ [exceptions]=instruction/05_exceptions \ + [sync-quota-bytes]=instruction/29_sync_quota_bytes \ + [sync-quota-msgs]=instruction/30_sync_quota_msgs \ [data-basic]=data/01_basic \ + [data-split]=data/02_split_load \ + [addr-compress]=data/03_addr_compress \ + [data-sync]=data/04_data_sync \ + [df-workload]=data/05_df_workload \ + [df-workload-full]=data/05_df_workload \ + [df-drop]=data/06_df_drop \ + [trig-regs]=instruction/32_trig_regs \ + [te-sync-req]=instruction/33_te_sync_req \ [overrun-recovery]=overflow/01_overrun_recovery \ [hsi-csr-cap]=hsi/01_csr_cap \ [combined]=combined/01_all ); \ @@ -89,8 +204,18 @@ sim: printf ' %-5s %s\n' "$${st[$$t]}" "$$sub"; \ done; \ printf '================================================================\n'; \ + skipped=0; \ + if [ -f bld/.decode_skipped ]; then \ + skipped=$$(sort -u bld/.decode_skipped | wc -l); \ + printf ' NOTE: no reference decoder -- %d test(s) SIMULATED but NOT decoded:\n' "$$skipped"; \ + sort -u bld/.decode_skipped | sed 's/^/ /'; \ + printf ' provision CTTD (py scripts/fetch_cttd.py) for a decode verdict.\n'; \ + printf '================================================================\n'; \ + fi; \ if [ $$overall -eq 0 ]; then \ - if [ -n "$(SIM_XFAIL)" ]; then \ + if [ $$skipped -gt 0 ]; then \ + printf ' RESULT: PASS (SIMULATION ONLY -- decode verdict skipped for %d test(s))\n\n' "$$skipped"; \ + elif [ -n "$(SIM_XFAIL)" ]; then \ printf ' RESULT: PASS (XFAIL, expected: %s)\n\n' "$(SIM_XFAIL)"; \ else \ printf ' RESULT: PASS\n\n'; \ @@ -100,18 +225,18 @@ sim: exit 1; \ fi -## sim-basic: tests/instruction/01_basic — sim + NexRv decode + address match. +## sim-basic: tests/instruction/01_basic — sim + CTTD decode + address match. ## Exercises instruction-trace pause/resume; trace-off emits a ## Program Trace Correlation Message (TCODE 33, EVCODE=Program ## Trace Disabled). --pc checks the PC stream, --disabled the ## trace-off message. -sim-basic: | bld - @cd bld && abc $(ABC_COV) -sim ../tests/instruction/01_basic/basic_tb.abc +sim-basic: ct-tools | bld + @cd bld && $(ABC) $(ABC_COV) -sim ../tests/instruction/01_basic/basic_tb.abc @scripts/decode_and_check.sh --pc --disabled basic_tb -## sim-interrupts: tests/instruction/02_interrupts — sim + NexRv decode + address match. -sim-interrupts: | bld - @cd bld && abc $(ABC_COV) -sim ../tests/instruction/02_interrupts/interrupts_tb.abc +## sim-interrupts: tests/instruction/02_interrupts — sim + CTTD decode + address match. +sim-interrupts: ct-tools | bld + @cd bld && $(ABC) $(ABC_COV) -sim ../tests/instruction/02_interrupts/interrupts_tb.abc @scripts/decode_and_check.sh --pc --disabled interrupts_tb ## sim-stress: tests/instruction/03_stress — instruction-trace stress. @@ -121,8 +246,8 @@ sim-interrupts: | bld ## regression gate for the branch-HIST sync-seed bug (periodic sync ## on a TAKEN branch seeded a stranded HIST bit -> "hist bits ## pending"); see the seed guard in rtl/ct_L2_msg_gen.sv. -sim-stress: | bld - @cd bld && abc $(ABC_COV) -sim ../tests/instruction/03_stress/stress_tb.abc +sim-stress: ct-tools | bld + @cd bld && $(ABC) $(ABC_COV) -sim ../tests/instruction/03_stress/stress_tb.abc @scripts/decode_and_check.sh --pc stress_tb ## sim-periodic-sync: tests/instruction/04_periodic_sync — periodic-sync HIST loss. @@ -138,11 +263,11 @@ sim-stress: | bld ## drives a 2-L + 1-BD loop (3 retires/iter) with a 16-cycle ## periodic-sync window so syncs reliably fall on a linear ## retire with Hist populated — the exact regime that exposes -## the bug on hardware (scenarios_a3 / roberts captures, where -## the trace_fs-vendored encoder pre-dates this fix). A clean +## the bug on hardware (earlier board captures taken with a +## predecessor integration that pre-dates this fix). A clean ## decode here confirms the pre-flush still fires. -sim-periodic-sync: | bld - @cd bld && abc $(ABC_COV) -sim ../tests/instruction/04_periodic_sync/periodic_sync_tb.abc +sim-periodic-sync: ct-tools | bld + @cd bld && $(ABC) $(ABC_COV) -sim ../tests/instruction/04_periodic_sync/periodic_sync_tb.abc @scripts/decode_and_check.sh --pc periodic_sync_tb ## sim-exceptions: tests/instruction/05_exceptions — synchronous exceptions, @@ -151,20 +276,138 @@ sim-periodic-sync: | bld ## are still communicated. Exercises the iretire=0 EXCEPTION_TRAP ## count_halfwords branch (uncovered by 02_interrupts, which uses ## iretire=1) and an iretire=0 exception right after a taken branch. -sim-exceptions: | bld - @cd bld && abc $(ABC_COV) -sim ../tests/instruction/05_exceptions/exceptions_tb.abc +sim-exceptions: ct-tools | bld + @cd bld && $(ABC) $(ABC_COV) -sim ../tests/instruction/05_exceptions/exceptions_tb.abc @scripts/decode_and_check.sh --pc --disabled exceptions_tb -## sim-data-basic: tests/data/01_basic — sim + NexRv data-trace check. +## sim-sync-quota-bytes: tests/instruction/29_sync_quota_bytes — byte-quota sync +## (P2). InstSyncMode=4 (TRACE_BYTES), InstSyncMax=2 -> 64-B quota +## window, driven over ALTERNATING compressibility (long linear +## runs vs. uninferable-jump storms) — exactly the workload shape +## where instruction-count sync (mode 6) gives no byte guarantee. +## --pc checks losslessness; --sync 7 the guaranteed sync floor +## (derivation in the TB header). The hard window bound +## (max distance <= 2^(Max+4) + Delta, measured on RAW ATB +## bytes — the scale the quota is defined on) is checked by +## scripts/check_sync_window.py via scripts/cli_syncquota_test.sh +## (Delta derivation documented there). +sim-sync-quota-bytes: ct-tools | bld + @cd bld && $(ABC) $(ABC_COV) -sim ../tests/instruction/29_sync_quota_bytes/sync_quota_bytes_tb.abc + @scripts/decode_and_check.sh --pc --sync 7 sync_quota_bytes_tb + +## sim-sync-quota-msgs: tests/instruction/30_sync_quota_msgs — message-quota sync +## (P2, collision design D8). InstSyncMode=1 (TRACE_MSG), Max=0 -> +## 16-message quota window, colliding with an ACT-CAP CF_SYNC and +## an (architecturally ignored, mode-gated) ATB sync request. The +## TB itself $fatals unless trTeSyncStatus.SyncReqSource reads 3 +## (SYNC_REQ_QUOTA) at test end. --pc checks losslessness; +## --sync 4 the guaranteed floor (derivation in the TB header). +sim-sync-quota-msgs: ct-tools | bld + @cd bld && $(ABC) $(ABC_COV) -sim ../tests/instruction/30_sync_quota_msgs/sync_quota_msgs_tb.abc + @scripts/decode_and_check.sh --pc --sync 4 sync_quota_msgs_tb + +## sim-data-basic: tests/data/01_basic — sim + CTTD data-trace check. ## Instruction trace is OFF in this scenario; verification ## compares the cpu_model's load/store sequence (address, -## size AND data value) against the NexRv CTXP export +## size AND data value) against the CTTD CTXP export ## (MEMREAD_n / MEMWRITE_n records). -sim-data-basic: | bld - @cd bld && abc $(ABC_COV) -sim ../tests/data/01_basic/data_basic_tb.abc +sim-data-basic: ct-tools | bld + @cd bld && $(ABC) $(ABC_COV) -sim ../tests/data/01_basic/data_basic_tb.abc @scripts/decode_and_check.sh --ctxp data_basic_tb -## sim-overrun-recovery: tests/overflow/01_overrun_recovery — sim + NexRv +## sim-data-split: tests/data/02_split_load — SPLIT_DATA_ACCESS=1 leg +## (STOREs at dretire, LOADs at lresp; pending-overwrite path). +## --pc + --data round-trip; the data oracle encodes the +## split-load contract (the lresp-less 0x8000_0300 load is +## overwritten and never emits). Not --ctxp: split-load MEM +## record values come from the TB-driven lresp data, which +## cpu_model cannot see (rationale in the TB header). +sim-data-split: ct-tools | bld + @cd bld && $(ABC) $(ABC_COV) -sim ../tests/data/02_split_load/split_load_tb.abc + @scripts/decode_and_check.sh --pc --data split_load_tb + +## sim-addr-compress: tests/data/03_addr_compress — P3 DF address XOR +## compression, data-only stream. WARL negative probes run +## in-sim ($fatal); offline: --data + --ctxp (reconstructed +## FULL addresses + values) + --sync 2 (the two 13/14 +## re-anchors count as synchronizing messages). The +## TCODE-sequence structure checks live in +## scripts/cli_dfcompress_test.sh. +sim-addr-compress: ct-tools | bld + @cd bld && $(ABC) $(ABC_COV) -sim ../tests/data/03_addr_compress/addr_compress_tb.abc + @scripts/decode_and_check.sh --data --ctxp --sync 2 addr_compress_tb + +## sim-data-sync: tests/data/04_data_sync — P3 13/14 re-anchor contract in a +## combined stream with overflow: T2(a) CF_SYNC re-anchor and +## T2(c) ERROR re-anchor, timestamps ON. Soft PC/data (the +## storm intentionally loses bytes), --overflow HARD; the hard +## first-DF-after-ERROR + subsequence + --tsmono gates run in +## scripts/cli_dfcompress_test.sh. +sim-data-sync: ct-tools | bld + @mkdir -p bld/data_sync_tb.vsim + @set -o pipefail; cd bld && $(ABC) $(ABC_COV) -sim ../tests/data/04_data_sync/data_sync_tb.abc \ + 2>&1 | tee data_sync_tb.vsim/data_sync_tb.sim.log + @scripts/decode_and_check.sh --soft --pc --data --overflow data_sync_tb + +## sim-df-workload: tests/data/05_df_workload — P3 step-6 bandwidth workload, +## XOR leg: 10 336 deterministic data accesses (sequential + +## scattered + stack mix), data-only stream, hard --data +## oracle compare. The FULL/XOR byte accounting and the +## cross-leg gates live in scripts/cli_dfworkload_test.sh. +sim-df-workload: ct-tools | bld + @cd bld && $(ABC) $(ABC_COV) -sim ../tests/data/05_df_workload/df_workload_tb.abc + @scripts/decode_and_check.sh --data df_workload_tb + +## sim-df-workload-full: tests/data/05_df_workload — the DataAddrCompress=FULL +## baseline leg of the same workload (identical access +## sequence, uncompressed DF addresses). +sim-df-workload-full: ct-tools | bld + @cd bld && $(ABC) $(ABC_COV) -sim ../tests/data/05_df_workload/df_workload_full_tb.abc + @scripts/decode_and_check.sh --data df_workload_full_tb + +## sim-df-drop: tests/data/06_df_drop — P7 data-trace drop policy +## (`trTeDataControl.DataDropEna`) + the G12 overflow status +## bits. The status contract (set / RW1C / clear-on-enable) is +## self-checking in sim ($fatal). `abc -sim` cannot pass +## plusargs, so the DROP leg is the testbench DEFAULT: this +## target verifies that the instruction trace survived the drop +## episode intact (--pc HARD — that is the whole point of the +## policy) and that the loss was announced (--overflow). The +## OFF/DROP contrast and the marker shape (ONE Error, ECODE +## 0x02, NO SYNC=7) live in scripts/cli_dfdrop_test.sh. +sim-df-drop: ct-tools | bld + @mkdir -p bld/df_drop_tb.vsim + @set -o pipefail; cd bld && $(ABC) $(ABC_COV) -sim ../tests/data/06_df_drop/df_drop_tb.abc \ + 2>&1 | tee df_drop_tb.vsim/df_drop_tb.sim.log + @scripts/decode_and_check.sh --pc --overflow df_drop_tb + +## sim-trig-regs: tests/instruction/32_trig_regs — P7 TCI trigger +## configuration registers (te 0x050/0x054/0x058). The WARL and +## "trigger does not exist" negatives are self-checking in sim +## ($fatal) and run in EVERY leg, so the testbench default (all +## trigger actions at their reset value) already exercises them; +## --pc additionally checks that the reset configuration is +## behaviourally inert. The six-leg action matrix lives in +## scripts/cli_trigregs_test.sh. +sim-trig-regs: ct-tools | bld + @cd bld && $(ABC) $(ABC_COV) -sim ../tests/instruction/32_trig_regs/trig_regs_tb.abc + @scripts/decode_and_check.sh --pc --sync 1 trig_regs_tb + +## sim-te-sync-req: tests/instruction/33_te_sync_req — P8 explicit sync +## request over the TE register (trTeControl.InstSyncReq). The +## write-1/read-0 field contract and the SyncReqSource read-backs +## are self-checking in sim ($fatal) in EVERY leg; the default +## (no request at all) is the negative leg, so --pc here checks +## that a build with the feature compiled IN traces exactly as +## before while nobody writes the bit. The ten-leg matrix +## (request, activity control, two- and three-write bursts, +## CF_SYNC collision, quota -- inside and after the window --, +## overflow) lives in scripts/cli_tesyncreq_test.sh. +sim-te-sync-req: ct-tools | bld + @cd bld && $(ABC) $(ABC_COV) -sim ../tests/instruction/33_te_sync_req/te_sync_req_tb.abc + @scripts/decode_and_check.sh --pc te_sync_req_tb + +## sim-overrun-recovery: tests/overflow/01_overrun_recovery — sim + CTTD ## decode (soft). Combined regression for the full overrun ## lifecycle: ATB stall + dense CF storm with interleaved data ## accesses triggers the composer's QueueOverrun injection; the @@ -178,9 +421,9 @@ sim-data-basic: | bld ## --overflow is HARD: the encoder MUST emit a ## NEXUS_MSG_ERROR(QueueOverrun) — otherwise the ovf_injector ## path never fired and the test is meaningless. -sim-overrun-recovery: | bld +sim-overrun-recovery: ct-tools | bld @mkdir -p bld/overrun_recovery_tb.vsim - @set -o pipefail; cd bld && abc $(ABC_COV) -sim ../tests/overflow/01_overrun_recovery/overrun_recovery_tb.abc \ + @set -o pipefail; cd bld && $(ABC) $(ABC_COV) -sim ../tests/overflow/01_overrun_recovery/overrun_recovery_tb.abc \ 2>&1 | tee overrun_recovery_tb.vsim/overrun_recovery_tb.sim.log @scripts/decode_and_check.sh --soft --pc --data --overflow --disabled overrun_recovery_tb @@ -189,18 +432,18 @@ sim-overrun-recovery: | bld ## every DAQ_* command routed to BOTH sinks (AXIS_NEXUS), plus one ## CF_SYNC (Nexus only). The AXIS beat (command + payload) is ## verified in-sim (self-checking; $fatal on mismatch). Offline: -## --ctxp : the NexRv CTXP export of the DAQ records +## --ctxp : the CTTD CTXP export of the DAQ records ## (DAQ_DATA / DAQ_COUNTER / DAQ_LAST_PC / SYNC / ## MEMx_n) matches the cpu_model's expected.ctxp. ## --sync 2 : >= 2 sync messages (startup + CF_SYNC). -sim-hsi-csr-cap: | bld - @cd bld && abc $(ABC_COV) -sim ../tests/hsi/01_csr_cap/csr_cap_tb.abc +sim-hsi-csr-cap: ct-tools | bld + @cd bld && $(ABC) $(ABC_COV) -sim ../tests/hsi/01_csr_cap/csr_cap_tb.abc @scripts/decode_and_check.sh --ctxp --sync 2 csr_cap_tb ## sim-combined: tests/combined/01_all — instruction + data + ACT-CAP sync. ## Mixed workload (linear, branch, call/return, varied ## loads/stores, ACT-CAP CF_SYNC) with the timestamp unit ON. -## One NexRv decode, five checks: +## One CTTD decode, five checks: ## --pc : reconstructed PC stream matches the model. ## --data : DataRead/DataWrite sequence matches. ## --sync 3 : >= 3 sync messages (startup + mid CF_SYNC + final). @@ -214,39 +457,41 @@ sim-hsi-csr-cap: | bld ## and the DAQ hsi/01_csr_cap tests use --ctxp. --tsmono only reads ## the per-record timestamp column, which advances regardless of ## record interleaving, so it applies here.) -sim-combined: | bld - @cd bld && abc $(ABC_COV) -sim ../tests/combined/01_all/combined_tb.abc +sim-combined: ct-tools | bld + @cd bld && $(ABC) $(ABC_COV) -sim ../tests/combined/01_all/combined_tb.abc @scripts/decode_and_check.sh --pc --data --sync 3 --disabled --tsmono combined_tb -## sim-tgc5b-soc: examples/tgc5b_soc — full SoC (MINRES TGC5B core + CEDARtools.TraceEncoder -## + RAM + timer/INTC) running the committed hello_trace program. -## Confirms the real core drives the encoder and it emits a decodable -## N-Trace synchronization message (hard check). The exact golden PC -## cross-check is reported (--soft) — see examples/tgc5b_soc/README.md. -sim-tgc5b-soc: | bld - @cp examples/tgc5b_soc/prog/hello_trace.hex examples/tgc5b_soc/prog/prog.hex - @cp examples/tgc5b_soc/prog/hello_trace.pcinfo examples/tgc5b_soc/prog/prog.pcinfo - @cd bld && abc $(ABC_COV) -sim ../examples/tgc5b_soc/test/ct_soc_tb.abc +## sim-tgc5b-soc: examples/kv260/common/tgc5b — the shared TGC5B library wired +## into a full SoC (MINRES TGC5B core + CEDARtools.TraceEncoder + RAM +## + timer/INTC) running the committed hello_trace program. This is the +## regression bench for RTL that EIGHT kv260 examples synthesise, which +## is why it outlived the tgc5b_soc example it came from. Confirms the +## real core drives the encoder and it emits a decodable N-Trace +## synchronization message (hard check). The exact golden PC +## cross-check is reported (--soft) — see +## examples/kv260/common/tgc5b/README.md. +sim-tgc5b-soc: ct-tools | bld + @cp examples/kv260/common/tgc5b/prog/hello_trace.hex examples/kv260/common/tgc5b/prog/prog.hex + @cp examples/kv260/common/tgc5b/prog/hello_trace.pcinfo examples/kv260/common/tgc5b/prog/prog.pcinfo + @cd bld && $(ABC) $(ABC_COV) -sim ../examples/kv260/common/tgc5b/test/ct_soc_tb.abc @scripts/decode_and_check.sh --sync 1 ct_soc_tb @scripts/decode_and_check.sh --soft --pc ct_soc_tb || true -## sim-tgc5b-ps: examples/tgc5b_soc/fpga/kv260 — devmem-flow simulation of the -## PS-controlled SoC (ct_soc_top). Drives the AXI4-Lite slave exactly as -## Linux devmem would: loads the program, configures + enables CEDARtools.TraceEncoder, -## starts the core, then reads the captured ATB back. Checks the -## read-back trace decodes (>=1 sync, >=1 branch-history message — -## guards against configs that degrade to sync-only traces). -sim-tgc5b-ps: | bld - @cp examples/tgc5b_soc/prog/hello_trace.hex examples/tgc5b_soc/prog/prog.hex - @cp examples/tgc5b_soc/prog/hello_trace.pcinfo examples/tgc5b_soc/prog/prog.pcinfo - @cd bld && abc $(ABC_COV) -sim ../examples/tgc5b_soc/fpga/kv260/test/ct_soc_ps_tb.abc - @scripts/decode_and_check.sh --sync 1 --hist 1 ct_soc_ps_tb - ## sim-examples: Run every worked integration under examples/ and print a -## PASS/FAIL summary — currently sim-tgc5b-soc + sim-tgc5b-ps. Needs +## PASS/FAIL summary — the list is the SIM_EXAMPLES variable above, +## not a fixed set named here: naming it twice is how the two got to +## disagree, and a line number is just a slower way to disagree. Needs ## only abc + a simulator (the program artifacts are committed, so no ## RISC-V toolchain), which is why CI runs this next to `make sim`. sim-examples: + @if [ -z "$(strip $(SIM_EXAMPLES))" ]; then \ + echo 'sim-examples: SIM_EXAMPLES is empty -- refusing to report PASS over'; \ + echo ' an empty list. That is exactly how an earlier merge produced a green'; \ + echo ' verdict for a run that executed nothing: the variable sat in a'; \ + echo ' conflicted hunk, -X ours dropped it, and a loop over nothing left'; \ + echo ' overall=0.'; \ + exit 1; \ + fi @overall=0; declare -A st; \ for t in $(SIM_EXAMPLES); do \ printf '\n===================== examples: sim-%s =====================\n' "$$t"; \ @@ -262,20 +507,13 @@ sim-examples: exit 1; \ fi -## impl-tgc5b-soc: Out-of-context Vivado synthesis of the example SoC for a -## resource/timing estimate (Kria KV260 / xck26). Needs Vivado 2022.1 -## on PATH and the vendored core; abc's part shortcuts do not include -## xck26, so select the part on the Vivado host (see the XDC header). -impl-tgc5b-soc: | bld - @cd bld && abc --vivado-version 2022.1 -netlist ../examples/tgc5b_soc/rtl/ct_soc_synth_wrap_ooc.abc - ## coverage: Re-run the whole suite under Verilator line coverage, merge every ## test's data, and print one suite-wide line-coverage rate. Also ## writes bld/coverage/: merged.info (lcov), an HTML report, and a ## shields endpoint JSON (coverage-badge.json) ready for a badge. ## The suite still runs even if a test FAILs, so the rate reflects ## whatever data was produced (failures are reported, not swallowed). -coverage: +coverage: ct-tools @$(MAKE) --no-print-directory sim ABC_COV=--coverage \ || echo " (note: a test FAILed — coverage computed from the data produced)" @scripts/coverage_report.sh $(COV_DIR) @@ -283,13 +521,366 @@ coverage: bld: @mkdir -p bld -## lint: Run verible-verilog-lint over the repo's SystemVerilog — rtl/, tests/ and -## examples/ (except vendored cores; rules in .rules.verible_lint). +## lint: Run the flag + discovery drift guards, then verible-verilog-lint +## over rtl/ and tests/ (rules in .rules.verible_lint). lint: + @$(MAKE) --no-print-directory check-flags + @$(MAKE) --no-print-directory check-discovery + @$(MAKE) --no-print-directory check-profile-deps + @$(MAKE) --no-print-directory check-core-xlen + @$(MAKE) --no-print-directory check-xsim + @$(MAKE) --no-print-directory check-negative-legs + @$(MAKE) --no-print-directory check-micro-csr + @$(MAKE) --no-print-directory check-swwel-census + @$(MAKE) --no-print-directory check-doc-evidence + @$(MAKE) --no-print-directory check-evidence-stamp + @$(MAKE) --no-print-directory check-sim-fmt + @$(MAKE) --no-print-directory check-orphan-gates + @$(MAKE) --no-print-directory check-sva-channel + @$(MAKE) --no-print-directory check-publication + @$(MAKE) --no-print-directory check-drawio @scripts/lint.sh +## check-drawio: Every doc drawing is its own editable source -- the draw.io +## XML rides inside the .drawio.png / .drawio.svg, and no sibling +## .drawio file duplicates it. Two copies of one drawing drift; +## an image exported without draw.io's -e loses the drawing while +## still looking correct. +check-drawio: + @$(PY) scripts/check_drawio_embedded.py + +## check-publication: The guards that decide whether this tree is fit to be +## PUBLISHED, as opposed to fit to be simulated. They used to hang off +## the internal CI stage-1 driver, which is why they had never run on +## a public CI: no lab addresses or credentials in a tracked file, +## English-only prose, every path a tutorial names resolves, nothing +## points a public reader at a private host or a retired repository +## name (and the version is the same everywhere it is stated, and +## every README link resolves), the vendored-CVA6 delta list matches +## what fetch.sh actually does, every SystemRDL enum a field +## declares is also assigned to it (or exporters drop its values +## silently), and the mbv CTRL map agrees with its RTL and the +## shared sink window. +## Python only -- no EDA tools, so this runs on any CI runner. +check-publication: + @$(PY) scripts/check_no_lab_internals.py + @$(PY) scripts/check_language.py + @$(PY) scripts/check_tutorial_paths.py + @$(PY) scripts/test_check_public_links.py + @$(PY) scripts/check_public_links.py + @$(PY) scripts/check_vendor_deltas.py + @$(PY) scripts/check_rdl_encode.py + @$(PY) examples/kv260/mbv/tools/check_regmap.py >/dev/null \ + && echo "[check_regmap] OK (mbv CTRL map: header vs RTL vs sink window)" \ + || { echo "[check_regmap] FAIL -- rerun: python3 examples/kv260/mbv/tools/check_regmap.py"; exit 1; } + +## check-core-xlen: CORE_XLEN declaration guard (P0-07) — every ct_encoder +## instantiation must DECLARE the attached hart's XLEN, and a +## declaration derived from the netlist's own width (directly or via +## a local parameter) must carry a waiver naming why that TIP has no +## external core. Red on a missing or hollow declaration. +check-core-xlen: + @$(PY) scripts/check_core_xlen.py + +## check-flags: Feature-flag drift guard — cross-checks the CT_EN_* switches in +## ct_pkg.sv, the RDL resets/offsets, the TCODE-58 CAPS map and the +## two documented flag tables (doc/trace-format.adoc matrix, +## doc/integration.adoc #feature-flags). Red on any drift. +check-flags: + @$(PY) scripts/check_feature_flags.py + +## check-discovery: Protocol-discovery drift guard — the protocol is a +## synthesis parameter (P9), so trTeProtocolSel.Protocol and +## trTeImpl.ProtocolMajor must stay read-only hardware mirrors: +## `sw = r; hw = w;` in the RDL, driven from EN_ETRACE in the wb +## shim, read back from hwif_in in BOTH register blocks (generated +## and CF-slim micro). Red if an RDL regen makes them writable again. +check-discovery: + @$(PY) scripts/check_protocol_discovery.py + +## check-profile-deps: Profile-dependency drift guard — every +## `CT_EN_x requires CT_EN_y` elaboration $fatal in the RTL must be +## honoured by every profile script that switches CT_EN_y off. +## Red if a new switch dependency is added without carrying it into +## the profile selectors (it would abort elaboration in scripts the +## feature author never runs). +check-profile-deps: + @$(PY) scripts/check_profile_deps.py + +## check-xsim: xsim-launch drift guard — xsim reports a failed engine start +## only in its LOG and still exits 0, so a bare call followed by +## `cp .atb.bin` silently promotes the PREVIOUS leg's dump. +## Every caller must go through ct_xsim/ct_xsim_ok (scripts/ct_env.sh). +## Red on a new bare xsim invocation. +check-xsim: + @$(PY) scripts/check_xsim_guard.py + +## check-negative-legs: compiled-out-negative bookkeeping — every build +## switch with a CT_PROFILE_NO_* RDL override must have either a +## compiled-out negative leg (`... ro`) or a WAIVED reason. Red on a +## new switch that has neither, and on a leg whose verdict marker +## disappeared. +check-negative-legs: + @$(PY) scripts/check_negative_legs.py + +## check-micro-csr: micro-CSR twin drift guard — the hand-written CF-slim +## register block (rtl/pkg/ct_cs_micro.sv, CT_MICRO_CSR) must read +## every field back at the SAME width as the generated block, and +## every register it does NOT decode needs a waiver (an elaboration +## $fatal, or a generated arm that is constant 0 anyway). Red on a +## widened field the twin did not follow — P8 widened SyncReqSource +## to three bits and the twin truncated it to two in silence. +check-micro-csr: + @$(PY) scripts/check_micro_csr_twin.py + +## check-swwel-census: Enable-lock intent guard — every CSR field the +## generated block leaves writable at trTeControl.Enable=1 must be +## named in the "Not gated (intentionally)" list of the RDL, and +## every name in that list must exist and really be ungated. The +## list used to name 10 of 31 ungated fields, so "not in the list" +## said nothing — and hid the eight trTeInstFeatures.InstEn* bits +## that both the register description and doc/integration.adoc +## declared locked (U10 F-1). +check-swwel-census: + @$(PY) scripts/check_swwel_census.py + +## check-doc-evidence: every documented resource number needs a report a +## reader can open. A doc section quoting CLB LUTs / flip-flops must +## name a utilization report under verification/evidence/**, that file must +## exist, and its numbers must be the ones in the table. Red on a +## reference into gitignored bld/ and on a table written from a +## different run than the report it names — the same defect twice, +## one commit apart (P4 audit B-1, P8 closing audit B-N2). +check-doc-evidence: + @$(PY) scripts/check_doc_evidence.py + +## check-evidence-stamp: every gate verdict under verification/evidence/** must carry a +## `# HEAD :` commit that is really in this branch's history, and a +## verdict may not be older than the RTL it judges unless a newer +## log supersedes it. Red on evidence from a rebased-away tree — +## five such logs went unnoticed until an inventory found them +## (P8 fix round). +check-evidence-stamp: + @$(PY) scripts/check_evidence_stamp.py + +## check-sim-fmt: every $$display/$$sformatf/... format argument in rtl/ and +## tests/ must be a string LITERAL. Verilator (the .abc.config +## default backend, i.e. `make sim`) does not substitute a +## non-literal format — it prints the format string itself. That is +## how every expected-PC file came to start with "0x%08x" while the +## same testbench passed under XSIM (D1-F2). +check-sim-fmt: + @$(PY) scripts/check_sim_fmt.py + +## check-orphan-gates: every cli_*_test.sh must be reachable from +## scripts/run_gates.sh, and every testbench must be named by some +## script — or be listed, WITH a reason, in the frozen orphan +## inventory of scripts/check_orphan_gates.py. A gate nobody starts +## cannot go red; that class was found by accident twice +## (P8 RC-2, D1-F6) before it was counted (V1: 9 gates, 16 tbs). +check-orphan-gates: + @$(PY) scripts/check_orphan_gates.py + +## check-sva-channel: xsim exits 0 even on $fatal, so a gate that does not read +## its simulation log cannot see an assertion fire. V1 counted 25 of +## 29 xsim gates in that state. The check now lives once, inside +## ct_xsim_ok (scripts/ct_env.sh); this guard keeps that the only +## road -- including for `xelab -R`, whose -log is elaboration only. +check-sva-channel: + @$(PY) scripts/check_sva_channel.py + +## check-rdl-encode: SystemRDL enum-encoding guard — a field that DECLARES an +## inline `enum` must also ASSIGN it (`encode = ;`). Without +## the second half the file compiles, simulates and reads back +## identically, but every exporter silently drops the value list: +## no `typedef enum` from PeakRDL-regblock, no value table from +## PeakRDL-html, `None` from `field.get_property("encode")` for +## anything walking the model. Found that way on +## sink_ctrl.pib_pattern (2026-08-24, reported from the doc repo). +## A deliberate bare type anchor is allowed if it says so: +## `// RDL-ENCODE-EXEMPT: ` above the declaration. +check-rdl-encode: + @$(PY) scripts/check_rdl_encode.py + +## doc-check: asciidoctor smoke over doc/*.adoc — build errors are red, +## warnings are printed but do not fail. Requires asciidoctor +## (not part of CI stage 1; run locally / on doc changes). +doc-check: + @AD=""; for c in asciidoctor asciidoctor.bat; do \ + command -v "$$c" >/dev/null 2>&1 && "$$c" --version >/dev/null 2>&1 && { AD="$$c"; break; }; \ + done; \ + [ -n "$$AD" ] || { echo "FAIL: no working asciidoctor on PATH"; exit 1; }; \ + fail=0; for f in doc/*.adoc; do \ + if "$$AD" --failure-level=ERROR -o /dev/null "$$f"; then \ + echo " [PASS] $$f"; \ + else \ + echo " [FAIL] $$f"; fail=1; \ + fi; \ + done; exit $$fail + ## clean: Remove generated artifacts (bld/, sim logs, etc.). clean: rm -rf bld/ @echo "[clean] removed bld/" + +## bld-bootstrap: Generate the three xsim projects every cli_*_test.sh gate +## clones (implicit_return_tb, repeated_history_tb, +## overrun_recovery_tb). bld/ is gitignored, so a fresh clone or +## `git worktree add` has none — the gates call this for themselves +## (ct_need_prj in scripts/ct_env.sh), the target is for warming a +## tree up before a long gate run. CT_PRJ_REFRESH=1 rebuilds them +## even when they exist (after a change to a project's FILE LIST). +bld-bootstrap: + @set -e; . scripts/ct_env.sh; \ + for tb in implicit_return_tb repeated_history_tb overrun_recovery_tb; do \ + ct_need_prj "$$tb" || exit $$?; \ + done; \ + echo "[bld-bootstrap] the three donor projects are in place" + +## bld-refresh: bld-bootstrap with CT_PRJ_REFRESH=1 — regenerate the donor +## projects even if they exist. Needed after a source file was added +## to or removed from one of them (the .prj pins the file LIST; its +## contents are recompiled on every run anyway). +bld-refresh: + @set -e; export CT_PRJ_REFRESH=1; . scripts/ct_env.sh; \ + for tb in implicit_return_tb repeated_history_tb overrun_recovery_tb; do \ + ct_need_prj "$$tb" || exit $$?; \ + done; \ + echo "[bld-refresh] the three donor projects were regenerated" + +# --------------------------------------------------------------------------- +# KV260 example simulations (package D3a). Appended as a block, and the only +# line touched above is SIM_EXAMPLES -- two other workers are editing this +# tree, and a target appended at the end cannot collide with a hunk in the +# middle of it. +# +# All three legs came from an internal predecessor repository, where they +# ran as PowerShell runners driving xvlog/xelab/xsim by hand. Here they are .abc graph nodes like every other +# testbench in this repository, so they run on the pinned default backend +# (.abc.config: verilator) with no runner script at all. +# +# The marker grep after each run is not decoration: `abc -sim` reports the +# SIMULATOR's exit status, and a testbench that ends early -- $finish in a +# branch that skipped the checks, a scenario that never started -- exits 0. +# The PASS marker is printed by the last line of the test sequence, so its +# ABSENCE is the only reliable statement that the sequence did not complete. +.PHONY: sim-ddr-sink-window sim-axis-wp-shim sim-tgc5b2-axis-soc sim-rvcfi-units sim-rvcfi-e2e + +## sim-ddr-sink-window: examples/kv260/common/sim — unit gate for the DDR +## sink's window guard (defect class B-C1-1): shrinking DDR_SIZE +## below the running write offset must not produce a single burst +## outside [base, base+size). Drives ct_soc_ddr_sink directly, which +## is how the tops that wire the sink themselves (rocket*, cva6_2, +## cva6_linux*) instantiate it -- they do not have the ct_trace_sinks +## register interlock. Marker: U6_WINDOW_UNIT_PASS. +sim-ddr-sink-window: ct-tools | bld + @set -o pipefail; cd bld && $(ABC) $(ABC_COV) -sim \ + ../examples/kv260/common/sim/tb_ddr_sink_window.abc 2>&1 \ + | tee tb_ddr_sink_window.simlog + @grep -q 'U6_WINDOW_UNIT_PASS' bld/tb_ddr_sink_window.simlog || { \ + echo 'sim-ddr-sink-window: FAIL — marker U6_WINDOW_UNIT_PASS missing'; \ + echo ' (the run ended without completing the test sequence:'; \ + echo ' bld/tb_ddr_sink_window.simlog)'; exit 1; } + @echo '[sim-ddr-sink-window] PASS (U6_WINDOW_UNIT_PASS)' + +## sim-axis-wp-shim: examples/kv260/tgc5b2_axis_wp/sim — unit bench of +## ct_axis_wp_shim (the AXIS watchpoint record packer), BOTH depth +## legs: FIFO_DEPTH=256 (the product default) and 16 (stress — +## frequent full/empty edges in the soak). Scenarios a..g: single +## beat, back-to-back, stall/overflow/resume, tstrb/tid into W3, +## 12k-beat randomized soak, fill_level plausibility, drop_count +## saturation. Green only if BOTH legs print their TB_PASS line. +sim-axis-wp-shim: ct-tools | bld + @set -o pipefail; cd bld && $(ABC) $(ABC_COV) -sim \ + ../examples/kv260/tgc5b2_axis_wp/sim/tb_axis_wp_shim_d256.abc 2>&1 \ + | tee tb_axis_wp_shim_d256.simlog + @set -o pipefail; cd bld && $(ABC) $(ABC_COV) -sim \ + ../examples/kv260/tgc5b2_axis_wp/sim/tb_axis_wp_shim_d16.abc 2>&1 \ + | tee tb_axis_wp_shim_d16.simlog + @for d in 256 16; do \ + grep -q "TB_PASS (tb_axis_wp_shim DEPTH=$$d)" bld/tb_axis_wp_shim_d$$d.simlog || { \ + echo "sim-axis-wp-shim: FAIL — DEPTH=$$d leg printed no TB_PASS"; \ + echo " (bld/tb_axis_wp_shim_d$$d.simlog)"; exit 1; }; \ + done + @echo '[sim-axis-wp-shim] PASS (TB_PASS for DEPTH=256 and DEPTH=16)' + +## sim-rvcfi-units: examples/kv260/tgc5b2_rvcfi -- unit + integration benches +## of the runtime-verification demo: shared URAM memory, ACT-CAP +## doorbell, console, adapter, SoC smoke. No RISC-V toolchain needed. +.PHONY: sim-rvcfi-units sim-rvcfi-e2e +sim-rvcfi-units: ct-tools | bld + @for t in tb_shared_mem tb_doorbell tb_console tb_actcap_adapter tb_rvcfi_smoke; do ( set -o pipefail; cd bld && $(ABC) $(ABC_COV) -sim ../examples/kv260/tgc5b2_rvcfi/sim/$$t.abc 2>&1 | tee $$t.simlog ) || exit 1; grep -q "TB_PASS" bld/$$t.simlog || { echo "sim-rvcfi-units: FAIL -- $$t printed no TB_PASS (bld/$$t.simlog)"; exit 1; }; done + @echo '[sim-rvcfi-units] PASS (5 benches)' + +## sim-rvcfi-e2e: the six end-to-end mode legs (both cores run the committed +## program images through the real load path) plus the analyser +## verdicts. The verdict CLAIMS are checked mechanically per mode by +## sim/run_verdicts.sh -- CLEAN where silence is the requirement, +## the intended monitor where a finding is. +sim-rvcfi-e2e: ct-tools | bld + @for t in m0 m1 m2 m3 m4 cap ddr; do ( set -o pipefail; cd bld && $(ABC) $(ABC_COV) -sim ../examples/kv260/tgc5b2_rvcfi/sim/tb_rvcfi_e2e_$$t.abc 2>&1 | tee tb_rvcfi_e2e_$$t.simlog ) || exit 1; grep -q "TB_PASS" bld/tb_rvcfi_e2e_$$t.simlog || { echo "sim-rvcfi-e2e: FAIL -- leg $$t printed no TB_PASS"; exit 1; }; done + @$(MAKE) --no-print-directory -C examples/kv260/tgc5b2_rvcfi/board/rvmon + @bash examples/kv260/tgc5b2_rvcfi/sim/run_verdicts.sh + +## sim-tgc5b2-axis-soc: examples/kv260/tgc5b2_axis_wp/sim — the watchpoint +## testbed's full chain: two TGC5B cores, each with its own encoder, +## the AXIS watchpoint shims, the L1 funnel and the three-sink +## subsystem (ring + DDR writer + PIB), driven through the AXI4-Lite +## slave exactly as Linux devmem would. Two legs, both run: +## C1a defaults — 13 real watchpoints, no timestamp checks +## C1b FULL_WP/CHECK_TS — full oracle (851 hits per core, in +## order), timestamp monotonicity + cross-core bound, and the +## negative probe (a table commit while the encoder is +## enabled must move nothing) +## Both legs also carry the DDR-sink accounting (D2) and the PIB +## calibration/beat balance (T2). Green only if BOTH legs print +## their ALL_PASS marker. This is the long one — the Verilator build +## of the two cores plus two encoders dominates its run time. +sim-tgc5b2-axis-soc: ct-tools | bld + @set -o pipefail; cd bld && $(ABC) $(ABC_COV) -sim \ + ../examples/kv260/tgc5b2_axis_wp/sim/tb_tgc5b2_axis_soc_c1a.abc 2>&1 \ + | tee tb_tgc5b2_axis_soc_c1a.simlog + @set -o pipefail; cd bld && $(ABC) $(ABC_COV) -sim \ + ../examples/kv260/tgc5b2_axis_wp/sim/tb_tgc5b2_axis_soc_c1b.abc 2>&1 \ + | tee tb_tgc5b2_axis_soc_c1b.simlog + @grep -q 'C1A_ALL_PASS' bld/tb_tgc5b2_axis_soc_c1a.simlog || { \ + echo 'sim-tgc5b2-axis-soc: FAIL — C1a leg printed no C1A_ALL_PASS'; \ + echo ' (bld/tb_tgc5b2_axis_soc_c1a.simlog)'; exit 1; } + @grep -q 'C1B_ALL_PASS' bld/tb_tgc5b2_axis_soc_c1b.simlog || { \ + echo 'sim-tgc5b2-axis-soc: FAIL — C1b leg printed no C1B_ALL_PASS'; \ + echo ' (bld/tb_tgc5b2_axis_soc_c1b.simlog)'; exit 1; } + @echo '[sim-tgc5b2-axis-soc] PASS (C1A_ALL_PASS + C1B_ALL_PASS)' + +# --------------------------------------------------------------------------- +# MicroBlaze-V example simulations (package D3b). Appended as a block for the +# same reason D3a's block was: the only line touched further up is +# SIM_EXAMPLES, and a target at the end of the file cannot collide with a hunk +# in the middle of it while other workers edit this tree. +# +# Only ONE of the nine benches migrated by D3b is wired here. The other eight +# instantiate `mbv_ctrace_soc_wrapper` -- the wrapper Vivado's make_wrapper +# generates from the `mbv_ctrace_soc` block design at build time, around the +# ENCRYPTED MicroBlaze-V core -- and, through mbv_soc_synth_wrap, the Xilinx +# XPM macro `xpm_memory_tdpram`. Neither has an in-repo .sv source, by design, +# so no Verilator path can exist for them. They are migrated, documented and +# runnable under Vivado xsim inside a generated project; the recipe and the +# measured error are in examples/kv260/{mbv,duo,trio}/sim/README.md. +.PHONY: sim-ctte-smoke + +## sim-ctte-smoke: examples/kv260/mbv/sim — the encoder ALONE (no core, no +## adapter, no Xilinx IP): ct_encoder at CORE_XLEN=32 with a quiet +## TIP and always-ready ATB/AXIS sinks, 5 us. Cheap elaboration + +## time-0 smoke, and the bisector the MBV bring-up used in 2026-07 to +## show that an xsim kernel FATAL came from the tool and not from the +## integration (that probe fires only under `abc --sim-backend xsim`; +## see the bench header). Marker: "[smoke] PASS". +sim-ctte-smoke: ct-tools | bld + @set -o pipefail; cd bld && $(ABC) $(ABC_COV) -sim \ + ../examples/kv260/mbv/sim/tb_ctte_smoke.abc 2>&1 \ + | tee tb_ctte_smoke.simlog + @grep -q '\[smoke\] PASS' bld/tb_ctte_smoke.simlog || { \ + echo 'sim-ctte-smoke: FAIL — marker "[smoke] PASS" missing'; \ + echo ' (the run ended without completing the 5 us window:'; \ + echo ' bld/tb_ctte_smoke.simlog)'; exit 1; } + @echo '[sim-ctte-smoke] PASS ([smoke] PASS)' diff --git a/README.md b/README.md index d62ac5c..ba8fd55 100644 --- a/README.md +++ b/README.md @@ -3,24 +3,43 @@ SPDX-FileCopyrightText: 2026 Accemic Technologies GmbH SPDX-License-Identifier: CC-BY-4.0 --> -> [!IMPORTANT] -> 📢 CTTE will soon be highly enhanced in functionality and integration examples. -> Expect changes in the next few days. -> [👁 Watch] the repository to get notified. - # CEDARtools.TraceEncoder -**RISC-V N-Trace encoder IP — SystemVerilog, dual-licensed.** +**Trace encoder IP for RISC-V cores — N-Trace and E-Trace, SystemVerilog, +dual-licensed.** [![License: CERN-OHL-S-2.0 OR Accemic-Commercial](https://img.shields.io/badge/license-CERN--OHL--S--2.0%20OR%20Accemic--Commercial-blue.svg)](LICENSE.md) [![REUSE compliant](https://img.shields.io/badge/REUSE-compliant-brightgreen.svg)](https://reuse.software) +[![Version 1.0.0](https://img.shields.io/badge/version-1.0.0-blue.svg)](doc/release-notes.adoc) + +> **Naming.** The product name is **CEDARtools.TraceEncoder**, abbreviated +> **CTTE**. The earlier name **C-Trace** is retired from prose but survives +> where renaming would break something outside this repository. + +## What is CEDARtools.TraceEncoder? -CEDARtools.TraceEncoder (formerly *C-Trace*) is an open-source hardware implementation of a [**RISC-V N-Trace -encoder**](https://docs.riscv.org/reference/nexus-trace/index.html). It +CEDARtools.TraceEncoder (CTTE) is an open-source hardware implementation of a +[**RISC-V N-Trace encoder**](https://docs.riscv.org/reference/nexus-trace/index.html). It ingests a core's [instruction-trace port (TIP / ITI)](https://docs.riscv.org/reference/nexus-trace/ntrace_ingress_port.html), -compresses the execution stream into [NEXUS-IEEE-ISTO-5001-2012-compliant](https://github.com/riscv-non-isa/riscv-nexus-trace/blob/main/docs/nexus-standard/IEEE-ISTO-5001-2012-v3.0.1-Nexus-Standard.pdf) -N-Trace messages, and emits them on an **ATB** (Nexus trace) output, with -an additional, uncompressed **AXI-Stream** event path for on-chip processing. +compresses the execution stream into N-Trace messages per the +[IEEE-ISTO 5001-2012 (Nexus) standard](https://github.com/riscv-non-isa/riscv-nexus-trace/blob/main/docs/nexus-standard/IEEE-ISTO-5001-2012-v3.0.1-Nexus-Standard.pdf), +and emits them on an **ATB** (Nexus trace) output, with an additional, +uncompressed **AXI-Stream** event path for on-chip processing. Conformance is +not certified by any official programme; the unimplemented optional messages +and the opt-in extensions that take the stream beyond strict N-Trace 1.0 are +listed in [`doc/trace-format.adoc`](doc/trace-format.adoc#conformance). + +A second back end produces [**E-Trace**](https://docs.riscv.org/reference/e-trace/v2.0/index.html) +(*Efficient Trace for RISC-V*) `te_inst` packets from the same internal +event stream. Which back end an encoder gets is a **synthesis parameter** +of that instance (`EN_NTRACE` / `EN_ETRACE`, defaulting to +`CT_EN_NTRACE` / `CT_EN_ETRACE` in +[`rtl/pkg/ct_pkg.sv`](rtl/pkg/ct_pkg.sv); the default is N-Trace only) — +exactly one per encoder, so a multi-encoder SoC can mix protocols in one +netlist and each encoder reports its own in the read-only +`trTeProtocolSel`. Everything ahead of the back end — filtering, +synchronization, data trace, timestamps — is protocol-agnostic and +shared. ![Overview](doc/images/ct-context.drawio.png) @@ -33,20 +52,38 @@ pipeline, the five clock domains, and the top-level IO. ## Features -- **Instruction (program) trace** — branch-history mode (HTM) with - Indirect Branch History, synchronization, program-trace correlation on - trace-off, and resource-full (ICNT / HIST overflow) handling. -- **Synchronization** — periodic, trace-enable, and CSR / quota-driven - sync requests. -- **Filtering & watchpoints** — control-flow and data-flow address - comparators and range filters. -- **Performance counters** and **timestamping** against a free-running - wall clock. -- **Overflow / overrun recovery** — queue-overrun error messages and a +- **Program trace** — both N-Trace instruction modes, branch history + (HTM, default) and branch trace (BTM), with Indirect Branch History, + program-trace correlation, and Resource Full (ICNT / HIST) handling. +- **Bandwidth optimizations** — the N-Trace chapter 9 suite (implicit + return, sequential jump, repeated history, repeat branch), plus branch + prediction (512 entries) and a jump-target cache (64 entries). +- **Synchronization** — reset, trace-enable, periodic, explicitly + requested, and quota-driven cadences that bound the re-anchor distance + by emitted messages or ATB bytes — what a live/ring consumer such as + [CEDARtools](https://accemic.com/cedartools/) needs. +- **Data trace** — read / write messages with address, size and value, + their sync variants, XOR address compression, and a shed-before-stall + drop policy. Unified or split load/store via `SPLIT_DATA_ACCESS`. +- **Filtering & watchpoints** — address, range and context comparators on + control and data flow, plus a 1023-slot indirect watchpoint table. +- **Instrumentation** — Data Acquisition messages (payload up to 192 bit) + driven by ACT-CAP / ACT-ST and routable to the ATB and/or AXIS sinks, + with per-region performance counters. +- **Timestamping** — absolute on sync, delta otherwise, against a + free-running wall clock; runtime type, prescale and width. +- **Overflow / overrun recovery** — announced loss plus re-anchor, and a FIFO-overrun resync path. -- **Output** — variable-length MDO/MSEO encoding onto a 32-bit ATB - stream, an AXIS instrumentation path, and an optional packet-aware +- **Output** — variable-length MDO/MSEO onto a 32-bit ATB port, a 96-bit + uncompressed AXIS instrumentation port, and an optional packet-aware funnel that merges up to four ATB streams. +- **E-Trace back end** — `te_inst` packets per the RISC-V Efficient Trace + specification, produced from the same internal event stream and framed + onto the same ATB output. The back end is a **per-instance synthesis + choice** (`EN_NTRACE` / `EN_ETRACE`, exactly one per encoder; a + multi-encoder SoC may mix both kinds in one netlist -- `examples/kv260/trio` + does). `trTeProtocolSel` is read-only discovery of that choice, not a + run-time switch. - **Configuration** — CSR interface generated from SystemRDL; the register map follows the [RISC-V Trace Control Interface](https://docs.riscv.org/reference/trace-control-interface/index.html) (standard `trTeControl` / `trTeImpl` component discovery and component @@ -54,20 +91,14 @@ pipeline, the five clock domains, and the top-level IO. PeakRDL-regblock natively targets **APB3/APB4**, **AXI4-Lite**, **Avalon-MM**, and **OBI** too — regenerate with a different `--cpuif`, or wrap the passthrough interface like the bundled Wishbone adapter. - -**Feature Bonus (beyond N-Trace)** - -- **Data trace** — read / write messages with address, size and data - value (plus their sync variants). Unified or split load/store data via - the `SPLIT_DATA_ACCESS` parameter. -- **Targeted for live processing** - Advanced periodic sync mechanisms - - for improved compatibility with technologies like [CEDARtools](https://accemic.com/cedartools/) -- **Lightweight instrumentation** - Data Acquisition messages driven by - ACT-CAP / ACT-ST, routable to the Nexus (ATB) and/or AXIS sinks. - -For the detail behind the CEDARtools.TraceEncoder-specific extensions, see -[`doc/enhanced-features.adoc`](doc/enhanced-features.adoc); for the -Nexus / N-Trace message formats, see +- **Scaling** — RV32 or RV64 address path (`CT_XLEN`; the E-Trace back end + is RV32 only), and per-feature `CT_EN_*` switches that omit logic *and* + the registers that would control it. + +Data trace, the DAQ / ACT instrumentation, filters, performance counters, +the AXIS port and the funnel are CTTE additions beyond N-Trace 1.0 — the +detail is in [`doc/enhanced-features.adoc`](doc/enhanced-features.adoc); +for the Nexus / N-Trace message formats, see [`doc/trace-format.adoc`](doc/trace-format.adoc). ## Quickstart @@ -83,6 +114,18 @@ Nexus / N-Trace message formats, see | Python 3 | ≥ 3.8 | Runs the pinned `make rdl` toolchain | | GNU Make | any | Umbrella commands | | Verible | latest | Lint (`make lint`) | +| [CTTD](https://github.com/accemic/CTTD) | pinned | Reference decoder for every decode verdict -- `py scripts/fetch_cttd.py` (`scripts/cttd.pin`) | + +Vivado 2022.1 is what the core simulation and gate battery are calibrated +against (`.abc.config`); the KV260 example flows under `examples/kv260/` are +verified with Vivado 2026.1 -- see `examples/README.md`, "Vivado versions". + +**Platforms and the `py` command.** The Make/abc flows are written for a +POSIX shell: Linux natively, Windows through Git Bash or MSYS2 (the +Windows-specific handling lives in the `Makefile` and `scripts/ct_env.sh`); +the Python helpers are stdlib-only. Commands in this repository's +documentation are written as `py …` — the Windows Python launcher. On Linux, +read every `py` as `python3`. **Run the tests** @@ -90,17 +133,57 @@ Nexus / N-Trace message formats, see make help # list available targets make sim # run all testbenches, print a PASS/FAIL summary make sim-basic # run a single testbench (any of the sim- targets) +make sim-examples # run the examples that have a sim leg (see below) +``` + +`make sim-examples` runs the examples that are wired into `SIM_EXAMPLES` +(the `SIM_EXAMPLES` variable in the [`Makefile`](Makefile)) — `tgc5b-soc` from +[`examples/kv260/common/tgc5b/`](examples/kv260/common/tgc5b/), plus `ddr-sink-window`, +`axis-wp-shim`, `tgc5b2-axis-soc` and `ctte-smoke` from +[`examples/kv260/`](examples/kv260/) (the shared TGC5B SoC bench, the two unit +benches of the shared sink/shim RTL, the watchpoint testbed's full chain, and +the bare-encoder probe — see +["Simulation legs of the KV260 examples"](examples/kv260/README.md)). +**Open point, now precise:** the MicroBlaze-V-based examples (`mbv`, `duo`, +`trio`) have their benches in the tree since 2026-08-18 but cannot run on the +default backend — they instantiate the Vivado block-design wrapper around the +encrypted MicroBlaze-V core, which has no in-repo source. What a re-user needs +in order to run them under `xsim` is written out in +[`examples/kv260/mbv/sim/README.md`](examples/kv260/mbv/sim/README.md). The +CVA6 and Rocket examples have no bench here at all yet. All of them are +exercised by their board gates (see +[`examples/kv260/README.md`](examples/kv260/README.md)) and by the +hardware-free dashboard demo below. + +**See it without hardware.** The fastest way to watch the encoder do real +work is the dashboard's demo mode — stdlib-only Python, no FPGA tools, no +board; it replays committed captures from real runs: + +```sh +py examples/dashboard/server.py --demo # then open http://localhost:8099 ``` +What the dashboard shows and how its demo captures were recorded is in +[`examples/dashboard/README.md`](examples/dashboard/README.md). + +The catalog of worked integrations — what exists, what each one gates, and +the KV260 board flows — is [`examples/README.md`](examples/README.md). +**Building a KV260 demo yourself**, or running a published one without Vivado, +is walked through command by command in +[`examples/kv260/TUTORIAL_build_demos.md`](examples/kv260/TUTORIAL_build_demos.md). + Either simulator can run the testbenches: `abc` drives both Vivado's `xsim` and Verilator, so only one of the two is required for simulation (Verilator is additionally needed for `make coverage`). Simulations run out of the gitignored `bld/` directory. `make sim` drives -each testbench through `abc` and checks the output against the NexRv -reference decoder (the CEDARtools.TraceEncoder port, -[accemic/NexRv-for-C-Trace](https://github.com/accemic/NexRv-for-C-Trace)) -— to run one by hand: +each testbench through `abc` and checks the output against the reference +decoder **[CTTD (CEDARtools.TraceDecoder)](https://github.com/accemic/CTTD)** +-- derived from the RISC-V Nexus Trace TG reference decoder NexRv, extended by +Accemic (E-Trace, DAQ, multi-target, CTXP export), and not committed here: +fetch the pinned build with `py scripts/fetch_cttd.py` (pin + sha256 per +platform in `scripts/cttd.pin`, whose `base_url` names where the assets are +published; details in [`bin/README.md`](bin/README.md)). To run one testbench by hand: ```sh mkdir -p bld && cd bld @@ -122,13 +205,25 @@ answer key, and the decode-and-compare loop) is described in │ └── images/ diagrams (editable .drawio.png — diagram source embedded) ├── rdl/ SystemRDL register definitions (source of truth) ├── rtl/ SystemVerilog RTL sources -│ └── pkg/ generated CSR SystemVerilog (committed; `make rdl`) +│ ├── pkg/ generated CSR SystemVerilog (committed; `make rdl`) +│ ├── adapters/ core-specific TIP ingress adapters (MicroBlaze V, CVA6 ITI, Rocket TCI, ...) │ └── /test/ per-module testbenches live next to the module ├── tests/ high-level / integration tests (multi-module) -├── examples/ worked integrations (e.g. tgc5b_soc: a RISC-V core + CEDARtools.TraceEncoder SoC) -├── scripts/ developer helpers (RDL gen, lint, decode/check, AXIS parse) -├── bin/ NexRv reference decoder (CEDARtools.TraceEncoder port — see bin/README.md) -├── .github/workflows/ CI: lint, sim (+ examples), REUSE compliance +├── formal/ SymbiYosys property gates for the emission core +├── scripts/ developer helpers (RDL gen, lint, decode/check, fetch_cttd, gate checkers) +├── tools/ host tooling (E-Trace te_inst dump/decode/compare, axis_wp_host) +├── verification/ versioned verification data: evidence/ (gate verdicts + utilization reports), +│ ref_final/ (pinned byte-neutrality reference families), corpus/ (decoder captures) +├── bin/ the FETCHED reference decoder CTTD (gitignored binaries; see bin/README.md) +├── examples/ worked integrations +│ ├── dashboard/ browser demo; replays committed captures without hardware +│ └── kv260/ nine KV260 board examples (mbv, cva6_linux/64, cva6_2, rocket_linux/2, duo, trio, +│ tgc5b2_axis_wp): fpga/ bitstream flow + fpga/prebuilt/ ready-to-load app, +│ board/ Bash board drivers, sw/; +│ common/ shared sinks + the TGC5B core/bridge/RAM library (common/tgc5b/); +│ common/board/ packaging+deploy+loader; third_party/ pinned reference cores (fetch.sh) +├── third_party/ vendored RISC-V trace-spec reference models +├── .github/workflows/ CI: lint, publication guards, dashboard tests, simulation, REUSE, formal └── LICENSES/ full text of every license used by this repo ``` @@ -136,46 +231,50 @@ answer key, and the decode-and-compare loop) is described in Full documentation lives under [`doc/`](doc/): +- **Reference Manual** — the complete CEDARtools.TraceEncoder reference + (interfaces, register map generated from the SystemRDL sources, message + catalog, core adapters, demonstrators, verification and conformance), + shipped as [PDF](doc/rm-ctte.pdf) and as a single self-contained + [HTML file](doc/rm-ctte.html). - [Architecture](doc/architecture.adoc) — block diagram, clock domains, top-level IO, pipeline stages, register-map overview. - [Trace format](doc/trace-format.adoc) — Nexus / RISC-V N-Trace compliance, message types, MDO/MSEO encoding. -- [Enhanced features](doc/enhanced-features.adoc) — the CEDARtools.TraceEncoder-specific +- [Enhanced features](doc/enhanced-features.adoc) — the CTTE-specific extensions (DAQ / ACT-CAP, filtering, sync variants, funnel, …). - [Verification](doc/verification.adoc) — the test harness and checking principle. +- [Integration](doc/integration.adoc) — the integrator-facing contract: + clocks, resets, ingress, control interface, egress, shutdown semantics. - [Development](doc/development.adoc) — build flow, RDL flow, and SoC integration. - -## Status & limitations - -The headline limitations: - -- History-mode (HTM) is the only program-trace method — traditional BTM is - intentionally omitted (bandwidth-inefficient); single-hart; no - return-stack compression. -- A known CSR-triggered-sync timestamp issue and some commented-out code - remain. - - -## Future ideas - -Larger enhancements under consideration: - -- **Self-describing trace** — emit a vendor `VENDOR_CONFIG` Nexus message - (Vendor Config, TCODE 56) carrying the encoder configuration, so a decoder - can interpret the stream without out-of-band setup. The - `trTeControl.SendConfig` control is reserved for this (today read-only - `CFG_NONE`; would select once / on-sync emission once implemented). -- **Ownership / Context message (TCODE 2)** — emit the standard - process / privilege correlation message (`scontext` / `hcontext`, - privilege mode). The control bit (`trTeControl.Context`, today reserved / - read-only) and the TIP context fields already exist; wiring up the - message enables OS-aware and multi-hart trace decode. +- [Ingress adapters](doc/adapters/README.adoc) — the core-specific TIP + adapters (AMD MicroBlaze-V, CVA6 ITI, Rocket TCI) and the trace semantics + each one maps. +- [Release notes](doc/release-notes.adoc) — current state and the + by-design limitations to read before filing a bug. + +The formal property gates for the emission core have their own writeup in +[`formal/README.md`](formal/README.md). + +## Related repositories + +CTTE is one of several public Accemic repositories that work together. The +one it *fetches from* is pinned by version **and** sha256 in `scripts/`, so a +verdict here is always taken against a known build. (The pre-built KV260 +demo apps are not fetched at all: every `examples/kv260//` carries its +own under `fpga/prebuilt/`, so a demo runs without Vivado straight from the +checkout — see the [build tutorial](examples/kv260/TUTORIAL_build_demos.md).) + +| Repository | What it is | How CTTE uses it | +|---|---|---| +| [accemic/CTTD](https://github.com/accemic/CTTD) — CEDARtools.TraceDecoder | the reference decoder: N-Trace and E-Trace, DAQ, multi-target streams, CTXP export; derived from the RISC-V Nexus Trace TG reference code (NexRv) | every decode verdict — fetched, never committed: `scripts/cttd.pin` + `py scripts/fetch_cttd.py` | +| [accemic/CTXP-format](https://github.com/accemic/CTXP-format) | the CTXP trace-export format specification | the value-aware data / DAQ checks compare CTTD's CTXP export against the model | +| [accemic/abc-flow](https://github.com/accemic/abc-flow) | `abc`, the text-file-based project / build / simulation driver | every `make sim-*` target | ## License -CEDARtools.TraceEncoder is licensed per artifact type — see [`LICENSE.md`](LICENSE.md) +CTTE is licensed per artifact type — see [`LICENSE.md`](LICENSE.md) for the full statement: - **Hardware IP** (RTL, RDL, constraints, and the SystemVerilog/`.abc` @@ -185,7 +284,7 @@ for the full statement: - **Software** (scripts, build, CI, config) is **ISC**. - **Documentation** (Markdown, AsciiDoc, images) is **CC-BY-4.0**. - **Third-party IP** — the MINRES TGC5B core vendored for the example SoC - (`examples/tgc5b_soc/cpu/`) is dual-licensed by **MINRES Technologies + (`examples/kv260/common/tgc5b/cpu/`) is dual-licensed by **MINRES Technologies GmbH** under the same open arm — `CERN-OHL-S-2.0 OR LicenseRef-MINRES-Commercial`. A commercial license for the core comes from MINRES, not Accemic. @@ -198,23 +297,34 @@ what. ## Trademarks -RISC-V is a trademark of RISC-V International; Arm, AMBA and CoreSight -are trademarks of Arm Limited (or its subsidiaries or affiliates); Xilinx -and Vivado are trademarks of AMD; MINRES is a registered trademark of -MINRES Technologies GmbH. AXI, AXI-Stream and ATB are protocol names -defined in the Arm AMBA specifications. These and any other third-party -marks are used descriptively to identify the relevant specifications, -interfaces, and tools, and do not imply endorsement. See -[`TRADEMARKS.md`](TRADEMARKS.md). +CEDARtools and Accemic are trademarks of the Accemic Technologies GmbH. + +RISC-V, RISC-V International, and the RISC-V logos are trademarks of RISC-V +International. Accemic is not a member of RISC-V International: the mark is +used here only descriptively, to name the architecture and the specifications +this encoder targets. + +MicroBlaze, Vivado, Xilinx and Kria are trademarks of Advanced Micro Devices, +Inc. Arm, AMBA, AXI, ATB and CoreSight are trademarks or registered trademarks +of Arm Limited (or its affiliates). + +All other product names, logos, and brands are the property of their +respective owners and are used here for identification purposes only; such use +does not imply affiliation with, sponsorship by, or endorsement from their +respective owners. See [`TRADEMARKS.md`](TRADEMARKS.md). ## Contributing See [`CONTRIBUTING.md`](CONTRIBUTING.md). Contributions require a CLA so -that the project can continue to be offered under both licenses. +that the project can continue to be offered under both licenses. The +maintainers are listed in [`MAINTAINERS.md`](MAINTAINERS.md); security +issues go the way [`SECURITY.md`](SECURITY.md) describes, not through the +public issue tracker. To cite CTTE, use [`CITATION.cff`](CITATION.cff). ## References -- RISC-V N-Trace specification — +- RISC-V E-Trace (Efficient Trace for RISC-V) specification v2.0 — +- RISC-V N-Trace specification — - RISC-V Trace Control Interface Specification v1.0 — - IEEE-ISTO 5001-2012 (Nexus) standard v3.0.1 — [IEEE-ISTO-5001-2012-v3.0.1-Nexus-Standard.pdf](https://github.com/riscv-non-isa/riscv-nexus-trace/blob/main/docs/nexus-standard/IEEE-ISTO-5001-2012-v3.0.1-Nexus-Standard.pdf) - REUSE Software (SPDX compliance) — diff --git a/REUSE.toml b/REUSE.toml index 4db0d32..35c8ee6 100644 --- a/REUSE.toml +++ b/REUSE.toml @@ -6,60 +6,377 @@ version = 1 SPDX-PackageName = "CEDARtools.TraceEncoder" +SPDX-PackageVersion = "1.0.0" SPDX-PackageSupplier = "Accemic Technologies GmbH " SPDX-PackageDownloadLocation = "https://github.com/accemic/TraceEncoder" [[annotations]] -path = ["VERSION", "**/.gitkeep"] +path = ["VERSION", "**/.gitkeep", "**/.gitignore"] precedence = "aggregate" SPDX-FileCopyrightText = "2026 Accemic Technologies GmbH" SPDX-License-Identifier = "ISC" -# Vendored NexRv reference decoder binary. Built from the CEDARtools.TraceEncoder port -# at https://github.com/accemic/NexRv-for-C-Trace, derived from the IAR -# Systems NexRv tool and licensed under ISC; Accemic's modifications are -# likewise ISC. The binary carries no in-file SPDX header, so the -# copyright and license are recorded here. -[[annotations]] -path = "bin/NexRv" -precedence = "aggregate" -SPDX-FileCopyrightText = ["2020 IAR Systems AB", "2026 Accemic Technologies GmbH"] -SPDX-License-Identifier = "ISC" +# Verible lint rule files: a list of +rule / -rule lines with # comments. +# They carry no SPDX header of their own, so the license is recorded here. -# Verible lint rule files. The format is a bare list of +rule / -rule -# lines and doesn't accept in-file comments without risking parser -# rejection, so license info lives here. [[annotations]] path = "**/.rules.verible_lint" precedence = "aggregate" SPDX-FileCopyrightText = "2026 Accemic Technologies GmbH" SPDX-License-Identifier = "ISC" -# Documentation images. PNG/SVG exports are binary/opaque and carry no -# in-file header (the editable .drawio sources do). License info lives here. +# Documentation images. Each `.drawio.png` IS its own editable source: the +# draw.io XML rides in a PNG text chunk, so opening the PNG in draw.io recovers +# the drawing. There is deliberately no sibling `.drawio` file -- two copies of +# one drawing drift, and the guard scripts/check_drawio_embedded.py (part of +# `make lint`) keeps it that way. No SPDX header survives a draw.io round-trip +# in any of these formats, so the license info lives here. [[annotations]] path = ["doc/images/*.png", "doc/images/*.svg"] precedence = "aggregate" SPDX-FileCopyrightText = "2026 Accemic Technologies GmbH" SPDX-License-Identifier = "CC-BY-4.0" -# Kria app manifest (JSON cannot carry an in-file SPDX comment). +# The Reference Manual, rendered from its AsciiDoc sources (maintained in +# Accemic's documentation repository) and shipped here as a PDF and a single +# self-contained HTML file. Build products carry no SPDX header of their own, +# and the legal chapter they render quotes SPDX expressions as text -- hence +# "override": this block is their whole declaration, the file is not parsed. [[annotations]] -path = "examples/tgc5b_soc/fpga/kv260/shell.json" +path = ["doc/rm-ctte.pdf", "doc/rm-ctte.html"] +precedence = "override" +SPDX-FileCopyrightText = "2026 Accemic Technologies GmbH" +SPDX-License-Identifier = "CC-BY-4.0" + +# Reference vectors and regression corpora: byte-exact input and expected +# data (trace captures, program descriptions, oracle PC streams, archived +# decoder captures). They have no comment syntax that could carry a header. +[[annotations]] +path = ["tests/etrace/vectors/*", "tests/overflow/**/*.u32", "verification/corpus/*.tar.gz", + "examples/kv260/*/board/refs/*"] precedence = "aggregate" SPDX-FileCopyrightText = "2026 Accemic Technologies GmbH" -SPDX-License-Identifier = "ISC" +SPDX-License-Identifier = "CERN-OHL-S-2.0 OR LicenseRef-Accemic-Commercial" + +# Pre-built KV260 demo apps: the bitstream (`.bit.bin`), its device-tree +# overlay, `shell.json`, the per-file `MANIFEST.sha256` and, for the Linux +# demos, `BOARD_SETUP.txt` -- extracted verbatim from the board-gated bundle +# series recorded in scripts/demo.pin. A bitstream is the built product of +# the Hardware IP and carries its license; the third-party cores compiled +# into it are licensed as stated in each example's README. The set is +# frozen by its manifest, so nothing in it can take a header. +[[annotations]] +path = "examples/kv260/*/fpga/prebuilt/*/**" +precedence = "aggregate" +SPDX-FileCopyrightText = "2026 Accemic Technologies GmbH" +SPDX-License-Identifier = "CERN-OHL-S-2.0 OR LicenseRef-Accemic-Commercial" + +# Reference states of the register image (CAPS words and their derivation +# table). Same class as the regression corpora above: byte-exact expected +# data with no comment syntax that could carry a header. +[[annotations]] +path = ["verification/ref_final/*.txt", "verification/ref_final/*.tsv"] +precedence = "aggregate" +SPDX-FileCopyrightText = "2026 Accemic Technologies GmbH" +SPDX-License-Identifier = "CERN-OHL-S-2.0 OR LicenseRef-Accemic-Commercial" + +# Gate evidence: run logs and Vivado utilization/timing reports of the +# CTTE design, kept verbatim as the measurement record behind the gate +# verdicts. They are machine output and are not edited after the run, so +# they carry no in-file header; the copyright and license recorded here +# cover Accemic's contribution (the design under measurement and the +# measurement itself). The Vivado reports additionally carry the tool +# vendor's banner in their first line, which stays untouched. +[[annotations]] +path = ["verification/evidence/**/*.log", "verification/evidence/**/*.rpt"] +precedence = "aggregate" +SPDX-FileCopyrightText = "2026 Accemic Technologies GmbH" +SPDX-License-Identifier = "CERN-OHL-S-2.0 OR LicenseRef-Accemic-Commercial" + +# Vendored subset of the RISC-V trace specification's reference flow +# (https://github.com/riscv-non-isa/riscv-trace-spec). The Python models +# carry their own BSD-2-Clause headers; the two files below do not. +[[annotations]] +path = ["third_party/riscv-trace-spec-ref/README.md", + "third_party/riscv-trace-spec-ref/scripts/common/__init__.py"] +precedence = "aggregate" +SPDX-FileCopyrightText = "2019-2021 Siemens" +SPDX-License-Identifier = "BSD-2-Clause" + +# The upstream repository's own licence document, kept verbatim for +# provenance and renamed from LICENSE: it carries the CC-BY-4.0 legal code, +# which upstream applies to the trace SPECIFICATION -- not to the Python +# models vendored next to it, which are BSD-2-Clause (see the README there). +# Under the old name it read like the licence of this directory's code and +# was skipped by `reuse` on top of that, so the contradiction stayed +# invisible. The annotation below records the document's own origin. +[[annotations]] +path = "third_party/riscv-trace-spec-ref/UPSTREAM-SPEC-LICENSE-CC-BY-4.0.txt" +precedence = "aggregate" +SPDX-FileCopyrightText = "Creative Commons Corporation" +SPDX-License-Identifier = "CC-BY-4.0" # Prebuilt program artifacts for the TGC5B example SoC. Generated from the # hardware-IP-licensed prog/src (crt0.S + main.c, via prog/src/build.sh); -# these data files (readmemh image, NexRv pcinfo, disassembly) carry no in-file -# header, so the license — inherited from the source — is recorded here. +# these data files (readmemh image, pcinfo, disassembly) carry no in-file +# header, so the license -- inherited from the source -- is recorded here. +[[annotations]] +path = [ + "examples/kv260/common/tgc5b/prog/hello_trace.hex", + "examples/kv260/common/tgc5b/prog/hello_trace.pcinfo", + "examples/kv260/common/tgc5b/prog/hello_trace.dis", +] +precedence = "aggregate" +SPDX-FileCopyrightText = "2026 Accemic Technologies GmbH" +SPDX-License-Identifier = "CERN-OHL-S-2.0 OR LicenseRef-Accemic-Commercial" + +# --------------------------------------------------------------------------- +# Artefact classes introduced by the consolidation into this repository: rule ONCE per +# class with directory globs, so files arriving with later migration steps are +# covered by the class, not by chasing individual paths. + +# Demo capture data for the dashboard's hardware-free demo mode: recorded +# trace streams plus the instruction maps and symbol tables to decode them. +# The demo dataset, split BY PROVENANCE (maintainer decision, 2026-08-19). +# +# It used to be one blanket claim -- everything under demo/ as "2026 Accemic, +# CC-BY-4.0". A licence audit pointed out what that swept up: the console +# captures carry OpenSBI's banner and Linux's boot messages, and the .pcinfo +# listings are disassemblies of OpenSBI. Claiming copyright in someone else's +# program output, and licensing it out, is not a small inaccuracy -- it is the +# kind a reviewer finds first. +# +# The split below follows what each file actually IS. + +# 1. Recordings: what our hardware measured. Trace byte streams and the raw +# console ring dumps they came from. These are measurements -- facts about +# a run, with no authorship to assert. CC0 says exactly that, instead of +# claiming a copyright and then licensing it back out. +[[annotations]] +path = ["examples/dashboard/demo/*.bin", "examples/dashboard/demo/raw/*.bin"] +precedence = "aggregate" +SPDX-FileCopyrightText = "2026 Accemic Technologies GmbH" +SPDX-License-Identifier = "CC0-1.0" + +# 2. Console transcripts: the guests' own output, cleaned of capture +# artefacts only (see make_demo_console.py). The text is OpenSBI's and +# Linux's, not ours; what is ours is the recording. CC0 again -- and the +# copyright line names the upstreams, because they wrote what you read. +[[annotations]] +path = ["examples/dashboard/demo/console_*.txt"] +precedence = "aggregate" +SPDX-FileCopyrightText = ["2026 Accemic Technologies GmbH (recording)", "OpenSBI contributors", "Linux kernel contributors"] +SPDX-License-Identifier = "CC0-1.0" + +# 3a. Listings of the OPENSBI firmware images the Linux guests ran. A +# disassembly is a derived work of the program it describes, so it +# carries that program's licence -- OpenSBI is BSD-2-Clause. The symbol +# and site maps of the same firmware are the same class. +# +# NAMED INDIVIDUALLY ON PURPOSE. The first version of this split used +# `demo/*.pcinfo`, which swept in mbv.pcinfo and tgc.pcinfo -- listings of +# our own and MINRES' bare-metal programs, which have nothing to do with +# OpenSBI. A glob that is convenient today mislabels the file someone +# adds tomorrow; a new listing should have to be classified, not +# absorbed. [[annotations]] path = [ - "examples/tgc5b_soc/prog/hello_trace.hex", - "examples/tgc5b_soc/prog/hello_trace.pcinfo", - "examples/tgc5b_soc/prog/hello_trace.dis", + "examples/dashboard/demo/cva6_linux.pcinfo", + "examples/dashboard/demo/cva6_linux64.pcinfo", + "examples/dashboard/demo/rocket64.pcinfo", + "examples/dashboard/demo/rocket2.pcinfo", + "examples/dashboard/demo/symbols_sbi.map", + "examples/dashboard/demo/sites_sbi.map", ] precedence = "aggregate" +SPDX-FileCopyrightText = "OpenSBI contributors" +SPDX-License-Identifier = "BSD-2-Clause" + +# 3b. Listing of our own MicroBlaze V bare-metal program (trace_test), and of +# the TGC5B example program. Both are Accemic sources; the listings +# inherit from them, exactly as examples/kv260/common/tgc5b/prog/ does above. +[[annotations]] +path = ["examples/dashboard/demo/mbv.pcinfo", "examples/dashboard/demo/tgc.pcinfo"] +precedence = "aggregate" +SPDX-FileCopyrightText = "2026 Accemic Technologies GmbH" +SPDX-License-Identifier = "CERN-OHL-S-2.0 OR LicenseRef-Accemic-Commercial" + +# 4. Everything else in demo/: our own program images and symbol maps, the +# dataset README. hello_trace.hex is a copy of the TGC5B example program +# and follows its source; see demo/README.md. +[[annotations]] +path = ["examples/dashboard/demo/*.elf", "examples/dashboard/demo/symbols_mbv.map", "examples/dashboard/demo/README.md"] +precedence = "aggregate" +SPDX-FileCopyrightText = "2026 Accemic Technologies GmbH" +SPDX-License-Identifier = "CC-BY-4.0" + +# hello_trace.hex is a copy of examples/kv260/common/tgc5b/prog/hello_trace.hex and +# follows its source. The program is ACCEMIC's (see prog/src/crt0.S and +# main.c) -- it merely runs ON the MINRES core; the core's licence is not the +# program's. Checked 2026-08-19, because the first draft of this split got it +# backwards. +[[annotations]] +path = ["examples/dashboard/demo/hello_trace.hex"] +precedence = "aggregate" SPDX-FileCopyrightText = "2026 Accemic Technologies GmbH" SPDX-License-Identifier = "CERN-OHL-S-2.0 OR LicenseRef-Accemic-Commercial" + +# Tool/scenario configuration in JSON (cannot carry an in-file SPDX comment). +[[annotations]] +path = ["examples/dashboard/*.json", "examples/dashboard/devtools/**/*.json"] +precedence = "aggregate" +SPDX-FileCopyrightText = "2026 Accemic Technologies GmbH" +SPDX-License-Identifier = "ISC" + +# Diagram sources and exports (draw.io); documentation-class artefacts. +[[annotations]] +path = ["examples/dashboard/devtools/*.drawio", "examples/dashboard/devtools/*.drawio.svg"] +precedence = "aggregate" +SPDX-FileCopyrightText = "2026 Accemic Technologies GmbH" +SPDX-License-Identifier = "CC-BY-4.0" + +# Adapter characterisation vectors (CSV truth tables): the measured record of +# what each core's trace port emits, i.e. specification-level documentation. +[[annotations]] +path = ["doc/adapters/*.csv"] +precedence = "aggregate" +SPDX-FileCopyrightText = "2026 Accemic Technologies GmbH" +SPDX-License-Identifier = "CC-BY-4.0" + +# Company logo shipped with the dashboard page (maintainer decision, 2026-08-19). +# +# It was CC-BY-4.0, and CC-BY expressly permits adaptations -- of a logo, +# which is the one thing a trade mark may not undergo. That put the file in +# direct conflict with TRADEMARKS.md in the same repository. A mark is never +# part of an open-source grant anyway; the usual answer, and the one Linux, +# Mozilla and Rust all use, is a separate trade-mark permission. That is what +# LicenseRef-Accemic-Trademark is: use it unaltered to identify Accemic +# products, do not modify it, do not use it as a badge of origin for anything +# else. The rest of the repository stays exactly as open as it was. +[[annotations]] +path = ["examples/dashboard/logo_acctech.svg"] +precedence = "aggregate" +SPDX-FileCopyrightText = "2026 Accemic Technologies GmbH" +SPDX-License-Identifier = "LicenseRef-Accemic-Trademark" + +# Adapter unit-test stimulus vectors (.vec): data files consumed by the +# itype-decoder testbenches, same class as the CSV truth tables. +[[annotations]] +path = ["rtl/adapters/*/test/*.vec"] +precedence = "aggregate" +SPDX-FileCopyrightText = "2026 Accemic Technologies GmbH" +SPDX-License-Identifier = "CERN-OHL-S-2.0 OR LicenseRef-Accemic-Commercial" + +# Prebuilt program artifacts for the tgc5b2_axis_wp example, same class as the +# common/tgc5b prog/ artifacts above: generated from the hardware-IP-licensed +# sw sources by its own pipeline (gen_program.py; regenerated and diffed +# byte-identical during the migration into this repository), no in-file header possible. +[[annotations]] +path = ["examples/kv260/tgc5b2_axis_wp/sw/axis_wp_demo.dis", + "examples/kv260/tgc5b2_axis_wp/sw/axis_wp_demo.hex", + "examples/kv260/tgc5b2_axis_wp/sw/axis_wp_demo.pcinfo", + "examples/kv260/tgc5b2_axis_wp/sw/axis_wp_demo_sites.map", + "examples/kv260/tgc5b2_axis_wp/sw/axis_wp_demo_symbols.map"] +precedence = "aggregate" +SPDX-FileCopyrightText = "2026 Accemic Technologies GmbH" +SPDX-License-Identifier = "CERN-OHL-S-2.0 OR LicenseRef-Accemic-Commercial" + +# Buildroot/kernel configuration fragments for the cva6_2 AMP guest. A +# defconfig is consumed by the kernel build verbatim and a comment line in the +# wrong place changes what it selects, so the licence is recorded here. +[[annotations]] +path = ["examples/kv260/cva6_2/sw/cva6_2_kv260_rv64_defconfig", + "examples/kv260/cva6_2/sw/cva6_2_rv64.config"] +precedence = "aggregate" +SPDX-FileCopyrightText = "2026 Accemic Technologies GmbH" +SPDX-License-Identifier = "CERN-OHL-S-2.0 OR LicenseRef-Accemic-Commercial" + +# Prebuilt trio branch-test payload, same class as the tgc5b2_axis_wp sw +# artifacts above: compiled from this example's own sources and committed so +# the demo runs without a RISC-V toolchain. Binaries carry no header. +[[annotations]] +path = ["examples/kv260/trio/sw/build/branch_test.bin", + "examples/kv260/trio/sw/build/branch_test.elf"] +precedence = "aggregate" +SPDX-FileCopyrightText = "2026 Accemic Technologies GmbH" +SPDX-License-Identifier = "CERN-OHL-S-2.0 OR LicenseRef-Accemic-Commercial" + +[[annotations]] +path = "examples/kv260/common/board/shell.json" +precedence = "aggregate" +SPDX-FileCopyrightText = "2026 Accemic Technologies GmbH" +SPDX-License-Identifier = "ISC" + +[[annotations]] +# Delta patches against the pinned upstream CVA6 (Solderpad); the patches +# carry the same licence as the files they modify (CVA6_PIN.md documents +# each delta and its upstream-worthiness). +path = "examples/kv260/third_party/patches/cva6/*.patch" +precedence = "aggregate" +SPDX-FileCopyrightText = "2026 Accemic Technologies GmbH" +SPDX-License-Identifier = "Apache-2.0 WITH SHL-2.0" + +# --------------------------------------------------------------------------- +# Vendored Rocket reference generat (maintainer decision, 2026-08-19) +# +# `system-nexys-video.v` is FIRRTL output of the vivado-risc-v flow around +# rocket-chip -- 8.8 MB of machine-written Verilog per variant, with no +# in-file header and no sensible place to put one. It is committed because +# there is no fetch path for it and the recipe to regenerate it needs patches +# this repository does not carry; without it, `rocket_linux` and `rocket2` +# are unbuildable for anyone who does not already have the file. +# +# The generat mixes three upstreams, and the SPDX expression says so instead +# of picking the most convenient one: rocket-chip is BSD-3-Clause (Regents of +# the University of California) and Apache-2.0 (SiFive), the JTAG parts carry +# the chisel-jtag terms (BSD-3-Clause in substance), and the surrounding +# vivado-risc-v flow is MIT. The upstream licence texts sit next to the file +# as LICENSE.Berkeley, LICENSE.SiFive, LICENSE.jtag and +# LICENSE.vivado-risc-v.md, exactly as they were delivered. +[[annotations]] +path = [ + "examples/kv260/third_party/rocket_ref/system-nexys-video.v", + "examples/kv260/third_party/rocket_ref/rocket64t2/system-nexys-video.v", +] +precedence = "aggregate" +SPDX-FileCopyrightText = ["2012-2014 The Regents of the University of California", "SiFive, Inc.", "2021-2025 Eugene Tarassov"] +SPDX-License-Identifier = "BSD-3-Clause AND Apache-2.0 AND MIT" + +# The upstream licence texts, delivered with the generat and left byte-identical. +[[annotations]] +path = [ + "examples/kv260/third_party/rocket_ref/LICENSE.Berkeley", + "examples/kv260/third_party/rocket_ref/LICENSE.SiFive", + "examples/kv260/third_party/rocket_ref/LICENSE.jtag", + "examples/kv260/third_party/rocket_ref/LICENSE.vivado-risc-v.md", +] +precedence = "aggregate" +SPDX-FileCopyrightText = ["2012-2016 The Regents of the University of California", "SiFive, Inc.", "2021-2025 Eugene Tarassov"] +SPDX-License-Identifier = "BSD-3-Clause AND Apache-2.0 AND MIT" + +# The rvcfi demo's generated program images, watchpoint tables and site maps +# (examples/kv260/tgc5b2_rvcfi/sw/, produced by build.sh / gen_sites.py from +# the ISC sources next to them; the programs are -nostdlib, so the images hold +# our code plus libgcc's runtime routines under GCC's runtime exception). +# NAMED INDIVIDUALLY, like the demo listings above: the malloc demo under +# sw/malloc/ links newlib and does NOT commit its images for that reason. +[[annotations]] +path = [ + "examples/kv260/tgc5b2_rvcfi/sw/rvcfi_core0.hex", + "examples/kv260/tgc5b2_rvcfi/sw/rvcfi_core0.dis", + "examples/kv260/tgc5b2_rvcfi/sw/rvcfi_core0.sym", + "examples/kv260/tgc5b2_rvcfi/sw/rvcfi_core1.hex", + "examples/kv260/tgc5b2_rvcfi/sw/rvcfi_core1.dis", + "examples/kv260/tgc5b2_rvcfi/sw/rvcfi_core1.sym", + "examples/kv260/tgc5b2_rvcfi/sw/sites_core0.csv", + "examples/kv260/tgc5b2_rvcfi/sw/sites_core1.csv", + "examples/kv260/tgc5b2_rvcfi/sw/sites_meta_core0.json", + "examples/kv260/tgc5b2_rvcfi/sw/sites_meta_core1.json", + "examples/kv260/tgc5b2_rvcfi/sw/wp_table_core0_full.txt", + "examples/kv260/tgc5b2_rvcfi/sw/wp_table_core0_hot.txt", + "examples/kv260/tgc5b2_rvcfi/sw/wp_table_core1_full.txt", + "examples/kv260/tgc5b2_rvcfi/sw/wp_table_core1_hot.txt", +] +precedence = "aggregate" +SPDX-FileCopyrightText = "2026 Accemic Technologies GmbH" +SPDX-License-Identifier = "ISC" diff --git a/SECURITY.md b/SECURITY.md new file mode 100644 index 0000000..6eb4f82 --- /dev/null +++ b/SECURITY.md @@ -0,0 +1,42 @@ + + +# Security policy + +CEDARtools.TraceEncoder is hardware IP plus the scripts, tools and a browser +dashboard that exercise it. A security issue here is most likely one of: + +- a decoder or tool that can be made to misbehave by crafted trace bytes + (the reference decoder itself is a separate project, + [accemic/CTTD](https://github.com/accemic/CTTD) — report decoder issues there); +- the dashboard (`examples/dashboard/`), which serves a board's registers and + captures over HTTP and is meant for a trusted lab network, not the internet; +- the board scripts under `examples/kv260/*/board/`, which run with `sudo` on + the board. + +## Reporting + +Please **do not** open a public issue for a vulnerability. Send a report to + (the same address [`MAINTAINERS.md`](MAINTAINERS.md) lists +for security disclosures) with: + +- the affected file or component and the version / commit; +- what an attacker can do, and how to reproduce it; +- whether you want to be credited. + +You will get an acknowledgement within a few working days. Fixes ship as a +normal release with a note in [`doc/release-notes.adoc`](doc/release-notes.adoc); +the reporter is credited there unless they ask not to be. + +## Scope notes + +- The `bin/` decoder is **fetched**, never committed, and pinned by sha256 + (`scripts/cttd.pin`). A checksum mismatch is a hard error by design; if you + see one on a fresh download, report it — do not work around it. +- The pre-built KV260 apps under `examples/kv260//fpga/prebuilt/` are + tracked and verified by their own `MANIFEST.sha256`; the bundle series they + were extracted from is recorded in `scripts/demo.pin`. +- Published KV260 bitstreams are built from the sources in this repository; + the build recipe is `examples/kv260/TUTORIAL_build_demos.md`. diff --git a/TRADEMARKS.md b/TRADEMARKS.md index 4fdca21..2fe5751 100644 --- a/TRADEMARKS.md +++ b/TRADEMARKS.md @@ -11,28 +11,65 @@ documentation identifies the project's origin; it does not grant any trademark rights beyond what the licenses in [`LICENSE.md`](LICENSE.md) state. +**The Accemic logo shipped with the dashboard** +(`examples/dashboard/logo_acctech.svg`) carries a trade-mark permission of +its own, +[`LICENSES/LicenseRef-Accemic-Trademark.txt`](LICENSES/LicenseRef-Accemic-Trademark.txt): +reproduce it unaltered to identify Accemic products, do not modify it, do not +use it as a badge of origin for anything else. It was previously offered +under CC-BY-4.0, which expressly permits adaptations -- of a mark, which is +the one thing that must not be adapted, and which this page relies on not +being adapted. Corrected 2026-08-19. Nothing else in the repository changed: +a mark is never part of an open-source grant, and separating the two is what +projects with a name worth protecting do. + This project implements and references several open specifications and -interoperates with third-party tools. The following trademarks are the -property of their respective owners and are used here **only -descriptively**, to identify those specifications, interfaces, and -tools. Their use does **not** imply any affiliation with, sponsorship -by, or endorsement by the trademark owners. - -| Mark | Owner | -|------|-------| -| RISC-V, RISC-V International, and the RISC-V logo | RISC-V International | -| Arm, AMBA, CoreSight | Arm Limited (or its subsidiaries or affiliates) | -| Xilinx, Vivado | Advanced Micro Devices, Inc. (AMD) | -| IEEE-ISTO 5001, Nexus 5001 Forum | IEEE Industry Standards and Technology Organization (IEEE-ISTO) | -| IAR, IAR Systems | IAR Systems AB | -| MINRES | MINRES Technologies GmbH | - -"RISC-V" is always written in block letters with a hyphen, per the -RISC-V International branding guidelines. - -MINRES Technologies GmbH is the licensor of the TGC5B core vendored under -`examples/tgc5b_soc/cpu/` (see [`LICENSE.md`](LICENSE.md)). Its name and -the TGC5B designation appear here only to identify that core and to -retain the notices CERN-OHL-S-2.0 requires (§3.1) — a factual use that -implies no endorsement or involvement by MINRES, as §8.2 of that license -requires. \ No newline at end of file +interoperates with third-party tools. Third-party marks appear here **only +descriptively**, to identify those specifications, interfaces and tools +(nominative use). Their use does **not** imply any affiliation with, +sponsorship by, or endorsement by the trademark owners. + +## Attribution + +CEDARtools and Accemic are trademarks of the Accemic Technologies GmbH. + +RISC-V, RISC-V International, and the RISC-V logos are trademarks of RISC-V +International. + +MicroBlaze, Vivado, Xilinx and Kria are trademarks of Advanced Micro Devices, +Inc. + +Arm, AMBA, AXI, ATB and CoreSight are trademarks or registered trademarks of +Arm Limited (or its affiliates). + +Nexus and IEEE-ISTO 5001 are marks of the IEEE Industry Standards and +Technology Organization (IEEE-ISTO) / Nexus 5001 Forum. + +IAR and IAR Systems are trademarks of IAR Systems AB. + +All other product names, logos, and brands are the property of their +respective owners and are used in this document for identification purposes +only; such use does not imply affiliation with, sponsorship by, or endorsement +from their respective owners. + +## Use of the RISC-V mark + +Accemic Technologies GmbH is **not** a member of RISC-V International. The +mark therefore appears in this repository **only** in its descriptive sense — +naming the architecture and the specifications this encoder targets, as in +*"trace encoder for RISC-V cores"* or *"implements the RISC-V N-Trace +specification"*. + +Specifically, this repository does not and must not: + +- use the RISC-V logo; +- use "RISC-V" as part of the product, module or domain name — the product is + **CEDARtools.TraceEncoder**, and RISC-V only describes what it targets; +- claim membership, partnership, certification, approval or endorsement; +- claim conformance or compatibility certified by any official RISC-V + programme. Deviations from the specifications are listed openly in + [`doc/trace-format.adoc`](doc/trace-format.adoc), and the vendor TCODEs + 56/57/58 are Accemic extensions that imply no claim of standard conformance. + +"RISC-V" is written in block letters with a hyphen; the only admissible +spellings are *RISC-V* and *RISC-V International*. diff --git a/VERSION b/VERSION index 6e8bf73..3eefcb9 100644 --- a/VERSION +++ b/VERSION @@ -1 +1 @@ -0.1.0 +1.0.0 diff --git a/bin/NexRv b/bin/NexRv deleted file mode 100755 index e5d88cb..0000000 Binary files a/bin/NexRv and /dev/null differ diff --git a/bin/README.md b/bin/README.md index ff78b39..606ba2a 100644 --- a/bin/README.md +++ b/bin/README.md @@ -3,42 +3,18 @@ SPDX-FileCopyrightText: 2026 Accemic Technologies GmbH SPDX-License-Identifier: CC-BY-4.0 --> -# `bin/` — vendored tools +# bin/ — the fetched decoder lives here -## `NexRv` +The reference decoder is **CTTD (CEDARtools.TraceDecoder)** and is no longer +committed. Get the pinned build: -The **NexRv** reference decoder for the Nexus RISC-V trace stream. This -is a dedicated port/fork maintained for CEDARtools.TraceEncoder compatibility — - — not the upstream -IAR Systems tool. Used by the testbenches as a post-simulation -verification step: the encoder emits an ATB byte stream, NexRv decodes -it back into PCs using the program description (`*.nexrv.info`), and the -result is diffed address-for-address against the sequence the -`cpu_model` claims it executed. + py scripts/fetch_cttd.py # this host + py scripts/fetch_cttd.py --all # all three platforms (board deploys need linux-arm64) -``` -NexRv -deco -pcinfo -pcout -full -``` - -The version bundled here is a **pinned binary** built from the CEDARtools.TraceEncoder -port at . This directory -may later become a git submodule (or a tiny build script) so the binary -drops out. - -### License - -NexRv (the CEDARtools.TraceEncoder port, -) is derived from the -IAR Systems NexRv tool and is distributed under the **ISC License** -(Copyright (c) 2020 IAR Systems AB, -Copyright (c) 2026 Accemic Technologies GmbH). This is independent of -CEDARtools.TraceEncoder's own CERN-OHL-S-2.0 / Accemic-Commercial dual license. The -SPDX record for the binary lives in [`REUSE.toml`](../REUSE.toml) and -the license text in [`LICENSES/ISC.txt`](../LICENSES/ISC.txt). - -### Why a pre-built binary in the repo? - -NexRv is small (~85 KB) and the decode step is part of every test's -PASS criterion. Vendoring the binary keeps the testsuite self-contained -and reproducible. Rebuild it from the CEDARtools.TraceEncoder port at - when an update is needed. +The pin (version + sha256 per platform) is `scripts/cttd.pin`; a checksum +mismatch is a hard error, because every decode verdict in this repository is +worth exactly what the decoder is. CTTD's home is +[github.com/accemic/CTTD](https://github.com/accemic/CTTD); `base_url` in +the pin names where its release assets are fetched from. The pin-by-pin +behavioural record that used to fill this file lives in the git history of +this README and in CTTD's `CHANGELOG.md`. diff --git a/doc/adapters/README.adoc b/doc/adapters/README.adoc new file mode 100644 index 0000000..57dec4b --- /dev/null +++ b/doc/adapters/README.adoc @@ -0,0 +1,38 @@ +// SPDX-FileCopyrightText: 2026 Accemic Technologies GmbH +// SPDX-License-Identifier: CC-BY-4.0 + += Ingress-adapter characterization -- index + +Specification-level documents for the ingress adapters under +link:../../rtl/adapters/[`rtl/adapters/`]. These are truth tables: +empirically measured signal semantics of a specific core/tool version, not +architecture prose. Migrated 2026-08 from an internal predecessor +repository; see link:../../rtl/adapters/README.md[`rtl/adapters/README.md`] +for the package-level provenance and what is deliberately not here. + +[cols="2,3,3", options="header"] +|=== +| Document | Adapter | Covers + +| link:microblaze_v_trace_semantics.adoc[`microblaze_v_trace_semantics.adoc`] | link:../../rtl/adapters/amd_microblaze_v/[amd_microblaze_v] | Gate G1: the AMD `TRACE` bus retirement/trap truth table (rounds 1-8) +| link:microblaze_v_trace_ports.adoc[`microblaze_v_trace_ports.adoc`] | amd_microblaze_v | Confirmed port list + widths (Gate G0) +| link:microblaze_v_adapter_mapping.adoc[`microblaze_v_adapter_mapping.adoc`] | amd_microblaze_v | AMD signal -> TIP field mapping table +| link:microblaze_v_supported_configurations.adoc[`microblaze_v_supported_configurations.adoc`] | amd_microblaze_v | Verified IP/Vivado versions, MVP config, explicit non-goals +| link:itype_decoder_vectors.csv[`itype_decoder_vectors.csv`] | amd_microblaze_v | Source data for `rtl/adapters/amd_microblaze_v/test/tb_mbv_itype_decoder.sv`'s `itype_vectors.vec` +| link:cva6_iti_semantics.adoc[`cva6_iti_semantics.adoc`] | link:../../rtl/adapters/cva6/[cva6] | Gate C1: the CVA6 ITI truth table (RV32/Sv32/RV64) + the I1 itype-refinement measurement +| link:rocket_tci_semantics.adoc[`rocket_tci_semantics.adoc`] | link:../../rtl/adapters/rocket/[rocket] | Gate G1/R3.2a: the Rocket TraceCoreInterface truth table + the M3 context-key measurement +|=== + +**Not migrated:** `microblaze_v_native_trace_port.md` (AMD's competing +native N-Trace encoder -- characterizes a different, non-CTTE signal path; +out of scope for "the adapter's specification", see +link:../../rtl/adapters/README.md[`rtl/adapters/README.md`]). + +**Scope note:** these documents empirically describe AMD's proprietary, +non-standardized `TRACE` bus (MicroBlaze V) and rocket-chip's generated +netlist internals (including line numbers into generated Verilog). They +record *measurements of third-party interfaces*, made in order to build the +adapters in link:../../rtl/adapters/[`rtl/adapters/`]; they are neither a +specification of nor a claim about those third-party designs, and every +statement in them is bound to the tool and core revision named in the +document. diff --git a/doc/adapters/cva6_iti_semantics.adoc b/doc/adapters/cva6_iti_semantics.adoc new file mode 100644 index 0000000..b27d1b3 --- /dev/null +++ b/doc/adapters/cva6_iti_semantics.adoc @@ -0,0 +1,277 @@ +// SPDX-FileCopyrightText: 2026 Accemic Technologies GmbH +// SPDX-License-Identifier: CC-BY-4.0 + += CVA6 ITI truth table (Gate C1) +:toc: macro +:toclevels: 2 + +Migrated 2026-08 from an internal predecessor repository; see +link:../../rtl/adapters/README.md[`rtl/adapters/README.md`] for the +package-level provenance. This is the specification level of +link:../../rtl/adapters/cva6/[the CVA6 adapter] -- +`cva6_iti_to_ctte_tip.sv`'s trap-iretire clamp and idle-cycle contract, +and `cva6_riscv_itype_refine.sv`'s CALL/RETURN/SWAP reconstruction, both +trace back to findings in this document. + +**Measured against** cv32a60x / cv32a6_ima_sv32_fpga / +cv64a6_imac_sv39_ctrace, CVA6 pin `a3dc2c5e` + deltas D1/D2 (D6 config); +measurements dated 2026-07-24, last updated 2026-08-09. +**Status:** C1 GREEN (RV32 68/68 + guard rerun 2026-08-03; Sv32 104/104; +RV64 106/106 beats 1:1, R2.1a), B1/B2 clean. + +toc::[] + +**Measurement setup:** `sim/cva6/tb_cva6_iti_char.sv` (cva6_trace_wrap +@cv32a60x, `block_mode=0`, NrCommitPorts=1) + `sw/cva6_char/char_test.S` +(RV32IMA, no C-ext, M-mode; ALU/branches/JAL/JALR/ecall/illegal/timer IRQ) + +checker `tools/cva6_iti_check.py` against the RVFI golden reference. XSIM +2026.1, 512 cycles, exit code 1. **Version:** vendored pin `a3dc2c5e` **+ +deltas D1/D2** (link:../../examples/kv260/third_party/CVA6_PIN.md[`examples/kv260/third_party/CVA6_PIN.md`]) -- without +the deltas the ITI is trap-blind (D1) resp. classifies interrupts as EXC (D2). + +== Beat semantics (single-retirement, block_mode=0) + +One ITI beat per event; `iretire` is constant 1 (an **instruction flag, not +a halfword count** -- the halfword count lives in `ilastsize`; exactly the +CTTE contract: ICNT += `1 << ilastsize` per `iretire=1` beat). Idle cycles: +`valid=0` (no beats). + +== Event -> beat (measured) + +[cols="3,2,2,1,1,1,1", options="header"] +|=== +| Event (`char_test`) | itype | iaddr | iretire (ITI) | cause | tval | Count + +| ALU/load/store/JAL/csrw/... | 0 STANDARD | PC of the instr | 1 | 0 | 0 | 52 +| `mret` | 3 ERET | PC of the mret | 1 | 0 | 0 | 3 +| branch non-taken | 4 NON_TAKEN_BR | PC of the branch | 1 | 0 | 0 | 5 +| branch taken | 5 TAKEN_BR | PC of the branch | 1 | 0 | 0 | 5 +| `jalr` (call/return) | 6 UNINF_JMP | PC of the jalr | 1 | 0 | 0 | 3 +| `ecall` (M) | 1 EXC | PC of the ecall | **1 (!)** | 11 | 0 | 1 +| illegal 32-bit instr | 1 EXC | PC of the instr | **1 (!)** | 2 | **0 (!)** | 1 +| timer IRQ | 2 INT | PC of the interrupted instr | **1 (!)** | 7 | 0 | 1 +|=== + +**Findings/consequences:** + +1. **JAL is STANDARD (0), not a call:** `itype_detector` only marks `jalr` + as `updiscon`. Correctly decodable for N-Trace HTM (a decoder follows + direct jumps statically); implicit-return compression is not possible + in principle with the 3-bit profile -- **since I1 (2026-08-09) the shim + lifts this limit by reconstruction from the instruction word, see + "itype refinement in the shim (I1)" below.** +2. **Trap/IRQ beats carry iretire=1** (single_retirement sets it constant + 1) -- at odds with E-Trace/CTTE (the faulting instr does not retire). + The shim `cva6_iti_to_ctte_tip` **forces iretire=0 on EXC/INT** + (otherwise the composer would count the faulting instr in ICNT -> + decoder shift). +3. **tval on illegal = 0** (the probe delivers no tval here). Irrelevant + for N-Trace (tval never goes on the wire). +4. **ilastsize:** 1 on all beats (32-bit code; RVC HW present, software without C). +5. **The upstream #3010 bug classes here:** B1 (iretire counting) clean -- + 68 beats == 68 retires; B2 (a hanging valid) not observed. The bugs + named in #3010 partly affect `block_mode` paths, which we do not use. + +== Extension, Linux class: `cv32a6_ima_sv32_fpga` with Sv32 + S-mode (Gate L1) + +Measured 2026-07-26 with `sv32_test.S` (Sv32 identity mapping, S-mode, page +faults), run `run_char.ps1 -Target cv32a6_ima_sv32_fpga -Prog sv32_test +-Profile sv32`. **RVFI 104 retires <-> ITI 104 retire beats, 1:1**; B1/B2 clean. + +[cols="3,2,2,1,1,1", options="header"] +|=== +| Event (`sv32_test`) | itype | iaddr | iretire (ITI) | cause | tval + +| `sfence.vma` | 0 STANDARD | PC of the instr | 1 | 0 | 0 +| `csrw satp` | 0 STANDARD | PC of the instr | 1 | 0 | 0 +| `mret` after S-mode | 3 ERET | PC of the mret | 1 | 0 | 0 +| `ecall` **from S-mode** | 1 EXC | PC of the ecall | **1 (!)** | **9** | 0 +| **load page fault** | 1 EXC | PC of the `lw` | **1 (!)** | **13** | faulting VA +| **store page fault** | 1 EXC | PC of the `sw` | **1 (!)** | **15** | faulting VA +| **instruction page fault** | 1 EXC | **target VA** (not the `jalr`!) | **1 (!)** | **12** | faulting VA +|=== + +**New findings:** + +6. **The instruction-page-fault beat carries the TARGET address** (here + 0x30000000), not the address of the jump that triggered it. That is the + right information for the trace (execution would have continued there), + but a decoder that reads `iaddr` as "PC of the retiring instruction" + must know this case. Our shim forces `iretire = 0`, so the + never-executed instruction never enters the ICNT -- the same rule as + for any trap. +7. **`tval` carries the faulting virtual address on page faults** (13/15/12 + each the VA). It does not go on the N-Trace wire; in the E-Trace 3.1 + format it **is visible** -- the most valuable addition for a kernel trace. +8. **The privilege change M->S is visible in the beat** (`priv` switches + from 3 to 1); the ITI delivers it from the RVFI probes, the shim passes + it through. Only the **context/ASID** is still missing for process + attribution (gap X3). +9. **`sfence.vma` produces no control-flow event** -- correct, but worth + mentioning: a decoder needs no special rule for the `satp` change in our + setup, since the address spaces do not actually differ anyway (identity + mapping, per the CVA6-trio plan's design decision D8). + +Two **elaboration/configuration defects** surfaced during this gate, both +previously invisible because `cv32a60x` generates the MMU away and has no +execute-region rules: **D4** (`cva6_mmu.sv`, a direction-reversed subrange +at XLEN=32 -- worth an upstream fix) and **D5** (the FPGA configuration's +address regions point at the Genesys2 board, our memory was therefore not +executable). Details: +link:../../examples/kv260/third_party/CVA6_PIN.md[`examples/kv260/third_party/CVA6_PIN.md`]. + +== Extension RV64: `cv64a6_imac_sv39_ctrace` (delta D6) -- R2.1a, encoder-free + +Measured 2026-08-03 22:44 WEDT with `char_test64.S` (RV64IMA, `-mabi=lp64`, +no C-ext, M-mode; the same event classes as `char_test.S` plus 64-bit +constant construction LUI/ADDIW/SLLI, W-ops, ld/sd, 64-bit branch +discriminators, a jalr target from 64-bit arithmetic), run +`run_char.ps1 -Target cv64a6_imac_sv39_ctrace -Prog char_test64 -Profile char +-WorkName r21a_cv64_char`. XSIM 2026.1, **635 cycles**, exit code 1. **RVFI +106 retires <-> ITI 106 retire beats, 1:1**; B1/B2 clean. **Holds for: +NrCommitPorts=1, block_mode=0, M-mode, no C-ext code** (the config's HW RVC +support unused; `ilastsize` constant 1). + +[cols="3,2,2,1,1,1,1", options="header"] +|=== +| Event (`char_test64`) | itype | iaddr | iretire (ITI) | cause | tval | Count + +| ALU/64-bit const./W-ops/ld/sd/JAL/csrw/... | 0 STANDARD | PC of the instr | 1 | 0 | 0 | 82 +| `mret` | 3 ERET | PC of the mret | 1 | 0 | 0 | 3 +| branch non-taken (incl. 64-bit `bltu` discr.) | 4 NON_TAKEN_BR | PC of the branch | 1 | 0 | 0 | 6 +| branch taken (incl. `bnez` with low32==0) | 5 TAKEN_BR | PC of the branch | 1 | 0 | 0 | 10 +| `jalr`/`ret` (incl. a target from 64-bit arith.) | 6 UNINF_JMP | PC of the jalr | 1 | 0 | 0 | 5 +| `ecall` (M) | 1 EXC | PC of the ecall | **1 (!)** | 11 | 0 | 1 +| illegal 32-bit instr | 1 EXC | PC of the instr | **1 (!)** | 2 | **0x0000_0000_FFFF_FFFF (!)** | 1 +| timer IRQ | 2 INT | PC of the interrupted instr (spin `beqz`) | **1 (!)** | 7 | 0 | 1 +|=== + +**RV64 findings:** + +10. **Beat semantics identical to RV32** -- one beat per retire, `iretire` + constant 1 (also on trap/IRQ, finding 2 still holds), idle cycles + `valid=0`. JAL stays STANDARD (finding 1 still holds). The upstream + #3010 classes B1/B2 stayed clean (106 beats == 106 retires, no hanging valid). +11. **`iaddr`/`tval` arrive as full 64-bit values** (`iti_types.svh` is + XLEN-parametric); PCs in the 0x64 window appear zero-extended. **Not + exercised:** PCs with bit 31/63 set -- not representable in the + 192-MiB window (0x6400_0000+0x0C00_0000); the ITI's sign-extension + behavior above 2^31 remains open. +12. **`tval` on an illegal instruction carries the instruction word on + RV64** (0xFFFFFFFF zero-extended) -- on RV32 (finding 3) the probe + delivered 0. Irrelevant for N-Trace (tval never goes on the wire), + visible in the E-Trace path; decoders must not carry an RV32 "tval=0" + assumption over. +13. **64-bit discriminators correct:** `bnez` on a register with low32==0 + (a full value != 0) is TAKEN, `bltu` against 1 with a huge unsigned + value is NON_TAKEN -- a 32-bit-truncated comparison view would have + inverted both outcomes. Classification 1:1 against the RVFI + `pc_wdata` golden reference. +14. **The timer-IRQ chain works unchanged under RV64** (mcause MSB = bit + 63; the INT beat carries cause=7, iaddr = the interrupted spin instr). + +**Open RV64 legs:** S/U-mode + Sv39 (page-fault causes 12/13/15 analogous +to Gate L1), C-ext code (stage-1 exclusion), PCs >= 2^31, +NrCommitPorts=2/block_mode=1 (only in a later phase). Encoder/decoder +connection (TIP at 64 bit) is NOT part of this measurement. + +== itype refinement in the shim (I1) -- CALL/RETURN/SWAP for the folding path + +Finding 1 above describes the **ITI**, not a limit of the adapter: since I1 +(2026-08-09) the shim `cva6_iti_to_ctte_tip` (module +`cva6_riscv_itype_refine`) reconstructs the missing 4-bit codes from the +instruction word that `cva6_trace_wrap.rvfi_insn_o` delivers cycle-exact +with the ITI beat -- `cva6_rvfi.sv` registers `insn` and +`rvfi_to_iti_o.*` in the same `always_ff` from the same `mem_q` entry. +**No delta in the vendored CVA6 tree** (there is no D7). + +* **Switch:** `ITI_ITYPE_REFINE` (default **0** = the previous state, + bit-identical zero extension; backward compatibility: RV32 Gate C3 + re-run PASS 1136/1136 after the change, no existing instantiation sets + the parameter). +* **Port:** `iti_insn_i` (default `'0`; a runtime assertion against an + unconnected port at REFINE=1 -- `'0` is not a legal RISC-V encoding, a + forgotten connection would otherwise be the most expensive silent + failure: folding would simply keep doing nothing). +* **Classification** (E-Trace v2.0.2 ch. 4, JALR table; the rule table is + identical to `mbv_riscv_itype_decoder.sv`, no second source of truth); + only ITI code 0 (where `jal` hides, finding 1) and 6 (the catch-all for + every `jalr`) are refined: + `jal rd in Link` -> IC(9) - `jalr rd in Link, rs1 not in Link` -> UC(8) - + both Link, `rd==rs1` -> UC(8) - both Link, `rd!=rs1` -> SWAP(12) - + `rd=x0, rs1 in Link` -> RET(13) - otherwise unchanged. +* **`ITI_LINK_REG_MASK`** (default {x1,x5} = `32'h22`): the reference + decoder CTTD only knows x1 as the return base (converter source + `NexRvConv.c:225` -- the file name predates the CTTD rename and is + quoted as-is) -- 8 `jr t0` divergences were measured across the + whole OpenSBI+Linux image (handoff I1, finding B-I1-1). Clamped to + `32'h2` = provably decoder-conformant, until the decoder learns x5. +* **PCINFO pitfall (B-I1-2):** a `.dis` with ABI register names makes + CTTD's converter read EVERY return as a call (`GnuRdNum` only accepts + `xNN`; + measured: 17 C / 0 R on `call_test64.dis`). Always generate listings for + IR decode with `-M no-aliases,numeric`. +* **Operating-point pitfall (B-I1-4):** `InstSyncMax=0` (the reset + default) forces a full ProgTraceSync every 16 instructions and chokes + call-dense runs (67/108 `NEXUS_MSG_ERROR`, never terminates); IR + measurements run at `InstSyncMax=6` (sync every 1024). + +**Gates (2026-08-09):** the unit testbench checked 180 vectors against an +independent assembler/objdump oracle, 0 deviations (incl. `jalr rd=x0`/ +`rs1=x0`, an x5 link, `rd==rs1`, a co-routine swap, RVC neighbor encodings); +mutants m1 (link set) / m2 (rd bits) / m3 (RVC swap) all turned red. E2E +`call_test64` (cv64a6, RV64IMA, 24413 instr. in the window, 3200 calls + +3200 returns, `InstSyncMax=6`, no range filter/watchpoint): + +[cols="3,1,1,1,2", options="header"] +|=== +| Leg | ATB | Messages | bit/instr | `-cs 0` + +| A `refine=0`, IR on (baseline) | 27560 B | 3433 | 9.031 | byte-identical (nothing folded) +| B `refine=1`, IR on | **2092 B** | **248** | **0.686** | **fails** (folding confirmed) +| C `refine=1`, IR off | 27560 B | 3433 | 9.031 | byte-identical +|=== + +The PC sequence is **identical** across all three legs (md5-equal, 24414 +PCs); `max_ret_sp` 0/9/9. **A == C down to the byte** -- refinement alone +does not change the stream, only refinement+IR produces the drop: +**25468 B saved (92.4 %) on this deliberately call-dense program** (every +7.6th instruction is a call/return -- not a general ratio; on the +883577-instr. board window, re-encoded from a reference decoder, it is +5.25 %, handoff I1 §6). The E2E mutants m4 (the shim assumes REFINE=1 but +does not refine) and m5 (the RETURN branch removed) must turn red at gate 4. + +== Upstream defects (deltas, upstream-worthy) + +[cols="1,3,4", options="header"] +|=== +| Delta | File | Defect + +| D1 | `core/cva6_rvfi.sv` | `valid_iti = commit_ack` -> exceptions/interrupts NEVER reach the ITI (0 EXC/INT beats) +| D2 | `ITI/cva6_iti/itype_detector.sv` | `exception` checked before `interrupt`, `ex_valid` is also 1 on IRQs -> every IRQ classified as EXC +|=== + +== Reproduction + +WARNING: **Not reproducible from this repository.** The characterization +flow that produced the measurements above is not part of this repository: +it needs an ELF-to-hex image converter, a simulation driver (compile + +simulate + check against the RVFI golden reference) and the vendored CVA6 +core. There is no `sim/` counterpart here. Only the stimulus build step is +quoted below; the driver tools are described, not pathed, because naming a +path that does not exist here would only mislead. + +---- +sw/cva6_char: riscv64-unknown-elf-gcc -march=rv32ima -mabi=ilp32 -nostdlib \ + -nostartfiles -Ttext=0x64000000 -o char_test.elf char_test.S + objcopy -O binary, then convert to a 64-bit hex image +---- + +NOTE: The link address was `0x7C000000` in the original characterization run +and is quoted here as `0x64000000`, the CVA6 window of address plan v4. The +old address lies outside the `reserved-memory` window the board actually +reserves, so quoting it verbatim would invite a write into host memory. + +Whoever needs to re-run the characterization has to supply the vendored +CVA6 core (see link:../../examples/kv260/third_party/[`examples/kv260/third_party/`]) +plus their own image converter and simulation driver. diff --git a/doc/adapters/itype_decoder_vectors.csv b/doc/adapters/itype_decoder_vectors.csv new file mode 100644 index 0000000..30b06b2 --- /dev/null +++ b/doc/adapters/itype_decoder_vectors.csv @@ -0,0 +1,33 @@ +instr_hex,asm,rd,rs1,funct3,jump_taken,itype,ilastsize,gate +0x00208463,beq x1,x2,off,1,2,0,0,NOT_TAKEN_BRANCH,1,G2 +0x00208463,beq x1,x2,off,1,2,0,1,TAKEN_BRANCH,1,G2 +0x00209463,bne x1,x2,off,1,2,1,0,NOT_TAKEN_BRANCH,1,G2 +0x00209463,bne x1,x2,off,1,2,1,1,TAKEN_BRANCH,1,G2 +0x0020c463,blt x1,x2,off,1,2,4,0,NOT_TAKEN_BRANCH,1,G2 +0x0020c463,blt x1,x2,off,1,2,4,1,TAKEN_BRANCH,1,G2 +0x0020d463,bge x1,x2,off,1,2,5,0,NOT_TAKEN_BRANCH,1,G2 +0x0020d463,bge x1,x2,off,1,2,5,1,TAKEN_BRANCH,1,G2 +0x0020e463,bltu x1,x2,off,1,2,6,0,NOT_TAKEN_BRANCH,1,G2 +0x0020e463,bltu x1,x2,off,1,2,6,1,TAKEN_BRANCH,1,G2 +0x0020f463,bgeu x1,x2,off,1,2,7,0,NOT_TAKEN_BRANCH,1,G2 +0x0020f463,bgeu x1,x2,off,1,2,7,1,TAKEN_BRANCH,1,G2 +0x0100006f,jal x0,off,0,-,-,n/a,OTHER_INFERABLE_JUMP,1,G2 +0x010000ef,jal x1,off,1,-,-,n/a,INFERRABLE_CALL,1,G2 +0x010002ef,jal x5,off,5,-,-,n/a,INFERRABLE_CALL,1,G2 +0x0100046f,jal x8,off,8,-,-,n/a,OTHER_INFERABLE_JUMP,1,G2 +0x000100e7,jalr x1,0(x2),1,2,0,n/a,UNINFERABLE_CALL,1,G2 +0x000302e7,jalr x5,0(x6),5,6,0,n/a,UNINFERABLE_CALL,1,G2 +0x00008067,jalr x0,0(x1),0,1,0,n/a,RETURN,1,G2 +0x00028067,jalr x0,0(x5),0,5,0,n/a,RETURN,1,G2 +0x00008467,jalr x8,0(x1),8,1,0,n/a,RETURN,1,G2 +0x000080e7,jalr x1,0(x1),1,1,0,n/a,UNINFERABLE_CALL,1,G2 +0x000280e7,jalr x1,0(x5),1,5,0,n/a,CO_ROUTINE_SWAP,1,G2 +0x000082e7,jalr x5,0(x1),5,1,0,n/a,CO_ROUTINE_SWAP,1,G2 +0x00010067,jalr x0,0(x2),0,2,0,n/a,OTHER_UNINFERABLE_JUMP,1,G2 +0x00048467,jalr x8,0(x9),8,9,0,n/a,OTHER_UNINFERABLE_JUMP,1,G2 +0x30200073,mret,-,-,-,n/a,EXCEPTION_IR,1,G2 +0x10200073,sret,-,-,-,n/a,EXCEPTION_IR,1,G2 (S-mode, not MVP) +0x00000073,ecall,-,-,-,n/a,EXCEPTION_TRAP?,1,G1 (iretire/trap coupling) +0x00100073,ebreak,-,-,-,n/a,EXCEPTION_TRAP?,1,G1 (iretire/trap coupling) +0x00000013,addi x0,x0,0 (nop),0,0,-,n/a,OTHER,1,G2 +0x00c58533,add x10,x11,x12,10,11,-,n/a,OTHER,1,G2 diff --git a/doc/adapters/microblaze_v_adapter_mapping.adoc b/doc/adapters/microblaze_v_adapter_mapping.adoc new file mode 100644 index 0000000..ba3126a --- /dev/null +++ b/doc/adapters/microblaze_v_adapter_mapping.adoc @@ -0,0 +1,94 @@ +// SPDX-FileCopyrightText: 2026 Accemic Technologies GmbH +// SPDX-License-Identifier: CC-BY-4.0 + += MicroBlaze V `TRACE` bus -> CTTE TIP -- signal mapping (living doc) + +Migrated 2026-08 from an internal predecessor repository; see +link:../../rtl/adapters/README.md[`rtl/adapters/README.md`] for the +package-level provenance. + +[NOTE] +==== +Consolidates the MicroBlaze V implementation concept §4 and the technical +integration report §8/§17.1 against the **authoritative** TIP types in the +pinned CTTE core (`rtl/pkg/tip_pkg.sv` / `tip_if.sv`). **Mapping rules +marked "G1" are hypotheses until confirmed by the truth table** +(link:microblaze_v_trace_semantics.adoc[`microblaze_v_trace_semantics.adoc`]). +==== + +== TIP target side (fact, from `tip_pkg.sv`) + +* `tip_if.master` fields: `itype, ecause, tval, priv, iaddr, _context, + _time, ctype, iretire, ilastsize, impdef` + data flow (`dretire, dtype, + daddr, dsize, data, sdata, lresp, ldata`). +* `tip_itype_e` (4 bit): OTHER=0, EXCEPTION_TRAP=1, INTERRUPT=2, + EXCEPTION_IR=3, NOT_TAKEN_BRANCH=4, TAKEN_BRANCH=5, UNINFERABLE_JUMP=6, + RESERVED=7, UNINFERABLE_CALL=8, INFERRABLE_CALL=9, + UNINFERABLE_TAIL_CALL=10, INFERRABLE_TAIL_CALL=11, CO_ROUTINE_SWAP=12, + RETURN=13, OTHER_UNINFERABLE_JUMP=14, OTHER_INFERABLE_JUMP=15. +* `tip_ecause_e` is **4 bit** (values 0-7 plus `ECALL_FROM_M=11`; the + sentinel `ECAUSE_NONE` sits at a reserved code, see the header comment + in `rtl/pkg/tip_pkg.sv`). Special causes -> `impdef`. +* `icause_e`: `MEXT=11` (machine external interrupt). +* The adapter **imports** `tip_pkg` -- the enums are **not** duplicated (AD-01). + +== Control-flow mapping (MVP-carrying) + +[cols="1,3,4,2", options="header"] +|=== +| TIP field | AMD `TRACE` source (§17.1) | Rule | Status + +| `iaddr` | `Trace_PC` | width/bit-order normalization | G0 bit check (table 7.4) +| `iretire` | `Trace_Valid_Instr` **+ trap rules** | 1 per retired instr; trap special cases | **G1** (tables 1+2) +| `itype` | instr decode(`Trace_Instruction`) + `Trace_Jump_Taken` + trap | priority §5.1: trap>return>branch>JAL>JALR | decode is spec-fixed; trap is **G1** +| `ilastsize` | instr length | RV32-without-C: **constant 1** (2 halfwords) | MVP-fixed +| `priv` | ~~`Trace_Privilege_Mode`~~ **not exposed** (microblaze_riscv:1.0) | MVP: constant M-mode | **corrected** (port list) +| `ecause` | `Trace_Exception_Kind[0:5]` (**6 bit confirmed**) | 0-15 direct; >15 -> special cause via `impdef` | **G1** (tables 2+4) +| `_time` | adapter cycle counter (64 bit) | free-running, `tip_clk` (AD-06) | adapter-internal +| `tval` | not exposed | **MVP = 0** (no program-flow blocker, AD-04) | MVP-fixed +| `_context` | ~~`Trace_PID_Reg`~~ **not exposed** (microblaze_riscv:1.0) | MVP = 0 | **corrected** (port list) +| `ctype` | no direct source | MVP `UNREPORTED` (=0) | MVP-fixed +|=== + +[NOTE] +==== +**Empirical correction (2026-07-15):** `Trace_Privilege_Mode` + +`Trace_PID_Reg` (assumed in the original integration report §17.1) are +**not** exposed on `microblaze_riscv:1.0`. NEWLY available: +`Trace_OF/EX/MEM_PipeRun` + `Trace_Halted` (a G1 retirement aid). All buses +are `[0:31]` VHDL-ascending (R4 confirmed) -> the normalizer mirrors them. +Full list: link:microblaze_v_trace_ports.adoc[`microblaze_v_trace_ports.adoc`]. +==== + +== itype decision priority (§5.1 -- the decode part is spec-fixed, G2) + +`1` reset/idle -> `2` trap entry (**G1**) -> `3` trap return +(`mret`/`sret`->EXCEPTION_IR) -> `4` cond. branch (`Trace_Jump_Taken`? TAKEN +: NOT_TAKEN) -> `5` JAL (rd in {x1,x5}->INFERRABLE_CALL; rd=x0->jump) -> +`6` JALR (rd/rs1 link relationship -> UNINFERABLE_CALL/RETURN/ +CO_ROUTINE_SWAP/...) -> `7` OTHER. The non-trap rows are already encoded as +a reference: link:itype_decoder_vectors.csv[`itype_decoder_vectors.csv`] + +`sw/.../build/*.oracle.csv`. + +== Data-flow mapping (P2/P3 -- not MVP, §4.2) + +[cols="1,3,4,2", options="header"] +|=== +| TIP field | AMD source | Rule | Status + +| `dtype` (STORE=1) | `Trace_Data_Write` | store directly derivable | P2 (G8) +| `daddr` | `Trace_Data_Address` | | P2 +| `dsize` | `Trace_Data_Byte_Enable` | 2^dsize bytes | P2 +| `sdata` | `Trace_Data_Write_Value` | store value at `dretire` | P2 +| `ldata`/`lresp` | **no direct load-data signal** | `Trace_New_Reg_Value` is ambiguous -> a bus monitor is needed | P3 (§4.2, table 6.2) +|=== + +== Adapter top interface (integration report §17.1) + +AMD inputs: `trace_valid_instr, trace_instruction[31:0], trace_pc, +trace_jump_taken, trace_exception_taken, trace_exception_kind[5:0], +trace_privilege_mode[1:0], trace_pid_reg[7:0]` (+ data: +`trace_data_access/_address/_read/_write/_write_value/_byte_enable, +trace_reg_write/_addr/_new_reg_value`) -> `tip_if.master`. MVP parameters: +`IADDR_WIDTH=32, DATA_WIDTH=32, SUPPORT_RVC=0, SUPPORT_DATA_TRACE=0` +(unsupported combinations are caught via an elaboration assertion, §17.2). diff --git a/doc/adapters/microblaze_v_supported_configurations.adoc b/doc/adapters/microblaze_v_supported_configurations.adoc new file mode 100644 index 0000000..cd08fc1 --- /dev/null +++ b/doc/adapters/microblaze_v_supported_configurations.adoc @@ -0,0 +1,87 @@ +// SPDX-FileCopyrightText: 2026 Accemic Technologies GmbH +// SPDX-License-Identifier: CC-BY-4.0 + += MicroBlaze V CTTE adapter -- supported configurations (living doc) + +Migrated 2026-08 from an internal predecessor repository; see +link:../../rtl/adapters/README.md[`rtl/adapters/README.md`] for the +package-level provenance. + +[NOTE] +==== +Version-bound support (AD-07, R1): the AMD `TRACE` bus is **not +standardized / not version-stable**. Every row holds only for the named +Vivado/MBV version. No generic future-compatibility claim. Source: the +MicroBlaze V implementation concept §1/§6/Appendix A and the technical +integration report Appendix A+C (both in `forge_kb`). +==== + +== Verified IP + part (2026-07-15) + +* **IP:** `xilinx.com:ip:microblaze_riscv:1.0` (= "MicroBlaze V"), Vivado **2026.1**. +* **Part/board:** Kria **KR260** -- `xck26-sfvc784-2LV-c`, + `xilinx.com:kr260_som:part0:2.0` (matches KriaTracer2). +* **Verified config property names:** `C_TRACE` (trace bus on), + `C_USE_COMPRESSION` (C-ext), `C_USE_MMU`, `C_USE_MULDIV` (M-ext), + `C_DEBUG_TRACE_SIZE`/`C_DEBUG_EXTERNAL_TRACE` (native N-Trace), + `C_BASE_VECTORS=0x0` (reset vector, matches the linker script). +* **M-extension ON** (`C_USE_MULDIV=1`): the rv32im software emits `mul`; + under `-nostdlib` this avoids a libgcc `__mulsi3`. M-extension + instructions are program-flow-neutral (itype=OTHER). +* **`Trace_Privilege_Mode` / `Trace_PID_Reg` are NOT exposed on this IP + version** (the original integration report §17.1 assumed them) -> the + `priv`/`_context` mapping does not apply; MVP: priv=M constant, + `_context=0`. Full port list: + link:microblaze_v_trace_ports.adoc[`microblaze_v_trace_ports.adoc`]. + +== MVP target configuration (Appendix A) + +---- +MicroBlaze V: RV32 - C-extension OFF - M-ext ON (C_USE_MULDIV=1) - Machine mode - MMU OFF - + Trace Bus Interface ON - native AMD N-Trace OFF (or reference instance only) +Adapter: IADDR_WIDTH=32 - DATA_WIDTH=32 - SUPPORT_RVC=0 - SUPPORT_DATA_TRACE=0 - + tval=0 - context=disabled - time=64-bit core cycle counter +CTTE: TIP_IRETIRE_WIDTH=1 - TIP_IADDRESS_WIDTH=32 - program-trace mode HTM - + SPLIT_DATA_ACCESS=0 - output=ATB -> sim/on-chip - decoder=CTTD +---- + +== Support matrix (fill in as verified) + +[cols="1,2,1,1,1,1,1,3,2", options="header"] +|=== +| Vivado | MBV IP version | RV32 | Trace bus | G0 | G1 | G6 (FPGA) | Adapter fingerprint | Status + +| 2026.1 | `microblaze_riscv:1.0` | Yes | Yes | Yes | Yes | **Yes, KV260 2026-07-21/22 hardened** | `mbv_to_ctte_tip` (sijump off) | **G6 + hardening: 7/7 programs green on silicon -- trace/branch/sijump/trap/illegal/misaligned with an exact reference prefix (26.6-26.8k PCs), interrupt_test with an HW IRQ pulse generator (CONTROL b3) + mei_handler evidence; WNS +2.38 ns @ 75 MHz, ~25.3k LUTs** +| 2025.2 (comparison, optional) | TBD | No | No | No | No | No | TBD | -- +|=== + +== Explicitly NOT supported in the MVP (per the original "list of not-yet-supported features") + +* **RVC / C-extension** -- Gate G7. **Update 2026-07-16:** the RVC + raw-encoding question (risk R3) is **empirically resolved** -- + `Trace_Instruction` carries the **original** RVC encoding, `ilastsize` is + **directly derivable** via `Trace_Instruction[1:0]!=2'b11` + (link:microblaze_v_trace_semantics.adoc[semantics table 5] / round 7). G7 + is therefore significantly cheaper; the MVP still keeps C-ext OFF (a + scope decision, no longer risk-driven). Experiment switch: + `MBV_USE_COMPRESSION=1` on the `create_project.tcl` run. +* **Data trace** (load/store/AMO) -- Gate G8; store first, a full load only + with a bus monitor (§4.2). +* **CSR trace** -- **not** traceable via the `TRACE` bus (only via instruction decode). +* **`tval`** -- MVP=0 (no program-flow blocker; relevant only for extended + exception diagnostics). +* **Context/ASID, ownership** -- P2 (`tip_context_t` narrow at the time of writing). +* **RV64** -- P3. +* **Supervisor/user mode, MMU, page faults** -- the MVP is machine-mode, MMU off. +* **External PIB pin sink** -- CTTE does not directly speak AMD's PIB + protocol (packetizer/bridge, §6). +* **AXI4-Lite CSR** -- the MVP uses CTTE's Wishbone (a small + wrapper/static init); AXI4-Lite is G9. + +== Version fingerprint (adapter manifest) + +The adapter carries a version fingerprint +(`rtl/adapters/amd_microblaze_v/mbv_trace_pkg.sv`) with: the tested Vivado +version, the MBV IP version, the CTTE pin commit, the adapter's SemVer. +Regression per Vivado release (G9). A fingerprint mismatch at +runtime/elaboration is an **error**, not a silent pass. diff --git a/doc/adapters/microblaze_v_trace_ports.adoc b/doc/adapters/microblaze_v_trace_ports.adoc new file mode 100644 index 0000000..1e8502d --- /dev/null +++ b/doc/adapters/microblaze_v_trace_ports.adoc @@ -0,0 +1,108 @@ +// SPDX-FileCopyrightText: 2026 Accemic Technologies GmbH +// SPDX-License-Identifier: CC-BY-4.0 + += MicroBlaze V `TRACE` bus -- confirmed port list (G0 ground truth) + +Migrated 2026-08 from an internal predecessor repository; see +link:../../rtl/adapters/README.md[`rtl/adapters/README.md`] for the +package-level provenance. + +[NOTE] +==== +**Empirically confirmed** via Vivado block-design introspection, +2026-07-15. Version-bound (R1/AD-07): Vivado **2026.1**, IP +**`xilinx.com:ip:microblaze_riscv:1.0`**, `CONFIG.C_TRACE=1`. Re-measure on +a version change. This is the source of truth for the real signal names -- +it **corrects/extends** the original integration report §17.1 (which was +written from documentation/assumption). +==== + +== Bit order (R4 -- now concretely confirmed) + +All multi-bit `TRACE` ports are **VHDL `(0 to N)` ascending** -> Vivado +reports them as `[0:N]` (bit 0 = MSB). The adapter's SV side uses `[N-1:0]` +(bit N-1 = MSB). `mbv_trace_normalizer` must establish the mapping +bit-exactly and verify it against the object dump +(`sw/.../*.oracle.csv`). + +== Program-flow ports (MVP-carrying) -- all DIR=O (observer, no backpressure) + +[cols="2,1,3,4", options="header"] +|=== +| AMD port | Width | -> TIP field | Note + +| `Trace_PC` | `[0:31]` | `iaddr` | mirror the bit order (R4) +| `Trace_Instruction` | `[0:31]` | instr decode -> `itype` | +| `Trace_Valid_Instr` | 1 | `iretire` (+ trap rules) | **retirement semantics: G1** +| `Trace_Jump_Taken` | 1 | cond. branch TAKEN/NOT | +| `Trace_Exception_Taken` | 1 | trap-entry flag | **G1 measured** (rounds 1+2) +| `Trace_Exception_Kind` | `[0:5]` | **bit 5 = interrupt flag; bits[4:0] = RISC-V cause** | **6 bit; encoding G1-confirmed** +|=== + +[NOTE] +==== +**G1 finding (2026-07-16):** `Trace_Exception_Kind[5]` distinguishes an +**interrupt (1)** from a **synchronous exception (0)**; `[4:0]` carries the +RISC-V `mcause` low value directly. Measured: ecall=0x0b, ebreak=0x03, +external interrupt (MEXT)=0x2b. Details + coupling: +link:microblaze_v_trace_semantics.adoc[`microblaze_v_trace_semantics.adoc`] +"Measurement results". +==== + +== NEW vs. the original integration report §17.1 -- pipeline/halt signals (G1 retirement aid) + +[cols="2,1,5", options="header"] +|=== +| AMD port | Width | Use + +| `Trace_OF_PipeRun` | 1 | operand-fetch stage runs (not stalled) -- **the only stall indicator** in the measured load +| `Trace_EX_PipeRun` | 1 | execute stage runs -- **measured: constant 1** (never stalled) +| `Trace_MEM_PipeRun` | 1 | memory stage runs -- **measured: constant 1** (never stalled) +| `Trace_Halted` | 1 | core halted (debug) +|=== + +**G1 round-4 finding (full-cycle measurement, `data_trace_test`):** +`Trace_OF_PipeRun=0` marks fetch stalls (295x in the settled window, +**exactly 1 cycle each**, 26.8 % of cycles); `EX/MEM_PipeRun` stayed +constant 1. **Important:** `Valid_Instr=1` occurred **68x while +`OF_PipeRun=0`** => PipeRun is **not** a retirement signal and must not +enter the `iretire` path +(link:microblaze_v_trace_semantics.adoc[`microblaze_v_trace_semantics.adoc`] +round 4). Workload-scoped: under cache/AXI load, `EX/MEM_PipeRun` could +well stall. + +== MISSING vs. the original integration report §17.1 (a real correction) + +[cols="2,4", options="header"] +|=== +| Assumed port | Status on microblaze_riscv:1.0 + +| `Trace_Privilege_Mode` | **not exposed** -> the `priv` mapping is unavailable this way. MVP: constant M-mode. +| `Trace_PID_Reg` | **not exposed** -> the `_context` mapping does not apply. MVP: `_context=0`. +|=== + +Not critical for the M-mode program-flow MVP, but documented in the adapter +manifest + `microblaze_v_supported_configurations.adoc`. Should +privilege/context tracing become necessary later (P2), a different source +(instruction-decode CSR accesses / an IP config option) needs to be +investigated. + +== Data-flow ports (P2/P3 -- not MVP; §4.2) + +`Trace_Data_Access` (1), `Trace_Data_Address [0:31]`, `Trace_Data_Read` (1), +`Trace_Data_Write` (1), `Trace_Data_Write_Value [0:31]`, +`Trace_Data_Byte_Enable [0:3]`, `Trace_Reg_Write` (1), `Trace_Reg_Addr +[0:4]`, `Trace_New_Reg_Value [0:31]`. Store is derivable; the load value is +ambiguous (§4.2). + +== Bundled interface + +The core additionally exposes a bundled `TRACE` interface (`get_bd_intf_pins +mbv/TRACE`) -- exposed externally in the G0 SoC +(`make_bd_intf_pins_external`) for ILA/sim observation. + +== Adapter consequence + +`rtl/adapters/amd_microblaze_v/mbv_trace_if.sv` (written against this list +and `xvlog`-elaborated) carries exactly these signals; +`Trace_Privilege_Mode`/`Trace_PID_Reg` are deliberately NOT included. diff --git a/doc/adapters/microblaze_v_trace_semantics.adoc b/doc/adapters/microblaze_v_trace_semantics.adoc new file mode 100644 index 0000000..c7609d5 --- /dev/null +++ b/doc/adapters/microblaze_v_trace_semantics.adoc @@ -0,0 +1,462 @@ +// SPDX-FileCopyrightText: 2026 Accemic Technologies GmbH +// SPDX-License-Identifier: CC-BY-4.0 + += MicroBlaze V `TRACE` bus -- semantics truth table (Gate G1) +:toc: macro +:toclevels: 2 + +Migrated 2026-08 from an internal predecessor repository; see +link:../../rtl/adapters/README.md[`rtl/adapters/README.md`] for the +package-level provenance. This is the specification level of +link:../../rtl/adapters/amd_microblaze_v/[the MicroBlaze V adapter] -- +every behavioral rule in `mbv_trap_mapper.sv` and +`mbv_riscv_itype_decoder.sv` traces back to a row in this document. + +toc::[] + +[NOTE] +==== +**Status: G1 CLOSED for the MVP scope (2026-07-16, rounds 1-7).** All +semantics the **RV32 program-flow MVP** needs are empirically confirmed: +retirement (table 1, done), trap entry for 6 causes + the interrupt +discriminator (table 2, done except access faults), trap return (table 3, +done), RVC/`ilastsize` (table 5, done, **R3 disproved**). `Trace_Valid_Instr` +is -- as feared -- **not** architectural retirement; the confirmed rule is +`iretire = Valid_Instr && !Exception_Taken`. + +**Deliberately left open (do NOT block the MVP adapter):** + +* **Access faults** (rows 2.6/2.7/2.9, causes 5/7/1): **cannot be triggered** + on the LMB-only SoC (no bus with an error response). The cause mapping is + generically confirmed (`ecause = Exc_Kind[3:0]` over 6 causes), these + causes follow the same rule. Verification with AXI peripherals is planned + **from Gate G4** on. +* **Special causes >15 / NMI / external break** (table 4): these ports are + **not exposed** on this IP configuration; unreachable in the MVP. The + `impdef` path (§5.3) remains a design decision, untested -> **P1**. +* **Data alignment** (table 6): data trace is **P2/G8**, not an MVP goal. +* **System questions** (table 7): Fmax/bandwidth/N-Trace coexistence -- + **non-semantic**, do not block the adapter logic (bandwidth/overflow + belong to Gates G5/G6, coexistence to the cross-validation work). + +=> **Adapter approval granted for the MVP program-flow scope.** Every row +above remains a **blocker for its own scope** (data trace, special causes, +FPGA bandwidth) and must be measured before the corresponding gate. +==== + +== Version pin (R1 -- the `TRACE` bus is not version-stable) + +Every measurement holds **only** for exactly this configuration. On a +version change: a new table. + +[cols="1,3", options="header"] +|=== +| Field | Value + +| Vivado version | **2026.1** +| MicroBlaze V IP version | **`xilinx.com:ip:microblaze_riscv:1.0`** +| MBV config | RV32 - C-ext OFF - M-ext ON - Machine mode - MMU OFF - Trace Bus IF ON (Appendix A) +| CTTE pin | `3a74ea5` (`tip_pkg` 4-bit `ecause`, `itype` 0-15) +| Board / sim | Kria **KR260** (`xck26`) - **behavioral XSIM** (`tb_mbv_g0_soc`) +| Measurement method | XSIM on the external `Trace_*` ports - object dump (`sw/.../build/*.oracle.csv`) as the oracle +| Measured by / on | Rounds 1-7: **2026-07-16** (ecall/ebreak/mret - external interrupt - illegal - full-cycle/PipeRun - misaligned L/S - interrupt-on-branch - **RVC/R3**; rest open) +|=== + +== Measurement methodology + +1. Stimulus: `sw/microblaze_v_ctrace_demo/` (Appendix B programs), object dump = static image. +2. Capture: ILA/XSIM on `Trace_PC, Trace_Instruction, Trace_Valid_Instr, Trace_Jump_Taken, + Trace_Exception_Taken, Trace_Exception_Kind` **+ `Trace_OF/EX/MEM_PipeRun` + `Trace_Halted`** + (newly discovered pipeline-run signals -- disambiguate retire vs. stall) (+ the data + `Trace_*` signals for §8). Note: `Trace_Privilege_Mode`/`Trace_PID_Reg` do **not** exist on + this IP version (see link:microblaze_v_trace_ports.adoc[`microblaze_v_trace_ports.adoc`]). +3. Per scenario: log the AMD signals cycle-by-cycle against the expected instruction sequence. +4. Derive the TIP target values (`iretire/itype/ecause/impdef`) from that and record them here -> + feeds `mbv_trap_mapper.sv` (G3) + finalizes the trap rows of the `tb_mbv_trap_mapper` vectors. + +''' + +== Table 1 -- basic retirement behavior + +Confirmed: does `Trace_Valid_Instr` deliver exactly one strobe per +**normal** (non-trap) instruction? + +[cols="1,3,3,2,2,3,1", options="header"] +|=== +| # | Scenario | Expectation (hypothesis) | `Trace_Valid_Instr` measured | Strobes / instr | `iretire` rule | Confirmed? + +| 1.1 | linear ALU sequence (`trace_test`) | 1 strobe per instr, `iretire=1` | **=1 per instr** | **1** (PC sequence 1:1 with retires, 4000/4000 == oracle) | `iretire=1` at `Valid_Instr=1 && !Exc_Taken` | Yes +| 1.2 | load-use stall / pipeline bubble (`data_trace_test`, full-cycle window) | strobe only on retire, not every cycle | **confirmed**: 531 strobes / 1101 cycles (48.2 %) | **1** (single-cycle pulse) | stall => `Valid_Instr=0`; **`Trace_OF_PipeRun=0`** marks a stall (295x, **exactly 1 cycle each**, 26.8 %) | Yes +| 1.3 | taken branch | strobe on the branch, `TAKEN_BRANCH` | **=1** at the branch, `Trace_Jump_Taken=1` | **1** | `iretire=1` | Yes +| 1.4 | not-taken branch | strobe, `NOT_TAKEN_BRANCH` | **=1**, `Trace_Jump_Taken=0` | **1** | `iretire=1` | Yes +| 1.5 | multi-cycle (`mul`, M-ext; `data_trace_test` @0x130) | exactly 1 strobe on completion | **=1 on completion** | **1** (no double strobe in the whole window) | `iretire=1` | Yes (`div` not tested) +|=== + +== Table 2 -- trap entry (the actual risk zone, §5.2) + +Core question: is the trap coupled to the **predecessor** (`iretire=1`) or +to the faulting instruction (`iretire=0`)? Is the faulting instruction even +presented on `Trace_Instruction`? + +[cols="1,3,3,3,2,2,1,1,1", options="header"] +|=== +| # | Trap scenario | AMD `Trace_Exception_Kind` | Faulting instr on the bus? | Expected `itype` | Expected `iretire` | `ecause` (4 bit) | `impdef` | Confirmed? + +| 2.1 | external machine interrupt (edge, in a loop, `interrupt_test`) | **0x2b** = `{bit5=1 INT, cause=0x0b=11 MEXT}` | at the **preempted** instr 0x16c (mepc=0x16c -> **re-executed**) | `INTERRUPT` | **`0`** (0x16c does NOT retire; `Valid_Instr=1`) | `icause` MEXT=11 (`Exc_Kind[4:0]`) | 0 | Yes +| 2.2 | external machine interrupt **on** a branch (`interrupt_test`, `bne` @0x178, hit **8x**) | **0x2b** (bit5=1 INT, cause=11 MEXT) | at the **preempted** branch instr; **`Trace_Jump_Taken=0`** (the branch never resolves) | `INTERRUPT` | **`0`** (re-executed after mret) | `icause` MEXT=11 | 0 | Yes +| 2.3 | `ecall` from M-mode (`trap_test`) | **0x0b=11 (RISC-V mcause directly)** | **YES** (PC=0xfc, `Valid_Instr=1`) | `EXCEPTION_TRAP` | **`0`** (despite `Valid_Instr=1`! trap rule) | `ECALL_FROM_M=11` (direct) | 0 | Yes +| 2.4 | `ebreak` (`trap_test`) | **0x03=3** | **YES** (PC=0x104, `Valid_Instr=1`) | `EXCEPTION_TRAP` | **`0`** (despite `Valid_Instr=1`) | `BREAKPOINT=3` (direct) | 0 | Yes +| 2.5 | illegal instruction (`illegal_test`, `.word 0x0` @0x104) | **0x02** (bit5=0 sync, cause=2) | **YES** (PC=0x104, instr=0, `Valid_Instr=1`) | `EXCEPTION_TRAP` | **`0`** (`Valid_Instr=1`; mepc+4 -> 0x108) | `ILLEGAL_INSTR=2` (direct) | 0 | Yes +| 2.6 | load access fault | 5? | | `EXCEPTION_TRAP` | `0`? | `LOAD_FAULT=5` | | No +| 2.7 | store access fault | 7? | | `EXCEPTION_TRAP` | `0`? | `STORE_FAULT=7` | | No +| 2.8 | misaligned **load** (`misaligned_test`, `lw` @0x104, addr 0x131) | **0x04** (bit5=0 sync, cause=4) | **YES** (`Valid_Instr=1`) | `EXCEPTION_TRAP` | **`0`** (rule 2) | `MISALIGNED_LOAD=4` (direct) | 0 | Yes +| 2.8b | misaligned **store** (`misaligned_test`, `sw` @0x114, addr 0x132) | **0x06** (bit5=0 sync, cause=6) | **YES** (`Valid_Instr=1`) | `EXCEPTION_TRAP` | **`0`** (rule 2) | `MISALIGNED_STORE=6` (direct) | 0 | Yes +| 2.9 | instruction access fault | 1? | | `EXCEPTION_TRAP` | `0`? | `INSTR_FETCH_FAULT=1` | | No +| 2.10 | page fault (only if MMU on -- MVP: MMU off) | 12/13/15? | | `EXCEPTION_TRAP` | | n/a MVP | | No +|=== + +== Table 3 -- trap return + +[cols="1,4,2,2,4,1", options="header"] +|=== +| # | Scenario | Instr | Expected `itype` | `iretire` | Confirmed? + +| 3.1 | `mret` after an interrupt (`interrupt_test`, rounds 2/6) | `mret` @0xe4 | `EXCEPTION_IR` (=3) | **`iretire=1`** (`Valid_Instr=1`, `Exc_Taken=0`); `Trace_Jump_Taken=1`, target = mepc (= the preempted instr, e.g. 0x16c) | Yes +| 3.2 | `mret` after a synchronous exception (`trap_test`) | `mret` @0xe4 | `EXCEPTION_IR` (=3) | **`iretire=1`** (`Valid_Instr=1`, `Exc_Taken=0`); AMD also sets **`Trace_Jump_Taken=1`**, target=mepc | Yes +| 3.3 | `sret` (only if S-mode -- MVP: M-only) | `sret` | `EXCEPTION_IR` | ? | No +|=== + +== Table 4 -- special causes (>4 bit, §5.3 -> `impdef` procedure) + +`tip_ecause` is **4 bit**; AMD causes that do not fit -> an `ecause` +fallback + the full code in `impdef[5:0]`, `impdef[6]=special_cause`, +`impdef[7]=tval_unavailable`. + +[cols="1,3,2,2,2,2,1,1", options="header"] +|=== +| # | AMD special case | `Trace_Exception_Kind` | itype correct? | `ecause` fallback | `impdef[5:0]` | `impdef[6]` | Confirmed? + +| 4.1 | AXI4-Stream exception | 24? | | | | 1 | No +| 4.2 | NMI | 32? | | | | 1 | No +| 4.3 | external break | 48? | | | | 1 | No +|=== + +== Table 5 -- RVC raw encoding (Gate G7 pre-clarification; MVP: C-ext off) -- **R3 DISPROVED** + +[cols="1,5,8,1", options="header"] +|=== +| # | Question | Measurement | Confirmed? + +| 5.1 | Does `Trace_Instruction[31:0]` carry the **original** RVC encoding for a 16-bit instr (`instr[1:0]!=2'b11`), or an **expanded** 32-bit instr? | **ORIGINAL RVC, zero-extended** (`rvc_test` with `C_USE_COMPRESSION=1`): `c.li x11,7` @0xf6 -> `Trace_Instruction=0x0000459d` -- **not** the expansion `0x00700593`. Likewise `c.addi`=0x1141, `c.mv`=0x862e, `c.nop`=0x0001, `c.add`=0x9532, `c.jr`=0x8082. All with `[1:0] in {01,10} != 2'b11`; a 32-bit instr (`auipc`=0x00001117) has `[1:0]=11`. `Trace_PC` counts correctly in **2-byte steps**. G0 check for `rvc_test`: **PASS 4000/4000**. | Yes +|=== + +== Table 6 -- data-trace alignment (Gate G8 pre-clarification; MVP: data trace off) + +[cols="1,5,4,1", options="header"] +|=== +| # | Question | Measurement | Confirmed? + +| 6.1 | Are `Trace_Data_*` exactly retirement-cycle-aligned with the corresponding instr? | | No +| 6.2 | Is `Trace_New_Reg_Value` unambiguously the bus read value for **all** loads (sign/zero ext, `rd==x0`, AMO/LR/SC, faulting)? | | No +|=== + +== Table 7 -- system questions (timing / coexistence / bandwidth) + +[cols="1,5,4,1", options="header"] +|=== +| # | Question | Measurement | Confirmed? + +| 7.1 | Can the native AMD N-Trace encoder **and** the `TRACE` bus be active at the same time? (-> cross-validation) | | No +| 7.2 | Fmax effect of the wide `TRACE` port on the target config? | | No +| 7.3 | Output bandwidth/overflow behavior under branch-dense load (`trace_test` loop, worst case §6)? | | No +| 7.4 | Bit order `Trace_PC`/`Trace_Instruction`: VHDL `(0 to N-1)` <-> SV `[N-1:0]` -- bit-exact against the object dump? (R4, G0 criterion) | | No +|=== + +''' + +''' + +== Measurement results -- round 1 (2026-07-16, behavioral XSIM, `trap_test`/`trace_test`/`branch_test`) + +**Raw data** (external `Trace_*` ports, `tb_mbv_g0_soc`): format `PC, valid, exc_taken, exc_kind, jump_taken`. + +---- +Normal (linear/branch): every instr valid=1 exactly once, exc=0. Branch taken: jump_taken=1. +ecall @0xfc : valid=1 exc=1 exc_kind=0x0b(11) jump_taken=0 +ebreak @0x104: valid=1 exc=1 exc_kind=0x03(3) jump_taken=0 +mret @0xe4 : valid=1 exc=0 exc_kind=0x00 jump_taken=1 -> next PC = mepc (0x100) +---- + +== Measurement results -- round 2 (2026-07-16, external interrupt, `interrupt_test`) + +SoC extension: `mbv/Interrupt` external (edge), pulsed from the testbench @cycle 500 (no INTC IP). + +---- +Interrupt @0x16c (add, in a loop): valid=1 exc=1 exc_kind=0x2b(=43) jump_taken=0 + -> handler 0x40 ... mret 0xe4 (jt=1) -> RESUME @0x16c (mepc=0x16c -> 0x16c re-executed, does NOT retire) +Compare: ecall exc_kind=0x0b(=0b001011) ebreak=0x03(=0b000011) IRQ=0x2b(=0b101011) +---- + +**KEY FINDING (resolves the interrupt/exception ambiguity):** +`Trace_Exception_Kind[5]` = **interrupt flag** (1=interrupt, 0=synchronous +exception); `Trace_Exception_Kind[4:0]` = the RISC-V cause. Without this +bit, ecall (cause 11) and an external interrupt (MEXT 11) would be +indistinguishable -- with it, cleanly separable. + +**Confirmed rules -- feed `mbv_trap_mapper` (G3), AFTER completion + review + CTTD E2E:** + +1. **Cause + discriminator from `Trace_Exception_Kind`:** + `is_interrupt = Trace_Exception_Kind[5]`; + `cause = Trace_Exception_Kind[4:0]` (the RISC-V `mcause` low bits + directly: ecall->11, ebreak->3, MEXT->11). + => `ecause` (4 bit) = `cause[3:0]` for 0-15; the special-cause `impdef` + path (table 4) only applies for cause>15 (open). +2. **`Trace_Valid_Instr != iretire`** -- on both a trap and an interrupt, + `Valid_Instr=1`, yet the instruction does NOT retire (sync: the faulting + instr; async: the preempted instr, mepc=this instr). => + **`iretire = Trace_Valid_Instr && !Trace_Exception_Taken`** (confirmed + for both; the §2 warning is confirmed). +3. **Trap entry:** `Trace_Exception_Taken=1` => + `itype = Trace_Exception_Kind[5] ? INTERRUPT : EXCEPTION_TRAP`, + `iretire=0`, `ecause=cause`, `iaddr=Trace_PC`. **The interrupt + iaddr/iretire encoding is confirmed via CTTD E2E (G5).** +4. **Trap return:** `mret`/`sret` => `itype = EXCEPTION_IR`, `iretire=1`; + AMD additionally sets `Trace_Jump_Taken=1` (target=mepc). Distinguished + from a normal branch/jump via instruction decode. + +**CORRECTION to the original integration report §5.2:** the hypothesis +"interrupt coupled to the predecessor -> iretire=1" is **disproved** by +measurement -- the interrupt is reported at the **preempted** instr (which +re-executes, iretire=0), not at the retiring predecessor. Rule 2 applies +uniformly to synchronous traps and interrupts. + +== Measurement results -- round 3 (2026-07-16, illegal instruction, `illegal_test`) + +---- +illegal @0x104 (.word 0x00000000): valid=1 exc=1 exc_kind=0x02(bit5=0,cause=2) jump_taken=0 + -> handler 0x40 ... mret -> RESUME @0x108 (mepc+4, the illegal instr is skipped) +---- + +Confirms the rules over a **fault** class (not requested like ecall/ebreak): +`EXCEPTION_TRAP`, `iretire=0`, `ecause=2` direct, discriminator +`Exc_Kind[5]=0`. The trap-class triad is now complete (requested trap 11/3 +- fault 2 - async interrupt 0x2b). + +== Measurement results -- round 4 (2026-07-16, full-cycle window, `data_trace_test`) + +The testbench additionally logs **every cycle without gaps** +(`cycle_capture.log`, window cycles 1-1200) including the PipeRun signals -- +stall cycles are otherwise never visible (retire capture only shows +`valid`/`exc`). + +---- +Settled (cycles 100..1200, 1101 cycles): + Valid_Instr=1 : 531 cycles (48.2 %) OF_PipeRun=0 (stall): 295 cycles (26.8 %) + OF-stall run lengths: {1: 295} -> EXCLUSIVELY 1-cycle stalls + EX_PipeRun==0 : 0 cycles MEM_PipeRun==0 : 0 cycles (never stalled) + consecutive cycles with Valid_Instr=1 at the SAME PC: 0 -> no double strobe + Startup: 77-cycle OF stall after reset deassert (cycle 20) until the first retire (cycle 100) +---- + +**Confirmed (answers the §11 core question):** + +5. **`Trace_Valid_Instr` is EXACTLY ONE single-cycle pulse per retiring + instruction.** No double strobe (0 cases), no strobes per cycle during + stalls. Together with G0 (PC sequence == object dump, 6x4000/4000), + this confirms **1 strobe <=> 1 retiring instruction**. Also holds for + multi-cycle `mul` (table 1.5) -- one strobe on completion. +6. **`Trace_OF_PipeRun` is the stall indicator** (the only PipeRun that + stalls under this load); `Trace_EX/MEM_PipeRun` stayed **constant 1**. + Stalls are consistently **1 cycle** long here. +7. **NEVER derive `iretire` from PipeRun:** in **68 cycles**, `Valid_Instr=1` + occurred **while** `OF_PipeRun=0` -- PipeRun is diagnostic context, **not** + a retirement signal. Rule 2 (`Valid_Instr && !Exception_Taken`) remains + the only `iretire` source. + +[NOTE] +==== +**Measurement-scope caveat:** one workload (`data_trace_test`, LMB BRAM, no +caches/AXI). `EX/MEM_PipeRun` could well stall under a different load +(cache miss, AXI latency, `div`) -- this statement is workload-scoped. +==== + +''' + +== Round 8 (2026-07-16) -- `Trace_Instruction` stays put AFTER the retire + +**Trigger:** Gate G5 bring-up. Four E2E tests (`trap`/`illegal`/`misaligned`/`rvc`) +failed; the CTTD decode derailed. The cause was **not** the trap semantics, +but the bus hold time. + +**Measurement** (TIP capture `mbv_ctte_env`, `trap_test`, at the `mret` @ `0xe4`): + +---- +Cycle Trace_PC Trace_Instruction Valid_Instr -> our itype (before the fix) +191 0x000000e4 0x30200073 (mret) 1 -> EXCEPTION_IR (correct) +192 0x000000e4 0x30200073 (mret) 0 -> EXCEPTION_IR (GHOST EVENT) +193 0x000000e4 0x30200073 (mret) 0 -> EXCEPTION_IR (GHOST EVENT) +---- + +**Confirmed:** + +8. **`Trace_Instruction` (and `Trace_PC`) stay stable for ~2 more cycles + after a retire**, while `Trace_Valid_Instr` is already 0. The word is + **dead** in those cycles -- it does not describe an instruction that is + currently doing anything. Any evaluation of `Trace_Instruction` **MUST** + therefore be gated on `Trace_Valid_Instr` (or `Trace_Exception_Taken`). + +**Consequence for the adapter (rule 3):** + +[quote] +Drive `itype` only on a **real event**: `Exception_Taken` -> the trap +itype, else `Valid_Instr` -> the decoder itype, **else `OTHER`**. Ungated, +one `mret` is reported to the encoder as **three** events. + +**Why this derails the encoder (and is not merely cosmetic):** CTTE +evaluates `itype` for control flow **without** an `iretire` gate +(`ct_L23_preproc_composer_etip`: `IsControlFlowInstruction(tip.itype)`; +`iretire` only steers the halfword count). The ghost events therefore +produce extra indirect-branch messages -> the message stream derails -> +CTTD aborts. + +**Boundary -- `iretire=0` is NOT the problem:** that is exactly how a +trapping instruction is correctly reported (upstream `cpu_model`: +`exception_trap(no_retire=1)`). What must be suppressed are cycles +**without an event**, not cycles without a retire. + +**Test lesson:** the adapter unit testbench had let this bug **through +unnoticed** -- its stall vector used a `nop`, which decodes to `OTHER` +anyway. Green, without checking anything. Idle-cycle vectors need a +**control-flow word** (a stale `mret`/`jalr`/`jal`) sitting on the bus -- +the constellation that actually occurs. + +== Measurement results -- round 5 (2026-07-16, misaligned load/store, `misaligned_test`) + +---- +misaligned LOAD @0x104 (lw x6,0(x5), addr 0x131): valid=1 exc=1 exc_kind=0x04 (bit5=0, cause=4) +misaligned STORE @0x114 (sw x10,0(x7), addr 0x132): valid=1 exc=1 exc_kind=0x06 (bit5=0, cause=6) + -> handler mepc+4 skips the access; G0 for this program also PASS (4000/4000) +---- + +Confirms rules 1-3 on another trap subclass (**data-access fault**). **Cause +coverage now: 2 (illegal) - 3 (ebreak) - 4 (misaligned load) - 6 (misaligned +store) - 11 (ecall) - 11+bit5 (MEXT IRQ)** -- all directly from +`Trace_Exception_Kind[4:0]`, discriminator `[5]` correct throughout. + +== Measurement results -- round 6 (2026-07-16, interrupt on a branch, `interrupt_test`) + +Method: interrupt pulsed **periodically** (period 37 cycles, coprime to the +~9-cycle loop) -> over the run the interrupts hit **rotating loop +positions**; a simulation instead of a pulse-timing gamble. + +---- +69 interrupt entries, exc_kind uniformly 0x2b. Hit loop PCs (all 7): + 0x160 (22x) 0x164 (8x) 0x168 (8x) 0x16c (8x) 0x170 (7x) 0x174 (8x) 0x178 (8x, bne = LOOP BRANCH) +Interrupt ON the branch 0x178: valid=1 exc=1 exc_kind=0x2b jump_taken=0 +Entries with jump_taken=1 : 0 / 69 Entries with valid_instr=0 : 0 / 69 +G0 for this run despite 69 interrupts: PASS (4000/4000) +---- + +**Confirmed:** + +8. **An interrupt on a branch behaves like on any other instruction** + (table 2.2): reported at the **preempted** branch instr, `iretire=0`, + re-execution after `mret`. +9. **`Trace_Jump_Taken` stays 0 when a branch is preempted** -- the branch + never resolves. => **`Exception_Taken=1` and `Jump_Taken=1` NEVER occur + together (0/69).** The §5.1 priority "trap entry before conditional + branch" is therefore **not actually contested by the hardware**; it + remains correct as a defensive rule but is not forced. (A *synchronous* + trap on a branch practically does not exist -- branches do not fault.) +10. **Rule 2 confirmed over 69 independent trap events** + (`valid_instr=1` without exception). + +== Measurement results -- round 7 (2026-07-16, RVC raw encoding -- **risk R3 disproved**) + +Setup: `rvc_test.S` (rv32imc, explicit `c.*` instructions; crt0 stays +`norvc`) on an SoC with `C_USE_COMPRESSION=1` (via `MBV_USE_COMPRESSION=1`; +**the MVP default stays 0**). + +---- +PC Trace_Instruction Oracle word Instr [1:0] +0x00f0 0x00001141 0x00001141 c.addi x2,-16 01 16-bit +0x00f4 0x00004505 0x00004505 c.li x10,1 01 16-bit +0x00f6 0x0000459d 0x0000459d c.li x11,7 01 16-bit <- NOT 0x00700593 (the expansion) +0x00fa 0x0000862e 0x0000862e c.mv x12,x11 10 16-bit +0x00fc 0x00000001 0x00000001 c.nop 01 16-bit +0x0000 0x00001117 0x00001117 auipc (crt0) 11 32-bit +G0 check rvc_test: PASS 4000/4000 (0 instr deviations) PC step size: 2 bytes +---- + +**Confirmed -- corrects the original integration report §5.4 / risk R3:** + +11. **`Trace_Instruction` carries the ORIGINAL RVC encoding** (zero-extended + into the 32-bit field), **not** the expanded 32-bit instruction. The + RISC-V length encoding therefore stays visible. +12. => **`ilastsize = (Trace_Instruction[1:0] == 2'b11) ? 1 : 0`** is + **directly derivable** -- **no extra source needed**. **Risk R3 ("RVC + length not recognizable") is therefore disproved; Gate G7 is + significantly cheaper than planned.** `Trace_PC` counts correctly in + 2-byte steps. + +[NOTE] +==== +**Side finding (a real bug, found by this run):** the linker script was +missing an `ALIGN(4)` before `_bss_start`. Without RVC, `.text` happened to +end word-aligned; **with** RVC it lands on a 2-byte boundary -> +`_bss_start` misaligned -> crt0's word store `sw x0,0(t0)` trapped +MISALIGNED_STORE **before** `mtvec` was set -> trap to vector 0 -> an +infinite restart loop. Fixed (`. = ALIGN(4);` before `_bss_start`); latent, +it could have hit any build whose `.text/.data` did not happen to end +aligned. +==== + +**Still OPEN (not measured) -- G1 NOT closed for this:** load/store +**access** faults + instruction fetch fault (table 2.6/2.7/2.9 -- need +unmapped addresses; presumably **cannot be triggered** with pure LMB BRAM +without an AXI error response -> clarification once AXI peripherals exist +from G4 on), special causes >15 (table 4) incl. NMI/external break (ports +not exposed on this config -- possibly via `C_ENABLE_DISCRETE_PORTS`), data +alignment (table 6), system questions (table 7). => +**`mbv_trap_mapper` was only implemented after the table was complete + +reviewed + CTTD E2E.** + +== Consequences for the adapter (round 1 confirmed; rest after completion) + +* **`mbv_trap_mapper.sv` (G3):** `iretire = Valid_Instr && !Exc_Taken`; + trap entry -> `Exc_Kind[5] ? INTERRUPT : EXCEPTION_TRAP` (iretire=0, + `ecause = Exc_Kind[3:0]` direct); `mret`/`sret` -> `EXCEPTION_IR` + (iretire=1). **Both the sync and the interrupt branch are confirmed** + (rounds 1-3, 5, 6 over 6 causes + 69 interrupt events); only special + causes >15 remain open. +* **`mbv_riscv_itype_decoder.sv` (G2):** the §5.1 priority "trap entry + before conditional branch" is **not contested** by the HW -- on a + preempted branch, `Jump_Taken=0` (0/69 collisions). The rule is still + implemented defensively (`Exc_Taken` dominates), but no special-casing + is needed. +* **`ilastsize` (MVP + G7):** in the MVP (C-ext off), constant **1**. For + G7 the confirmed rule is + **`ilastsize = (Trace_Instruction[1:0] == 2'b11) ? 1 : 0`** -- no extra + source needed (round 7, R3 disproved). +* **`mbv_trace_normalizer.sv`:** bit order -- no mirroring needed at the + word level (confirmed by G0); sub-field mapping at G4. +* **PipeRun NOT in the `iretire` path:** `Trace_OF/EX/MEM_PipeRun` are + diagnostic/stall context (confirmed: `Valid_Instr=1` occurred 68x + **while** `OF_PipeRun=0`). Usable as an optional cover property/debug + sideband, **never** as a retirement source. +* **Assertions:** the confirmed invariants "`Trace_Exception_Taken => + tip.iretire==0`", "`!Valid_Instr && !Exc_Taken => !iretire`" and "no + `Valid_Instr` in two consecutive cycles at the same `Trace_PC`" (round 4: + 0 cases). + +== Sources + +* The MicroBlaze V implementation concept (itype/retirement/trap, open + measurement questions) and the technical integration report (the itype + priority, the assertions) are internal Accemic documents that are not part + of this repository; everything from them that an integrator needs -- the + itype priority, the retirement and trap semantics, the assertions -- is + stated in this document and enforced by the adapter under + `rtl/adapters/amd_microblaze_v/`. +* Authoritative TIP enums: `rtl/pkg/tip_pkg.sv` (`tip_itype_e`, + `tip_ecause_e`, `icause_e`). diff --git a/doc/adapters/rocket_tci_semantics.adoc b/doc/adapters/rocket_tci_semantics.adoc new file mode 100644 index 0000000..6c7d393 --- /dev/null +++ b/doc/adapters/rocket_tci_semantics.adoc @@ -0,0 +1,299 @@ +// SPDX-FileCopyrightText: 2026 Accemic Technologies GmbH +// SPDX-License-Identifier: CC-BY-4.0 + += Rocket TraceCoreInterface truth table (G1, R3.2a + M3 context) +:toc: macro +:toclevels: 2 + +Migrated 2026-08 from an internal predecessor repository; see +link:../../rtl/adapters/README.md[`rtl/adapters/README.md`] for the +package-level provenance. This is the specification level of +link:../../rtl/adapters/rocket/[the Rocket adapter] -- every clamp in +`rocket_tci_to_ctte_tip.sv` traces back to a finding in this document. + +**Measured against** RocketSystem rocket64t1/rocket64t2, rocket-chip pin +`e01cf19f`/`f517abbf` + trace-ingress patches; measurements dated +2026-08-04, last updated 2026-08-08. +**Status:** R3.2a GREEN (TB_PASS 432 cycles, checker PASS: 104 retire + 4 +trap beats, gapless PC sequence from the reset vector `0x10040`; 4 checker +mutation counter-probes red), 3 upstream trace defects U1-U3 measured. M3 +GREEN (the context edge measured on the 2-hart netlist rocket64t2: TB_PASS +321 cycles, checker PASS, 4 CSV mutation counter-probes red). + +toc::[] + +**Measurement setup (CTTE-free):** `sim/rocket/tb_rocket_char.sv` +instantiates the vendored generated netlist +`third_party/rocket_ref/system-nexys-video.v` (top module `RocketSystem`, +config `rocket64t1` = RV64IMAC without an FPU, retireWidth 1, +`ROCKET_PIN.md`) standalone under XSIM 2026.1 -- without CTTE, without the +shim. Testbench-own models: `rocket_axi_ram_sim` (mem_axi4, 4 MiB +@0x8000_0000, `$readmemh`) + `rocket_axi_mmio_sim` (mmio_axi4, EXIT +@0x6000_0000); DMI/l2_frontend/interrupts idle. Workload +`sw/rocket_char/char_test.S` (RV64IMAC, M-mode, `-Ttext=0x80000000`, +deterministic). Checker `tools/rocket_tci_check.py`: a static oracle = a PC +walk over the instruction semantics from `char_test.dis` + `rom.dis` (NO +RVFI on this netlist); cross-reference: the netlist's built-in commit-log +printer delivered **108 `C0:` lines == 104 retire + 4 trap beats** in the +same run (1:1). Checker sharpness: 4 mutation counter-probes +(branch-verdict, mret-code, line-drop, ilastsize) -> all `== FAIL ==`. + +**Bootrom redirection (D-R32a-1):** reset vector 0x10040 +(Frontend.scala:117, netlist `:68830`). There, hart 0 jumps via +`jal zero,0x10016` into the nexys-video bootrom's SD-card bootloader +(C code @0x11462, polls SDC/UART -- a dead path in simulation that would +otherwise zero word 0 of the workload). The run therefore compiles a +work-local netlist copy with ONE patched ROM word (index 0xb: +`jal zero,0x10016`->`jal zero,0x10000`, 0xfbfff06f-> 0xfa9ff06f; +`sim/rocket/extract_tlrom.py`, self-verifying) -- hart 0 then takes the +existing ROM direct entry 0x10000 (`c.jr s0`) into 0x8000_0000. The +vendored file itself stays untouched; the same patched image is the oracle +basis (`rom.dis`), the ROM preamble (13 instructions) is walked through by +the checker too. A conditional `force` on the TLROM data bus did NOT work +under XSIM 2026.1 (the commit log showed the original word) -- +compile-time patching is simulator-independent. + +== Beat semantics (measured) + +Combinational tap of the WB stage, 1 retire/cycle. `iretire` = `valid` = +`wb_valid || wb_xcpt` -- **trap beats ALSO carry iretire=1** (U1). itype +priority exception->interrupt->trap_return->br_taken->br_ntaken->jal->jalr +(TraceCoreIngress, netlist `:76861-76886`). **Idle cycles are NOT +neutral:** itype holds the decode of the last instruction (wb_ctrl +unchanged), in the 432-cycle run **161 hanging classification lines at +iretire=0** (37x TAKEN_BR, 71x ITUnJump, 53x ITInJump) -- a consumer MUST +gate itype with iretire (shim idle-cycle rule, point 3). Not a single +`iretire=0 + itype=EXC/INT` beat (the clamp does not swallow any traps). + +== Event -> beat (measured, `char_test` @ rocket64t1) + +[cols="3,1,2,1,1,1,1,1", options="header"] +|=== +| Event | itype | iaddr | iretire | ilastsize | cause | tval | Count + +| ALU/load/store/csr/auipc/... | 0 | PC of the instr | 1 | 1 (32-bit) | 0* | 0 | 62 +| branch not-taken (incl. 64-bit discr., c.bnez) | 4 | PC of the branch | 1 | per encoding | 0* | 0 | 9 +| branch taken (incl. 64-bit discr., c.beqz) | 5 | PC of the branch | 1 | per encoding | 0* | 0 | 4 +| `jal` / `j` / `c.j` | 15 | PC of the jump | 1 | per encoding | 0* | 0 | 18 +| `jalr` call, `jalr` return, `c.jr`, `c.jalr` | 14 | PC of the jump | 1 | per encoding | 0* | 0 | 7 +| `mret` | **13 (ITReturn, U2!)** | PC of the mret | 1 | 1 | 0* | 0 | 4 +| `ecall` (M) | 1 EXC | PC of the ecall | **1 (U1!)** | 1 | **4 (U3!) instead of 11** | 0 | 1 +| illegal instr (`csrrs hgatp` without RVH) | 1 EXC | PC of the instr | **1 (U1!)** | 1 | 2 | **the instruction word** (0x680022f3) | 1 +| `ebreak` | 1 EXC | PC of the ebreak | **1 (U1!)** | 1 | **4 (U3!) instead of 3** | 0 | 1 +| MSIP IRQ (CLINT @0x0200_0000) | 2 INT | PC of the interrupted instr | **1 (U1!)** | 1 | **0x8000_0000_0000_0003 (MSB bit 63)** | 0 | 1 +|=== + +\* cause/tval on non-trap beats are NOT zeroed, they carry the leftover +state of the data path (in this run 0 resp. the last-seen values) -- only +evaluate them at itype 1/2. + +`ilastsize`: 0 = 16-bit, 1 = 32-bit encoding -- measured over 10 compressed ++ 94 32-bit retires (golden from the `.dis` encoding length, 0 errors); +the source is `valid & ~(&raw_inst[1:0])`, i.e. 0 on idle cycles. + +`priv`: constant 0x3 (M-mode); the 4-bit top port = +`{1'd0, Cat(reg_debug, prv)}` (netlist `:79630`) -- bit 3 constant 0, bit 2 += debug flag (not exercised). + +`time`: **free-running cycle counter of the CSR** (WideCounter, `:73982`; +measured delta_time == delta_cycle == 362, ratio 1.0000) -- NOT CLINT mtime +(which ticks at /100 = 1 MHz). `ctx`: **no port on this netlist** (0 hits +in the 8.8 MB netlist; the `csr.io.ptbr.asid` path from the R0-A3 report +does not exist at this rocket-chip pin's TraceCoreInterface export). + +== Upstream trace defects (measured; upstream PR candidates) + +[cols="1,3,3,4", options="header"] +|=== +| # | Defect | Evidence | Consequence + +| U1 | Trap beats carry `iretire=1` (`iretire := valid`, `valid = wb_valid \|\| wb_xcpt`) | all 4 trap beats had iretire=1 | shim clamp 1 (EXC/INT => iretire=0) is MANDATORY -- otherwise the composer counts the faulting instr in ICNT +| U2 | `trap_return -> ITReturn (13)` instead of `ITExcReturn (3)` | 4/4 mret beats = 13, 13 ONLY at mret PCs; jalr returns = 14 | shim clamp 2 (13->3) is unambiguous + lossless; `MAP_TRAP_RETURN_TO_ERET` default=1 FIXED. Statically: `trap_return = insn_ret` (CSR decode) also covers sret/dret +| U3 | **NEW:** the trace `cause` = `wb_reg_xcpt ? wb_reg_cause : ` (netlist `:79663`) -- for traps raised internally by the CSR (ecall/ebreak, wb_xcpt=0) the beat carries the data-path leftover **4** instead of mcause 11/3 | the ecall beat cause=4, the ebreak beat cause=4; illegal (2) and IRQ (MSB\|3) correct; mcause correctness is **structurally** confirmed (audit C-R32a-A3): the CSR raises ecall/ebreak internally via `insn_call/insn_break` (`system-nexys-video.v:71775-71776`), and the trace-cause mux's value list at `:79663` does not contain 11/3 at all -- the defect sits exclusively in the trace path (the workload handler only discriminates bit 63, so it is NOT sufficient evidence by itself) | `ecause` at the TCI is NOT trustworthy for ecall/ebreak; not fixable in the shim (no discriminating information). The N-Trace wire is unaffected (ecause never goes out); E-Trace-format-3.x users must know this case +|=== + +Plus an ergonomics finding (not a defect, but a contract): **hanging itype +classifications on idle cycles** (see above) -- Rocket's own encoder chain +gates internally with iretire, every external consumer must do the same. + +== G1 questions -> answers (the measurement list from R3.1a §5) + +[cols="1,3,4,3", options="header"] +|=== +| # | Question | Answer | Evidence + +| 1 | iretire on trap beats? | **1**, iaddr = PC of the faulting/interrupted instr (wb_reg_pc) | 4 trap-beat rows (table above; CSV cycle 299/318/337/381) +| 2 | Code 13 only from trap_return? | **YES** -- 4/4 mret = 13, no 13 elsewhere; function returns = 14 | xRET beats @0x800000f4 (3x) + @0x80000110; checker gate "13 only at xRET" +| 3 | iretire=0+EXC/INT beats? | **NONE** (hanging rows only itype 5/14/15) | the checker's hanging-classification histogram +| 4 | priv encoding | 4-bit port `{1'd0, reg_debug, prv}`; constant 0x3 in M-mode; debug bit = bit 2, **not exercised** | netlist `:79630`; priv value set {0x3} +| 5 | Codes 8-12 observed? | **NO** -- the emission set = {0,1,2,4,5,13,14,15}; 3/6/7 never either | itype histogram; TraceCoreIngress `:76877-76885` only emits these +| 6 | ilastsize semantics | 0 = 16-bit, 1 = 32-bit (log2 halfwords); valid-gated | 10 compressed + 94 32-bit retires, 0 golden errors +| 7 | cause MSB on IRQ | interrupt flag on **bit 63** of the 64-bit field | the INT beat cause=0x8000000000000003 +| 8 | ctx | `rocket64t1`: **no ctx export** (the connection binds `tci_ctx_i='0`). `rocket64t2` (M2): `trace_core_N_context[63:0]` = the satp image, **the edge and WARL measured in §Context (M3)** | t1: grep 0 hits, top ports `:98742-98749`. t2: top ports `:101303`/`:101312`, driver `:81054`/`:81645` +| 9 | time behavior | 64 bit, monotonic, **+1 per cycle** = the CSR cycle counter (WideCounter), not mtime | ratio 1.0000 over 362 cycles; netlist `:73982` +| 10 | port widths (D12) | iretire/ilastsize 1 - iaddr 64 (**only 40 driven**: `{24'd0, wb_reg_pc}`) - itype 4 - priv **4** (not 3; MSB const. 0) - tval 64 (**only 40 driven**) - cause/time 64 - **ctx missing** | netlist `:98742-98749`, `:79775`, `:79630-79633` +|=== + +== Context (M3, 2026-08-08) -- context edge, WARL and hart binding + +**Measurement setup (CTTE-free, a second run on the same bank):** +`sim/rocket/tb_rocket_ctx.sv` instantiates the **2-hart** netlist +`third_party/rocket_ref/rocket64t2/system-nexys-video.v` (M2) standalone +under XSIM 2026.1 -- the same testbench models, the same one-word bootrom +patch (D-R32a-1, now via `extract_tlrom.py --gen`), but a **cycle-exact** +log of all context signals for **both** harts. Workload +`sw/rocket_char/ctx_test.S` (M-mode, six `csrw satp`); checker +`tools/rocket_ctx_check.py`. The run ends after **321 cycles** with +`### TB_PASS` and `== PASS ==`; two independent runs produced an +**md5-identical** CSV (`0E5C8351F897CBB30934C97325E50B47`, 271 rows). + +Why M-mode is sufficient: `satp` only affects translation in S/U, the write +access itself is privilege-independent, and the edge sought is a +pipeline/register property of the WB stage. What is measured is the +**port**, not the translation. + +=== Context edge (the actual question) + +Port value = `{satp.MODE[63:60], 16'h0, satp.PPN[43:0]}` (netlist `:81054` +/ `:81645`; the ASID slice is the literal `16'h0` -- M2 §1). + +[cols="1,1,1,1,2,2,2,1,1,2", options="header"] +|=== +| # | Symbol | PC | Cycle | satp write value | Port BEFORE the beat | Port after | Edge after | Retires in between | Next retire + +| 1 | `w1_satp` | `0x80000024` | 151 | `0x8000000000000111` | `0x0000030f07d7b30f` | `0x8000000000000111` | 1 cycle | 0 | `0x80000028` carries `0x8000000000000111` +| 2 | `w2_satp` | `0x80000040` | 187 | `0x8000000000000222` | `0x8000000000000111` | `0x8000000000000222` | 1 cycle | 0 | `0x80000044` carries `0x8000000000000222` +| 3 | `w3_satp` | `0x8000005c` | 202 | `0x0000000000000000` | `0x8000000000000222` | `0x0000000000000000` | 1 cycle | 0 | `0x80000060` carries `0x0000000000000000` +| 4 | `w4_satp` | `0x8000007c` | 214 | `0x80000fffffffffff` | `0x0000000000000000` | `0x80000000003fffff` | 1 cycle | 0 | `0x80000080` carries `0x80000000003fffff` +| 5 | `w5_satp` | `0x80000098` | 245 | `0x9000000000000555` | `0x80000000003fffff` | *(no edge)* | **discarded** | 10 retires without motion | `0x8000009c` carries `0x80000000003fffff` +| 6 | `w6a_satp` | `0x800000c0` | 284 | `0x8000000000000666` | `0x80000000003fffff` | `0x8000000000000666` | 1 cycle | 0 | `0x800000c4` carries `0x8000000000000666` +| 7 | `w6b_satp` | `0x800000c4` | 289 | `0x8000000000000777` | `0x8000000000000666` | `0x8000000000000777` | 1 cycle | 0 | `0x800000c8` carries `0x8000000000000777` +|=== + +**Answer: the beat of the writing instruction still carries the OLD value; +the new one appears exactly ONE cycle later, with NO retire in between.** +The next retiring instruction therefore already carries the new context +(column "next retire", 6/6 edges). Structural cause: the port hangs off the +REGISTERS `reg_satp_mode`/`reg_satp_ppn` (`assign io_ptbr_* = +reg_satp_*`, `:75988-75989`), which only update on the clock edge -- the +trace beat of the `csrw` instruction is generated combinationally from the +same WB stage, i.e. before that. + +**Consequence for the shim: NOTHING to compensate.** The placement is +exactly the desired one -- the writing instruction still semantically +belongs to the old address space (it is part of the predecessor's switch +code), the first instruction after it belongs to the new one. Delaying by +one beat would be a bug, not a fix. `rocket_tci_to_ctte_tip` correctly +reports the change with `ctype = PRECISELY` on exactly this first beat of +the new context. + +**Global gate (E9):** over the whole run there were **6 context changes, +all in the cycle following a `csrw satp`**. In particular, `sfence.vma` +(`w2_sfence` @`0x80000048`) does **not** move the context, nor do jumps, +idle cycles, or the ROM preamble. + +=== WARL: only 22 of the 44 PPN bits are live + +[cols="2,3,4", options="header"] +|=== +| Property | Measurement | Structural evidence (rocket64t2) + +| PPN field width at the port | 44 bit (`context[43:0]`) | `reg [43:0] reg_satp_ppn` `:73977` +| **writable** PPN bits | **22** -- `0x80000FFFFFFFFFFF` becomes port `0x80000000003FFFFF` | `reg_satp_ppn <= {{22'd0}, new_satp_ppn[21:0]}` `:77358` (paddrBits 34 - pgIdxBits 12) +| MODE values | 0 (Bare) and 8 (Sv39) accepted | `_reg_satp_mode_T = new_satp_mode & 4'h8` `:75694` +| illegal MODE (9 = Sv48) | the write access fails **entirely**: MODE **and** PPN unchanged over the following 10 retires | gate `_T_1854 = (mode==0) \| (mode==8)` `:75691-75693` encloses BOTH assignments `:77350` / `:77357` +|=== + +The **ownership key of this core is therefore 22 bit wide**, not 44: +`CT_CONTEXT_WIDTH = 22` suffices for uniqueness, 44 is the field width (and +also the composer's maximum, `NEXUS_MSG_PROCESS_WIDTH`). The shim names +this via `SATP_PPN_LIVE_WIDTH` and warns loudly below that width +(`CTX_REQUIRE_UNIQUE_KEY=1` turns it into an elaboration abort). + +=== Hart binding and reset + +[cols="3,5", options="header"] +|=== +| Question | Measurement + +| Is the port a per-hart quantity? | **Yes.** Hart 1 -- never woken, stays in the bootrom's `wfi`/MSIP loop @`0x1005c`, 3 retires -- holds its context **constant** at `0x424921ad424` over the whole run, while hart 0 changes six times, and carries a **different** value than hart 0. A broadcast would have been caught here (counter-probe CM2). +| Reset value of satp? | **Only MODE is reset** (`if (reset) reg_satp_mode <= 4'h0`, `:77346-77348`); `reg_satp_ppn` has **no** reset branch at all -- its only occurrences are the `csr_wen` path `:77358` and the RANDOMIZE init `:77866`. Measured: hart 0 starts with `0x0000030f07d7b30f`, hart 1 with `0x0000042492 1ad424`; both RANDOMIZE garbage with a MODE nibble of 0. +|=== + +[NOTE] +==== +**Disclosure note:** the context is therefore **undefined between reset and +the first `satp` write** (in real hardware, the power-on state of the +flip-flops). An ownership filter armed for a specific PPN can hit randomly +in this window. This is not a shim defect -- the shim passes through +whatever the core carries -- and is manageable in practice as long as +filtering is only armed after kernel boot; it must, however, be considered +when evaluating a board run. +==== + +=== Checker sharpness (mutation counter-probes, CSV copies in the scratchpad) + +[cols="4,2", options="header"] +|=== +| Mutation | Result + +| CM1 the edge of `w1` moved one cycle earlier (the write beat already carries the new value) | `== FAIL ==` (E2 + E9) +| CM2 hart 1 mirrors hart 0 (a broadcast instead of a per-hart quantity) | `== FAIL ==` (E6) +| CM3 the illegal MODE-9 write access takes effect anyway | `== FAIL ==` (E5 + E2) +| CM4 the edge of `w2` delayed by two cycles | `== FAIL ==` (E3 + E9) +|=== + +**Self-finding on gate blindness:** the **first** version of the checker +stayed **green** on CM1. It derived the expectation from the port value *at +the checked beat itself* -- an early edge shifted both the observed and +the expected value together. The checker now runs an **independent WARL +state model** (seeded once from the initial value, then advanced only from +that model) plus the global gate E9. The same failure class as the three +blind gates elsewhere in this program; it only became visible because the +counter-probe ran BEFORE the result was accepted. + +== Open legs (explicit) + +* **S-/U-mode + Sv39:** not exercised (an M-mode workload; priv!=3 beats, + page-fault causes 12/13/15, satp activation open -- analogous to CVA6 + Gate L1). +* **Debug mode:** priv bit-2 behavior not exercised (no debugger attached + in the sim). +* **sret/dret:** statically covered by `insn_ret`, dynamically only mret. +* **PCs >= 2^40:** iaddr is only 40 bit driven; behavior above vaddrBits is + not representable in the 512-MiB window. +* **ilastsize on trap beats:** carries the value of the faulting instr + (here always 1) -- semantically without retire meaning, not further + characterized. +* The WFI/CEASE paths and Rocket's own in-tile encoder (TraceEncoder.scala) + are not part of this measurement. +* **Context (M3):** the edge is measured in **M-mode**. A real Linux + `switch_mm` (S-mode, a `satp` write + `sfence.vma` with active + translation, then `sret` to U) is therefore NOT exercised; the measured + property is a pipeline/register property and hence + privilege-independent, but the S/U run is still open. +* **Context (M3):** the ASID is not exercised because it is structurally 0 + on this netlist (M2 §1); a `satp` write from inside a trap handler and a + change that coincides with a trap beat are open on the netlist (covered + in the shim's unit gate `tb_rocket_tci_unit`, vector Vc8). + +== Reproduction + +WARNING: **Not reproducible from this repository.** The characterization +needs the vendored Rocket generated netlist (see +link:../../examples/kv260/third_party/ROCKET_PIN.md[`examples/kv260/third_party/ROCKET_PIN.md`]), +a bootrom patch, the stimulus programs `char_test`/`ctx_test`, and an XSIM +run with an oracle and a checker (gate: `TB_PASS` plus the checker's own +`== PASS ==`). The M3 context run additionally needs the 2-hart netlist +`rocket64t2`. None of those drivers are part of this repository, and the +raw data of the M3 green run (`ctx_log.csv`, md5 +`0E5C8351F897CBB30934C97325E50B47`, 271 rows, plus the run log) is not +either. + +What *is* reproducible here is the shim's own unit gate, which encodes the +same truth table -- including the width-neutral 2-bit and 44-bit context +builds and the deliberately-red `CtxWidth` probe: + +---- +bash scripts/cli_adapters_test.sh # includes tb_rocket_tci_unit +---- diff --git a/doc/architecture.adoc b/doc/architecture.adoc index 0c524ef..8dea210 100644 --- a/doc/architecture.adoc +++ b/doc/architecture.adoc @@ -6,9 +6,11 @@ :toclevels: 3 :nexus-spec: https://github.com/riscv-non-isa/riscv-nexus-trace/blob/main/docs/nexus-standard/IEEE-ISTO-5001-2012-v3.0.1-Nexus-Standard.pdf -The CEDARtools.TraceEncoder (`ct_encoder`, link:../rtl/ct_encoder.sv[`rtl/ct_encoder.sv`]) -turns a RISC-V core's instruction-trace port into a compressed, -{nexus-spec}[NEXUS-IEEE-ISTO-5001-2012-compliant] N-Trace byte stream. This page +The CEDARtools.TraceEncoder (CTTE) encoder +(`ct_encoder`, link:../rtl/ct_encoder.sv[`rtl/ct_encoder.sv`]) +turns a RISC-V core's instruction-trace port into a compressed N-Trace byte +stream per the {nexus-spec}[IEEE-ISTO 5001-2012 (Nexus) standard]; the known +deviations are listed in link:trace-format.adoc#conformance[trace-format]. This page describes the top-level module: its block diagram, clock domains, interfaces, pipeline stages, parameters, and a register-map overview. @@ -21,7 +23,7 @@ toc::[] == Block diagram -image::images/ct_encoder_elements.drawio.png[CEDARtools.TraceEncoder encoder elements,width=900] +image::images/ct_encoder_elements.drawio.png[CTTE encoder elements,width=900] Data flows left to right: the TIP enters in the `tip_clk` domain, the preprocessor crosses it into the `proc_clk` pipeline, and the MSEO/MDO @@ -149,11 +151,11 @@ each discoverable through a `trXxControl` (active bit) + `trXxImpl` Encoder (`te`, CompType `0x1`) and ATB Bridge (`atb`, CompType `0xE`) follow the standard component layouts (N-Trace Control Interface Table 4 and Chapter 10); the Performance-Counter, Watchpoint and DF-Filter blocks -are CEDARtools.TraceEncoder **vendor components** (CompType `0x3`/`0x4`/`0x5`) using the +are CTTE **vendor components** (CompType `0x3`/`0x4`/`0x5`) using the same discovery framework. NOTE: The CPU interface is generated by PeakRDL-regblock from the same RDL. -CEDARtools.TraceEncoder ships a Wishbone adapter over the passthrough interface, but the +CTTE ships a Wishbone adapter over the passthrough interface, but the bus is swappable — APB3/APB4, AXI4-Lite, Avalon-MM and OBI are supported by regenerating with a different `--cpuif`. @@ -163,9 +165,9 @@ by regenerating with a different `--cpuif`. | `0x0000-0x0FFF` | `te` | Trace Encoder (implements N-Trace) | `0x1` | `0x1000-0x1FFF` | `atb` | Trace ATB Bridge | `0xE` -| `0x3000-0x3FFF` | `pc` | Performance Counters (CEDARtools.TraceEncoder vendor) | `0x3` -| `0x4000-0x4FFF` | `wp` | Watchpoints / ACT-ST (CEDARtools.TraceEncoder vendor) | `0x4` -| `0x5000-0x7FFF` | `df` | DF Range Filter (CEDARtools.TraceEncoder vendor) | `0x5` +| `0x3000-0x3FFF` | `pc` | Performance Counters (CTTE vendor) | `0x3` +| `0x4000-0x4FFF` | `wp` | Watchpoints / ACT-ST — 1023-slot table, indirect load/readback registers (CTTE vendor) | `0x4` +| `0x5000-0x7FFF` | `df` | DF Range Filter (CTTE vendor) | `0x5` |=== Within the Trace Encoder block, the principal registers are @@ -196,11 +198,20 @@ the optional timestamp unit, and the `trTeFilter[]`/`trTeComp[]` arrays all match the spec; encoder-local extensions live in the spec's vendor range (`0xE00-0xFFF`). -The few deviations, all marked `[CEDARtools.TraceEncoder]` in the RDL and none breaking +The few deviations, all marked `[CTTE specific]` in the RDL and none breaking discovery: the `pc`/`wp`/`df` vendor components use unassigned `CompType` codes (`0x3`/`0x4`/`0x5`); a handful of `trTeControl` fields (`SendConfig`, the widened `InstSyncMode`, `InstSyncReq`) and -`trTeDataControl.DataSplitLoad` occupy spec-reserved bits. Unimplemented -optional features (triggers, the `trTeInstFeatures` compression options, -data-trace stall/drop, Ownership/Context emission, the RTL funnel's control -header) read as 0 — the spec-conformant way to advertise an absent option. +`trTeDataControl.DataSplitLoad` occupy spec-reserved bits. + +Optional features this encoder does not implement — the dedicated +trigger-configuration registers (`trTeTrigDbgControl` `0x050`, +`trTeTrigExtInControl` `0x054`, `trTeTrigExtOutControl` `0x058`), +data-trace hart stall / packet drop, and the RTL funnel's control header — +read as 0, the spec-conformant way to advertise an absent option. The same +applies, per build profile, to any feature compiled out via `ct_pkg.sv`: +in the full profile the `trTeInstFeatures` compression options, the +trigger-input path (`InstTrigEnable`) and Ownership/Context emission +(`trTeControl.Context`) are all present and writable, but a slim profile +turns exactly those bits read-only-0. See +link:trace-format.adoc#build-profiles[Trace format → Build profiles]. diff --git a/doc/development.adoc b/doc/development.adoc index 9c44d4f..b643e07 100644 --- a/doc/development.adoc +++ b/doc/development.adoc @@ -6,7 +6,8 @@ :toclevels: 3 This page covers the build flow, the SystemRDL register flow, the -contribution rules, and how to integrate CEDARtools.TraceEncoder into an SoC. +contribution rules, and how to integrate CEDARtools.TraceEncoder (CTTE) +into an SoC. toc::[] @@ -20,19 +21,169 @@ Every umbrella command is routed through the link:../Makefile[`Makefile`]: |=== | Target | What it does -| `make help` | List available targets. -| `make sim` | Run all encoder testbenches; print a PASS/FAIL summary. -| `make sim-` | Run one testbench (e.g. `sim-basic`) — see link:verification.adoc[Verification] for the scenarios. -| `make sim-tgc5b-soc` | Simulate the example SoC (`examples/tgc5b_soc`): real TGC5B core → encoder → NexRv decode. -| `make sim-tgc5b-ps` | Simulate the KV260 devmem flow around that SoC (`ct_soc_top`). -| `make sim-examples` | Run every worked integration under `examples/` (both of the above) with a PASS/FAIL summary — what CI runs next to `make sim`. -| `make impl-tgc5b-soc` | Out-of-context Vivado synthesis of the example SoC (resource / timing estimate). -| `make coverage` | Re-run the suite under Verilator line coverage and report one suite-wide rate. -| `make lint` | `verible-verilog-lint` over the repo's SystemVerilog. -| `make clean` | Remove the `bld/` directory. -| `make rdl` | Regenerate the PeakRDL-derived SV from `rdl/ct_cs_cpuif.rdl`. -| `make rdl-soc` | Regenerate the example SoC's peripheral regblock from `examples/tgc5b_soc/rdl/ct_soc.rdl`. -| `make rdl-html` | Render the browsable HTML register reference into `bld/rdl-html/`. +| `make help` | List available targets. +| `make sim` | Run all testbenches; print a PASS/FAIL summary. +| `make sim-` | Run one testbench (e.g. `sim-basic`). +| `make lint` | The eight host guards, then `verible-verilog-lint` over `rtl/` and `tests/`. +| `make clean` | Remove the `bld/` directory. +| `make rdl` | Regenerate the PeakRDL-derived SV from `rdl/*.rdl`. +| `make bld-bootstrap` | Generate the three xsim projects the gates clone (see <>). +| `make bld-refresh` | The same, but regenerate them even if they exist. +|=== + +[#fresh-tree] +=== Starting from a fresh clone or worktree + +`bld/` is gitignored, and every `cli_*_test.sh` gate drives +`xvlog`/`xelab`/`xsim` by hand over an xsim project that `abc` generates +below it. A tree that has never been built therefore has no project, and +that used to be reported as + +[source] +---- +FAIL: donor prj missing (.../repeated_history_tb.abc.sim/...) +FAIL: no prj at .../implicit_return_tb.abc.sim/... +---- + +by nineteen gates at once — and the byte-neutrality gates layered on top +summarised it as `BYTE NEUTRALITY: DRIFT / OVERALL: FAIL`, i.e. as a +drift verdict about an encoder that had never been built. **That is not +what those messages mean any more.** The gates bootstrap the project they +need (`ct_need_prj` in link:../scripts/ct_env.sh[`scripts/ct_env.sh`]), +so a fresh worktree runs them without a warm-up step. The first gate to +need a given project pays about a minute for it and says so: + +[source] +---- +ct_env: BOOTSTRAP -- bld/ carries no xsim project for repeated_history_tb (it is + gitignored, so a fresh clone or worktree has none). Generating it + with abc; this takes about a minute. Log: .../bld/abc_bootstrap_repeated_history_tb.log +ct_env: bootstrap ok -- repeated_history_tb_vlog.prj (abc rc=0) +---- + +`make bld-bootstrap` does all three up front if you would rather pay it +once before a long gate run. Three projects exist because the gates clone +them with the testbench source substituted: +`implicit_return_tb` (instruction tests), `repeated_history_tb` +(feature tests) and `overrun_recovery_tb` (overflow tests). + +The generated project pins the **file list**, not the file contents — +`xvlog` recompiles every source it names on each run. So a stale project +only matters when a source was added to or removed from one of the three; +`make bld-refresh` (or `CT_PRJ_REFRESH=1`) regenerates them then. + +*How a failure is reported.* Three outcomes are now distinct, because +merging them is what cost the time: + +[cols="1,3", options="header"] +|=== +| Exit / line | Meaning + +| `77` → `SKIP` | The gate needs an input this repository does not ship + (a captured hardware run, a decoder build with `-decoe`). Not a pass, + not a failure. +| `78` → `TOOL` | The toolchain or the build tree could not be + established: no Vivado, no `abc`, no working `python`, a bootstrap that + did not produce a project. Red — but never a statement about the + encoder. +| anything else → `FAIL` | The gate ran and its check failed. +|=== + +A byte-neutrality run whose legs did not all complete now reports +`BYTE NEUTRALITY: INCONCLUSIVE` instead of `DRIFT`: an incomplete +manifest cannot say anything about byte identity. + +[#sim-backend] +=== Simulation backends, and why `abc -sim` "fails" + +link:../.abc.config[`.abc.config`] pins `sim_backend=verilator`. That is +deliberate and it is the right default: Verilator is the Vivado-free +route, it is what `make sim` and the coverage runs use, and it works on +this workstation too — on Windows it needs `VERILATOR_ROOT` pointed at a +native path, which both the `Makefile` and `ct_env.sh` do for you (the +binary reports an MSYS-internal path it cannot open itself, and without +the repair it aborts in `Cannot find verilated_std.sv`). + +What the Verilator backend does **not** produce is an xsim project, and +the whole `cli_*` gate battery needs one. So those scripts ask for the +other backend explicitly — `abc --sim-backend vivado -sim ...` — instead +of depending on the repository-wide setting. Do the same when you drive +`abc` by hand for a gate; there is no need to edit `.abc.config`, and +editing it inside a worktree under test leaves a dirty file in the very +tree whose byte identity is being measured. + +*`Spawn failed: Broken pipe` is expected, and it is not your fault.* +On this Windows workstation, `abc --sim-backend vivado -sim` always ends +with + +[source] +---- +ERROR: [Common 17-180] Spawn failed: Broken pipe +ERROR: [USF-XSim-62] 'compile' step failed with error(s) while executing '.../compile.bat' +ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors. +---- + +Vivado's `launch_simulation` cannot spawn its own `compile.bat` from this +shell. How far the isolation goes, measured 2026-08-06: + +* the project, the `.prj` and `compile.bat` are **written before** the + spawn step and are complete and correct; +* the very `compile.bat` Vivado could not spawn runs to completion when + started directly from the same shell (`cmd //c ./compile.bat`, rc=0, + every source analysed); +* `cmd.exe` spawns fine from this shell, `TMP`/`TEMP`/`COMSPEC` are + native Windows values — the failure is inside Vivado's own spawn, not + in the environment it inherits. + +The workaround follows from that and is what every gate does: let `abc` +generate the project, ignore its exit code, and drive `xvlog`, `xelab` +and `xsim` on the command line. `ct_need_prj` therefore judges the +bootstrap by *whether the `.prj` exists*, never by `abc`'s return code. + +=== Toolchain discovery for the developer scripts + +Everything under link:../scripts/[`scripts/`] sources +link:../scripts/ct_env.sh[`scripts/ct_env.sh`], which resolves the toolchain +without any machine-specific paths in the scripts themselves: + +[cols="1,3", options="header"] +|=== +| Variable | Meaning + +| `CT_VIVADO_BIN` +| Vivado `bin/` directory. Without it the pinned version from `.abc.config` + is searched in both installer layouts (`/Vivado//bin` and, + from 2026.1, `//Vivado/bin`). An `xvlog` that is already on + `PATH` is only accepted if it *is* the pinned version — set + `CT_VIVADO_ANY=1` for a deliberate cross-version run. + +| `CT_ABC_BIN` | Directory holding the abc-flow driver. +| `CT_ABC_TIMEOUT` | Seconds a bootstrap `abc -sim` may take (default 900). +| `CT_PRJ_REFRESH` | `1` regenerates an xsim project even if it exists + (see <>). +| `CT_PYTHON_BIN` | A working Python 3 (abc is a Python program). On a + fresh Windows shell both `python` and `python3` are usually the + Microsoft Store stubs, which print an installation hint instead of + running; `ct_need_python` resolves one real interpreter and writes + `bld/pyshim/` wrappers for both names. **A script that calls `python` + must call `ct_need_python` first** — every gate script was audited for + this on 2026-08-06. +| `NEXRV` | Explicit path to the reference decoder CTTD; otherwise the + fetched build matching the host is used (`bin/cttd-linux-x86_64`, + `bin/cttd-linux-arm64`, `bin/cttd-windows-x64.exe` -- `py + scripts/fetch_cttd.py`, pin `scripts/cttd.pin`). The variable keeps its + historical name. +| `VERILATOR_ROOT` | Verilator prefix. On Windows the `Makefile` and + `ct_env.sh` derive a native path from the binary location, because + Verilator otherwise reports an MSYS-internal path it cannot open itself. +| `CT_REPLAY_PCINFO` | Program description of a captured hardware run, needed + by the two replay gates. Not part of this repository — without it those + gates skip (exit 77) instead of failing. +| `NEXRV_DECOE` | Optional override for the E-Trace CTXP gate + (`cli_etrace_ctxp_test.sh`): a decoder build carrying the `-decoe` front + end. Since 2026-08-17 the pinned CTTD carries it, so the gate runs on + `$NEXRV` by default (6/6 legs) and this override is only for a deliberate + cross-check against another build. |=== === Running simulations @@ -53,6 +204,36 @@ exercise (`rtl//test/`); end-to-end / multi-module scenarios live under link:../tests/[`tests/`]. See link:verification.adoc[Verification] for the test harness and the check flags. +=== The examples flow + +The worked integrations under link:../examples/[`examples/`] run through +the same machinery, one level up: `make sim-examples` drives every +simulable example and prints a PASS/FAIL summary. It refuses to report +PASS over an empty example list — a summary over nothing must never read +as green (that exact failure happened once, when a merge silently dropped +the list variable). + +The ingress adapters under `rtl/adapters/` (MicroBlaze V TRACE bus, CVA6 +ITI, Rocket TCI) are part of the IP, not of the examples; their unit +benches run through `scripts/cli_adapters_test.sh`, which CI stage 2 +starts. The example catalog and feature matrix live in +link:../examples/README.md[`examples/README.md`]. + +Multi-source merging has its own gate since 2026-08-19: +`scripts/cli_dualsrc_test.sh` drives `tests/instruction/39_dual_src`, where +two encoder instances with `SrcBits`=2 and `SrcID` 0/1 send **at the same +time** and the merged stream is split again by source. Two details of that +bench are deliberate and worth copying if you write a similar one: + +* The two sources run **different programs at disjoint addresses**. Two + sources running the same image differ in exactly one bit per message, and + a test that cannot fail confirms nothing — that is precisely why a board + run with two identical guests looked like a passing multi-source proof and + was none. +* The bench checks the *negative* case too: cross-decoding one source against + the other's reference must fail, and it does (`rc=9`). Without that, a + decoder that simply ignored the source field would still look green. + == Register (RDL) flow SystemRDL is the source of truth for the register map @@ -67,6 +248,40 @@ SystemRDL is the source of truth for the register map Never hand-edit the generated files; they are overwritten on regen. +=== The PeakRDL toolchain is found, never guessed + +`make rdl` installs the pinned PeakRDL into a local `.venv-rdl*/`, which +is gitignored and therefore belongs to the **main checkout**: a linked +`git worktree` has none of its own. +link:../scripts/gen_rdl_profile.py[`scripts/gen_rdl_profile.py`] resolves +it through `git rev-parse --git-common-dir`, so a worktree finds the main +checkout's venv: + +[source,sh] +---- +$ cd +$ py scripts/gen_rdl_profile.py --pkg ... --rdl-dir ... --out-dir ... +[gen_rdl_profile] ct_profile.inc.rdl: full profile (no defines) +[gen_rdl_profile] wrote .../ct_cs_cpuif.sv +[gen_rdl_profile] done. # rc=0 +---- + +If it cannot find a pinned venv it **stops**; it does not fall back to a +`peakrdl` on `PATH`: + +[source] +---- +ERROR: no pinned peakrdl venv found in ... -- refusing the PATH peakrdl at +... (its output has no addrmap localparams). Run scripts/gen_rdl.sh once, +or set GEN_RDL_ALLOW_PATH_PEAKRDL=1 to override deliberately. +---- + +That refusal exists because the silent fallback happened three times: the +unpinned PeakRDL emits a regblock without the addrmap `localparam`s, so +the whole xsim battery dies hours later in +`'NUM_PERFCNT_IFETCH_TH_RANGES' is not declared` — wrong tool, and the +error message points anywhere but at it. + == Coding rules * Every source / doc file carries an SPDX header: @@ -79,21 +294,18 @@ SPDX-License-Identifier: CERN-OHL-S-2.0 OR LicenseRef-Accemic-Commercial + This is enforced by the REUSE CI job; files that cannot carry an in-file header are annotated in link:../REUSE.toml[`REUSE.toml`]. -* New RTL must pass `make lint` (Verible, rules in - `.rules.verible_lint`). +* New RTL must pass `make lint` (Verible). The rule set is **opt-in**: + `scripts/lint.sh` runs with `--ruleset=none`, so only the rules listed + in `.rules.verible_lint` are active, and `--rules_config_search` picks + up per-directory overrides (`rtl/pkg/` for generated code, `formal/` + for the property harnesses). Both the root file and the overrides say + in a comment why each deviation exists. * See link:../CONTRIBUTING.md[`CONTRIBUTING.md`] for branch naming, the CLA, and the PR workflow. == SoC integration -A worked end-to-end example lives under `examples/tgc5b_soc/` (see its -`README`): a MINRES TGC5B RV32I core wired to `ct_encoder` with RAM, a -timer/interrupt controller (from the example's `rdl/ct_soc.rdl`), an AXI4-Lite -→ Wishbone CSR bridge, and a system testbench that runs a real program and -decodes the resulting trace with NexRv. It is a concrete template for the -steps below. - -To drop CEDARtools.TraceEncoder (`ct_encoder`) into a design: +To drop CTTE (`ct_encoder`) into a design: * **TIP** — connect the core's instruction-trace port to the `tip_if.slave` (in the `tip_clk` domain). Choose `SPLIT_DATA_ACCESS` to diff --git a/doc/enhanced-features.adoc b/doc/enhanced-features.adoc index f3c9f0f..cbc6299 100644 --- a/doc/enhanced-features.adoc +++ b/doc/enhanced-features.adoc @@ -6,7 +6,8 @@ :toclevels: 3 :nexus-spec: https://github.com/riscv-non-isa/riscv-nexus-trace/blob/main/docs/nexus-standard/IEEE-ISTO-5001-2012-v3.0.1-Nexus-Standard.pdf -Beyond the baseline RISC-V N-Trace program- and data-trace, CEDARtools.TraceEncoder adds +Beyond the baseline RISC-V N-Trace program- and data-trace, +CEDARtools.TraceEncoder (CTTE) adds a set of vendor extensions on top of the {nexus-spec}[Nexus] framework. They reuse the standard message machinery (vendor TCODEs, reserved sync reasons, variable-length fields) so a Nexus-aware decoder can still frame the @@ -23,7 +24,7 @@ toc::[] == Data Acquisition (DAQ) and ACT-CAP / ACT-ST -CEDARtools.TraceEncoder can export instrumentation data as **Data Acquisition** messages +CTTE can export instrumentation data as **Data Acquisition** messages (TCODE 7): an `IDTAG` plus a variable-length payload up to `NEXUS_MSG_DATA_WIDTH` (192 bits), optionally timestamped. This carries more than the 64 bits a standard data-trace message allows, which is why @@ -46,11 +47,60 @@ IMPORTANT: `0x0B10` is a CPU-side CSR, **not** a Wishbone register. It is documented in the RDL only so the register exporter can describe it; the encoder hardware does not decode `0x0B10` on the Wishbone bus. +[IMPORTANT] +.ACT-CAP needs a data channel on the ingress port, and most integrations do not have one +==== +ACT-CAP is decoded off the **TIP data channel**: `ct_L23_preproc_act_cap` +fires on `dretire && dtype == CSR_READ_WRITE && daddr == 0x0B10` and reads +the command word from `tip.data`. A core therefore has to do two separate +things for ACT-CAP to work: accept the CSR access without trapping *and* +**report it on its trace port as a CSR-write data beat**. The second is the +one integrations miss. + +Of the four cores wired up in this repository, **none** reports CSR writes, +and three of them expose no data channel at all — the CVA6, Rocket and +MicroBlaze V adapters tie `tip.dretire` to 0 +(see link:../examples/kv260/README.md[the KV260 example README], section +"What each core's trace ingress can and cannot carry"). ACT-ST is +unaffected: it triggers on a retired PC and needs only `iaddr`. + +Where the ingress *does* carry stores, an integration can close the gap +without touching the core: convert a store to a chosen doorbell address into +the CSR beat the encoder expects, taking the command word from the store +data. Note that on a split-data ingress the adapter must also drive +`tip.data` (ACT-CAP reads `data`, not `sdata`) — an adapter that leaves +`tip.data` at 0 decodes every command as `ACT_CAP_ST_NONE`, which is a +silent no-op rather than an error. + +ACT-CAP's verification in this repository is simulation-only +(`tests/lib/cpu_model.sv` synthesises the beat; scenario +`sim-hsi-csr-cap`). There is no silicon evidence for it yet, so treat a +first hardware use as bring-up with its own verdict. +==== + The `Sink` routing lets the same instrumentation event go to the Nexus trace stream, to the 96-bit AXIS instrumentation port, or both — see the `sim-hsi-csr-cap` scenario in link:verification.adoc[Verification], which fires the full command set and self-checks the AXIS beat. +**ACT-ST watchpoint table (1023 slots, indirect access).** ACT-ST +dispatches a command word without CPU involvement when a retired PC +matches a table entry. The table is a RAM-backed binary search tree +(ten levels, `trWpCap.Entries` = 1023 slots, one lookup per cycle) and +is loaded through an indirect register pair — `trWpIndex` (`0x400C`) +picks the slot, `trWpDataLow`/`trWpDataHigh` (`0x4010`/`0x4014`) stage +and commit one 64-bit entry per `DataHigh` write, auto-advancing the +index; `trWpReadLow`/`trWpReadHigh` read the table back the same way. +The three *load* registers (`trWpIndex`/`trWpDataLow`/`trWpDataHigh`) +are locked while `trTeControl.Enable` = 1; readback stays live — a +`trWpReadHigh` read still advances the index (by design, so a debugger +can inspect the table of a running session without unlocking it). +*Breaking change (C0b):* the former direct memory window at `0x4100` is +gone — 1023 entries no longer fit below the `df` component; see the +integration manual (`integration.adoc`, _Indirect watchpoint table +access_) for the migration recipe and the unchanged programming rules +(fill all slots, strictly ascending keys). + == Filtering and watchpoints The preprocessor (`ct_L23_preproc`) filters both control flow and data @@ -67,21 +117,124 @@ flow before messages are generated: These let a user restrict tracing to a region of interest, cutting trace bandwidth at the source. -== Synchronization variants +NOTE: the exception-cause match is a *bitmap* spanning the whole +`MatchChoiceEcause{Low,High}` register pair — 64 bits, one per cause — +and the RTL carries it at that width rather than reading only the low +register, which is what it used to do. That is not the same as being able +to select 64 causes: the TIP cause bus is four bits wide in the default +configuration (`TIP_ECAUSE_WIDTH`), so only bits 0..15 are reachable at +all. The high half exists for a wider cause bus and is inert until one +does — a register that can hold a value is not evidence that anything +produces it. + +[[filter-anchoring]] +=== What a filtered stream looks like on the wire + +A filter does not merely delete messages — it creates a *gap* the decoder +has to be told about, otherwise it keeps walking from the position it had +before the gap. `CT_EN_FILTER_SYNC` closes that with the machinery a +software trace pause already uses, so no decoder learns anything new: + +* leaving the filter region emits a **Program Trace Correlation** (TCODE + 33, `EVCODE = Program Trace Disabled`) carrying the residual `ICNT` and + the pending branch history, and both sides drop their call stacks; +* re-entering it emits a **`SYNC = 5` (Trace Enable)** re-anchor with the + full address; +* a sync verdict that happens to land on an instruction the filter + rejects is *held* until the next qualified retire instead of being + dropped with the message that would have carried it. + +The block is armed by `trTeInstFilters` being non-zero. With the reset +value 0 ("trace all") it is dead, so every unfiltered stream is +byte-identical to earlier builds by construction. + +The filter suppresses **at the source**, it does not mark: a rejected +instruction never reaches the message-generating block at all, so it +contributes nothing — not even to the instruction count. That is what +makes the residual `ICNT` in the correlation message exact rather than +an approximation, and it is what a consumer measures when it checks that +a filtered run reconstructs the selected process *completely* and the +other one *not at all* (see +link:verification.adoc#process-filter[Verification — tracing one +process, end to end]). + +Two things a filtered stream deliberately does *not* do. **Trap delivery +is always traced**, whatever the filter selects — exception and interrupt +beats bypass the control-flow qualifier (`is_trap_event` in the eTIP +composer), because losing the entry into a handler would desynchronise +the reconstruction rather than narrow it. And the correlation message +says *that* there was a gap, not *how long* it was: the skipped +instructions are gone, which is the point of filtering. + +A worked example — two processes on one hart, told apart by +`satp.ASID`, and the trace restricted to one of them — was measured on a +CVA6 RV64 Linux integration; the simulation driver for it is not part of +this repository. -In addition to the standard periodic and trace-enable sync, CEDARtools.TraceEncoder -defines vendor sync reasons (see link:trace-format.adoc#sync-reasons[Trace -format]): +== Synchronization variants -* **`REQ_CSR` / `REQ_ATB`** — a sync explicitly requested by software via - CSR or APB. -* **`TRACE_QUOTA`** — a sync emitted when a configured quota (number of - trace messages or trace bytes) is reached, bounding how long a decoder - must wait to re-synchronize. +Beyond the standard reset / trace-enable / periodic sync, CTTE can be +asked for a synchronization explicitly. All three request paths — a +write of 1 to `trTeControl.InstSyncReq` (the TCI-standard field, +`CT_EN_INST_SYNC_REQ`), an ACT-CAP `CF_SYNC` CSR command and the ATB +sync-request input — produce the *same* on-wire sync reason, the single +Vendor-Defined code 14 (`REQ`). A decoder does not care where the +request came from, since every sync is a full re-anchor; the source is +recorded for diagnosis in the read-only CSR field +`te.trTeSyncStatus.SyncReqSource`. The request field is independent of +the cadence (it works in every `InstSyncMode`) and carries a one-message +-per-request contract with a depth of one request in flight plus one +remembered: a write during an outstanding request gets its own message, +and only a further write on top of the queued one collapses into it. A +request written during a tracing pause is served after the resume anchor +instead of being dropped. See +link:trace-format.adoc#sync-reasons[Trace format → Synchronization +reasons] for the complete list, including the event-driven reasons +(debug exit, power-down exit, external trigger, watchpoint) and the +periodic-cadence modes. + +NOTE: The trace-*quota* cadences are implemented (`CT_EN_QUOTA_SYNC`, +CAPS bit 18): `trTeControl.InstSyncMode` 1 counts on-wire messages, +mode 4 counts bytes as accepted on ATB (whole beats, incl. alignment +padding and flush idle beats), each against a 2^(`InstSyncMax`+4)^ +threshold. A dedicated counter in the active egress path raises a held +request at the threshold; the resulting sync is an ordinary `PERIODIC` +(2) on the wire and reports `SyncReqSource = 3` for diagnosis. This +bounds decoder re-synchronization by *emitted volume* — the property a +ring-buffer consumer needs. Window recipe and measured re-anchor +distance: link:integration.adoc#quota-sync-live[Integration → +Live / ring operation]. + +== Program-trace compression suite + +On top of the N-Trace chapter 9 optimizations, CTTE bundles a set of +individually switchable compression features, each with its own compile +switch in link:../rtl/pkg/ct_pkg.sv[`ct_pkg.sv`] and its own runtime +enable in `trTeInstFeatures` (full flag reference incl. CAPS bits, +profile defaults and measured costs: +link:integration.adoc#feature-flags[Integration → Feature flags]): + +[cols="2,2,1,3", options="header"] +|=== +| Feature | Build switch | Enable | Effect + +| Implicit return | `CT_EN_IMPLICIT_RETURN` | `InstEnImplicitReturn` | Returns matching a 16-slot call/return stack become inferable — no address on the wire. +| Repeated history | `CT_EN_REPEATED_HISTORY` | `InstEnRepeatedHistory` | Identical consecutive history patterns collapse into Resource Full RCODE=2 plus a repeat count. +| Wide instruction count| `CT_EN_WIDE_ICNT` | `InstEnWideIcnt` | Raises the internal ICNT cap from 8 to 16 bit, cutting Resource Full (ICNT) drains. Wire format unchanged. +| Repeat Branch | `CT_EN_REPEAT_BRANCH` | `InstEnRepeatBranch` | Identical repeated Indirect Branch History messages collapse into TCODE 30 with a repeat count. +| Repeat Instruction | `CT_EN_REPEAT_INSTR` | `InstEnRepeatInstr` | Single-instruction spin loops are counted into TCODE 31/32 instead of one history bit per iteration. +| Indirect Branch History w/ Sync | `CT_EN_IBHS` | `InstEnIbhs` | Synchronizing messages carry the pending history (TCODE 29) instead of pre-flushing it — one message where two went before. +| Jump-target cache | `CT_EN_JTC` | `InstEnJumpTargetCache` | [vendor] Indirect targets seen before are sent as a 64-entry cache index (TCODE 57) instead of a full address. +| Branch prediction | `CT_EN_BP` | `InstEnBranchPrediction` | [vendor] A 512-entry predictor runs bit-identically on both sides; only the run length up to the next mispredict is sent (TCODE 56). +|=== -Periodic sync is arbitrated against the actual emitted byte count: the -MSEO/MDO formatter reports bytes back to the preprocessor so sync cadence -tracks real output, not just cycles. +All of them reset to 0. The two vendor features and Repeat Instruction +take the stream outside strict N-Trace 1.0 — see +link:trace-format.adoc#extensions[Trace format → Extensions beyond strict +N-Trace 1.0]. Sequential-jump inference is not a runtime switch but an +ingress convention of the attached core, fixed at build time by the +`CT_SIJUMP` parameter of `ct_encoder` and advertised in the config +message. == Performance counters and timestamping @@ -94,7 +247,7 @@ along as the `TSTAMP` field of sync, data and DAQ messages. == Overflow and overrun recovery Under sustained back-pressure (ATB stalled while TIP keeps retiring), the -internal queues can overrun. CEDARtools.TraceEncoder handles this explicitly: +internal queues can overrun. CTTE handles this explicitly: * The composer injects a **QueueOverrun** condition; the encoder emits an **Error** message (TCODE 8, `ETYPE = QUEUE_OVERRUN`) whose **ECODE** @@ -137,7 +290,7 @@ The element layout per command (`ct_L23_preproc_composer_axis.sv`): |=== | Command (`tid`) | element 0 | element 1 | element 2 -| `DAQ_PC_CURR` | current PC | direct-data tag | — +| `DAQ_PC_CURR` | current PC | direct-data tag | timestamp[31:0] (`CT_EN_AXIS_TS`) | `DAQ_PC_CURR_LAST` | current PC | last PC before exception/interrupt | direct-data tag | `DAQ_DIRECT_DATA` | direct-data tag | — | — | `DAQ_DATA` | last data value | dtype/dsize | — @@ -146,14 +299,37 @@ The element layout per command (`ct_L23_preproc_composer_axis.sv`): | `DAQ_DATA_RD` / `_WR` / `IFETCH_TH` / `DATA_RD_TH` | perf-counter value (region from direct-data) | — | — |=== +With `CT_EN_AXIS_TS` (full-profile default 1) a `DAQ_PC_CURR` beat carries +the selected timestamp — lower 32 bit of the value the timestamp unit +produces per `trTsControl.Type` / `Active` / `Count` / `Prescale` — as +element 2, so an in-fabric consumer can order and correlate PC samples +without a Nexus decoder. Compiled out, the beat keeps the historical +two-element shape (strobe `0xFF`). Note the split: `trTsControl.Enable` +gates only the TSTAMP fields of the Nexus/E-Trace messages, not this +element; requires `CT_EN_TIMESTAMP` and `CT_EN_ACT` (elaboration guards). + The `sim-hsi-csr-cap` scenario fires every command above to the AXIS sink and self-checks the decoded beat (`ct_axis_decoder.sv`); see link:verification.adoc[Verification]. == Vendor configuration message -A **Vendor Config** message (TCODE 56, in the Nexus vendor range) is -*defined* to convey the encoder's configuration to the decoding device, -so a decoder could adapt to the active feature set without out-of-band -knowledge. It is **not currently emitted** — the formatter path is -stubbed (commented out) pending finalization of the payload. +A **Vendor Config** message (**TCODE 58**, in the Nexus vendor range) +conveys the encoder's configuration to the decoding device, so a decoder +adapts to the active feature set without out-of-band knowledge. It +carries the format version, the compiled-in capability map (`CAPS`), the +currently enabled subset (`ENAB`) and the structural sizes of the return +stack, jump-target cache and branch predictor. + +The feature is compile-gated by `CT_EN_CONFIG_MSG` (profiles without it +read `SendConfig` as a `CFG_NONE` constant). Emission is selected by +`trTeControl.SendConfig`: `CFG_NONE`, `CFG_ONCE` (at trace start) or +`CFG_ON_SYNC` (additionally after every periodic sync). The full build +profile resets to `CFG_ONCE`, so a default full build produces a +self-describing stream. The field layout is documented in +link:trace-format.adoc#config-message[Trace format → Vendor Config +message]. + +NOTE: TCODE **56** is *not* the config message — it is the vendor +branch-prediction message. The config message moved to 58 when 56 was +taken; a decoder that still assumes 56 will misparse. diff --git a/doc/images/ct-context.drawio.png b/doc/images/ct-context.drawio.png index 8a2f8b4..238cb57 100644 Binary files a/doc/images/ct-context.drawio.png and b/doc/images/ct-context.drawio.png differ diff --git a/doc/integration.adoc b/doc/integration.adoc new file mode 100644 index 0000000..b8d1b56 --- /dev/null +++ b/doc/integration.adoc @@ -0,0 +1,1194 @@ +// SPDX-FileCopyrightText: 2026 Accemic Technologies GmbH +// SPDX-License-Identifier: CC-BY-4.0 + += Integration guide — dropping `ct_encoder` into an SoC + +NOTE: The product name is *CEDARtools.TraceEncoder*, abbreviated *CTTE*. +The earlier name *C-Trace* is retired from prose; it survives only in the +`ct_*` identifier prefix (the IP's public API), in board- and +bundle-visible names (`*_ctrace_kv260`, `ctrace_resmem.dtso`, +`ctrace-pl-ddr`, the `mbv_ctrace_soc` block design) and in recorded +captures and evidence files, which are raw data with published checksums. +See the naming note in the README. + +This is the integrator-facing contract: clocks, resets, the instruction +ingress, the control interface, the trace egress, and the shutdown +semantics. The architectural background lives in +link:architecture.adoc[architecture], the on-wire format in +link:trace-format.adoc[trace-format], and the register reference is +generated from the SystemRDL source in link:../rdl/[`rdl/`]. + +== Clocks and resets + +`ct_encoder` spans five clock domains; every domain has its own +synchronous reset. All CDC crossings are internal (gray-pointer FIFOs + +2-FF synchronizers) — the integrator only connects clocks: + +[cols="1,2,2", options="header"] +|=== +| Clock | Drives | Notes + +| `tip_clk` | Instruction ingress (`tip_if`), preprocessor front +| **Must be the core clock** — the `TRACE`/TIP bus is synchronous to + retirement. + +| `proc_clk` | Message generation, formatting +| May equal `tip_clk` (1:1 is the proven board profile) or run faster + for headroom. + +| `atb_atclk` | ATB egress, `trTeControl.Empty` view +| Sink-side clock. 1:1 with `tip_clk` is proven on hardware; a slower + drain simply raises the FIFO-overrun rate (announced loss, see below). + +| `wb_clk` | Wishbone CSR access | Any frequency. +| `wall_clk` | Wall-clock timestamp source | Optional feature clock. +|=== + +A fully single-clock integration (all five tied to one clock, as on the +KV260 reference design) is supported and is the configuration the +hardware robustness campaign runs on. + +[#independent-resets] +*Resetting one domain without the others is allowed, and what it costs.* +The resets are independent inputs, so an integrator may hold the core +(and with it `tip_rst`) in reset while the CSR domain keeps running — +that is what makes the encoder programmable across a core reset. Two +consequences are worth stating because they are contract, not accident: + +* *An explicit sync request survives a reset of the CONSUMER's domain.* + The request over `trTeControl.InstSyncReq` crosses as a four-phase + LEVEL handshake (`ct_sync_req_pacer`), for exactly this reason: a + `tip_rst` clears the generator's pending state without acknowledging + it, and a request that is still standing is simply seen again when the + domain comes back. The ATB sync request has the same property, by the + same means. ++ +The direction matters and the sentence is only true in it. A `wb_rst` +resets the *launch* side, and there the request has nowhere to survive: +`ct_sync_req_pacer` clears `Req` and `Queued` on its own reset +(`rtl/pkg/ct_sync_req_pacer.sv`), so a request written but not yet +served is **gone** — no message, no error, no status bit. That is the +correct behaviour (a reset CSR domain has no pending software intent to +honour), but it is not what "not lost" would mean if the word were left +unqualified: what is claimed here is survival of a `tip_rst`, not of a +`wb_rst`, and not of a reset of both. Software that resets the CSR +domain re-issues its request. ++ +Proven for one clock as P-SYNC-12 (`formal/preproc_sync`, task +`tereqrst`) and measured at two unrelated clocks by +`scripts/cli_syncreqrst_test.sh`, + which also shows what a pulse-based request would do instead (the + request is dropped and the launch side waits for ever). +* *It may cost one extra synchronization message.* If the reset lands + after the generator has served the request but before the launch side + has seen the acknowledgement, the request is asked for again. A + synchronization message is always safe to emit, and a reset re-anchors + the decoder anyway (`EXIT_FROM_SYS_RST`), so this is a byte, not a + hazard. Exactly-once across a one-sided reset is **not** claimed. + +Everything else in the encoder is reset per domain in the ordinary way: +state in the domain that was reset is gone, and the trace stream +re-anchors on the first qualifying retirement afterwards. + +== Instruction ingress (`tip_if`) + +One beat per retirement opportunity. The essentials that integrations +get wrong (all are asserted or gate-tested): + +* `iretire=1` marks a retired instruction; `iaddr`/`ilastsize` must be + valid on that beat. +* A synchronously faulting instruction (ecall/ebreak/illegal) does + **not** retire: `iretire=0`, `itype=EXCEPTION_TRAP`, and its PC never + appears in the decoded stream (1:1 retirement rule). Interrupts use + `itype=INTERRUPT` with `iretire=0`; the pre-empted instruction is + re-executed after `mret` and appears then. +* `itype` must be valid **whenever it is non-OTHER**, even with + `iretire=0` (trap markers ride non-retiring beats). +* Sideband levels (`debug_mode`, `power_down`) must rise after the last + pre-window retire and fall before the first post-window retire. + +[#block-ingress] +=== Block ingress — more than one instruction per beat + +The rules above describe the *single-retirement* ingress, which is the +default (`CT_EN_BLOCK_TIP = 0`, `iretire` one bit). A superscalar hart +retires several instructions in one cycle and cannot use it without +serialising its commit stream. `CT_EN_BLOCK_TIP = 1` switches `iretire` +to the meaning the RISC-V trace ingress port gives it — the number of +**halfwords** retired by the block reported on this beat — and widens +the bus to `CT_IRETIRE_WIDTH`: + +[cols="1,3,3", options="header"] +|=== +| Signal | Single-retirement (default) | Block ingress + +| `iretire` | 1 = one instruction retired | halfwords retired by the block (0 = none) +| `iaddr` | that instruction's address | address of the **first** instruction of the block +| `ilastsize` | that instruction's size | size of the **last** instruction of the block +| `itype` | that instruction's type | how the block **terminated** +|=== + +Consequences an integrator has to honour: + +* Only the **last** instruction of a block may be a control-flow event — + that is what ends a block. Everything before it is linear. The encoder + derives the control-flow source address as + `iaddr + 2*(iretire - 2^ilastsize)` and the block's successor as + `iaddr + 2*iretire`. +* `iretire` must not exceed `2^CT_IRETIRE_WIDTH - 1`. That width is + checked at elaboration and must lie in **2..8** — the lower bound + because a one-bit block bus cannot report even a single 32-bit + instruction, the upper because a beat that alone reaches the `ICNT` + pre-drain threshold (`2^NEXUS_MSG_I_CNT_WIDTH`) wedges the + indirect-branch history hold. A core whose block generator has + no bound of its own (CVA6's ITI accumulates until the next + control-flow instruction) must have its adapter split longer linear + runs into several `itype=OTHER` blocks. That is free on the wire: an + `OTHER` block raises no message, it only accumulates the count. +* Trap beats are unchanged: a synchronously faulting instruction still + reports `iretire=0`. +* The address comparators, the ACT watchpoint search and the + performance counters compare **one** address per beat and see the + block start. A block spans an address range, so instruction-granular + address filtering is not expressible on a block ingress at all — a + property of the port, not a shortfall of the filter. Use the + single-retirement ingress where per-instruction filtering matters. + +The switch adds no message **type** and no wire field, which is why it +carries no capability bit: there is nothing a decoder would have to be +told. In the reset configuration a block beat also produces exactly the +messages a serialised beat sequence would produce, with the same `ICNT` — +measured, not asserted (`scripts/cli_blocktip_test.sh`: one scenario driven +both ways in the same build, identical reconstructed PC sequences against a +per-instruction reference, and byte-identical ATB output). + +What that does *not* mean is that the stream is independent of how the +adapter cuts its blocks. Two configurations make the cut visible, and both +are the integrator's to reason about: + +* `trTeControl.InstSyncMode` = 6 counts *retirement beats*, not + instructions, so at a block ingress the periodic synchronisation lands + after a different amount of program. Mode 3 ("instruction half-words") + has a pre-existing defect of its own, unrelated to this switch and + documented at its source (`rtl/preproc/ct_L23_preproc_sync.sv`, finding + B-R13-1): the counter increments by one per beat, so it counts 32-bit + instructions and misses compressed ones entirely. The message-, byte- and + cycle-based cadences are unaffected either way, because they measure the + output rather than the ingress. +* With an instruction filter armed, the comparator sees block starts only + (bullet above), so which instructions qualify depends on the block + boundaries. + +Neither is a decoding hazard — the emitted stream is well-formed and +self-describing in every case — but "the same instructions produce the same +bytes" holds for the reset configuration, not for every configuration. + +`tip_if` is deliberately the *only* ingress contract: everything +core-specific lives in an adapter outside the encoder. Three adapter +families exist today and are maintained with the SoC integration project +rather than here — the AMD MicroBlaze V `TRACE` bus +(`mbv_to_ctte_tip.sv`), the CVA6 instruction-trace interface fed from +the core's RVFI probes (`cva6_iti_to_ctte_tip.sv`), and the Rocket +`TraceCoreInterface` (`rocket_tci_to_ctte_tip.sv`). Writing a fourth +means answering the same questions for the new core — which beat is a +retirement, how a trap is signalled, whether the address is the +instruction's or the next one's — and the answer belongs in a measured +truth table before it belongs in RTL; see +link:verification.adoc#rv64-cores[Verification — hardware-in-the-loop and +SoC integration]. + +== Control interface and programming contract + +CSR access is Wishbone (`wb_if`); an AXI-Lite bridge +(`ct_axil_to_wb`) is available at integration level. + +* **Feature configuration is Enable-locked.** All `trTeInstFeatures` + and sync-mode fields are writable only while `trTeControl.Enable=0` + (the protocol is not among them — it is a synthesis parameter, see + <>). Writes after arming are silently void — always + program in the order _Active → configuration → Enable+InstTracing_. ++ +NOTE: Until 2026-08-16 this sentence was true of the sync-mode fields and +of `SrcID`/`SrcBits`, but *not* of the eight `trTeInstFeatures.InstEn*` +bits: the RDL `swwel` list did not carry them, so they could be flipped +mid-session (found by an external register-access audit, U10 F-1). They +are locked now, like the rest of the register. Software that relied on +programming them after `Enable` was relying on a documented-void write and +must move those writes ahead of the arming step. +* **Not everything is locked, and the exceptions are deliberate.** The + session handles themselves (`Active`, `Enable`, `InstTracing`, + `DataTracing`, `InstSyncReq`), the status clear bits (including the RW1C + overflow flags and the FIFO-histogram controls), the message-class + enables whose messages a decoder recognises by TCODE (`SendConfig`, + `Context`, `InstSeqSyncEnable`, `InstTrigEnable`), the timestamp unit's + own run control (`trTsControl`) and the two ACT stall thresholds + `trPerfCntControl.{IFetchThreshold,DataWrThreshold}` stay writable while + the trace runs. The thresholds are compared against a counter that + restarts at every retire, so a new value simply applies from the next + measurement window — while the perf-counter address *ranges* next to them + are locked, because a range is two registers and a mid-trace update is + observable as a nonsense interval made of the new `Low` and the old + `High`. The complete list with a reason per group is the header of the + `swwel` block in `rdl/ct_cs_cpuif.rdl`, and `make lint` + (`check-swwel-census`) fails if a field leaves that list without either + a lock or an entry. +* `trTeControl.Active` gates the encoder's clock enables; keep it set + for the whole session, including shutdown polling. +* The decoder must be invoked with flags matching the programmed + features (e.g. `-bp` iff `InstEnBranchPrediction` was set). With + `trTeSendConfig` the encoder emits a config message (TCODE 58) that + advertises the active configuration in-stream for auto-configuration. + +== Trace egress + +Trace bytes leave on ATB (`atb_if`) in the framing of the back end this +encoder was built with — Nexus MDO/MSEO chunks for N-Trace, reference-raw +`te_inst` packets for E-Trace. The output `atb_te_raw` advertises which of +the two it is (0 = Nexus, 1 = `te_inst`), so a downstream funnel/sink +parses what the netlist actually produces instead of a second, +software-programmed copy of that truth; it is a constant of the +`EN_ETRACE` parameter. Backpressure via `atready` is legal at any time: +sustained backpressure raises FIFO-overrun episodes, which are +**announced loss** — an ERROR message plus a recovery sync re-anchor +the decoder; nothing is lost silently (verdict-tested across +backpressure duty/random/burst profiles). + +[#protocol-parameter] +=== Protocol choice — a synthesis parameter, per encoder instance + +Which protocol an encoder speaks is decided at synthesis, not at run +time. `ct_encoder` takes two parameters, `EN_NTRACE` and `EN_ETRACE`, +defaulting to the build profile (`CT_EN_NTRACE` / `CT_EN_ETRACE` in +`rtl/pkg/ct_pkg.sv`). **Exactly one of them must be set** per instance; +both-0 and both-1 abort elaboration with a `$fatal`. Only the selected +back end is instantiated, so an unused protocol costs nothing. + +Because the choice is per *instance*, a multi-encoder SoC can mix: one +encoder N-Trace, the next E-Trace, out of the same netlist sources. In +that case set the profile switches so the netlist contains what both +need — `CT_EN_ETRACE = 1` widens the internal eTIP sideband +(ecause/tval/priv/ilastsize) that the E-Trace back end consumes — and +give **every** instance an explicit `EN_NTRACE`/`EN_ETRACE`, since the +default would then be ambiguous. + +NOTE: The `ct_L1_funnel` derives Nexus packet boundaries from the MSEO +bits, which E-Trace bytes do not carry; merging a mixed set of channels +therefore needs the raw-framing extension `EN_TE_RAW = 1`, with +`chan_te_raw` selecting the framing **per channel** (an MSEO channel and a +`te_inst` channel may share one session). The funnel then frames a te_raw +channel by the packet's own header length and prefixes a source-tag byte +(`8'h80 | channel index`) so the merged stream stays self-describing once +ATID is gone. That container is called **CTMX**; splitting it yields +per-source byte streams byte-identical to a single-core capture, so an +unmodified E-Trace reference decoder consumes them +(`examples/kv260/trio/tools/etrace_trio_demux.py`). At `EN_TE_RAW = 0` the +te_raw inputs constant-fold away and the netlist is the historical +N-Trace-only funnel. The encoder side advertises what it produces on +`atb_te_raw` (0 = Nexus MSEO/MDO chunks, 1 = E-Trace reference-raw), so a +sink parses the netlist's truth rather than a programmed copy of it. +Bench: `rtl/test/ct_L1_funnel_teraw_tb.sv`; worked design: +`examples/kv260/trio` (board leg pending). + +Software discovers the built-in protocol read-only, per instance: +`trTeProtocolSel.Protocol` (0x030[0]: 0 = N-Trace, 1 = E-Trace) and +`trTeImpl.ProtocolMajor` (0x004[19:16]: 1 = N-Trace 1.x, 2 = E-Trace +2.x). Both are driven by the hardware parameter, so they stay truthful +in a mixed SoC. There is no write path — the earlier dual build, in +which `trTeProtocolSel` selected the active back end at run time, was +removed in 2026-08; it was never used in a product and cost a full +second back end in area. Software that used to *write* the register now +only reads it; the field, its address and its encoding are unchanged. + +The gate for this is `scripts/cli_etrace_test.sh mixed` +(`tests/instruction/24_protocol_param`): two differently parameterised +encoders in one netlist, each checked for its own `atb_te_raw` framing +advertisement and its own discovery values. + +[#quota-sync-live] +=== Live / ring operation — bounded re-anchor distance + +A live consumer that cuts a window out of a ring buffer needs a sync +message *inside* the window to anchor the decode. With the trace-quota +cadence (`CT_EN_QUOTA_SYNC`; `trTeControl.InstSyncMode = 4`, trace +bytes) the maximum distance between two syncs becomes a *programmed* +number instead of a workload property: the egress counter requests a +periodic sync every 2^(`InstSyncMax`+4)^ output bytes (16 B … 512 KiB), +counted exactly as the ring sees them — whole ATB beats, including +alignment padding and flush idle beats. + +Recipe for a window of W bytes: program `InstSyncMode = 4` and choose +`InstSyncMax` so that `2^(Max+4) <= W/2`. Every W-byte window then +contains at least one sync in steady state (the factor 2 absorbs the +in-flight overshoot below plus the sync message itself). The +16-KiB dashboard window, for example, takes `Max = 9` (8 KiB quota). +Leaving `InstSyncMax` at its reset value 6 gives a 1 KiB quota, i.e. a +2-KiB window — a usable default for a ring consumer, which is why the +period is pre-set and only the mode has to be written. + +All distances below are counted in *raw ATB bytes* — whole output +beats as the ring stores them, alignment padding and flush idle +included. That is the scale the quota itself is defined on, and the +only scale a ring consumer can act on. + +Measured (simulation, gate `29_sync_quota_bytes`: 64-B quota +`Max = 2`, mixed compressible/incompressible workload): 12 syncs in +1100 raw ATB bytes (133 messages, 335 idle/pad bytes), maximum +re-anchor distance **96 B** = the 64-B quota + 32 B of in-flight/CDC +overshoot. The analytic ceiling for the overshoot is +324 B +(derivation in `scripts/check_sync_window.py`); the formal window bound +is proven against the modelled egress counter (P-SYNC-5 family, +`formal/preproc_sync`). + +Measured (board, KV260 ring-capture path, `InstSyncMode = 4`, +`Max = 9` → 8192-B quota, 1-MiB URAM ring filled 3.08×, decoded +16 631 920 PCs from 131 071 messages): sync-to-sync distance constant +**8192 B** over 127 gaps — the programmed quota exactly. 40 randomly +cut 16-KiB windows were **40/40 anchorable**, with a maximum distance +from the window start to its first sync of **8111 B**. The three +numbers order as designed: + + 8111 B measured ≤ 8192 B quota ≤ 8516 B quota + Δ + +so the measurement sits 81 B under the programmed quota and 405 B +under the never-exceed bound. That headroom is *not* a proven reserve: +the workload of this capture is highly repetitive, which is why the +gaps come out constant; the guarantee is the bound, not the constancy. +The cost of the cadence was **0.061 %** of the stream (640 sync bytes +in 1 048 571 raw bytes). Discriminance was checked with the same +capture path at `InstSyncMode = 0`: **0/40** windows anchorable. +The raw capture and its re-analysis are not part of this repository. + +The message-count cadence (`InstSyncMode = 1`) works the same way with +on-wire messages as the unit. The runtime cost of either cadence is the +sync messages themselves; while modes 1/4 are not selected the counters +hold at zero and add no trace bytes. + +== Pause, stop, flush — the shutdown contract + +These semantics are contract-tested (gate `11_pause_edge`, campaign +verdicts V7/V8) and matter for integration software: + +* **Pause** (`InstTracing` 0→…→1 with Enable held): the encoder closes + the stream with a trace-off correlation (TCODE 33), suppresses + everything positionless, and re-anchors with a TRACE_ENABLE sync. Gap + re-anchors are side-effect-free on both sides. Pauses may be issued + asynchronously at any time — edge collisions with any retire type are + covered by the qualifier pipeline and the resume gate. +* **Flush** (`afvalid` or the sink's flush control): drains all queued + trace. To reach `Empty=1` afterwards, **close the stream while the + core still retires**: with `InstTracing=1` and a stopped core, exactly + one control-flow event is permanently in flight (its successor address + can never be observed) and `Empty=0` is the *correct* report. The + proven shutdown order is: flush → `InstTracing=0` (core still + running) → stop the core → poll `trTeControl.Empty`. +* **`trTeControl.Empty`** is a conservative, CDC-safe status: it rises + only after the entire chain (accumulators, formatter, packer, CDC + FIFOs, ATB queue) has been observably quiet, and falls immediately on + any visible substance. + +[#feature-flags] +== Feature flags + +One reference for every `CT_EN_*` compile switch in +link:../rtl/pkg/ct_pkg.sv[`rtl/pkg/ct_pkg.sv`]: its runtime-control CSR +field (register offset within the `te` component at `0x0000`, unless +prefixed), the field's reset value, its bit in the TCODE-58 CAPS/ENAB +capability map, its default in the committed *full* profile and in the +two slim reference profiles, and the measured LUT cost where an isolated +measurement exists. Consistency of this table with `ct_pkg.sv`, +`rdl/ct_cs_cpuif.rdl` and the CAPS map is machine-checked by +`scripts/check_feature_flags.py` (`make check-flags`, CI stage 1). + +Profile definitions live in `scripts/ct_profiles.sh` — one definition, +sourced by every measurement flow (`scripts/phase_d_matrix_v2.sh`, the +gold-standard flow these numbers come from, and +`scripts/p10_timing_matrix.sh`), so that no flow has to re-derive a +profile by hand-editing `ct_pkg.sv`: +*featparity* = DAQ/data-trace/ACT/filters/compression suite off, +single-clock, `CT_TS_WIDTH=32`, slicer steps 1, compact packer on, +serialize off; *featparity_gold* additionally switches the nine +gold-standard feature switches on (debug/power/EVTI/trigger/seq-sync +events, ownership, config message, IBHS, repeat instruction); +*slimfull_gold* = featparity_gold plus `CT_ETIP_CDC_SLIM=1`, +`CT_EN_ETIP_WATERMARK=0`, `CT_EN_TIMESTAMP=0`. `CT_EN_DF_ADDR_COMPRESS` +and `CT_EN_DF_DROP` follow `CT_EN_DATA_TRACE` and are therefore **0** in +the featparity-class profiles — not a preference but an elaboration +dependency (`scripts/check_profile_deps.py`). What the profiles do *not* +touch is `CT_EN_BTM`, `CT_EN_SYNC_STATUS`, `CT_EN_FIFO_HIST`, +`CT_EN_QUOTA_SYNC`, `CT_EN_DEVICE_ID`, `CT_EN_TRIG_REGS` and +`CT_EN_INST_SYNC_REQ`: those stay at their committed full-profile value +1 in both gold profiles, which is why the slim profiles carry everything +P2, P4, P7 and P8 added (see <>).footnote:[An +older featparity definition in `scripts/profile_matrix.sh` predates the +compact-packer and slicer-step knobs and differs from the v2 profile; +the `ct_profiles.sh` definitions — byte-identical to the sequences +`phase_d_matrix_v2.sh` used to carry inline — are behind every number +quoted here.] + +[cols="2,3,^1,^1,^1,^1,3", options="header"] +|=== +| Build switch | Runtime control (RDL) | Reset | CAPS | Default full | featparity_gold / slimfull_gold | LUT cost (measured, see note) + +| `CT_EN_NTRACE` | `trTeProtocolSel.Protocol` 0x030[0] — read-only discovery (hw-driven by the `EN_NTRACE`/`EN_ETRACE` instance parameters, see <>) | 0 | — | 1 | 1 / 1 | N-Trace-only CF backend: 6 842 LUTs (OOC, Vivado 2026.1) +| `CT_EN_ETRACE` | `trTeProtocolSel.Protocol` 0x030[0] — read-only discovery | 0 ^(committed profile is N-Trace-only; an E-Trace instance reads `Protocol`=1 / `ProtocolMajor`=2)^ | — | 0 | 0 / 0 | E-Trace-only CF backend: 3 439 LUTs vs 6 842 N-Trace-only (OOC, Vivado 2026.1). ^HISTORICAL^ Adding the E-Trace backend to a *dual* build cost +5 526 LUTs / +3 055 FFs (in-design KV260, Vivado 2026.1) — that build no longer exists, the protocol is a synthesis parameter since 2026-08 and only one backend is instantiated per encoder. +| `CT_EN_BLOCK_TIP` | — (build-time shape of the `tip_if` ingress: `iretire` becomes a halfword count of width `CT_IRETIRE_WIDTH`, see <>) | — | — ^(no message type and no wire field — a block beat produces exactly the messages a serialised beat sequence would)^ | 0 | 0 / 0 | not measured yet (R1.3) +| `CT_EN_BTM` | `trTeControl.InstMode` 0x000[6:4] (WARL — 3 legal iff compiled in, else legalized to 6) | 6 | — | 1 | 1 / 1 | switching **off** measured **+35 LUTs** in featparity (case-label restructuring of the msg_gen mux) +| `CT_EN_CONFIG_MSG` | `trTeControl.SendConfig` 0x000[8:7] | 1 (CFG_ONCE) | — ^(by design)^ | 1 | 1 / 1 | +350 LUTs / +511 FFs / +5 BRAM (featparity_cfgonly − featparity_base_v2); full-profile delta +491 / +451^1^ +| `CT_EN_OWNERSHIP` | `trTeControl.Context` 0x000[9] | 0 | 7 | 1 | 1 / 1 | +113 LUTs / +23 FFs (full profile)^1^ +| `CT_EN_DATA_TRACE` | `trTeDataControl.DataTracing` 0x010[1] (hwset/hwclr) | 0 | 16 | 1 | 0 / 0 | **+2 859 LUTs / +3 750 FFs / +6 BRAM** (base *B*, see note — OOC, Vivado 2026.1) +| `CT_EN_DF_ADDR_COMPRESS` | `trTeDataControl.DataAddrCompress` 0x010[19:18] (WARL — 1 = XOR legal iff compiled in; 2/3 always legalize to 0; Enable-locked; requires `CT_EN_DATA_TRACE` — formatter elaboration guard) | 0 | 21 | 1 | 0 / 0 (follows `CT_EN_DATA_TRACE`) | not measured yet (P3 stage 6) +| `CT_EN_DF_DROP` | `trTeDataControl.DataDropEna` 0x010[6] (runtime policy — deliberately NOT Enable-locked; requires `CT_EN_DATA_TRACE` — composer elaboration guard). Sticky status `trTeDataControl.DataDrop` 0x010[5] and `DataStallOrOverflow` 0x010[3], both RW1C | 0 | 22 | 1 | 0 / 0 (follows `CT_EN_DATA_TRACE`) | see <> +| `CT_EN_DAQ` | — (ACT-CAP/ACT-ST command-driven via CPU CSR `0x0B10`) | — | 17 (shared with `CT_EN_ACT`) | 1 | 0 / 0 | **+8 965 LUTs / +10 514 FFs / +12.5 BRAM** (base *B*, see note — OOC, Vivado 2026.1). ^This is the cost of the **group** `CT_EN_DAQ` + `CT_EN_ACT` + `CT_EN_WATCHPOINT_MSG`: `CT_EN_DAQ` alone is functionally dead (its only producer sits behind `CT_EN_ACT`) and `CT_EN_WATCHPOINT_MSG` fails elaboration without `CT_EN_ACT`. Named drivers: <>.^ +| `CT_EN_ACT` | indirect watchpoint table `trWpIndex` 0x400C / `trWpDataLow` 0x4010 / `trWpDataHigh` 0x4014 (Enable-locked; readback `trWpReadLow/High` 0x4018/0x401C, capacity `trWpCap` 0x4020 — see <>), `pc.trPerfCntControl` + range registers (no single enable bit) | — | 17 (shared with `CT_EN_DAQ`) | 1 | 0 / 0 | included in the `CT_EN_DAQ` group figure above — not separable by construction; ^measured at the historical 15-slot table — C0b grew it to 1023 slots, see <>^ +| `CT_EN_FILTERS` | `trTeInstFilters.Filters` 0x00C, `trTeDataFilters.Filters` 0x01C, `trTeFilter[]` 0x400+, `trTeComp[]` 0x600+ | 0 | — | 1 | 0 / 0 | **+7 822 LUTs / +5 085 FFs** (base *A*, see note — OOC, Vivado 2026.1) — the largest single-switch cost in this table, and it scales with `NUM_TRACE_FILTER` / `NUM_TRACE_COMPARATORS` (16 / 8 here): <> +| `CT_EN_FILTER_SYNC` | none of its own — armed by `trTeInstFilters.Filters` 0x00C being non-zero (0 = "trace all", the reset value, and then the whole block is dead). Requires `CT_EN_FILTERS` | 0 ^(via `trTeInstFilters`)^ | — ^(no new message type and no new wire field: a filter pause looks exactly like a software trace pause — TCODE 33 `EVCODE=Program Trace Disabled` on region exit, `SYNC=5 Trace Enable` on region entry)^ | 1 | 0 / 0 (follows `CT_EN_FILTERS`) | not measured yet (W2 is sim-only) +| `CT_EN_TIMESTAMP` | `trTsControl.Enable` 0x040[15] (+ `Type` / `Prescale` / `Width`) | 1 | 15 | 1 | 1 / 0 | switching off: −300 LUTs / −490 FFs (featparity single-clock context) +| `CT_EN_AXIS_TS` | — (build-time shape of the AXIS beat: a `DAQ_PC_CURR` beat carries the selected timestamp as element 2, strobe 0xFFF instead of the historical 0xFF; the value follows the timestamp unit — `trTsControl.Type` / `Active` / `Count` / `Prescale` — while `trTsControl.Enable` keeps gating ONLY the wire TSTAMP fields, not this element; requires `CT_EN_TIMESTAMP` and `CT_EN_ACT` — composer elaboration guards) | — | — ^(the AXIS sink is not a Nexus wire format — the ATB byte stream is identical either way, same rule as `CT_EN_BLOCK_TIP`)^ | 1 | 0 / 0 (follows `CT_EN_ACT`) | not measured yet (C0a) +| `CT_EN_DEBUG_EVENTS` | — (generic `tip.debug_mode` event port) | — | 10 | 1 | 1 / 1 | ≈ 0 (events group measured −5 LUTs / +22 FFs as a group)^1^ +| `CT_EN_POWER_EVENTS` | — (`tip.power_down` event port) | — | 11 | 1 | 1 / 1 | ≈ 0 (events group)^1^ +| `CT_EN_EVTI` | — (`tip.evti` event port) | — | 12 | 1 | 1 / 1 | ≈ 0 (events group)^1^ +| `CT_EN_TRIG_SYNC` | `trTeControl.InstTrigEnable` 0x000[11] | 0 | 13 | 1 | 1 / 1 | ≈ 0 (events group)^1^ +| `CT_EN_SEQ_SYNC` | `trTeControl.InstSeqSyncEnable` 0x000[10] | 0 | 14 | 1 | 1 / 1 | ≈ 0 (events group)^1^ +| `CT_EN_TRIG_REGS` | `trTeTrigExtInControl.ExtInAction0` 0x054[3:0] (WARL — 0/2/3 legal iff compiled in, 4 additionally iff `CT_EN_TRIG_SYNC`; everything else legalizes to 0; Enable-locked). Actions 2/3 (trace-on/-off) fire only while `trTeControl.InstTrigEnable` = 1 — the TCI couples the actions to that enable, so a pulse with `InstTrigEnable` = 0 is a no-op by design (see link:trace-format.adoc#extensions[trace format → extensions]). `ExtInActionN` 0x054[31:4], `trTeTrigDbgControl` 0x050 and `trTeTrigExtOutControl` 0x058 are read-only 0 in every profile ("trigger does not exist", TCI Tables 19–21) | 0 (no action) | — ^(no message type and no wire field — the notify's on-wire effect is CAPS bit 13)^ | 1 | 1 / 1 | see <> +| `CT_EN_QUOTA_SYNC` | `trTeControl.InstSyncMode` 0x000[19:16] (trace-output quota cadence modes 1 = trace messages / 4 = trace bytes) + `trTeControl.InstSyncMax` 0x000[23:20] | 0 | 18 | 1 | 1 / 1 | **+≈50 FFs; LUT cost below the resolution of both measurements.** Two independent runs agree on the flip-flops (+48 full profile / +52 base *A*) and disagree in *sign* on the LUTs (+138 full profile / −27 base *A*) — both magnitudes are inside the ±300 repacking band of rule ^1^, so neither is a cost. Quoting the LUT number would be quoting noise. ^Base *A* is measured **inverted** (switch off in the base): `scripts/ct_profiles.sh` does not touch this switch, so it otherwise stays at the committed value 1 and the naive delta is 0.^ +| `CT_EN_DEVICE_ID` | `trTeControl.SendDeviceId` 0x000[29:28] (WARL — 1 = `DID_ONCE` legal iff compiled in; 2/3 always legalize to 0; Enable-locked). Payload = the `CT_DEVICE_ID` elaboration parameter of `ct_encoder` | 0 (`DID_NONE`) | 19 | 1 | 1 / 1 | see <> +| `CT_EN_WATCHPOINT_MSG` | `trWpMask.WEM` 0x4008[15:0] (Enable-locked) + ACT-ST command `ACT_CAP_ST_WATCHPOINT`; requires `CT_EN_ACT` — composer elaboration guard | 0 (mask empty) | 20 | 1 | 0 / 0 (follows `CT_EN_ACT`) | see <> +| `CT_EN_IMPLICIT_RETURN` | `trTeInstFeatures.InstEnImplicitReturn` 0x008[3] | 0 | 0 | 1 | 0 / 0 | **+71 LUTs / +553 FFs** (base *A*) — the highest FF-to-LUT ratio in the table: `CT_RET_STACK_DEPTH` (16) × `tip_iaddr_t` (32 bit) = 512 register bits, i.e. 93 % of the FFs, with trivial push/pop logic +| `CT_EN_REPEATED_HISTORY` | `trTeInstFeatures.InstEnRepeatedHistory` 0x008[8] | 0 | 1 | 1 | 0 / 0 | **+86 LUTs / +91 FFs** (base *A*) +| `CT_EN_WIDE_ICNT` | `trTeInstFeatures.InstEnWideIcnt` 0x008[12] | 0 | 2 | 1 | 0 / 0 | **+66 LUTs / +29 FFs** (base *A*) +| `CT_EN_REPEAT_BRANCH` | `trTeInstFeatures.InstEnRepeatBranch` 0x008[11] | 0 | 3 | 1 | 0 / 0 | **+31 LUTs / +162 FFs** (base *A*) +| `CT_EN_JTC` | `trTeInstFeatures.InstEnJumpTargetCache` 0x008[5] | 0 | 4 | 1 | 0 / 0 | **+262 LUTs / +71 FFs** (base *A*) +| `CT_EN_BP` | `trTeInstFeatures.InstEnBranchPrediction` 0x008[4] | 0 | 5 | 1 | 0 / 0 | **+618 LUTs / +56 FFs** (base *A*) — the most expensive of the six compression switches +| `CT_EN_IBHS` | `trTeInstFeatures.InstEnIbhs` 0x008[13] | 0 | 8 | 1 | 1 / 1 | full-profile delta −446 LUTs — not causally isolable^1^ +| `CT_EN_REPEAT_INSTR` | `trTeInstFeatures.InstEnRepeatInstr` 0x008[14] | 0 | 9 | 1 | 1 / 1 | full-profile delta −381 LUTs — not causally isolable^1^ +| `CT_EN_INST_SYNC_REQ` | `trTeControl.InstSyncReq` 0x000[27] (TCI, write-1, self-clearing — always reads back 0; NOT Enable-locked and not tied to an `InstSyncMode`) | 0 | — ^(no message type and no wire field: SYNC = 14 exists either way — see below)^ | 1 | 1 / 1 | see <> +| `CT_EN_SYNC_STATUS` | `trTeSyncStatus.SyncReqSource` 0xE08[2:0] (RO; the whole register is omitted from the map when 0) | 0 | — | 1 | 1 / 1 | switching off: −44 LUTs (featparity, BTM-off base) +| `CT_EN_FIFO_HIST` | `trTeTipFifoHistCtrl.HistClear` 0xE10[0] + `trTeTipFifoHistData` 0xE14 (registers omitted when 0) | 0 | — | 1 | 1 / 1 | **+213 LUTs / +12 FFs / 0 BRAM** (base *A*, measured inverted — see note; OOC, Vivado 2026.1). Timing untouched: WNS +1.196 → +1.197 ns. ^Unusually logic-heavy for a feature that keeps a histogram — where the counts live was not investigated, and ΔBRAM is 0, so not in an added block RAM.^ +| `CT_EN_ETIP_WATERMARK` | `trTeTipFifoStatus.trTeTipFifoMaxFill` 0xE04[14:0] (no RDL gate — the CSR reads 0 when off) | 0 | — | 1 | 1 / 0 | switching off: −24 LUTs / −32 FFs (featparity context) +|=== + +Timing is not a property of a switch but of the whole build, so it rows +by profile instead: <>. + +[NOTE] +==== +All cost figures are OOC syntheses on `xck26-sfvc784-2LV-c` +(`scripts/synth_encoder_ooc*.tcl`; profiles per +`scripts/ct_profiles.sh`, which `scripts/phase_d_matrix_v2.sh` sources). + +*The tool version is not uniform across this column, and the difference +is not cosmetic.* The seq-22/phase-D generation of these numbers was +measured with Vivado 2025.1 at a 5 ns target; the `CT_EN_NTRACE` / +`CT_EN_ETRACE` back-end comparison and the `CT_EN_QUOTA_SYNC` row with +Vivado 2026.1; the P4, P7 and P8 rows (<>, <>, +<>) and the profile table in <> with Vivado +2022.1.2, the version `.abc.config` pins. Deltas are only comparable +*inside* one of those groups — each block states its own version, and a +row that does not is a seq-22 number. Re-measuring the older rows on the +pinned version is not done here; it would be a measurement round of its +own and the numbers below are quoted as what was actually run. +^1^ *Interpretation rule:* full-profile deltas below roughly ±300 LUTs +are restructuring-affected — the netlist repacks around the change, so a +negative delta does *not* mean the feature is free. The featparity/slim-class +measurements (small deterministic netlists) are the causally reliable +per-feature costs. "not measured individually" = no isolated OOC +measurement exists for this switch; the profile aggregates below bound +it. *No switch in this table carries that marker any more.* + +*The two differential bases (2026-08-11/12, Vivado 2026.1, 5.0 ns +target).* Eleven switches that previously read "not measured +individually" now carry differential figures. They were measured against +**two** bases, and the split is not a convenience — it is forced: + +[cols="1,4,3", options="header"] +|=== +| Base | Profile | Anchor + +| *A* | `featparity` (compact packer *on*) | 3 552 LUTs / 3 598 FFs / 6.5 BRAM, WNS +1.196 ns +| *B* | `featparity_noc` (compact packer *off*) | 4 570 LUTs / 4 221 FFs / 6.5 BRAM, WNS −0.718 ns +|=== + +`CT_EN_DATA_TRACE` and the `CT_EN_DAQ` group cannot be measured on base +*A* at all: `ct_L2_compact_packer` stops elaboration with +"`CT_COMPACT_PACKER` requires a CF-only profile" — the lean egress path +and the DF/DAQ message formats are mutually exclusive by construction. +That is precisely why these switches carried "not measured individually" +for so long: the obvious differential measurement runs into an +elaboration guard, not into a missing test. + +*Deltas must never be arithmetic across the two bases.* A by-product of +the split is the cost of the egress path itself: the historical formatter +path is **+1 018 LUTs / +623 FFs** over the compact packer in the same +profile. + +*Two switches are measured **inverted*** — base with the switch *off*, +variant with it *on*, sign flipped: `CT_EN_QUOTA_SYNC` and +`CT_EN_FIFO_HIST`. `scripts/ct_profiles.sh` does not touch either, so +both otherwise stay at the committed value 1 and the naive delta is 0. +That is not a null result, it is a measurement that never happened — and +one of the two produced exactly that silent zero on a first attempt. +Whenever a switch is added to this table, check first whether the profile +script sets it at all. + +[#filter-cost-drivers] +*Where the `CT_EN_FILTERS` cost sits.* The switch gates two things: the +`ct_L23_preproc_comp_filters` instance, and — through +`CT_PROFILE_NO_FILTERS` — the entire CSR bank behind it, whose storage +and write decode vanish with it. Counting the register bits directly: +16 filters × 180 bits + 8 comparators × 206 bits + 16 bits = +**4 544 register bits**, i.e. **89 %** of the measured +5 085 FFs. The +remainder is per-filter exception stacks, two sets of 16 saturating +trap-window counters, and a hit pipeline that also deepens because +`PREPROC_DELAY_MAX` goes 2 → 4 with filters on. The LUT side is the match +datapath: 8 dual 32-bit magnitude comparators feeding 16 parallel +per-filter AND trees. `NUM_TRACE_FILTER` and `NUM_TRACE_COMPARATORS` are +genuine RDL parameters, so the figure is the cost *of the default 16/8 +configuration* — the scaling law itself is not measured here. + +[#daq-cost-drivers] +*Where the `CT_EN_DAQ` group cost sits.* Unlike the filters this one is +**not** reconciled to a bit count, and it is quoted as a group for the +reason given in the row. What is code-verified are five mechanisms that +trip at the same threshold and compound inside the same P-wide compacting +queue: the DAQ payload (3 × 32-bit elements + a 32-bit address = 128 bits) +becomes the widest arm of the packed message union and is therefore paid +by *every* queued message; the queue depth quadruples (32 → 128); the +parallel slot count grows 3 → 4; the watchpoint CSR read-back shadow is an +explicit block-RAM copy; and the ACT-ST engine is a pipelined binary +search over the watchpoint table with 32-bit comparators per level. +The first three multiply, which is the most plausible explanation for the ++12.5 BRAM appearing here while the filters — which have no such queue — +stay at ΔBRAM = 0. *No bit-level accounting is claimed.* + +NOTE: The group figure above was measured at the historical table shape +(`M0_DIM` = 4: a four-level tree, 15 slots). Since C0b the tree has +**ten levels / 1023 slots** and the preproc alignment budget +`PREPROC_DELAY_MAX` grew 20 → 44 for `CT_EN_ACT` profiles — every +`EXTRA_DELAY_MAX`-deep alignment pipe in the preprocessor follows it. +Measured cost of the 68× capacity step (full profile, OOC, +Vivado 2022.1.2, `xck26-sfvc784-2LV-c`; verdict +`verification/evidence/C0b/ooc_pair.log`): + +[cols="3,^1,^1,^1", options="header"] +|=== +| C0b OOC pair | CLB LUTs | Register as FF | BRAM tiles + +| pre — `64ae043979`, `M0_DIM` = 4 (`verification/evidence/C0b/ooc_pre_util_flat.rpt`) | 26307 | 20743 | 9.5 +| post — `b4cc804692`, `M0_DIM` = 10 (`verification/evidence/C0b/ooc_post_util_flat.rpt`) | 30432 | 31204 | 14.5 +| delta | +4125 | +10461 | +5 +|=== + +The FF side is the alignment pipes (predicted +8–11 k in the C0b +analysis), the BRAM side is the ten-level tree plus the 1024 × 64 +readback shadow. + +[#wp-indirect] +*Indirect watchpoint table access (C0b) — BREAKING CHANGE.* The direct +64-bit memory window at `0x4100` is **removed**: 1023 entries × 8 B span +`0x4100-0x60F7` and collide with the `df` component at `0x5000` (PeakRDL +refuses the map), and a wider register space would drag the micro-CSR +twin and every integrator window with it. Software that wrote +`0x4100 + 8*slot` must switch to the indirect protocol: + +. write the start slot to `trWpIndex.Idx` (`0x400C`) once, +. per slot: `trWpDataLow` (`0x4010`) = Addr, then `trWpDataHigh` + (`0x4014`) = Cmd — the High write *commits* the pair to slot `Idx` and + increments `Idx` (wrap at the last slot), +. capacity discovery: `trWpCap.Entries` (`0x4020`, reads 0 in profiles + without `CT_EN_ACT`), +. readback: `trWpReadLow`/`trWpReadHigh` (`0x4018`/`0x401C`) return the + shadow entry at `Idx`; the High read advances `Idx` (serial readback, + the `trTeTipFifoHistData` pattern). The shadow is zero-initialized at + configuration load and not cleared by a soft reset. + +All three load registers are Enable-locked (`swwel`), and the commit +pulse is additionally suppressed while `trTeControl.Enable` = 1 — rule 4 +of the programming contract ("change the table only while disabled") is +now hardware-enforced instead of procedural. The lock covers the *load* +path only: the readback pair stays live while enabled, and a +`trWpReadHigh` read still advances `Idx` (by design — a debugger can +walk the table of a running session without unlocking it). The +programming rules themselves (fill ALL slots, strictly ascending unique +keys, odd addresses for padding slots) are unchanged and live in the RDL +description of `trWpDataHigh`. + +[#profile-timing] +*Timing per profile.* The table above rows by *switch*; timing is a +property of the whole build, so this one rows by *profile*. +Out-of-context synthesis of +`ct_encoder` on `xck26-sfvc784-2LV-c`, **Vivado 2022.1.2** (the version +`.abc.config` pins), commit `7a0b7b2`, 2026-08-06. Reproduce with + + bash scripts/p10_timing_matrix.sh + +Two budgets, because a slack figure without its budget says nothing: +**13.333 ns (75 MHz)** is the clock the KV260 reference design is +*constrained* to and therefore the "slack in the target configuration"; +**5.0 ns (200 MHz)** is a headroom probe, and the budget the phase-D +matrix used. What the PL is constrained to is not automatically what it +is clocked at on the board — see the caution in +link:verification.adoc#ooc-timing[verification, *Timing and resources*] +before reading the 75 MHz column as a statement about silicon. + +[cols="4,^1,^1,^1,^1,^1", options="header"] +|=== +| Profile | CLB LUTs | Register as FF | WNS @ 13.333 ns | WNS @ 5.0 ns | Fmax + +| `voll_gold` — the committed full profile | 25 784 | 20 168 | *+4.175 ns* | −4.158 ns | 109.2 MHz +| `featparity_gold` — CF-only, compact packer, single clock | 4 938 | 4 824 | *+8.672 ns* | +0.339 ns | 214.5 MHz +| `slimfull_gold` — `featparity_gold` + slim eTIP CDC, no watermark, no timestamp unit | 4 290 | 3 984 | *+8.695 ns* | +0.362 ns | 215.6 MHz +| `nonly` — full profile, N-Trace back end (the same build as `voll_gold`) | 25 784 | 20 168 | *+4.175 ns* | −4.158 ns | 109.2 MHz +| `eonly` — full profile, E-Trace back end | 26 372 | 16 953 | *+1.753 ns* | −6.580 ns | 86.4 MHz +|=== + +*At the board budget every profile meets timing*, the smallest margin +being the E-Trace build's +1.753 ns; Vivado's own verdict line in those +five reports is "All user specified timing constraints are met", with +zero failing endpoints. At 200 MHz the two slim profiles still make it +and the three full-profile builds do not (2 777 resp. 1 155 failing +endpoints). 200 MHz is not a requirement anywhere in this project — the +column is headroom information, and it is here as measured rather than +dropped for being inconvenient. + +The reports these rows are read from are **in the tree**, one directory +per profile under `verification/evidence/P10/`. LUTs and flip-flops come from +link:../verification/evidence/P10/voll_gold/timing_75mhz_util_flat.rpt[`voll_gold`], +link:../verification/evidence/P10/featparity_gold/timing_75mhz_util_flat.rpt[`featparity_gold`], +link:../verification/evidence/P10/slimfull_gold/timing_75mhz_util_flat.rpt[`slimfull_gold`], +link:../verification/evidence/P10/nonly/timing_75mhz_util_flat.rpt[`nonly`] and +link:../verification/evidence/P10/eonly/timing_75mhz_util_flat.rpt[`eonly`]; the WNS +figures from the `timing__summary.rpt` next to each of them, and +the verdict from `verification/evidence/P10/timing.log`. + +[NOTE] +==== +*What this number is, and what it is not.* Out-of-context synthesis of +`ct_encoder` alone, with one clock per clock port at the same budget and +`set_clock_groups -asynchronous` between them — the encoder's CDC +structures are exactly what a real SoC XDC decouples the same way, and +cross-domain paths are consequently outside this analysis. It is a +post-synthesis figure, not a placed-and-routed one; routing takes some +of the margin back. The one P&R number this project has is the +`mbv_kv260` reference design of 2026-08-01 further down, which predates +P2..P9. + +*Two controls came out of the runs themselves.* `nonly` and `voll_gold` +are the same build — the two profile definitions produce a +byte-identical `ct_pkg.sv`, and the two independent synthesis runs then +agree on every figure including TNS and the failing-endpoint count. And +the two budgets of each profile agree on the critical path (budget minus +WNS) to the picosecond, which is what makes the second run of a profile a +control rather than a repetition. + +*The slim profiles are no longer the ~2.5 k-LUT builds of seq 22.* Those +figures date from 2026-07-20; the gold profiles deliberately leave +`CT_EN_BTM`, `CT_EN_SYNC_STATUS`, `CT_EN_FIFO_HIST`, `CT_EN_QUOTA_SYNC`, +`CT_EN_DEVICE_ID`, `CT_EN_TRIG_REGS` and `CT_EN_INST_SYNC_REQ` at their +full-profile value, so everything P2, P4, P7 and P8 added is inside the +4 938 LUTs above. A build that wants the seq-22 size has to switch those +off as well. +==== + +[#xlen-cost] +*Address width (X2a).* What 64-bit addresses cost. OOC on +`xck26-sfvc784-2LV-c`, **Vivado 2022.1.2**, the committed profile +unchanged except for `ct_pkg::CT_XLEN`, commit **`efb715a22`**, +2026-08-08. Reproduce with + + bash scripts/r11_ooc_xlen_pair.sh both committed + +[cols="3,^1,^1,^1", options="header"] +|=== +| `CT_XLEN` | CLB LUTs | Register as FF | Block RAM Tile + +| 32 (default) | 26 283 | 20 712 | 9.5 +| 64 | 30 180 | 22 564 | 11 +| *delta* | *+3 897* | *+1 852* | *+1.5* +|=== + +Reports in the tree: +link:../verification/evidence/R1_1/committed_xlen32/util_flat.rpt[`committed_xlen32/util_flat.rpt`] +and +link:../verification/evidence/R1_1/committed_xlen64/util_flat.rpt[`committed_xlen64/util_flat.rpt`], +with the per-instance breakdown next to each of them in `util_hier.rpt`. + +Where it goes, from the hierarchical reports: **+2 418 LUTs / +1 655 FFs +in `ct_L23_preproc`** — the comparator chain (twice the compare width), +the two `vector_binary_search` trees of ACT-ST and the DF range filter, +the composer's eTIP payload and the TIP delay line, i.e. every place +that stores or compares an address. The remaining ~1 100 LUTs are spread +over `msg_gen` (+507, JTC cache and the wider fold), the eTIP FIFOs and +the formatter. The +1.5 BRAM tiles are **not** the jump-target cache — an +earlier revision of this section said so and the report it cites +contradicts it: `msg_gen`, which contains that cache, holds 0 RAMB in both +builds (its cache is LUTRAM, 384 → 416). The step sits entirely in the +clock-crossing FIFOs of the composer: `etip_cvs_cdc_fifo` (8/2 → 10/0 +RAMB36/RAMB18) and `next_iaddr_fifo` (0/1 → 1/0), i.e. the payload that +crosses domains got wider, not the cache (R1.1 audit, B-2). + +One number deserves a caveat rather than a confident story: the +generated register block grows by 858 LUTs *without a single additional +flip-flop* (5 969 in both builds). The likely reason is that the +comparator `*High` registers have no reader at 32 bit — their output +logic folds away — and acquire one at 64; that is a plausible reading of +two reports, not a measurement of its own, and it is written here as +such. + +*What this measurement is not:* it is not the cost of "RV64 support" as +a whole. The E-Trace back end is excluded by construction (elaboration +guard), the reference decoder is a separate work package, and this is +post-synthesis, not placed-and-routed. + +[#p4-cost] +*Status messages (P4).* OOC on `xck26-sfvc784-2LV-c`, **Vivado +2022.1.2**, full profile otherwise, five runs of +`scripts/synth_encoder_ooc.tcl` differing only in the two switches (and, +in the last row, in the slot formula). Reproduce with + + vivado -mode batch -source scripts/synth_encoder_ooc.tcl \ + -tclargs xck26-sfvc784-2LV-c + +after setting the two `localparam bit` lines in `rtl/pkg/ct_pkg.sv`. The +two rows below were measured at commit **`28bb49e`**, and the reports +they were read from are in the tree: +link:../verification/evidence/P4/ooc_both_on_util_flat.rpt[`verification/evidence/P4/ooc_both_on_util_flat.rpt`] +and +link:../verification/evidence/P4/ooc_both_off_util_flat.rpt[`verification/evidence/P4/ooc_both_off_util_flat.rpt`]. +Per-run copies also land in `bld/p4_ooc__util_flat.rpt` / +`_util_hier.rpt`, but `bld/` is gitignored and its files are per-host and +per-generation — the tree copies are the quotable ones. (The script +itself always writes `bld/synth_ooc/util_flat.rpt`, which the NEXT run +overwrites; never quote that path.) + +IMPORTANT: A resource figure is only meaningful together with the commit +it was measured at. The full profile keeps growing while packages land: +a run of the same `both_on` configuration at a later HEAD gave **25 787** +CLB LUTs, +78 over the row below, and those 78 belong to P8's RTL between +`28bb49e` and that HEAD (among others the new +link:../rtl/pkg/ct_sync_req_pacer.sv[`rtl/pkg/ct_sync_req_pacer.sv`]) — +not to P4. The **pair delta** below is the P4 statement and is unaffected +by that drift, because both of its runs sit on the same commit. + +[cols="3,^1,^1,^1", options="header"] +|=== +| `CT_EN_DEVICE_ID` / `CT_EN_WATCHPOINT_MSG` | `ETIP_PAR_MSG` | CLB LUTs | Register as FF + +| 1 / 1 (committed full profile, `both_on`) | 9 | 25 709 | 20 172 +| 0 / 0 (both compiled out, `both_off`) | 8 | 25 454 | 20 199 +|=== + +Both features together cost **+255 LUTs / −27 FFs** — inside the ±300-LUT +restructuring band of the interpretation rule above, i.e. at this +resolution they are close to indistinguishable from free. The Device ID +takes the slot; the watchpoint arm shares the DAQ slot, which is why the +pair moves the count by exactly one. + +.The rows this table used to carry, and why they are gone +[NOTE] +==== +An earlier revision of this table listed five rows measured at +`ETIP_PAR_MSG` = 5/6/7 (`both_on` 25 635, `wp_off` 25 851, `devid_off` +25 269, `both_off` 25 530, and a `both_on_p7` control at 7 slots giving +25 722). Those numbers are still true *for the builds they were taken +from*, but those builds carry a slot bound that has since been **refuted** +(see <>) — quoting them next to the current rows would invite +a subtraction across two different designs. They are kept in the raw +reports (`bld/p4_ooc_*`) and in the package handoff, not here. + +What the pair of measurements *does* say about the correction: the same +committed profile went from 6 to 9 slots and from 25 635 to 25 709 +CLB LUTs, i.e. **+74 LUTs / −6 FFs for three additional slots** — the +soundness fix is far below the restructuring band. The single-feature +rows are not repeated: at this resolution they measure the netlist +repacking, not the feature. +==== + +The sharing claim itself is checked against a design that really raises +DAQ slots: the `wpdaq` leg of `tests/instruction/31_status_msgs` issues a +DAQ command in place of the second watchpoint command, so ONE run carries +two watchpoint messages *and* one Data Acquisition message. Before that +leg no leg produced a DAQ message at all and `a_p4_wp_daq_exclusive` was +vacuously true. Removing the exclusion `Cmd != ACT_CAP_ST_WATCHPOINT` +from the DAQ arm makes the assertion fire and lifts the measured +watermark from 1 to 2 slots per beat — the property is alive. The same +mutation is the R-EXCL red cross-check of the formal gate. + +The Device ID slot is additive to the config slot of the *same* beat, and +that is measured rather than argued: the composer's P4 telemetry prints +"ONE beat carries Device ID (slot 0) AND Config (slot 1)" for every +`did`/`both`/`src` leg of `tests/instruction/31_status_msgs`. An earlier +reading of that leg — "four slots out of ONE trace-start beat" — was +wrong and is retracted: the sync CF and the ownership message land in +LATER beats, and the per-run watermark of that leg is **2**. + +[#slot-bound] +.The slot bound is proven, not counted +**** +`ETIP_PAR_MSG` is the number of eTIP slots one tip beat may allocate. An +exceeded bound writes `etip_msg_next[]` out of range, which writes +*nowhere*: messages are lost **silently**, with no error indication on +the wire. Until the P4 re-audit the constant was a closed-form sum over +five of the composer's **thirteen** allocation sites, described as a +"structural worst case" — an argument, not a proof, and three allocation +sources sat outside every term of it. + +It is now proven. `formal/composer_slots` (P-SLOT-1) checks the +composer's own immediate assertion `a_p4_slot_bound` over the real module +with a completely free environment — every tip beat, every sync verdict, +every ACT-ST command and every CSR value the solver can construct — for +`SPLIT_DATA_ACCESS` 0 **and** 1, by k-induction, i.e. unbounded. The +proof refuted the previous value: the bound broke at BMC step 1 on a beat +carrying **eight** slots (a trace-on edge with device ID and config, a +still-pending sticky trace-off correlation from the previous beat, a +low-power entry marker, a processed retire with a sync verdict giving CF +and ownership, a qualified data access, and an ACT-ST watchpoint +command). The corrected formula names every source, and the red +cross-check shows one slot less is refuted — the value is the minimum, +not padding. + +The one place where the constant is deliberately *not* minimal is the +shipped `SPLIT_DATA_ACCESS = 0` build: there a bound of 8 also passes +k-induction while the formula gives 9, because the same constant has to +cover the `= 1` integration (see below). That single slot of margin is +the price of not having a second source of truth for a module parameter, +and it is stated rather than hidden — the tightness cross-check therefore +runs in the `= 1` configuration, where the constant is exact. + +Two sources that had no term before: + +* the **trace-off correlation** (TCODE 33). `DoCorrDisable` is sticky + until the flush ack, so it can still be pending on the *next* trace-on + beat. This is why a control-flow-only profile needs three slots, not + two — the previous CF-only bound of 2 was unsound as well, and that is + older than P4. +* the **second data-flow arm**. With `SPLIT_DATA_ACCESS = 1` the store + arm and the split-load response arm are independent `if` statements and + one beat can raise both. `SPLIT_DATA_ACCESS` is a parameter of + `ct_encoder` and a package constant cannot see it, so the constant now + budgets the worse of the two settings rather than introducing a second + source of truth for the same fact. Integrations with the parameter set + therefore need no special build. + +Two exclusions keep the constant down to the proven value, and both are +*combinational* (which is why the induction goes through with free +state): the ICNT pre-drain and the debug/low-power entry marker share one +slot (the marker clears the cumulated halfword count first, after which +the pre-drain condition cannot hold), and the watchpoint arm shares the +DAQ slot (same beat qualifier, mutually exclusive command codes). + +The **measured** demand is a separate, weaker statement and is kept as +one: reproduce it with + + scripts/collect_slot_watermarks.sh [] + +which aggregates the composer's per-run watermark line ("eTIP max slots +per beat") over the xsim logs under `bld/`. A measured maximum bounds +nothing — it is a sanity check that the shipped configuration operates +far from the bound, not evidence for the bound. +**** + +The absolute numbers above are NOT comparable with the older P4 table: +they were taken at commit `c793942` (RTL-identical to `a04b37b`, which +only adds test and script files), whose baseline already contains the P7 +register/drop-policy work. The Vivado version also differs from the rows +above, so these figures must not be subtracted from the 2025.1 numbers +either. + +NOTE: Several runs needed a repeat. Vivado 2022.1.2 aborts `synth_design` +with `couldn't read file …: No error` on files of *its own* installation +under host load — first seen with a second Vivado running, later +reproduced with **no** second Vivado at all and only three `yosys` +processes on the machine (`…/retarget/retarget_vhdl.tcl: No error`). The +trigger is concurrent load on the installation directory, not +specifically a second Vivado; the repeat under the same conditions then +produces the report. Not a design property — `bld/p4_ooc_retry.log` +records every attempt. + +Profile aggregates (same flow): featparity_base_v2 2 517 LUTs (~254 MHz) · +featparity_cfgonly 2 867 · featparity_gold 3 646 (~206 MHz) · slimfull_base_v2 +2 106 (~255 MHz) · slimfull_gold_v2 3 147 (~182 MHz) · voll_gold 24 354 +(~111 MHz). All nine gold-standard features together on the featparity base: ++1 129 LUTs / +1 142 FFs / +6.5 BRAM. + +[#p7-cost] +*Trigger registers and the data-trace drop policy (P7) — measured as a +pair.* OOC on `xck26-sfvc784-2LV-c`, **Vivado 2022.1.2**, full profile +otherwise, two runs differing only in the two switches (both from the +same detached worktree at commit `c793942`, RDL profile regenerated per +run). Reproduce with + + bash scripts/p7_ooc_pair.sh + +The reports these four rows are read from are **in the tree**, one per +row: +link:../verification/evidence/P7/ooc_on_util_flat.rpt[`ooc_on`] (1/1), +link:../verification/evidence/P7/ooc_drop_off_util_flat.rpt[`ooc_drop_off`] (1/0), +link:../verification/evidence/P7/ooc_trig_off_util_flat.rpt[`ooc_trig_off`] (0/1), +link:../verification/evidence/P7/ooc_off_util_flat.rpt[`ooc_off`] (0/0), all under +`verification/evidence/P7/` (+ the `_util_hier` twins). `scripts/p7_ooc_pair.sh` +writes its per-run copies to `bld/p7_ooc__util_*.rpt`, but `bld/` is +gitignored and the next run overwrites them — never quote that path +(P4 audit B-1 / P8 closing audit B-N2, checked by +`scripts/check_doc_evidence.py`). + +NOTE: The absolute figures in this table belong to commit `c793942` and +those in <> to `28bb49e`; the full profile grew between them. +Do not subtract a number in one table from a number in another — only +the **pair delta** inside a single table is a statement about a feature, +because both of its runs sit on the same commit. + +[cols="3,^1,^1", options="header"] +|=== +| `CT_EN_TRIG_REGS` / `CT_EN_DF_DROP` | CLB LUTs | Register as FF + +| 1 / 1 (committed full profile) | 25 635 | 20 178 +| 1 / 0 (`drop_off`) | 25 395 | 20 141 +| 0 / 1 (`trig_off`) | 26 078 | 20 156 +| 0 / 0 (both compiled out) | 25 641 | 20 119 +|=== + +Both features together cost **−6 LUTs / +59 FFs**. + +*The flip-flop column attributes; the LUT column does not.* The FFs are +exactly additive — `CT_EN_TRIG_REGS` +22, `CT_EN_DF_DROP` +37, and +20 119 + 22 + 37 = 20 178, the measured 1/1 value. Those registers are +the 4-bit action field with its clock-domain crossing, the two registered +trace-on/off strobes, the drop-policy enable with its crossing, the +watermark arm and episode latch, and the three sticky RW1C status bits +with their event strobe synchronizers. The LUT deltas of the same four +runs are −246 / +437 / −6 with no additive structure at all (a spread of +~680 LUTs, one of them outside the ±300 band): that is the restructuring +effect of the interpretation rule above, so **no per-switch LUT figure is +quoted**, and the pair delta is quoted only as "in the noise". Neither +switch raises `ETIP_PAR_MSG` (the drop marker takes the slot the +suppressed data-trace message would have used), so the structural term +that dominates <> does not apply here — which is why the LUT +count has no reason to move in the first place. + +NOTE: the `1 / 1` row reproduces, to the LUT and to the flip-flop, an +independent earlier run of the same configuration in the main tree +(`bld/p7_ooc_on_util_flat.rpt` was written twice, 2026-08-05 08:08 and +10:10, from different trees) and equals the `both_on` row of +<>, which is the same profile. +==== + +[#p8-cost] +*Explicit sync request over the TE register (P8).* OOC on +`xck26-sfvc784-2LV-c`, **Vivado 2022.1.2**, full profile otherwise, two +runs differing only in `CT_EN_INST_SYNC_REQ` (same detached worktree, +commit `d0eba9b`; no RDL profile regeneration — the switch has no +profile define, so both legs synthesize the identical CSR block). +Reproduce with + + bash scripts/p8_ooc_pair.sh both + +The reports these numbers are read from are **in the tree**: +`verification/evidence/P8/ooc_off_util_flat.rpt` / +`verification/evidence/P8/ooc_on_util_flat.rpt` (+ the `_util_hier` twins). They +used to be named under `bld/`, where the next run of the same script +overwrites them with a different configuration — a reader following the +reference then arrived at numbers that contradicted this table +(P8 closing audit B-N2, the same defect P4 had one commit earlier). + +[cols="3,^1,^1", options="header"] +|=== +| `CT_EN_INST_SYNC_REQ` | CLB LUTs | Register as FF + +| 1 (committed full profile) | 25 784 | 20 168 +| 0 | 25 707 | 20 156 +| *delta* | *+77* | *+12* +|=== + +[NOTE] +==== +*The flip-flops attribute exactly.* The 12 registers are the CSR-side +pacing pair (`ct_sync_req_pacer`: `Req`, `Queued`), the two `signal_cdc` +crossings — request out and acknowledge back, two flip-flops each in +this profile, which builds multi-clock (`CT_SINGLE_CLOCK = 0`) — the +generator's pending latch and its acknowledge level, and the third bit +of `SyncReqSource` with the two data stages of its `vector_cdc2`. +2 + 2 + 2 + 2 + 1 + 2 + 1 = 12, the last one being the `InstSyncReq` +field storage itself, which had no consumer before and was therefore +optimized away. + +*It got cheaper when it got safer.* The first P8 build crossed the +request as a pair of paced STROBES and cost +80 LUTs / +16 flip-flops. +Two `strobe_cdc` instances are four flip-flops each (edge flop, two-flop +synchronizer, edge flop) where a `signal_cdc` is two, and the closing +audit's B-N1 finding forced the change for a different reason +altogether: a strobe cannot survive a reset of the consumer's domain +alone, a held level can (see <>). The four +flip-flops the crossings give back are a side effect of doing it right, +not the argument for it. + +*The LUT column is restructuring, and that is measured, not asserted.* +An earlier run of the same pair, before the field moved to the +`sw = w; singlepulse;` idiom and before the pacing became a module of +its own, reported +3 LUTs at a +16 flip-flop delta. Two controls, run on +the strobe-based build in the session that produced +`verification/evidence/P8/ooc_resources.log`, pin down where the difference comes +from — they are quoted here as the attribution of the LUT column, and +they were NOT repeated for the level handshake (the flip-flop count is +what this feature is quoted by, and it attributes exactly, above): + +* the pre-change commit `0eff631`, feature ON, re-synthesized there: + **25 622 / 20 194** — exactly the earlier number, so the session and + the tool were stable; +* the same commit with the pacer body inlined back into the shim + (isolation build, never committed): **25 699 / 20 194** — exactly the + number of the extracted build, so extracting `ct_sync_req_pacer` costs + *nothing* (the hierarchical report shows the instance as 2 LUTs / 2 + FFs and Vivado flattens it). + +What remains is the register-block idiom: behaviourally identical logic +(the self-clear moved from a shim tie-off into the generated block), a +different source shape, and the synthesizer restructures around it. No +flip-flop moved, which is the number this feature is quoted by; the LUT +delta stays inside the ±300 band described above. + +*Zero cost when off is measured, not assumed:* the OFF leg lands on +25 707 LUTs / 20 156 flip-flops, bit for bit what the OFF leg of the +earlier, strobe-based build reported — the B-N1 redesign touches only +logic that `CT_EN_INST_SYNC_REQ = 0` removes, which is what "zero cost +when off" has to mean. That includes the widened `SyncReqSource`: with +the TE source compiled out, its third bit can never be written, so the +bit and the extra `vector_cdc2` stage trim away with it. + +One thing the OFF build is *not*: the pre-P8 encoder. The one-cycle +double-emission window in the shared sync arm was closed outside +`CT_EN_INST_SYNC_REQ` (see the release notes), so the ATB request path +behaves better in both builds. The flip-flop count is identical; the +behaviour of that path is not. +==== + +=== Runtime fields without a build switch + +Fields that exist in every profile (base programming model and +diagnostics): + +* `trTeControl` — `Active`, `Enable`, `InstTracing`, `Empty` (RO), + `InhibitSrc` (reset **1**), `InstSyncMode` (reset **0**, no periodic + cadence), `InstSyncMax` (reset **6** = a period of 1024 units in + whichever unit the mode selects), `Format` — the base programming + model (see the programming contract above). +* `trTeInstFeatures.SrcID` (reset 10) / `SrcBits` (reset 4) — source-ID + configuration. +* `trTeDataControl.DataImplemented` (RO, discovery), + `DataAddrCompress` (only `DTR_ADDR_FULL` implemented — XOR/DIFF modes + are stubbed), `DataSplitLoad` (RO, mirrors the `SPLIT_DATA_ACCESS` + elaboration parameter). +* `trTsControl.Active` / `Count` / `Reset` — timestamp-unit runtime + control (subordinate to `CT_EN_TIMESTAMP`). +* `trTeCsrControl` (te 0xE00, RO) — CSR-driven send-request mirror. +* `trTeTipFifoStatus.trTeTipFifoNumOverflows` + the two clear bits — + overflow diagnostics, always present. + +=== Build switches without a runtime field + +Four `CT_EN_*` switches in the table above have no runtime CSR field at +all — their Runtime cell is `—` (`CT_EN_DAQ`, `CT_EN_DEBUG_EVENTS`, +`CT_EN_POWER_EVENTS`, `CT_EN_EVTI`); they are event- or command-driven +at run time. (`CT_EN_ACT` likewise has no single enable *bit* — its +runtime surface is the indirect watchpoint table (<>) and +the command word.) The +remaining build knobs configure structure rather than switchable +features: + +* `CT_SIJUMP` — elaboration parameter of `ct_encoder` (sequential-jump + ingress convention of the attached core); advertised as CAPS bit 6. +* `CT_XLEN` — architectural address width of the attached hart, 32 + (default) or 64; advertised as CAPS bit 23 (`ADDR64`). Not a feature + and not a runtime mode: it sizes the TIP address ports, the Nexus + address fields, the address comparators, the JTC index fold and the + eTIP payload in one place. A decoder cannot infer the width from the + stream (variable-length address fields with leading zeros stripped), + which is why it is on the wire; see `doc/trace-format.adoc`. At 32 the + emitted bytes are identical to every earlier build. Constraints: the + comparator bounds and the ACT-ST / DF-range keys are CSR-programmable + in the low 4 GiB only (the CSR side stays a 32-bit word pair — the + compared address is full width), and `CT_EN_ETRACE` with `CT_XLEN` = 64 + is rejected at elaboration (the te_inst address fields are sized by + `CT_ETRACE_ADDR_BITS` = 31; 64-bit E-Trace is a separate step). +* `CT_CONTEXT_WIDTH` — width of the TIP context bus (`tip._context`), 2 + (default) or as wide as the attached hart's context identifier: 16 for + a RISC-V `satp.ASID` under Sv39/Sv48, 9 under Sv32. Unlike `CT_XLEN` + this width is **not** advertised on the wire and needs no CAPS bit: the + Ownership message carries the value in the 44-bit `PROCESS` field, + which leaves the encoder as a variable-length field with leading zeros + stripped, so the whole value is on the wire and self-delimiting. + Legal range 1..44 (`NEXUS_MSG_PROCESS_WIDTH`), checked at elaboration + in `ct_encoder` — a wider bus would be truncated silently by the + composer's cast and the stream would name the wrong process. At 2 the + emitted bytes are identical to every earlier build; with the reset + configuration (`trTeControl.Context` = 0) no Ownership message is + emitted at any width. +* `CT_SINGLE_CLOCK`, `CT_TS_WIDTH`, `CT_SLICER_STEPS`, + `CT_COMPACT_PACKER`, `CT_MICRO_CSR`, `CT_ETIP_SERIALIZE`, + `CT_ETIP_CDC_SLIM`, `CT_ETIP_FIFO_STYLE`, `CT_FIFO_HIST_BINS` — + structural sizing/architecture knobs, each documented at its + definition in `ct_pkg.sv`. +* `CT_EN_COMPRESSION` — *derived* OR over the eight compression-suite + switches (`ct_pkg.sv`), not an independent switch. +* `CT_RET_STACK_DEPTH`, `CT_JTC_ENTRIES`, `CT_BP_ENTRIES` — structure + constants advertised in the config message (`PARAM3`). + +== Resource footprint (measured) + +For the *current* per-profile figures — LUTs, flip-flops and the slack +each profile reaches against the board budget — see <>. +The snapshot below is the only *placed-and-routed* measurement this +project has, and it is **historical**: 2026-08-01, i.e. before P2..P9. + +*HISTORICAL (2026-08-01, pre-P2..P9).* Placed-and-routed on a Kria KV260 +(`xck26-sfvc784-2LV-c`, Vivado 2026.1, reference design `mbv_kv260`, +full profile including all compression features, timestamps, DAQ/ACT and +the V8 empty chain; WNS +2.679 ns at 75 MHz single-clock — that figure +belongs to this design and this tool version, not to today's encoder. +Corrected 2026-08-14: earlier revisions of this document quoted +2.186 ns, +which is traceable in the artifacts only as Vivado's *router estimate* +(`[Route 35-416]`, carrying the tool's own pre-signoff caveat). The value +above is the one the routed timing summary reports +(`impl_1/mbv_kv260_top_timing_summary_routed.rpt`: WNS 2.679, TNS 0.000, +0 of 74 269 endpoints failing) — a router estimate must not be quoted as +a placed-and-routed result): + +[cols="2,1,1,1", options="header"] +|=== +| Instance | LUTs | FFs | BRAM + +| `ct_encoder` (total) | 23 428 | 19 065 | 8×RAMB36 + 3×RAMB18 +| — preprocessor (`ct_L23_preproc`) | 6 429 | 4 966 | 8×RAMB36 + 3×RAMB18 +| — CSR block (`ct_cs_cpuif_wb`) | 4 954 | 7 829 | — +| — E-Trace generator (`ct_L2_te_inst_gen`) | 4 177 | 1 258 | — +| — MSEO/MDO formatter | 4 005 | 2 712 | — +| — message generator (`ct_L2_msg_gen`) | 3 760 | 737 | — +| — E-Trace packetizer | 83 | 289 | — +| `mbv_to_ctte_tip` adapter | 1 | 64 | — +|=== + +NOTE: This snapshot predates P9 (2026-08-04): the design was built with +BOTH back ends instantiated, which is why an E-Trace generator and an +N-Trace message generator appear side by side in one `ct_encoder`. That +configuration no longer exists — an encoder now instantiates exactly one +back end — so the total and the two unused-back-end rows are historical. +The numbers are kept because they are what was measured; a rebuilt +single-protocol encoder drops the second back end (the isolated cost of +the second one was +5 526 LUTs / +3 055 FFs, same design and tool +version). Re-measure before quoting a current figure. + +The full profile is the *maximum* configuration; compile-time profile +switches (`ct_pkg::CT_EN_*`) shrink unused feature groups to zero. The +~2.1–2.5 k-LUT class this section used to quote for the slim CF-only +profile is a seq-22 figure (2026-07-20): the same profile measures +4 938 LUTs today, because the gold profiles keep the P2/P4/P7/P8 +features on — see <>, which is the table to quote from, +and `scripts/p10_timing_matrix.sh` to re-measure per release. + +== Versioning caveat for core-specific adapters + +Adapters from non-standardized core trace buses (e.g. the AMD +MicroBlaze V `TRACE` bus) are **pinned to a specific core/tool +version** by construction — the bus is documented as not +backward-compatible. Keep the adapter outside the encoder core and +re-characterize it per core version; the characterization gate lives with +the SoC integration project, not with the encoder. diff --git a/doc/release-notes.adoc b/doc/release-notes.adoc new file mode 100644 index 0000000..226d388 --- /dev/null +++ b/doc/release-notes.adoc @@ -0,0 +1,465 @@ +// SPDX-FileCopyrightText: 2026 Accemic Technologies GmbH +// SPDX-License-Identifier: CC-BY-4.0 + += Release notes and known limitations + +NOTE: The product name is *CEDARtools.TraceEncoder*, abbreviated *CTTE*. +The earlier name *C-Trace* is retired from prose; it survives only in the +`ct_*` identifier prefix (the IP's public API), in board- and +bundle-visible names (`*_ctrace_kv260`, `ctrace_resmem.dtso`, +`ctrace-pl-ddr`, the `mbv_ctrace_soc` block design) and in recorded +captures and evidence files, which are raw data with published checksums. +See the naming note in the README. + +== 1.0.0 (2026-08-28) + +The first tagged release. Nothing about the encoder changed for it -- the RTL +is the one the verdicts below were measured against. What changed is that the +repository became publishable: + +* **Two back ends, one event stream.** N-Trace (IEEE-ISTO 5001-2012 Nexus + messages on ATB) and E-Trace 2.0 (`te_inst` packets). Which one an encoder + instance speaks is a synthesis parameter (`EN_NTRACE` / `EN_ETRACE`), so a + multi-encoder SoC can mix protocols in one netlist -- demonstrated on the + KV260 by the `trio` example. + +* **Nine worked KV260 integrations** under `examples/kv260/`, four of them + gated on real hardware, plus a no-hardware browser dashboard that replays + committed captures. The shared MINRES TGC5B building blocks moved to + `examples/kv260/common/tgc5b/`; the `tgc5b_soc` example they came from is + gone, superseded by `tgc5b2_axis_wp`. + +* **Ingress adapters** for AMD MicroBlaze-V (TRACE bus), CVA6 (ITI) and + Rocket (TCI), named `*_to_ctte_tip`. + +* **Formal property gates** (`formal/`, SymbiYosys) for the emission core, on + a licence-free toolchain, now run by GitHub Actions: a fast subset per pull + request, the full set nightly. + +* **CI that a fresh clone can run.** `make lint` carries 14 drift guards plus + Verible over 308 files; `make check-publication` adds the six guards that decide whether + the tree is fit to publish (no lab internals, English-only, tutorial paths + resolve, no private host or retired repository name and every README link + resolves, vendored-CVA6 deltas documented, mbv register map consistent). + Five of them used to hang off an internal driver and had therefore never run + on a public CI; the sixth came out of the cross-repository audit before the + GitHub release. + +* **Naming.** The earlier product name *C-Trace* is retired from prose. It + survives only where renaming would break something outside this repository + -- see the naming note above. + +Known limitations are unchanged and listed below; read them before filing a +bug. What CI cannot run on a hosted runner is stated plainly in +link:../CONTRIBUTING.md[`CONTRIBUTING.md`]: the 51-gate XSIM battery needs +Vivado, hardware verdicts need a KV260 board, and the decode verdict needs the +pinned CTTD reference decoder. + +== Current state (2026-08-08) + +Verification highlights (details: +link:verification.adoc[verification]): + +* **Hardware robustness campaign all-green** (2026-08-01): 95/95 directed + runs on the KV260 reference design (overflow regimes incl. ATB + backpressure, feature/mix/sync/window/stop axes, IRQ, BTM, bisection, + determinism pair), machine-judged V1–V8 against an RV32 reference + model. +* **Simulation battery 15/15** as measured on 2026-08-01 (robustness + gates 01–11 + five compression byte-identity legs), Verilator line + coverage 93.42 % measured / 100.00 % effective (waiver-disposed + remainder). Both figures carry that date: gates have been added since + (the current list is the table in + link:verification.adoc[verification]) and the coverage rate has not + been re-measured since P9 changed numerator and denominator — so + neither number is quoted here as a *current* one. +* Full-SoC simulation twin (real MicroBlaze V + adapter, 1:1 board + clock profile, 343 629 retires, 24 natural overflow recoveries) + decodes transitions-exact. +* **64-bit harts, on hardware** (2026-08-08): Linux boots on cv64a6 and + on Rocket in the KV260 PL with the encoder built at `CT_XLEN` = 64. A + recorded window of the running cv64a6 kernel decodes with **zero error + messages**, 32 413 of 34 453 reconstructed PCs above 2^32, checked + against the disassembly by a tool that does not use the decoder. With + the current decoder pin the same stream yields 818 663 instructions, + bounded by the capture ring rather than by the trace. +* **The reference decoder was re-pinned twice** (2026-08-08): 64-bit + address decode with a per-source width, and a context switch reported + as a visible re-anchor instead of a fatal abort — without which no + preemptive kernel is decodable past its first task switch. Both + re-pins carry byte-neutrality evidence over the frozen 32-bit corpora; + the record is link:../bin/README.md[`bin/README.md`]. + +Functional changes in this cycle: + +* **Watchpoint capacity 15 → 1023 + indirect table access** (C0b, + 2026-08-13). The ACT-ST binary search tree grew from four levels/15 + slots to **ten levels/1023 slots** (`M0_DIM` 4 → 10); the preproc + alignment budget follows (`PREPROC_DELAY_MAX` 20 → 44, charged to + `CT_EN_ACT` profiles only) and the truncation class that would have + silently mis-aligned ACT-ST at the larger depth is now guarded at + elaboration (width guard in `vector_binary_search_2clk`, constant + budget guards in `act_st`/`df_range`, poison pattern for backends + that demote `$fatal`). + **BREAKING CHANGE:** the direct watchpoint memory window at `0x4100` + is removed (1023 entries collide with the `df` component at + `0x5000`); loading and readback go through `trWpIndex` (`0x400C`) / + `trWpDataLow`/`High` (`0x4010`/`0x4014`) / `trWpReadLow`/`High` + (`0x4018`/`0x401C`) with hardware auto-increment, and `trWpCap` + (`0x4020`) reports the capacity for software discovery. The load + registers are Enable-locked; commit is suppressed while tracing is + enabled. Migration recipe: + link:integration.adoc#wp-indirect[Integration → Indirect watchpoint + table access]. + +* **Trace-pause contract fixed end to end** (encoder + reference + decoder): qualifier pipelining aligns the effective + `Enable&&InstTracing` level with the delayed instruction beats; a + resume gate suppresses position-less beats until the re-anchor sync; + the open `next_iaddr` pairing of the last pre-pause control-flow + event is captured across the edge; the implicit-return stack is + cleared at the pause edge; gap re-anchor syncs are side-effect-free. + CTTD treats a correlation as a full decoder unlock (with JTC mirror + init) and re-locks anchor-only. +* **`trTeControl.Empty` is now driven** (was structurally tied + inactive): a conservative empty chain per backend tail (2-FF + synchronizer + quiet filter into the ATB domain). +* **Overflow-anchor hardening:** the recovery-sync injector defers + emission around any branch retire in the emission cycle + (`inject_hold` incl. not-taken branches). +* Twelve standing SVA invariants (I1–I12) encode the campaign's contract + lessons directly in the RTL (simulation-only). +* **Trace-quota sync cadence** (2026-08-04, `CT_EN_QUOTA_SYNC`): + `trTeControl.InstSyncMode` 1 (trace messages) and 4 (trace bytes) are + now functional — dedicated counters in all three egress paths bound + the decoder re-anchor distance by *emitted volume* (see + link:integration.adoc#quota-sync-live[Integration → Live / ring + operation]). The TCODE-58 CAPS/ENAB map grew **append-only** from 18 + to 19 bits (new bit 18, `QUOTA_SYNC`); with the feature compiled out + the emitted stream is **byte-identical** to the previous reference + family (md5-verified), and the ATB sync-request input now emits + `SYNC = 14` (REQ) instead of `PERIODIC`, aligning the wire with the + documented request semantics. +* **Protocol choice is a synthesis parameter** (2026-08-04): the + N-Trace/E-Trace decision moved from a runtime select to the + `EN_NTRACE`/`EN_ETRACE` parameters of `ct_encoder` — exactly one back + end per instance, checked by an elaboration guard. The dual build (both + back ends plus an eTIP demux and an ATB mux steered by + `trTeProtocolSel`) is **removed**; it was never used in a product and + cost a second full back end. `trTeProtocolSel.Protocol` and + `trTeImpl.ProtocolMajor` remain at the same addresses with the same + encoding but are now **read-only, hardware-driven discovery** of the + compiled-in back end, so a mixed SoC (one N-Trace encoder next to an + E-Trace one — supported, and gated by + `tests/instruction/24_protocol_param`) reports the truth per instance. + *Software impact:* a write to `trTeProtocolSel` no longer has an + effect; read it instead. Single-protocol builds are byte-identical to + the previous reference family (md5-verified), which is what the + committed profile has always been. + +* **TCI trigger configuration registers and a data-trace drop policy** + (2026-08-05, `CT_EN_TRIG_REGS` / `CT_EN_DF_DROP`): + `trTeTrigExtInControl` (`0x054`) now selects what a pulse on the + external trigger input does — 0 none, 2 trace-on, 3 trace-off, 4 + trace-notify (TCI Table 20). The historical + `trTeControl.InstTrigEnable` path to the `SYNC = 6` marker is + **unchanged**; action 4 is an additional *source* of the same + one-shot, so enabling both still yields exactly one marker per pulse. + `trTeTrigDbgControl` (`0x050`) and `trTeTrigExtOutControl` (`0x058`) + read 0 — the answer TCI prescribes for a trigger that does not exist + (there is no debug-trigger sideband and no trigger output port). + `trTeDataControl.DataDropEna` sheds data-trace messages once the eTIP + queue reaches 3/4 fill, to keep the instruction trace intact; each + drop episode is announced by ONE `Error`/`QueueOverrun` with + `ECODE = 0x02` and, deliberately, *without* the `SYNC = 7` re-anchor + of the generic overflow path. CAPS/ENAB grew append-only from 22 to 23 + bits (new bit 22, `DF_DROP`). `trTeControl.InstStallOrOverflow` and + `trTeDataControl.{DataStallOrOverflow,DataDrop}` are implemented as + sticky RW1C status (overflow half; the *stall* half has no back + channel to the hart and stays unimplemented — see + link:trace-format.adoc[trace format → conformance]). With both + switches compiled out the emitted stream is byte-identical to the + pinned reference family (md5-verified). *Decoder impact:* a stock + decoder needs no change to parse the drop marker, but one that treats + every `Error` as a full desync loses the instruction trace the marker + promises is intact — CTTD now scopes `ECODE = 0x02` to the data-trace + reference only. + +* **Explicit synchronization request over the TE register** + (2026-08-05, `CT_EN_INST_SYNC_REQ`): `trTeControl.InstSyncReq` (bit + 27, write-1) — the TCI-standard way of asking for an instruction + synchronization message — is now effective. It always existed and + always auto-cleared; what was missing was a consumer. On the wire it + is the explicit-request code `SYNC = 14`, the same one the ACT-CAP + `CF_SYNC` command and the ATB sync-request input produce, so **no + decoder change is needed**. The field is not tied to a cadence: it + works in every `InstSyncMode`, including mode 0. Contract: *one + message per request*, with a request depth of one in flight plus one + remembered — a write that lands while a request is still outstanding + is **not** swallowed, it becomes its own request and gets its own + message; only a write on top of an already queued one collapses into + it. Measured (`scripts/cli_tesyncreq_test.sh`): one write → one + `SYNC = 14`, two back-to-back writes → two, three → still two. A + request written while instruction tracing is paused is **deferred** + (served after the resume anchor `SYNC = 5`, not dropped), and requests + from two sources landing on the same retire are satisfied by that one + message. `trTeSyncStatus.SyncReqSource` grew to three bits and reports + the new source `4`, kept apart from `1` (ACT-CAP `CF_SYNC`) because + the requester is a different actor: the external control bus versus + the traced hart. No CAPS bit — the feature adds neither a message type + nor a wire field, so the stream is unchanged until software writes the + bit; with the switch compiled out the write is accepted and inert + again, exactly as before. Byte-neutral in both builds against the + pinned reference family — 31 of 31 streams md5-identical with the + switch ON as well as OFF. Read that ON run for what it is: none of the + reference testbenches ever writes bit 27, so it shows the feature is + *dormant* until asked, not that it works. The activity proof is the + `req` leg of the system test, which shows the same build with the same + stimulus producing exactly one additional message — the `SYNC = 14` — + and byte-identical output up to the point where it is inserted. + Across a reset of one domain the request behaves asymmetrically, and + the asymmetry is contract: it survives a `tip_rst` (the four-phase + level handshake re-presents it), and it does *not* survive a `wb_rst`, + which clears the pacer's own state. See + link:integration.adoc#independent-resets[Integration — resetting one + domain without the others] for what is and is not claimed. ++ +*Fixed along the way, same release:* one explicit request could produce +**two** `SYNC = 14` messages when the hart retired on consecutive +cycles. The handshake output only drops one cycle after the +acknowledgement, so the sync arm stayed eligible for one more retire. +This affected the pre-existing **ATB** request path as well and is +closed for both (regression gates: the back-to-back-retire legs in +`rtl/preproc/test/ct_L23_preproc_sync_tb.sv`). Note the scope: that fix +sits in the shared sync arm, *outside* `CT_EN_INST_SYNC_REQ`, so it is +in the build with the new feature compiled out too. "Compiled out = the +pre-P8 build" is true for the request path and for the flop count; it is +not true for the ATB path, which is one message better off. + +* **64-bit addresses are a build knob** (2026-08-08, `ct_pkg::CT_XLEN`, + default 32): the architectural address width of the attached hart now + has ONE definition instead of a 32 repeated across five packages. It + sizes the TIP instruction/data address, the Nexus `F-ADDR`/`U-ADDR` + fields and their reference registers, the address comparators, the + jump-target-cache index fold, the ACT-ST / DF-range search keys and + the eTIP payload. Two things it does *not* do: change a single byte at + `CT_XLEN` = 32 (every downstream expression reduces to the historical + constant — verified against the pinned reference family), and turn + into a runtime mode. The width is a synthesis parameter and is + announced on the wire as CAPS bit 23 (`ADDR64`, `CFGVER` unchanged at + 1), because a decoder cannot infer it from a stream whose address + fields are variable-length with leading zeros stripped. Two behaviour + changes come with it. The jump-target-cache index folds the whole + address at 64 bit instead of stopping at bit 25 — otherwise every Sv39 + kernel target would hash as if its upper half were zero; the reference + decoder mirrors the same fold, switched by the CAPS bit. And the + `TR_COMP_SFUNC_PMASK` comparator mode takes its mask from the new + register pair `trTeCompSMask{Low,High}` (`0x008`/`0x00C`) instead of + from `SMatchHigh`, which is now what the RDL always said it was: bits + 63:32 of the secondary bound. Software that used the old mask location + has to move one register; the reset configuration is unaffected + (`SFunction` resets to `EQUAL`). Constraints of this step: comparator + bounds and ACT-ST / DF-range keys are CSR-programmable in the low + 4 GiB only (the CSR side stays a 32-bit word pair — the *compared* + address is full width), and an E-Trace instance with `CT_XLEN` = 64 is + rejected at elaboration, since the `te_inst` address fields are sized + by `CT_ETRACE_ADDR_BITS` = 31 and would truncate silently. Also in this + step: the `ECAUSE_NONE` simulation sentinel moved off cause 15, which + is the real Store/AMO page fault — under Sv39 Linux the most frequent + trap there is — onto the architecturally reserved cause **14**. (An + interim revision of this change used cause 10; that was wrong. With the + ratified H extension, 10 is "Environment call from VS-mode", so the + sentinel would have collided again the moment a hart ran with H enabled. + 14 is the only code the 4-bit cause space reserves unconditionally.) + +* **Trace one process, not one address range** (2026-08-08, + `ct_pkg::CT_CONTEXT_WIDTH` default 2, `ct_pkg::CT_EN_FILTER_SYNC`): + the context bus `tip._context` is a build knob now, so an integrator + can feed it the hart's real process identifier — a RISC-V `satp.ASID` + is 16 bits under Sv39/Sv48 and did not fit in the previous fixed 2. + Unlike the address width this needs no CAPS bit: the Ownership message + carries the value in the 44-bit `PROCESS` field, which goes out as a + variable-length field with leading zeros stripped, so the whole value + is on the wire and self-delimiting. At the default 2 the emitted bytes + are unchanged. ++ + With that in place, `trTeComp[].PInput` = 1 (context) turns the + existing filter bank into a *per-process* trace filter — and that + exposed a hole worth naming, because it is a hole in a feature that + looked finished. A filtered stream was **not decodable**: the sync + generator anchors on any retire, but the message slot that carries the + verdict only exists for a retire the filter accepted, so anchors + landing on filtered-out instructions were dropped — including the + trace-enable anchor. And `region_entered`/`region_exited`, computed by + `ct_L23_preproc_cf` since the beginning and routed all the way into the + eTIP composer, had no reader there, so coming back into the region + produced no re-anchor at all. Measured before the fix, with a context + filter selected: not one `ProgTraceSync` in the stream and 0 of 218 + instructions decoded. ++ + `CT_EN_FILTER_SYNC` closes both with the vocabulary a software trace + pause already uses — Program Trace Correlation (TCODE 33, + `EVCODE = Program Trace Disabled`, with the residual `ICNT`/history and + a call-stack clear) on region exit, `SYNC = 5` on region entry, and a + dropped verdict held for the next qualified retire. **No new message + type, no CAPS bit, no decoder change.** The correlation is a second + source of the *same* message slot as the trace-off path, so the proven + `ETIP_PAR_MSG` bound is untouched. Byte neutrality is structural: the + whole block is gated on `trTeInstFilters` being non-zero, and that + register resets to 0 ("trace all"). There is deliberately no runtime + opt-out — what it replaces is an undecodable stream, not an + alternative mode. Note what a filter still does *not* suppress: trap + delivery is traced whatever the filter selects (exception/interrupt + beats bypass the control-flow qualifier by design), and the + correlation says *that* there was a gap, not how long it was. + +=== Changed reset value: `trTeControl.InstSyncMax` 0 → 6 (2026-08-12) + +The periodic-sync *period* now resets to 2^(6+4)^ = **1024 units** +instead of 2^(0+4)^ = 16. `InstSyncMode` is unchanged (0 = no periodic +cadence at all), so a build that never enables the cadence is +bit-for-bit unaffected. What changes is the *natural* programming path: +enabling the cadence is one write of `InstSyncMode` and takes the +period from reset, and that period used to be the tightest the hardware +has, in whichever unit. + +Measured over 100 010 retires with only the period varied (gate +`tests/instruction/37_sync_cadence`): the old reset cost 97 844 trace +bytes, the new one 41 072, against 40 060 with the cadence effectively +off — a factor 2.44 versus 2.5 % overhead. Against a finite sink +(40 MB/s, same workload) the old reset announced 790 overflows and lost +5 064 events; the new one is byte-identical to the same run against an +infinite sink. + +Integrators who *program* `InstSyncMax` see no change. Anyone relying +on the reset now gets a period of 1024 — in mode 4 (trace bytes) that +is a 1 KiB re-anchor bound, the number a ring consumer wants. The +minimum period stays available as an explicit stress configuration; +it is simply no longer what you get by not asking. + +== Known limitations (by design — read before filing a bug) + +[cols="1,3", options="header"] +|=== +| Topic | Contract + +| One hart per encoder instance +| An encoder traces exactly one hart, so an N-hart system needs N + instances. Both sides of that are in place: the packet-aware merge + (`rtl/ct_L1_funnel.sv`, never switching mid-packet, sources told apart by + the SRC field) and the per-source split (CTTD `-target`), verified by + `tests/instruction/39_dual_src` and board-proven on the KV260 + (`examples/kv260/duo`). What is *not* covered is following one process as + the scheduler migrates it between harts: per-hart streams decode + independently, and cross-hart process tracking is host-side work on top. + +| `Empty` with a stopped core +| With `InstTracing=1` and the core halted, exactly one control-flow + event is permanently in flight (its successor address can never be + observed) — `Empty=0` is the correct report. Close the stream + (`InstTracing=0`) while the core still retires, then stop; see + link:integration.adoc[integration]. + +| Byte-level run-to-run determinism under overflow +| FIFO-overrun drop positions depend on real CDC/ATB phase relations; + two identical runs produce equivalent but not byte-identical streams. + The verified property is decode equivalence. Byte identity holds in + drop-free regimes with timestamps off. + +| Trace-off correlation under overflow +| The correlation is an ordinary message: if the pause edge falls into + a drop episode it is lost *announced* (ERROR + recovery sync); the + resume re-anchor still recovers the decoder. + +| Post-pause position ambiguity +| After a pause, the first decoded segment may be positionally + ambiguous against a full execution reference when the code is + homogeneous (the pause length is unknowable from the stream). Content + remains fully checkable; tooling should pair by anchor and verify + transitions, not force positional alignment. + +| Trace-quota window semantics +| The quota counter rearms when the sync is *emitted*: the sync + message's own bytes count into the new window, and no second request + is raised while one is pending (no sync avalanche at small quotas). + After a FIFO-overrun recovery the counter is *not* re-based — the + first post-recovery quota sync can arrive earlier than one full + quota (a harmless extra re-anchor, never a late one). With + `CT_EN_QUOTA_SYNC = 0`, modes 1/4 stay writable but inert (no WARL + clamp — exactly the pre-feature behaviour). + +| Non-standard core trace buses +| Core-side adapters (e.g. MicroBlaze V `TRACE`) are pinned to the + characterized core/tool version; the bus is documented as not + backward-compatible. + +| ACT-CAP counter selector out of range +| A DAQ counter read (`DAQ_DATA_RD`, `DAQ_DATA_WR`, `DAQ_IFETCH_TH`, + `DAQ_DATA_RD_TH`) whose selector in `trActCapStCmd.DirectData` exceeds + the number of configured ranges is *not* rejected: on the AXIS sink the + beat is still emitted, with `tid` = the command but `tdata`/`tstrb` + unchanged from the previous beat, and no error is signalled. Keep the + selector inside `0..NUM_PERFCNT__RANGES`; a host that does is + unaffected. + +| XSIM waveform debug of encoder internals +| Vivado XSIM 2026.x crashes with wave instrumentation on this code + base (`-debug off` required); use Verilator (with coverage) or the + `$display`/counter instrumentation instead. +|=== + +== Resource and timing snapshot (2026-08-06, xck26-sfvc784-2LV-c) + +[#p10-timing] +Out-of-context synthesis of `ct_encoder`, **Vivado 2022.1.2** (the +version `.abc.config` pins), commit `7a0b7b2`, two clock budgets per +profile. Reproduce with `bash scripts/p10_timing_matrix.sh`. Full table +with the caveats: +link:integration.adoc#profile-timing[integration, *Timing per profile*]. +The reports are in the tree — LUTs and flip-flops from +link:../verification/evidence/P10/nonly/timing_75mhz_util_flat.rpt[`nonly`], +link:../verification/evidence/P10/eonly/timing_75mhz_util_flat.rpt[`eonly`], +link:../verification/evidence/P10/featparity_gold/timing_75mhz_util_flat.rpt[`featparity_gold`] +and +link:../verification/evidence/P10/slimfull_gold/timing_75mhz_util_flat.rpt[`slimfull_gold`], +WNS from the `timing__summary.rpt` beside each of them, verdict +in `verification/evidence/P10/timing.log`. + +[cols="2,^1,^1,^1,^1", options="header"] +|=== +| Profile | CLB LUTs | Register as FF | WNS @ 13.333 ns (75 MHz) | WNS @ 5.0 ns (200 MHz) + +| full profile / N-Trace | 25 784 | 20 168 | *+4.175 ns* | −4.158 ns +| full profile / E-Trace | 26 372 | 16 953 | *+1.753 ns* | −6.580 ns +| `featparity_gold` | 4 938 | 4 824 | *+8.672 ns* | +0.339 ns +| `slimfull_gold` | 4 290 | 3 984 | *+8.695 ns* | +0.362 ns +|=== + +* **At the 75 MHz board budget all profiles meet timing**, smallest + margin +1.753 ns (E-Trace). At 200 MHz only the two slim profiles do; + 200 MHz is not a requirement in this project, the column is headroom. +* This is a post-synthesis figure with `set_clock_groups -asynchronous` + between the five clock domains, not a placed-and-routed one. +* The slim profiles are no longer the ~2.5 k-LUT builds of seq 22: the + gold profiles keep `CT_EN_BTM`, `CT_EN_SYNC_STATUS`, + `CT_EN_FIFO_HIST`, `CT_EN_QUOTA_SYNC`, `CT_EN_DEVICE_ID`, + `CT_EN_TRIG_REGS` and `CT_EN_INST_SYNC_REQ` on, so everything P2, P4, + P7 and P8 added is inside the 4 938 LUTs. + +=== Historical snapshot (2026-08-01) — pre-P2..P9, kept as measured + +* Full profile with BOTH back ends instantiated, OOC synthesis: + **26 123 LUTs / 20 022 FFs / 9.5 BRAM** + (`scripts/synth_encoder_ooc.tcl`). +* Same profile placed in the `mbv_kv260` reference design: + **23 428 LUTs / 19 065 FFs**, WNS +2.679 ns at 75 MHz single-clock + (corrected 2026-08-14; the previously quoted +2.186 ns was Vivado's + router estimate, not the routed timing summary). +* Historical N-Trace-only full profile (before the E-Trace backend, + 2026-07-20): 24 354 LUTs — not directly comparable to the two-back-end + numbers above. Slim CF-only profiles measure in the ~2.1–2.5 k-LUT + class; re-run the OOC script per profile when quoting. +* NOTE: the two-back-end configuration was retired on 2026-08-04 (P9, + protocol = synthesis parameter). The figures above stay as measured, + but no current build looks like that; a single-protocol encoder drops + the second back end. diff --git a/doc/rm-ctte.html b/doc/rm-ctte.html new file mode 100644 index 0000000..27a05a7 --- /dev/null +++ b/doc/rm-ctte.html @@ -0,0 +1,32789 @@ + + + + + + + + +Reference Manual: CEDARtools.TraceEncoder (CTTE) + + + + + + + +
+
+
+
+

Public ~ Build 9f968d5e

+
+
+
+
+
+

Revision History

+
+
+

The following table shows the revision history for this document.

+
+ +++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
VersionDateChanges

1.0 — 1.3

2025-06-20 — 2026-08-03

See rm-ctrace.adoc (superseded by this document)

2.0

2026-08-18

Complete rewrite as the CEDARtools.TraceEncoder reference manual. Restores the interface and register chapters removed in 1.2 (now generated from the SystemRDL and RTL sources instead of hand-written); adds a full message catalog, the core-adapter chapters (MicroBlaze™ V, Rocket, CVA6 ITI), the demonstrator chapter, a single resource/timing table with tool version and artefact paths, the configuration-pitfall section, and the standards-baseline and conformance chapters.

2.1

2026-08-24

Adds the demonstrator register maps as an appendix, generated from the example designs' own SystemRDL under the same drift gate as the encoder tables. The encoder tables gain the one register the SystemRDL declares and hides (trActCapStCmd, not addressable on the control bus) and the descriptions of the range-filter key words. States that a build profile changes the answer a configuration field gives, never its address.

2.2

2026-08-25

Brought up to CEDARtools.TraceEncoder release 1.0.0, which the title page now names. Corrects every source path the encoder repository moved (the shared TGC5B base, the dissolved ci/ tree, the renamed core adapters, the featparity build profile) and drops the retired repository prefix from repo-relative paths. Recounts the test suite (62 system-level testbenches) and the SystemRDL sources (ten), and prints the address map of the delivered two-core KV260 device as a further generated appendix. States the ingress each shipped core can carry, and therefore on which cores the instrumentation commands produce a payload at all. Records the second cause of the instruction-count cap defect, the board conditions of the 2026-08-21 runs, and the reproduction limits of the coverage figures. Removes two figures that showed a different subject than their captions claimed, and the blanket "documentation is being updated" banner: where a chapter is incomplete, the gap is named in Chapter 33 instead.

2.3

2026-08-27

Structures the format documentation by protocol: the trace-format chapter opens with the N-Trace/E-Trace split, groups the message machinery under an explicit N-Trace section and gains an E-Trace wire-format section; the message catalog and the self-identification chapter carry the N-Trace name in their titles. Replaces the two remaining predecessor-era architecture figures with CTTE-own drawings verified against the RTL — the timestamp unit is drawn at last, the overflow injection is named and placed where it lives (inside the eTIP composer), dead blocks are gone — and replaces a third figure whose content did not match its caption. Prints the runtime-verification testbed’s register maps as a further generated appendix, now that the example carries its own SystemRDL source, and records that testbed’s first board verdicts (2026-08-26), which also end the "never exercised on silicon" statement for the doorbell ACT-CAP path. Corrects the Trace-FS reference (the demonstrator as published integrates an earlier C-Trace release, not CTTE 1.0.0), the wall-clock role (periodic-sync cadence, not the timestamp source), and every claim that cited a gitignored or untracked file as if it were part of the published tree; the publication guard now checks citations and counts against git’s tracked-file set instead of the working tree, which is how those claims had survived it.

+
+
+
+

1. Introduction, Scope and Naming

+
+
+

1.1. What this manual describes

+
+

CEDARtools.TraceEncoder (CTTE) is a RISC-V trace encoder in SystemVerilog. It takes a core’s instruction-trace port, compresses the execution stream into Nexus-style trace messages, and emits them on a 32-bit ATB output; an additional, uncompressed AXI-Stream path carries the same events to on-chip consumers. Beyond branch trace it provides hardware-assisted instrumentation, data trace, performance counters and a self-identification message that lets a decoder configure itself from the stream.

+
+
+

This manual is the reference for that IP: what it does, how it is parameterised, what contract it presents to the surrounding SoC, and what has been verified. It is written for three readers, and each will use a different part of it:

+
+ ++++ + + + + + + + + + + + + + + + + + + + + +
ReaderWhere to start

Integrator — dropping the encoder into an SoC

Chapter 17 (the signal and clocking contract), then Chapter 25 and Chapter 26. The register model is Chapter 16.

Software and tools author — programming the encoder, decoding its output

Chapter 13 and Chapter 14 for the wire format, Chapter 16 for the control surface, Chapter 19 for instrumentation, and Chapter 27 for the decode path.

Assessor — judging maturity and evidence

Chapter 29, Chapter 30, Chapter 31 and Chapter 32, then Chapter 33.

+
+
+

1.2. How this manual is organised

+ ++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
PartContents

A — Orientation

This chapter, the position of the encoder in the surrounding trace system, the standards it implements, and where it goes beyond them.

B — Architecture

The encoder’s stages from trace ingress to formatted output: sources and core adapters, preprocessor, message generation, the compression suite, the output stage, the funnel and the parallel pin output.

C — Formats and interfaces

The wire format, the complete message catalog, the Data Acquisition payload, the register model, the interface contract, and self-identification.

D — Features

Hardware-supported instrumentation (ACT-CAP, ACT-ST, ACT-Proc), the command CSR, HSI transfer, the raw event path, performance analysis, and the footprint profiles with their measured resource and timing figures.

E — Integration and operation

The integration guide, configuration recipes and their pitfalls, the decode paths, and the demonstrator designs.

F — Verification and status

The verification strategy, the test catalog, coverage evidence, the implementation-status matrix, and known limitations.

G — Appendices

Development support, references, and the licence and trademark terms.

+
+
+

1.3. Relationship to the public documentation

+
+

The encoder is open source. Part of its documentation is published with the source and is deliberately more detailed than this manual — in particular the integration guide, the verification description and the trace-format description in the repository’s doc/ tree.

+
+
+

The division is by purpose, not by secrecy:

+
+
+
    +
  • +

    This manual states the contract and the decisions: what the encoder guarantees, what a user must configure, what has been verified, and what the current limitations are. It is meant to be read end to end once, and consulted thereafter.

    +
    • +
  • +

    The public documentation carries the derivations, the long-form argumentation and the per-case detail behind those statements.

    +
    • +
+
+
+

Where both cover the same subject, this manual states it once and points outward rather than repeating it. Two chapters go the other way: the register model (Chapter 16) and the message catalog (Chapter 14) are generated from the SystemRDL and RTL sources during the build, so that they cannot drift from the implementation they describe.

+
+
+
+

1.4. Naming

+
+

The product is CEDARtools.TraceEncoder, abbreviated CTTE. The name places the encoder in the CEDARtools family from Accemic Technologies — tools for the live processing of trace data — because it grew out of the experience of building that family.

+
+
+

The earlier name C-Trace remains admissible as informal shorthand. It survives in the source identifier prefix ct_*, and — outside the source — in names that are nailed down beyond the repository: the nine KV260 application names _ctrace_kv260, the device-tree overlay ctrace_resmem.dtso, the reserved-memory node ctrace-pl-ddr and the block design mbv_ctrace_soc. It is no longer a general prefix in the RTL: the core adapters were renamed to *_to_ctte_tip on 2026-08-21, and the encoder’s prose no longer uses the old name at all. Its C stands for *CEDARtools, the same house mark the current name carries in full.

+
+
+ + + + + +
+
Note
+		 +The ACT- prefix of the instrumentation protocols ACT-CAP, ACT-ST and ACT-Proc reads *A*ccemic *C*EDAR*T*ools. It derives from the house mark, not from the encoder’s own name, and is therefore unaffected by the rename. +
+
+
+

Several component and repository names changed during 2026. Where a reader may still encounter the earlier name, both are given:

+
+ +++++ + + + + + + + + + + + + + + + + + + + + + + + + +
Earlier nameCurrent nameNote

C-Trace

CEDARtools.TraceEncoder (CTTE)

The product described by this manual.

NexRv for C-Trace

CTTD — CEDARtools.TraceDecoder

The reference decoder; see Chapter 27. Descended from the NexRv reference code of the RISC-V Nexus trace project.

C-Trace eXPort format

CTXP

The architecture-agnostic trace export format; see Chapter 27.

+
+
+

1.5. Conventions

+
+

Authority. Where this manual and the implementation disagree, the implementation is right and the manual has a defect. The order of authority is: the RTL and the SystemRDL register model first, then the measurement and test artefacts, then the published documentation, then this manual. Chapters state which of these a statement rests on.

+
+
+

Numbers. Every measured figure in this manual names its source — a file in the source tree, a commit, a test, or a report path — so that a reader can reproduce it. Where a figure could not be traced to such a source, it has been left out rather than estimated; the affected chapter says so.

+
+
+

Register and signal names are written as they appear in the sources (trTeControl.SendConfig, iretire), and are generated into the register chapter rather than transcribed.

+
+
+

Version. This revision describes CEDARtools.TraceEncoder release 1.0.0 (2026-08-28), as the title page states. The release notes of that version list what changed and what is known not to work; a reader who needs to know whether a given statement applies to a different netlist has a finer instrument in the register chapter, where every generated table carries the SHA-256 of the SystemRDL source it was produced from (Chapter 16). Document revision and product release are separate numbers and are not kept in step: this manual is revised when its text is wrong, the encoder when its behaviour changes.

+
+
+

Paths. Every path written in backticks without a repository prefix — rtl/ct_encoder.sv, tests/instruction/, doc/integration.adoc — is relative to the root of the CTTE repository. The earlier prefix c-trace/ has been dropped throughout: the repository is named accemic/TraceEncoder, and a repo-relative path survives the next rename where a prefixed one does not.

+
+
+

Standards. Statements about what a standard does or does not define carry the clause of the standard they rest on. Where the position is genuinely unclear, this manual says so instead of resolving the doubt in its own favour; see Chapter 4.

+
+
+
+
+
+

2. CTTE in Context

+
+
+

2.1. What the encoder is for

+
+

CTTE is built for continuous observation of a running system, not for post-mortem capture of a short window. That premise shapes every design decision in this manual: the compression suite exists so that a full instruction trace fits through a narrow link for hours rather than milliseconds; the instrumentation path exists so that software can contribute observations without stopping; the self-identification message exists so that a decoder attaching to a long-running stream can configure itself from what it receives.

+
+
+

The use cases it was designed against:

+
+
+
    +
  • +

    measurement of test completeness (code coverage),

    +
    • +
  • +

    test-case prioritisation,

    +
    • +
  • +

    hybrid WCET (worst-case execution time) analysis,

    +
    • +
  • +

    performance optimisation,

    +
    • +
  • +

    online control-flow-integrity checking.

    +
    • +
+
+
+

The design goals that follow from them:

+
+
+
    +
  • +

    strict adherence to standard interfaces — the RISC-V Trace Ingress Port (TIP), AXI-Stream, ATB and Nexus messages (Chapter 17),

    +
    • +
  • +

    comprehensive support for hardware-assisted instrumentation (Chapter 19),

    +
    • +
  • +

    multi-core support,

    +
    • +
  • +

    controllable forwarding of TIP data elements to a core acting as watchdog, CFI checker or runtime-verification unit (Section 17.7),

    +
    • +
  • +

    no architectural side effects on the observed system: the encoder observes the trace port, it does not participate in execution.

    +
    • +
+
+
+

The encoder is organised into clearly separated stages — ingress from the trace port, filtering and synchronisation control, message generation, and formatting — described in Chapter 5.

+
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+ Software Tool (@PC) +
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+
Figure 1. CTTE Overview
+
+
+
+

2.2. Accemic’s trace layers

+
+

The CEDARtools trace system follows a layered architecture (L0–L7) with defined interfaces (IF0–IF6), covering physical transport, trace collection and encoding, context handling, application reconstruction and metrics, compilation and instrumentation mapping, and objective evaluation across the toolchain and the system under test.

+
+
+

The encoder described by this manual implements layers L1–L3 — Transport, Trace and Context. The remaining layers belong to the surrounding CEDARtools ecosystem and to host-side tooling, and are outside the scope of this document.

+
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+ Application Layer B +
+ (L4B) +
+ + application observation + +
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+
+
+ + System Under Test (SUT) +
+ here: RISC-V hart +
+ +
+
+
+ + + System Under Test (SUT)... + + + + + + + + + + + +
+
+
+ + IF0: ATB (funneled multi-source trace) +
+ +
+
+
+ + + IF0: ATB (funneled multi-source trace) + + + + + + + + + + + +
+
+
+

+ + Link Layer (L0) +
+ + + + physical connection +
+ of SUT and CEDARtools + +
+ +

+
+
+
+ + + Link Layer (L0)... + + + + + + + + + + + +
+
+
+

+ + Transport Layer (L1) +
+ + + + observation source +
+ + + multiplexing + + +
+

+
+
+
+ + + Transport Layer (L1)... + + + + + + + + + + + +
+
+
+ Trace Layer (L2) +
+ + source-specific +
+ trace encoding + +
+
+
+ + + Trace Layer (L2)... + + + + + + + + + + + +
+
+
+ Context Layer (L3) +
+ + application context filtering +
+ and selection + +
+
+
+ + + Context Layer (L3)... + + + + + + + + + + + +
+
+
+ Application Layer A +
+ (L4A) +
+ + application observation + +
+
+
+ + + Application Layer A... + + + + + + + + + + + +
+
+
+ Objective Layer (L7) +
+ + observation objectives + +
+
+
+ + + Objective Layer (L7)... + + + + + + + + + + + +
+
+
+ + Control Address +
+ Assignment +
+ +
+
+
+ + + Control Addres... + + + + + + + + + + + +
+
+
+ + Set Context ID +
+ +
+
+
+ + + Set Context ID + + + + + + + + + + + +
+
+
+ + Config Trace +
+ +
+
+
+ + + Config Trace + + + + + + + + + + + +
+
+
+ + Config Funnel +
+ +
+
+
+ + + Config Funnel + + + + + + + + + + + +
+
+
+ + Set Funnel mode +
+ +
+
+
+ + + Set Funnel mod... + + + + + + + + + + + +
+
+
+ + Config trace output +
+ +
+
+
+ + + Config trace o... + + + + + + + + + + + +
+
+
+ + Trace Splitter +
+ +
+
+
+ + + Trace Splitter + + + + + + + + + + + +
+
+
+ + IF1: ATB (multi-source trace) +
+ +
+
+
+ + + IF1: ATB (multi-source trace) + + + + + + + + + + + +
+
+
+ + IF2 (binary observation) +
+ +
+
+
+ + + IF2 (binary observation) + + + + + + + + + + + +
+
+
+ + Config Trace +
+ +
+
+
+ + + Config Trace + + + + + + + + + + + +
+
+
+ + Multi-Binary Execution +
+ +
+
+
+ + + Multi-Binary Execution + + + + + + + + + + + +
+
+
+ + Get Context ID +
+ +
+
+
+ + + Get Context ID + + + + + + + + + + + +
+
+
+ +
+ Cross-Core +
+
+ Application Context Identification +
+ +
+
+
+ + + Cross-Core... + + + + + + + + + + + +
+
+
+ + IF3 (single-binary observation, e.g. PFT trace filtered for single application) +
+ +
+
+
+ + + IF3 (single-binary observation, e.g. PFT trace filtered for single application) + + + + + + + + + + + +
+
+
+ +
+ Binary Execution +
+ +
+
+
+ + + Binary Execution + + + + + + + + + + + +
+
+
+ + Instructions and +
+ Addresses +
+ +
+
+
+ + + Instructions a... + + + + + + + + + + + +
+
+
+ +
+ Binary Reconstruction +
+ +
+
+
+ + + Binary Reconst... + + + + + + + + + + + +
+
+
+ + IF4 (binary-representive, e.g. ELF / CCGraph) +
+ +
+
+
+ + + IF4 (binary-representive, e.g. ELF / CCGraph) + + + + + + + + + + + +
+
+
+ + Tests +
+ +
+
+
+ + + Tests + + + + + + + + + + + +
+
+
+ + Requirements +
+ +
+
+
+ + + Requirements + + + + + + + + + + + +
+
+
+ +
+ Test Execution +
+
+ Test specification +
+
+ Plausibilty checks +
+
+ +
+
+
+ + + Test Execution... + + + + + + + + + + + +
+
+
+ + Verification +
+ +
+
+
+ + + Verification + + + + + + + + + + + +
+
+
+ + Statistics +
+ +
+
+
+ + + Statistics + + + + + + + + + + + +
+
+
+ + CF Trace +
+ +
+
+
+ + + CF Trace + + + + + + + + + + + +
+
+
+ + DF Trace +
+ +
+
+
+ + + DF Trace + + + + + + + + + + + +
+
+
+ + User Trace +
+ +
+
+
+ + + User Trace + + + + + + + + + + + +
+
+
+ + HSI +
+ +
+
+
+ + + HSI + + + + + + + + + + + +
+
+
+ +
+ Tool +
+ Status +
+ +
+
+
+ + + Tool... + + + + + + + + + + + +
+
+
+ + Application +
+ Layer A +
+ State +
+ +
+
+
+ + + Application... + + + + + + + + + + + +
+
+
+ + Context Layer State +
+ +
+
+
+ + + Context Layer... + + + + + + + + + + + +
+
+
+ + Trace Layer +
+ State +
+ +
+
+
+ + + Trace Layer... + + + + + + + + + + + +
+
+
+ + Transport Layer State +
+ +
+
+
+ + + Transport Laye... + + + + + + + + + + + +
+
+
+ + Link Layer State +
+ +
+
+
+ + + Link Layer Sta... + + + + + + + + + + + +
+
+
+ + Objective +
+ Layer +
+ State +
+ +
+
+
+ + + Objective... + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+
+
+ Compilation Layer (L5) +
+ + source code compilation + +
+
+
+ + + Compilation Layer (L5)... + + + + + + + + + + + +
+
+
+ +
+ Compilation +
+ +
+
+
+ + + Compilation + + + + + + + + + + + +
+
+
+ +
+ Transformation +
+
+ Object Code -> Source Code +
+ +
+
+
+ + + Transformation... + + + + + + + + + + + +
+
+
+ + IF5 (Instrumented source code) +
+ +
+
+
+ + + IF5 (Instrumented source code) + + + + + + + + + + + + + + + + + + + + + + + +
+
+
+ Instrumentation +
+ Layer (L6) +
+ + application observation + +
+
+
+ + + Instrumentation... + + + + + + + + + + + +
+
+
+ +
+ Instrumentation +
+ +
+
+
+ + + Instrumentation + + + + + + + + + + + +
+
+
+ +
+ Back-Transformation +
+ +
+
+
+ + + Back-Transformation + + + + + + + + + + + +
+
+
+ + IF6 (source code) +
+ +
+
+
+ + + IF6 (source code) + + + + + + + + + + + + + + + + + + + + + + + +
+
+
+ + HSI +
+ +
+
+
+ + + HSI + + + + + + + + + + + +
+
+
+ + Control Compiler +
+ Flags +
+ +
+
+
+ + + Control Compil... + + + + + + + + + + + +
+
+
+ + Debug +
+ Information +
+ +
+
+
+ + + Debug... + + + + + + + + + + + +
+
+
+ + Compilation +
+ Layer +
+ State +
+ +
+
+
+ + + Compilation... + + + + + + + + + + + +
+
+
+ + Trace Transmission +
+ +
+
+
+ + + Trace Transmission + + + + + + + + + + + +
+
+
+ + Trace Reception +
+ +
+
+
+ + + Trace Reception + + + + + + + + + + + +
+
+
+ + PHYSICAL LAYER +
+ +
+
+
+ + + PHYSICAL LAYER + + + + + + + + + + + +
+
+
+ + Calibration +
+ +
+
+
+ + + Calibration + + + + + + + + + + + + + + + + + +
+
+
+ + + Meta-Informationen + +
+ + ( + + Tool spec. mapping) + + +
+ +
+
+
+ + + Meta-Informati... + + + + + + + + + + + +
+
+
+ + Observation +
+ Goals +
+ +
+
+
+ + + Observation... + + + + + + + + + + + +
+
+
+ + Instrumentation +
+ Layer +
+ State +
+ +
+
+
+ + + Instrumentatio... + + + + + + + + + + + +
+
+
+ +
+ + Time-stamps + +
+
+ +
+
+
+ + + Time-stamps + + + + + + + + + + + +
+
+
+ + Binary Statistics +
+ (CC Counter, WCET, WCRT) +
+ +
+
+
+ + + Binary Statist... + + + + + + + + + + + +
+
+
+ + Application +
+ Layer B +
+ State +
+ +
+
+
+ + + Application... + + + + + + + + + + + + + + + + + + +
+
+
+ +
+ HSI +
+ +
+
+
+ + + HSI + + + + + + + + + + + + + +
+
+
+ + Trace Funnel +
+ +
+
+
+ + + Trace Funnel + + + + + + + + + + + + + +
+
+
+ + Sink: +
+ TSN +
+ +
+
+
+ + + Sink:... + + + + + + + + + + + + +
+
+
+ + Sink: +
+ Aurora +
+ +
+
+
+ + + Sink:... + + + + + + + + + + + +
+
+
+ + TIP preprocessing +
+ with trace filter +
+ +
+
+
+ + + TIP preprocessing... + + + + + + + + + + + +
+
+
+ + TIP generation +
+ +
+
+
+ + + TIP generation + + + + + + + + + + + +
+
+
+ + CF / DF / HSI Trace message generation +
+ Nexus Msg / E-Trace formatter +
+ MSEO/MDO Formatter +
+ +
+
+
+ + + CF / DF / HSI Trace message ge... + + + + + + + + + + + + +
+
+
+ + Trace IP control +
+ +
+
+
+ + + Trace IP control + + + + + + + + + + + + +
+
+
+ + Sink: +
+ PIB +
+ +
+
+
+ + + Sink:... + + + + + + + + + + Text is not SVG - cannot display + + + + +
+
Figure 2. CTTE layer model
+
+ + +++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 1. Layer definitions
LayerNameDescription

L0

Link Layer

Physical I/O for trace, including sinks such as Aurora, transmission, calibration and reception; exposes a Link Layer State for health and readiness.

L1

Transport Layer

Multiplexes sources through a trace funnel and splitter, controls funnel mode, and reports a Transport Layer State for source-aggregation status.

L2

Trace Layer

Generates CF/DF/HSI trace messages and formats them (Nexus, MSEO/MDO), with a Trace Layer State covering source-specific encoding.

L3

Context Layer

Filters and preprocesses TIP/trace, assigns or retrieves context IDs, and performs cross-core application-context identification.

L4

Application Layer

Reconstructs execution from instructions and addresses, adds timestamps, and derives binary statistics such as counters and WCET/WCRT.

L5

Compilation Layer

Correlates binaries and source through debug information and code/object transformations, tracking source–object mapping fidelity.

L6

Instrumentation Layer

Applies HSI instrumentation, attaches meta-information (tool-spec mapping) and supports back-transformation.

L7

Objective Layer

Drives test execution and plausibility checks and consolidates verification and statistics against observation objectives.

+ + ++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 2. Interface definitions
InterfaceDescription

IF0

Funnelled multi-source ATB trace on the physical link between transport concentration and the receiver path.

IF1

Multi-source ATB trace prior to funnelling/splitting, for source-aggregation control.

IF2

Binary observation stream after trace decoding into CF/DF/HSI events, for downstream context selection.

IF3

Single-binary observation (for example filtered to one application), enabling per-application reconstruction and timing.

IF4

Binary representation boundary (ELF, call-context graph) connecting reconstruction and statistics with compilation artefacts.

IF5

Instrumented source code handed to compilation and mapping tools.

IF6

Source-code boundary for requirements, tests and instrumentation planning.

+
+
+

2.3. What the integrator must supply

+
+

Two functions that a trace system normally needs are deliberately not part of the CTTE deliverable. Both are named here so that an integrator plans for them rather than discovering the gap during bring-up.

+
+
+

2.3.1. Cross-trigger fabric

+
+

Cross-triggering lets components broadcast events to each other. CTTE does not implement a cross-trigger fabric; an integrator who wants it pairs the encoder with an external implementation such as ARM CoreSight.

+
+
+

References:

+
+
+
    +
  • +

    Arm CoreSight SoC-400 Technical Reference Manual (DDI0480G): Cross Trigger (p. 332)

    +
    • +
  • +

    Arm CoreSight SoC-400 Technical Reference Manual (DDI0480G): Cross Trigger Registers (p. 192)

    +
    • +
+
+
+
+

2.3.2. Debug unit

+
+

CTTE relies on an external debug IP for system-bus access and for configuring its control and status registers. That debug IP is outside the CTTE deliverable and must be supplied by the integrator. The register interface CTTE presents to it is specified in Section 17.8.

+
+
+

Reference: RISC-V Debug Specification

+
+
+
+
+
+
+

3. Standards Baseline

+
+
+

The CEDARtools.TraceEncoder is built against four public specifications. This chapter is the map: which document, in which revision, defines what; which parts of each CTTE implements; which parts it deliberately does not; and where the documents overlap or contradict each other. After reading it, an assessor knows which document to hold the encoder against for any given observation — a byte on the trace port, a register access, an ingress signal.

+
+
+

Two conventions from Chapter 1 apply with full force here. Every statement about what a standard does or does not define carries the clause it rests on, and each such statement was checked against the primary document, not against a summary of it. Where the position is genuinely unclear, this chapter says so and takes the more cautious reading. What CTTE does beyond these documents is deliberately not this chapter’s subject — that is Chapter 4.

+
+
+

3.1. The four documents

+ +++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
SpecificationRevisionRole for CTTE

IEEE-ISTO 5001™-2012, The Nexus 5001 Forum™ Standard for a Global Embedded Processor Debug Interface

v3.0.1 (2012)

The base standard. Assigns every transfer code (Table 4-5, p. 35), defines the message formats (sections 4.3.1 — 4.3.29), the field vocabulary and transmission order (Tables 4-2/4-3), and the vendor-defined code spaces CTTE’s extensions live in.

RISC-V N-Trace (Nexus-based Trace) Specification, RISC-V International

Version 1.0, ratified 2024-11-21

The primary wire protocol. A profile of the Nexus standard for RISC-V: message subset (Table 9), fixed MSEO/MDO framing (chapter 3), control semantics (chapter 4, Table 8), synchronization (section 8.4, Table 25) and the optional bandwidth optimizations (chapter 9). The stream of an N-Trace-built CTTE instance is measured against this document first.

Efficient Trace for RISC-V, RISC-V International

Version 2.0, ratified 2022-05-05

Two distinct roles. Its chapter 4 defines the trace ingress interface that CTTE’s TIP follows (Chapter 6) — this role is active in every build. Its chapter 7 defines the te_inst packet format that CTTE’s alternative E-Trace back end emits — this role is active only in an EN_ETRACE build.

RISC-V Trace Control Interface Specification (TCI), RISC-V International

Version 1.0, ratified 2024-11-21

The register model. Component conventions and address map (chapter 4), the Trace Encoder register set (chapter 6), the trace funnel component (chapter 8), the PIB sink and its pin protocol (chapter 9), and the ATB bridge (chapter 10).

+
+

The reference list with source locations and mirrors is in
+Chapter 36.

+
+
+
+

3.2. How the four documents relate

+
+

N-Trace is a profile of Nexus, not a fork. Its own words: it describes "an appropriate selection of N-Trace messages compatible with the original IEEE-5001 Nexus Standard" (N-Trace chapter 1), and its transmission protocol is "a strict subset of IEEE-5001 Nexus Standard trace" (N-Trace Table 5). Where Nexus leaves the port geometry to the vendor — one or two MSEO bits, at least two MDO bits, vendor-defined bit order — N-Trace fixes one choice: 6-bit MDO plus 2-bit MSEO packed into a byte, MSEO in the least significant bits, least significant bit of each field first (N-Trace Table 5, section 3.3). A TCODE can therefore be a fully defined Nexus Public Message and be "Reserved for future extensions" from an N-Trace decoder’s point of view (N-Trace Table 9); the complete per-TCODE resolution of that double bookkeeping is Chapter 14.

+
+
+

N-Trace declares exactly one incompatibility with Nexus. Its ECODE field is variable-length where Nexus defines a fixed-length error code, so that the optional TSTAMP field stays byte-aligned (N-Trace chapter 12). Everything else N-Trace adds is marked as a compatible, default-off extension in its text. CTTE follows the N-Trace form.

+
+
+

The ingress port comes from E-Trace. N-Trace does not define its own core interface; it references the "ratified Efficient Trace for RISC-V Specification …​ chapter 4 Instruction Trace Interface" (N-Trace section 1.1). CTTE’s TIP carries the full 4-bit instruction-type vocabulary of E-Trace Table 4.4, which is why the same eTIP stream can feed either back end (Chapter 6, Chapter 5).

+
+
+

The register model comes from TCI and is shared. "Both N-Trace and E-Trace encoders are controlled by the same set of bits/fields in the same trTe??? registers" (TCI section 4.3); N-Trace chapter 4 (Table 8) then states, field by field, which of those TCI controls apply to N-Trace, which are optional, and which "must be hard coded as 0". Because almost every TCI field is individually optional and WARL, an implementation reports an absent option by legalizing the write — which is exactly how CTTE’s register model behaves (Chapter 16).

+
+
+

Nexus compliance classes do not transfer. The Nexus standard defines compliance Classes 1 — 4, but from Class 2 upward they mandate the Nexus-defined interfaces, and from Class 3 the Auxiliary Access read/write service (IEEE-ISTO 5001-2012 section 4.1, Table 4-1). N-Trace says of these levels that they "are not directly applicable to N-Trace as Nexus levels always include debug levels" (N-Trace chapter 5, note). CTTE takes the same position: it implements Nexus message formats under the N-Trace profile, it does not implement the Nexus AUX port, the TAP path or the read/write-access service, and it claims no Nexus compliance class — and no certification of any kind; see Chapter 4.

+
+
+
+

3.3. What CTTE implements from each document

+
+

3.3.1. N-Trace 1.0 — the primary back end

+
+

CTTE implements the complete N-Trace 1.0 program-trace message set — every message of Table 9 — in both instruction trace modes: history (HTM, InstMode = 6) and branch (BTM, InstMode = 3). Table 8 of the specification requires "at least a value of 3 or 6" to be settable; CTTE makes both settable when CT_EN_BTM is built. The per-message generation conditions are in Chapter 14; the reset configuration emits N-Trace Table 9 messages exclusively, with the single exception of the self-identification message (Section 14.2.1).

+
+
+

Beyond the mandatory core, CTTE implements the specification’s optional parts as follows:

+
+ +++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
N-Trace 1.0 featureClauseCTTE

Repeated history (ResourceFull RCODE = 2 with repeat count)

Table 20, section 9.3

Implemented (InstEnRepeatedHistory, the control bit the specification itself names). Section 9.3 leaves the pattern detection method open ("the exact way to detect these patterns is not specified"); CTTE’s partial-window trim lives inside that latitude. See Chapter 9.

Implicit return

Section 9.2, TCI Table 11 bits [3] and [7:6]

Implemented as the specification’s strongest variant — a stack of full expected return addresses (the trTeInstImplicitReturnMode = 3 behaviour), 16 entries deep, within the specification’s 32-level bound. The TCI mode field itself is not implemented as a register; the structure is reported in the configuration message instead (Chapter 18).

Sequential jump inference

Section 9.1, TCI Table 11 bit [2]

Implemented as a build-time ingress convention (CT_SIJUMP) of the attached core rather than a runtime register bit; advertised on the wire as CAPS bit 6. See Chapter 4 for the register-side consequence.

Virtual-address MSB elision

Section 9.4 (trTeInstExtendAddrMSB)

Not implemented — the one chapter-9 optimization CTTE omits. The control field is a commented stub in the register source. At 32-bit addresses the measured benefit is zero, because leading-zero suppression is already byte-minimal there; the public trace-format documentation records this as planned for a 64-bit follow-on.

Timestamps

Section 8.5

Implemented exactly as specified: absolute value on every synchronizing message, delta to the previous timestamp otherwise, variable-length with leading zeros suppressed (Chapter 14).

Synchronization reasons

Table 25

All standard codes the ingress can observe, including the three Required codes 2, 3 and 7; one vendor code (14) from the range Table 25 designates for vendors. Codes 10 — 13, which Table 25 reserves for future standard use, are not emitted.

Address compression

Sections 8.1, 9.4

The base scheme: XOR against the previous transmitted address in the same address thread, least significant always-zero bit dropped, leading zeros suppressed (see Chapter 13).

+
+
+

3.3.2. IEEE-ISTO 5001-2012 — messages beyond the N-Trace profile

+
+

The N-Trace profile is deliberately narrower than the standard it profiles. CTTE optionally implements six Nexus Public Message groups that N-Trace 1.0 Table 9 does not adopt — each defined by the base standard, each off by default, each leaving the strict N-Trace 1.0 envelope when enabled (details and switches in Chapter 14):

+
+
+
    +
  • +

    Data trace — Data Write/Read (TCODE 5/6, section 4.3.17) and their with-sync forms (13/14, section 4.3.18). N-Trace 1.0 excludes data trace ("must be 0 as IEEE-5001 Nexus Standard data trace messages are not part of version 1.0", Table 8) while naming Nexus-compatible data trace a likely future enhancement (Table 27).

    +
    • +
  • +

    Data Acquisition (TCODE 7, section 4.3.21) — a Nexus Public Message, not a vendor extension; the payload contract is Chapter 15.

    +
    • +
  • +

    Device ID (TCODE 1, section 4.3.2, Table 4-7) and Watchpoint (TCODE 15, section 4.3.23).

    +
    • +
  • +

    Repeat Instruction (TCODE 31/32, sections 4.3.14/4.3.15) — defined by Nexus, Reserved from N-Trace 1.0’s point of view.

    +
    • +
  • +

    Vendor-defined messages (TCODE 56/57/58) — inside the range 56 — 62 that both Table 4-5 of the standard and Table 9 of N-Trace designate for exactly this purpose.

    +
    • +
+
+
+

The remaining Nexus message space CTTE does not implement, with the reason stated rather than implied:

+
+ +++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Nexus messageClauseWhy not

Debug Status (0)

Section 4.3.1

No core contract for the 16 status bits: all three ingress adapters tie the debug-related TIP inputs to 0, and the two facts CTTE could state (debug entry, stop) are already carried more precisely by Correlation EVCODE 0/1 and SYNC 3/9. See Chapter 17.

Program Trace Correction (10)

Section 4.3.12

The message retracts an instruction count already sent for a branch later cancelled. CTTE does not emit speculative trace, so there is nothing to correct. N-Trace 1.0 likewise leaves TCODE 10 Reserved (Table 9).

Port Replacement (20/21), Auxiliary Access (22 — 26)

Sections 4.3.24 — 4.3.29

CTTE is a trace source. It does not implement the Nexus auxiliary port or its read/write-access service; register access is by the TCI system-bus path instead (Section 17.8).

In-Circuit Trace (34/35)

Sections 4.3.19/4.3.20

Not implemented; no generation logic exists.

+
+

CTTE also does not implement the Nexus physical AUX port. The MSEO/MDO framing is used as N-Trace fixes it; the physical serialization onto pins is the TCI PIB (chapter 9 of the TCI specification), not the Nexus AUX (see Chapter 12).

+
+
+
+

3.3.3. Efficient Trace for RISC-V 2.0 — ingress always, back end optionally

+
+

The ingress role is unconditional: the TIP’s instruction-type vocabulary is E-Trace Table 4.4, its privilege and trap sidebands follow E-Trace chapter 4, and the adapters for cores with narrower native vocabularies normalize into it (Chapter 6).

+
+
+

The back-end role is per instance: exactly one of EN_NTRACE / EN_ETRACE is set per encoder (Chapter 5). An E-Trace instance implements the instruction trace packet format of chapter 7 — the Format 3 synchronization, trap and support packets (subformats 0, 1 and 3, including qual_status = trace_lost loss reporting), Format 2 and Format 1 address and branch-map reporting, and both optional Format 0 efficiency extensions (0.0 correctly-predicted-branch count, 0.1 jump-target cache index, section 7.8) — following the reference algorithm of chapter 9 (baseline, with the optional modes of section 3.2 that CTTE’s compression suite maps onto; see Chapter 9).

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Not implemented on the E-Trace side:

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    Data trace — neither the data-trace interface (E-Trace sections 4.3/4.4) nor the data-trace packets (chapter 8). Data trace, where built, is Nexus data trace on the N-Trace back end.

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  • +

    The Format 3 subformat 2 context packet (E-Trace section 7.4) — not emitted by the te_inst generator (its format inventory is the module header of rtl/ct_L2_te_inst_gen.sv); process context on the N-Trace back end travels as the Ownership message instead.

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  • +

    64-bit addresses — an EN_ETRACE build with CT_XLEN = 64 is rejected at elaboration rather than truncating silently (Chapter 33).

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  • +

    A non-zero irdepth field width — with the field at width zero, one implicit-return corner cannot be expressed on the wire; the consequence is measured and stated in Chapter 33.

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3.3.4. TCI 1.0 — the register model and the sinks

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CTTE implements the TCI component convention throughout: each component carries its tr??Control register with the Active bit at offset 0x000 and its tr??Impl identification register at 0x004 (TCI Table 3), and optional features are WARL fields whose write-read behaviour reports their presence (TCI chapter 6). Of the component set in TCI Table 1, CTTE provides:

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TCI componentType codeCTTE

Trace Encoder

0x1

The te block: control, instruction and data trace configuration, timestamp unit (TCI section 6.1), trigger registers (section 6.2, Tables 19 — 21), and the filter/comparator window 0x400 — 0x7FC (section 6.3, Tables 22 — 24). See Chapter 16.

Trace ATB Bridge

0xE

The atb block (TCI chapter 10).

Trace PIB Sink

0xA

The examples ship a sink implementing the chapter-9 4-bit DDR mode (Section 12.2); the full component, including the Table 55 calibration patterns and a TCI chapter-8 funnel with its own trFunnel?? register block, is a separate reference implementation outside this repository. See Chapter 12.

Trace Funnel

0x8

Not implemented as a TCI register component on the encoder side: CTTE’s own funnel is configured by elaboration ports and has no registers (Chapter 11). The only trFunnel?? registers in the system belong to the PIB’s funnel.

Trace RAM Sink

0x9

Not implemented (TCI chapter 7). Off-chip capture uses the ATB/PIB path; on-chip consumers use the AXI-Stream export (Chapter 17).

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For the trigger registers CTTE follows the TCI prescription for absent hardware: external trigger input #0 is implemented with the Table 20 actions 0/2/3/4, inputs #1 — 7, the trigger outputs (Table 21) and the vendor debug-trigger register (Table 19) read as fixed 0 — "if external trigger input #0 does not exist, then its action is fixed at 0" is the specification’s own wording for this answer. The hart-stall options (trTeInstStallEna, trTeDataStallEna; TCI Table 9 bit 13, Table 13 bit 4) are not implemented: CTTE’s ingress port is unidirectional by construction and drives no signal toward the hart; the drop policy (trTeDataDropEna, a TCI-defined control) is the implemented alternative (Chapter 4).

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Three register-map components — performance counters (pc, type 0x3), watchpoints (wp, 0x4) and the data-flow range filter (df, 0x5) — are CEDARtools extensions. Their type codes are not assigned by TCI Table 1, and the TCI does not designate a vendor range for component type codes; the registers carry [CTTE …​] markers in the generated tables, and the conformance consequences are stated in Chapter 4.

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3.4. Where the documents overlap or contradict

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These are the known friction points between the four documents themselves — places where an assessor with two of the PDFs open side by side will see a difference. Each row names CTTE’s position.

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Friction pointThe two readingsCTTE’s position

Watchpoint mask polarity (within the Nexus standard itself)

Section 4.3.23 prose: watchpoints "can be masked …​ by writing a '1'" — reads as 1 = suppressed. Table B-26 (register B.8.4): WEM "1 = enabled for WTM".

Follows Table B-26: a 1 enables reporting. A consumer written against the prose reading inverts the mask (Section 14.3.4).

ECODE field length

Nexus: fixed-length error code (Table 4-34 context). N-Trace: made variable-length — the profile’s single declared incompatibility (N-Trace chapter 12).

Follows N-Trace: variable-length ECODE, TSTAMP stays byte-aligned.

ECODE bit meanings

Nexus Table 4-36 defines the full bitmap (watchpoint, data trace, program trace, ownership, status, data acquisition, in-circuit trace, vendor). N-Trace Table 16 adopts only program trace, ownership and vendor, and marks the rest Reserved — calling its encoding "a subset of IEEE-5001 Nexus Standard encoding".

Emits the full Nexus Table 4-36 granularity. The positions N-Trace leaves Reserved carry their Nexus meanings, which is the reading the N-Trace subset wording points back to (Chapter 14).

Synchronization cadence bound

Nexus: a with-sync message at least every 256 trace messages (Table 4-2, "Periodic Message Counter"). N-Trace/TCI: a configurable mechanism (trTeInstSyncMode / InstSyncMax, interval 2^(InstSyncMax+4) in a selectable unit) that does not restate the 256 bound.

Implements the N-Trace/TCI mechanism. A legal N-Trace configuration can therefore exceed the older Nexus bound; the CTTE reset cadence is stated, with its measured rationale, in the register model (Chapter 16).

Sequential-instruction-counter sync (SYNC = 4)

N-Trace section 8.3: "may be only used in BTM mode".

CTTE optionally uses it in HTM as a full synchronization — a documented deviation, off by default (Chapter 4).

Branch prediction and jump-target cache

E-Trace section 7.8 defines both as optional efficiency extensions. N-Trace Table 8 requires their TCI enable bits to be "hard coded as 0".

Standard-defined on the E-Trace back end; a documented vendor extension (TCODE 56/57, writable enables) on the N-Trace back end (Chapter 4).

Device ID field width and occasion

Nexus Table 4-7: ID is a fixed 32-bit field, emitted after a debug-logic reset of an AUX-only implementation.

CTTE emits the ID variable-length and per trace-on edge — both documented deviations, stated with their reasons in Chapter 4.

Terminology: "branch"

Nexus calls every flow change a branch. N-Trace deliberately uses RISC-V ISA terms — direct conditional branch, unconditional jump (N-Trace chapter 6, note).

This manual follows the N-Trace/RISC-V usage except when quoting Nexus message names.

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3.5. Which document to measure against

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ObservationYardstick

Byte stream of an N-Trace instance

N-Trace 1.0 Table 9 and chapter 3 framing; field formats per IEEE-ISTO 5001-2012 sections 4.3.x for the messages the profile does not detail; the per-TCODE resolution is Chapter 14.

Byte stream of an E-Trace instance

E-Trace 2.0 chapter 7, reference algorithm chapter 9.

Register accesses

TCI 1.0 chapters 4/6 with the N-Trace clarifications of N-Trace chapter 4 (Table 8); authoritative field-by-field tables, generated from the same source as the hardware, in Chapter 16.

Ingress signals of the attached core

E-Trace 2.0 chapter 4, with the per-core adapter contracts of Chapter 6.

Instrumentation payloads (TCODE 7)

IEEE-ISTO 5001-2012 section 4.3.21 for the message; Chapter 15 for the CTTE payload contract inside its DQDATA field.

Everything CTTE claims beyond these documents

Chapter 4, one claim per row, each with its checked clause.

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4. Conformance and Differentiation

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This chapter answers two questions an assessor asks in this order: where does CTTE deviate from the specifications it implements, and what does it do that those specifications do not define. The deviations come first, because a differentiation claim is only worth reading from a document that is honest about its departures.

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Three ground rules govern every statement here:

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+
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  • +

    The comparison is against four published documents — IEEE-ISTO 5001-2012, RISC-V N-Trace 1.0, Efficient Trace for RISC-V 2.0 and the RISC-V Trace Control Interface 1.0, in the revisions named in Chapter 3 — and against nothing else. "Not defined there" is checkable against those texts. It is not a claim about any vendor’s product, and this chapter makes no such claim.

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  • +

    Every clause citation was checked against the primary document, not against a summary. The line-by-line check, including the claims that did not survive it, is recorded in an internal audit protocol.

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  • +

    CTTE implements; it is not certified. No Nexus compliance class is claimed (Chapter 3), and no conformance mark, compliance certification or endorsement by RISC-V International or by the IEEE-ISTO is claimed or implied.

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4.1. The conformance position in one paragraph

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+

A freshly reset CTTE instance with the committed full build profile emits a stream that stays within the N-Trace 1.0 message set, with one exception: the self-identification message, a Vendor-Defined message in the TCODE range 56 — 62 that both IEEE-ISTO 5001-2012 Table 4-5 and N-Trace 1.0 Table 9 designate for vendor use, and which any N-Trace decoder frames and skips by the self-delimiting MSEO framing even if it does not understand it. Setting trTeControl.SendConfig = CFG_NONE removes that exception (Section 14.2.1). Every departure from that envelope must be switched on twice — a compile switch and a runtime control, both default-off — and each such departure is listed either in the deviation table below or in the message catalog (Chapter 14).

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4.2. Documented deviations

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+

Each row is a place where CTTE’s behaviour differs from a clause of one of the four documents. "Documented deviation" means: deliberate, default-off where a default exists, stated with its reason, and — where the wire is affected — announced to the decoder in-band.

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DeviationStandard position (clause)CTTE behaviour and reason

SYNC = 4 used in history mode

N-Trace 1.0 section 8.3: the sequential-instruction-counter synchronization "may be only used in BTM mode"; Table 25 marks the code "Not required".

Optionally emitted in HTM as a full synchronization instead of the leaner RCODE = 0 drain (CT_EN_SEQ_SYNC and trTeControl.InstSeqSyncEnable, reset 0). A full re-anchor at a known instruction-count cadence is what a mid-stream consumer can attach to; the deviation is off by default and byte-invisible until enabled.

Branch-prediction and jump-target-cache enables are writable on the N-Trace back end

N-Trace 1.0 Table 8: trTeInstEnBranchPrediction and trTeInstEnJumpTargetCache "must be hard coded as 0".

When built (CT_EN_BP / CT_EN_JTC), the two TCI Table 11 bits [4]/[5] are writable and the resulting messages are vendor TCODEs 56/57 in the designated vendor range. The stream deliberately leaves the N-Trace 1.0 message set; a decoder without the bit-identical model cannot follow it, which is why both structure sizes and enables are advertised in the configuration message (Chapter 18). Reset 0 on both bits keeps the default stream conformant.

Data trace built despite the N-Trace 1.0 profile

N-Trace 1.0 Table 8: trTeDataImplemented and "other trTeData…​" "must be 0", because Nexus data-trace messages "are not part of version 1.0"; Table 27 names Nexus-compatible data trace a likely future enhancement.

With CT_EN_DATA_TRACE, CTTE implements the IEEE-ISTO 5001-2012 data-trace messages (sections 4.3.17/4.3.18) and the TCI trTeDataControl register. This is an opt-in Nexus extension outside strict N-Trace 1.0, reset-off (trTeDataControl.DataTracing = 0).

Device ID field width and emission occasion

IEEE-ISTO 5001-2012 Table 4-7: the ID is a fixed 32-bit field; section 4.3.2 ties emission to a tool-initiated debug-logic reset of an AUX-only implementation.

CTTE emits the ID as a variable-length field (leading zeros stripped) and once per trace-on edge. Reasons: a fixed field would need a special case in both egress paths for a value a decoder reads as an integer anyway, and CTTE has no Nexus AUX or tool-reset concept — the trace-on edge is the moment a decoder needs the identity. A consumer expecting 32 fixed bits must be told; the pinned reference decoder reads the variable form (Section 29.4).

Sequential-jump inference without its TCI register bit

TCI 1.0 Table 11 bit [2] (trTeInstEnSequentialJump) is the runtime enable for the N-Trace section 9.1 optimization.

CTTE fixes the choice at elaboration (CT_SIJUMP, an attribute of the attached core’s ingress convention); the TCI bit is not implemented and reads 0 even when the inference is active. A tool that reads only the register would misjudge the stream; the authoritative advertisement is CAPS bit 6 in the configuration message (Chapter 18). The same holds for the implicit-return mode field (TCI Table 11 bits [7:6], not implemented): the model structure is reported in-band, not in the register map.

CTTE register extensions occupy TCI-reserved bit positions

TCI 1.0 Table 9 reserves trTeControl bits [8:7], [10], [19:18] and [31:27]; Table 11 reserves trTeInstFeatures bits [15:11]. TCI’s designated vendor space is the register range 0xE00 — 0xFFF (Table 3); no vendor designation exists for reserved bits ("software should always write 0 to reserved bits", TCI chapter 5).

CTTE places SendConfig [8:7], InstSeqSyncEnable [10], the two upper InstSyncMode bits [19:18], SendDeviceId [29:28] and the four extension enables InstEnRepeatBranch [11], InstEnWideIcnt [12], InstEnIbhs [13], InstEnRepeatInstr [14] in reserved positions. All reset to the value a TCI-only tool would write (0), except SendConfig (reset CFG_ONCE, documented in Chapter 18); every one is marked [CTTE …​] in the generated register tables (Chapter 16). Risk, stated plainly: a future TCI minor revision may assign these bits differently; the register source would then be revised, and the tr??Impl version fields are the discovery path for that case.

Extension components use unassigned TCI component type codes

TCI 1.0 Table 1 assigns component types 0x1, 0x8, 0x9, 0xA, 0xE; it does not assign 0x3, 0x4, 0x5 and does not designate a vendor range for type codes.

The performance-counter, watchpoint and range-filter components report types 0x3/0x4/0x5. Whether unassigned codes are free for vendor use is not stated by the TCI — the honest reading is "not assigned by TCI Table 1", and a future revision could assign them. The components follow the TCI register conventions (Control/Impl pair, Active bit) so that TCI-aware tooling can at least identify and skip them (Chapter 16).

Repeat Instruction messages on an N-Trace stream

IEEE-ISTO 5001-2012 sections 4.3.14/4.3.15 define TCODE 31/32; N-Trace 1.0 Table 9 leaves them Reserved.

Opt-in (CT_EN_REPEAT_INSTR, InstEnRepeatInstr, reset 0): an enabled stream is an Accemic/ISTO extension rather than a strict N-Trace 1.0 stream. A strict N-Trace decoder skips the messages by framing but loses the loop compression (Chapter 9).

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+

Two earlier deviations no longer exist and are listed so that a reader of older captures can date them: CTTE once used the standard-reserved sync codes 12/13 for vendor sync requests (now the single vendor-designated code 14, N-Trace Table 25) and once emitted Correlation messages with CDF = 0 in history mode (now always CDF = 1 with the HIST field present, per N-Trace Table 24). Both corrections are pinned by the byte-identity test legs (Chapter 30).

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4.3. Differentiation — what CTTE adds beyond the four documents

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The discipline of this table is the reason it is short. For every candidate row the question was asked verbatim: does one of the four documents already define this? If yes, the row does not appear as differentiation — however well CTTE implements it. What survives is listed with the clause that marks the boundary of the standard’s territory and the in-repository evidence for CTTE’s part. Announced loss, source filtering, repeated-history compression, implicit return and delta timestamps are examples of capabilities that did not survive — the standards define them, and CTTE simply implements them; the audit protocol records each such verdict.

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CapabilityWhat the standards define (clause)What CTTE addsEvidence

Software-triggered instrumentation

IEEE-ISTO 5001-2012 section 4.3.21 defines the Data Acquisition message as a Public Message and expressly allows "vendor-defined mechanisms for instrumenting software" as its trigger. N-Trace 1.0 Table 9 does not adopt TCODE 7.

The vendor-defined mechanism itself: the ACT-CAP/ACT-ST command protocol — a single retiring csrw to CPU CSR 0x0B10 composes a complete DQM with up to three 64-bit elements (192-bit payload) and routes it to the trace port, the AXI-Stream port, or both. The message on the wire is standard; the composition path is the CEDARtools contribution.

Chapter 19, Chapter 15

Event-triggered instrumentation with identity

IEEE-ISTO 5001-2012 section 4.3.23 defines the Watchpoint message and B.8.4/Table B-26 its 16-bit enable mask. N-Trace 1.0 does not adopt TCODE 15.

A 1023-slot watchpoint table driven through the ACT-ST command path, reported through the standard 16-bit WPHIT/WEM mechanism with a software-owned bit-to-slot convention — and a documented resolution of the standard’s own mask-polarity conflict (Chapter 3).

Chapter 19, Section 14.3.4

Announced loss, with measured recovery behaviour

Loss announcement itself is standard three times over: IEEE-ISTO 5001-2012 section 4.3.22 (Error before the next sync), N-Trace 1.0 section 7.4 with SYNC = 7 Required (Table 25), and E-Trace 2.0 section 7.5 (qual_status = trace_lost). CTTE claims no novelty for announcing loss.

What the documents do not provide is evidence of how an implementation behaves across a loss: CTTE carries a 15-scenario overflow/robustness suite — injected and natural overflow, compression-model state across recovery, pause edges, trap-window anchors, flush ordering — each gated in CI, plus the full IEEE-ISTO Table 4-36 ECODE class granularity beyond the subset N-Trace 1.0 Table 16 adopts.

Chapter 30, Chapter 33

Data-trace shedding with a non-desynchronizing announcement

TCI 1.0 Table 13 defines the policy bit (trTeDataDropEna: suppress data trace "at some watermark level" to protect the instruction trace) — the policy is standard.

The defined contract on top of the bit: shedding starts at a named watermark (3/4 of the eTIP queue), each drop episode is announced by exactly one Error message with ECODE = 0x02 and deliberately without the SYNC = 7 re-anchor — the instruction trace was not lost and is not forced to re-anchor. The consequence of getting this wrong is measured: a decoder treating the marker as a full desynchronization recovered 269 of 760 PCs on the gate test; the scoped reference decoder recovers 760 of 760 (tests/data/06_df_drop).

Chapter 30, Chapter 32

Filter gaps announced in standard vocabulary

Source filtering is standard: TCI 1.0 section 6.3 defines the filter and comparator register machinery, E-Trace 2.0 section 2.3 the filtering model. CTTE claims no novelty for filtering at the source.

The gap contract: leaving a filtered region emits Correlation EVCODE = 4, re-entering re-anchors with SYNC = 5 — the existing pause vocabulary, so a stock decoder needs no change to consume a filtered stream; plus per-process filtering by routing the TIP context bus into a standard comparator input. Verified end to end in simulation with real core RTL; the board-level kernel-written-ASID leg is an open follow-on, stated as such.

Chapter 16, Chapter 33

In-band self-description of build and configuration

The vendor space is standard-designated (Table 4-5; N-Trace 1.0 Table 9: TCODEs 56 — 62 "for use by Vendor Defined messages"). E-Trace 2.0 reports its run-time option bits in-band (section 7.5 ioptions) and its structural parameters out-of-band (chapter 10 discovery). Neither Nexus nor N-Trace defines a configuration message.

A vendor message (TCODE 58) that separates compiled-in (CAPS) from currently enabled (ENAB) and carries the structural sizes of the compression models — return stack, jump-target cache, branch predictor — and the address width, so a decoder attaching to a stream configures both of its model sets from the stream alone, with no out-of-band step. Forward compatibility is append-only and versioned (CFGVER).

Chapter 18

Compression beyond the defined schemes

N-Trace 1.0 chapter 9 defines sequential jump, implicit return and repeated history; IEEE-ISTO 5001-2012 defines Repeat Branch and Repeat Instruction; E-Trace 2.0 section 7.8 defines branch-prediction and jump-target-cache packet formats. The schemes as such are standard territory.

Three additions. (1) Branch prediction (512-entry) and jump-target cache (64-entry) on the N-Trace back end, as vendor TCODEs 56/57 with the model structure advertised in-band — N-Trace itself hard codes these features off. (2) A replayability condition on Repeat Branch collapse that the base standard’s match rule (section 4.3.13: same I-CNT and target) does not require but that decode correctness does — found by seeded soak, pinned by a regression gate. (3) A per-feature proof obligation: every compression feature has a byte-identity leg showing the same decoded PC sequence at a strictly smaller byte count, and an off-state byte-identical to a build without the feature.

Chapter 9, Chapter 30

Per-instance protocol choice from one netlist

TCI 1.0 Table 9 (trTeFormat) anticipates that a trace encoder speaks E-Trace or N-Trace; none of the documents addresses building both from one source with per-instance selection.

One netlist source elaborates to an N-Trace or an E-Trace encoder per instance (EN_NTRACE/EN_ETRACE, exactly one), with read-only discovery (trTeProtocolSel, trTeImpl.ProtocolMajor) and a hardware framing advertisement (atb_te_raw) so downstream logic parses what the netlist actually emits. The funnel’s CTMX container carries an N-Trace stream next to E-Trace reference-raw channels and re-splits them byte-identically.

Chapter 17, Section 11.9

Uncompressed on-chip event output

Within the four documents, trace leaves an encoder through the trace path: TCI 1.0 Table 2 enumerates the allowed component connections (encoder to sink, funnel or ATB bridge); no second, uncompressed consumer-facing output is defined. The statement is scoped to these documents, not to the market.

A 96-bit AXI-Stream export that carries instrumentation events — including program-counter and timestamp elements — to in-fabric consumers (watchdogs, CFI checkers, runtime verification) in parallel with, and independent of, the compressed trace stream.

Section 17.7, Chapter 19

Per-region performance counters at the encoder

None of the four documents defines a performance-counter component (mechanically checked: the term does not occur in any of the four texts); the TCI component list (Table 1) has no entry for one. Scoped to these documents.

A counter block with address-range regions and stall thresholds, implemented as a CEDARtools register-map component (type 0x3 — see the deviation table above for the type-code caveat).

Chapter 16

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4.4. What supports these statements

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+

Conformance claims are only as good as the evidence path behind them. Three properties of the CTTE verification setup carry the weight:

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  • +

    An independent decoder is the oracle. Every stream check round-trips through CTTD, a separately maintained decoder pinned by checksum, and is compared against the CPU model’s expected output — the encoder is never its own referee (Chapter 29, Section 29.4).

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  • +

    The wire format is pinned byte-exactly. Byte-identity legs turn any unintended stream change into a red gate, which is what makes "the reset stream stays inside N-Trace 1.0" a regression-checked property rather than a design intention (Chapter 30).

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  • +

    Coverage and status are published with their provenance. The line-coverage figures, their waivers and their currency caveats are in Chapter 31; the per-feature implementation status, with its evidence column, is Chapter 32; the known limitations, including the spec-compatibility corners, are Chapter 33.

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+
+
+

On real hardware, the deepest single conformance datapoint to date is the CVA6/Linux demonstrator: an OpenSBI and Linux boot captured through the trace-encoder port and decoded to 4,619,090 instructions with zero errors (Chapter 28).

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5. Encoder Architecture

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5.1. Overview

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+

The CEDARtools.TraceEncoder (CTTE) converts a RISC-V hart’s Trace Ingress Port (TIP) into a compressed, standards-based trace byte stream on an ATB output, plus an uncompressed AXI-Stream event path for on-chip processing. It is the central element of the trace subsystem: everything upstream of it is core-specific adaptation, everything downstream of it is transport and decoding.

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+

The top-level module is ct_encoder (rtl/ct_encoder.sv). Its responsibilities, in the order the data flows through them, are:

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+
+
    +
  • +

    accept TIP retirement beats in the tip_clk domain and preprocess them into an internal extended TIP (eTIP) event stream (ct_L23_preproc),

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  • +

    turn eTIP events into protocol messages in the proc_clk domain (ct_L2_msg_gen for N-Trace, ct_L2_te_inst_gen for E-Trace),

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  • +

    serialize those messages into the on-wire byte format and cross into the atb_atclk output domain (ct_L2_nexus_formatter + ct_L2_mseo_mdo_formatter, or ct_L2_compact_packer, or ct_L2_te_packetizer),

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  • +

    and export selected instrumentation payloads on AXI-Stream without passing through the trace format at all.

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    • +
+
+
+
+ + + + + + + + + + +
+
+
+ TIP +
+ retirement beats (tip_clk) +
+
+
+ + + TIP... + + + + + + + + + + + +
+
+
+ ct_L23_preproc +
+ preprocessing stage (tip_clk) +
+ sync generation, timestamp unit, +
+ performance counters, ACT, filters, +
+ TIP delay, AXIS + eTIP composers +
+
+
+ + + ct_L23_preproc... + + + + + + + + + + + +
+
+
+ eTIP event stream +
+ + next-IADDR sideband +
+ CDC tip_clk to proc_clk +
+
+
+ + + eTIP event stream... + + + + + + + + + + + +
+
+
+ ct_L2_msg_gen +
+ Nexus message generation +
+ (proc_clk) +
+
+
+ + + ct_L2_msg_gen... + + + + + + + + + + + +
+
+
+ ct_L2_nexus_formatter +
+ TCODE + field list +
+
+
+ + + ct_L2_nexus_formatter... + + + + + + + + + + + +
+
+
+ ct_L2_mseo_mdo_formatter +
+ MDO/MSEO chunks, ATB beats +
+ proc to atb_atclk CDC, flush detect +
+
+
+ + + ct_L2_mseo_mdo_formatter... + + + + + + + + + + + +
+
+
+ ATB +
+ (atb_atclk) +
+
+
+ + + ATB... + + + + + + + + + + + +
+
+
+ wall clock +
+ periodic-sync cadence +
+
+
+ + + wall clock... + + + + + + + + + + + +
+
+
+ AXI-Stream +
+ instrumentation, no trace format +
+
+
+ + + AXI-Stream... + + + + + + + + + + + +
+
+
+ ct_cs_cpuif_wb +
+ configuration (wb_clk) +
+
+
+ + + ct_cs_cpuif_wb... + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+
+
+ generic +
+ trace +
+
+ messages +
+
+
+
+ + + generic... + + + + + + + + + + + + +
+
+
+ Nexus +
+ field list +
+
+
+
+ + + Nexus... + + + + + + + + + + + + + + + + + + + + +
+
+
+ configuration +
+
+
+ + + configuration + + + + + + + + + + + + +
+
+
+ trace-quota levels +
+
+
+ + + trace-quota levels + + + + + + + + + + + + +
+
+
+ quota_cnt_clr +
+
+
+ + + quota_cnt_clr + + + + + + + + + + + + +
+
+
+ syncreq, afvalid +
+
+
+ + + syncreq, afvalid + + + + + + + + + + Text is not SVG - cannot display + + + + +
+
Figure 3. CTTE trace encoder overview — the N-Trace egress path
+
+
+

The overview above and the element diagram further below draw the N-Trace egress chain only — message generation, the Nexus formatter and the MSEO/MDO formatter. The figure below shows all three egress paths: the same preprocessor output, eTIP, reaches the ATB output on any of them.

+
+
+
+ + + + + + + + + + +
+
+
+ TIP +
+ (tip_clk) +
+
+
+
+ + + TIP... + + + + + + + + + + + +
+
+
+ ct_L23_preproc +
+
+
+ + + ct_L23_preproc + + + + + + + + + + + +
+
+
+ eTIP +
+
+
+ + + eTIP + + + + + + + + + + + +
+
+
+ ct_L2_msg_gen +
+
+
+ + + ct_L2_msg_gen + + + + + + + + + + + +
+
+
+ ct_L2_nexus_formatter +
+
+
+ + + ct_L2_nexus_formatter + + + + + + + + + + + +
+
+
+ ct_L2_mseo_mdo_formatter +
+
+
+ + + ct_L2_mseo_mdo_formatter + + + + + + + + + + + +
+
+
+ ct_L2_compact_packer +
+
+
+ + + ct_L2_compact_packer + + + + + + + + + + + +
+
+
+ ct_L2_te_inst_gen +
+
+
+ + + ct_L2_te_inst_gen + + + + + + + + + + + +
+
+
+ ct_L2_te_packetizer +
+
+
+ + + ct_L2_te_packetizer + + + + + + + + + + + +
+
+
+ ATB +
+ (atb_atclk) +
+
+
+
+ + + ATB... + + + + + + + + + + + +
+
+
+ AXI-Stream (instrumentation) +
+
+
+ + + AXI-Stream (inst... + + + + + + + + + + + +
+
+
+ ct_cs_cpuif_wb +
+ (wb_clk) +
+
+
+
+ + + ct_cs_cpuif_wb... + + + + + + + + + + + + +
+
+
+ retirement +
+ beats +
+
+
+
+ + + retirement... + + + + + + + + + + + + + + + + +
+
+
+ N-Trace +
+
+
+ + + N-Trace + + + + + + + + + + + + +
+
+
+ E-Trace +
+
+
+ + + E-Trace + + + + + + + + + + + + + Nexus + + + messages + + + + + + + + + + + + control-flow + + + only + + + + + + + + + + + + + + + + + + + + + + + +
+
+
+ te_inst packets +
+
+
+ + + te_inst packets + + + + + + + + + + + + + + + + +
+
+
+ no trace format +
+
+
+ + + no trace format + + + + + + + + + + + + +
+
+
+ configuration +
+
+
+ + + configuration + + + + + + + + + + Text is not SVG - cannot display + + + + +
+
Figure 4. One event stream, three egress paths
+
+
+

The three are alternatives, not stages. The N-Trace chain is ct_L2_msg_gen → ct_L2_nexus_formatter → ct_L2_mseo_mdo_formatter; the compact path replaces the last two with ct_L2_compact_packer for control-flow-only builds; the E-Trace path is ct_L2_te_inst_gen → ct_L2_te_packetizer. Which of them a given build contains is fixed at synthesis, not selected at runtime — see Section 5.3. The AXI-Stream output leaves the preprocessor without passing through any trace format at all, and the Wishbone CSR shim in the wb_clk domain configures every stage.

+
+
+
+

5.2. Elements

+
+
+ + + + + + + + + + +
+
+
+ ct_L23_preproc (tip_clk) +
+
+
+ + + ct_L23_preproc (tip_clk) + + + + + + + + + + + +
+
+
+ core adapter +
+ TIP source +
+
+
+ + + core adapter... + + + + + + + + + + + +
+
+
+ wall clock +
+ periodic-sync cadence +
+
+
+ + + wall clock... + + + + + + + + + + + +
+
+
+ on-chip consumer +
+ e.g. watchdog CPU +
+
+
+ + + on-chip consumer... + + + + + + + + + + + +
+
+
+ ct_L2_msg_gen +
+ Nexus message generation +
+ (proc_clk) +
+ I-CNT, HIST, compression +
+
+
+ + + ct_L2_msg_gen... + + + + + + + + + + + +
+
+
+ ct_L2_nexus_formatter +
+ TCODE + up to 10 fields +
+
+
+ + + ct_L2_nexus_formatter... + + + + + + + + + + + +
+
+
+ ct_L2_mseo_mdo_formatter +
+ msg buffer, bit slicer, +
+ chunk packer, proc-to-ATB +
+ CDC, flush detect +
+
+
+ + + ct_L2_mseo_mdo_formatter... + + + + + + + + + + + +
+
+
+ ATB interface +
+ atdata, atbytes, +
+ atvalid / atready, +
+ afvalid / afready, syncreq +
+
+
+ + + ATB interface... + + + + + + + + + + + +
+
+
+ bus master +
+ Wishbone +
+
+
+ + + bus master... + + + + + + + + + + + +
+
+
+ wb_to_cpuif bridge +
+
+
+ + + wb_to_cpuif bridge + + + + + + + + + + + +
+
+
+ ct_cs_cpuif_wb (wb_clk) +
+ PeakRDL ct_cs_cpuif CSRs +
+ cs_tip / cs_proc / cs_atb +
+
+
+ + + ct_cs_cpuif_wb (wb_clk)... + + + + + + + + + + + + +
+
+
+ TIP +
+ (tip_clk) +
+
+
+
+ + + TIP... + + + + + + + + + + + + + + + + +
+
+
+ etip_q +
+
+
+ + + etip_q + + + + + + + + + + + + +
+
+
+ generic +
+ trace +
+
+ messages +
+
+
+
+ + + generic... + + + + + + + + + + + + +
+
+
+ Nexus +
+ field +
+
+ list +
+
+
+
+ + + Nexus... + + + + + + + + + + + + + + + + +
+
+
+ AXIS +
+
+
+ + + AXIS + + + + + + + + + + + + + + + + + + + + + + + + +
+
+
+ configuration +
+ (all stages) +
+
+
+
+ + + configuration... + + + + + + + + + + + + +
+
+
+ quota_cnt_clr +
+
+
+ + + quota_cnt_clr + + + + + + + + + + + + +
+
+
+ trace-quota levels +
+
+
+ + + trace-quota levels + + + + + + + + + + + + +
+
+
+ syncreq, afvalid +
+
+
+ + + syncreq, afvalid + + + + + + + + + + + +
+
+
+ ACT blocks (CT_EN_ACT) +
+ act_cap, act_st, act_proc +
+
+
+ + + ACT blocks (CT_EN_ACT)... + + + + + + + + + + + +
+
+
+ ct_L23_preproc_perfcnt +
+ performance counters +
+ (CT_EN_PERFCNT) +
+
+
+ + + ct_L23_preproc_perfcnt... + + + + + + + + + + + +
+
+
+ ct_L23_preproc_ts (ts_inst) +
+ timestamp unit (CT_EN_TIMESTAMP) +
+ trTsControl: none / prescaled +
+ counter / core tip._time +
+
+
+ + + ct_L23_preproc_ts (ts_inst)... + + + + + + + + + + + +
+
+
+ ct_L23_preproc_sync +
+ periodic / one-shot +
+ sync generation +
+
+
+ + + ct_L23_preproc_sync... + + + + + + + + + + + +
+
+
+ ct_L23_preproc_tip_delay +
+ TIP alignment delay +
+
+
+ + + ct_L23_preproc_tip_delay... + + + + + + + + + + + +
+
+
+ filter chain +
+ comp_filters, df_range, +
+ cf, df +
+
+
+ + + filter chain... + + + + + + + + + + + +
+
+
+ ct_L23_preproc_composer_etip +
+
+
+ + + ct_L23_preproc_composer_etip + + + + + + + + + + + +
+
+
+ ct_L23_preproc_composer_axis +
+ AXIS composer +
+
+
+ + + ct_L23_preproc_composer_axis... + + + + + + + + + + + + +
+
+
+ instrumentation +
+ records +
+
+
+
+ + + instrumentation... + + + + + + + + + + + +
+
+
+ compose +
+ CF / DF / DAQ +
+ eTIP messages +
+
+
+ + + compose... + + + + + + + + + + + +
+
+
+ ovf_injector +
+ overflow marker +
+ on queue-full +
+
+
+ + + ovf_injector... + + + + + + + + + + + +
+
+
+ eTIP CDC FIFO +
+ cvs_cdc_fifo2 +
+ P-to-1 slots +
+ P = ETIP_PAR_MSG +
+
+
+ + + eTIP CDC FIFO... + + + + + + + + + + + +
+
+
+ next-IADDR FIFO +
+ 1 msg per slot +
+
+
+ + + next-IADDR FIFO... + + + + + + + + + + + + + + + + + + + + + + + + +
+
+
+ sync requests +
+
+
+ + + sync requests + + + + + + + + + + + + +
+
+
+ counter events +
+
+
+ + + counter events + + + + + + + + + + + + +
+
+
+ DAQ events +
+
+
+ + + DAQ events + + + + + + + + + + + + +
+
+
+ ts_value +
+
+
+ + + ts_value + + + + + + + + + + + + + + + + +
+
+
+ next_iaddr_q +
+
+
+ + + next_iaddr_q + + + + + + + + + + Text is not SVG - cannot display + + + + +
+
Figure 5. CTTE trace encoder elements — the N-Trace egress path
+
+
+

Data flows left to right. The TIP enters in the tip_clk domain; the preprocessor crosses it into the proc_clk pipeline through a dual-clock FIFO; the output stage crosses again into the atb_atclk domain. The Wishbone CSR shim (wb_clk) configures every stage. The free-running wall_clk paces the periodic-synchronization generator (ct_L23_preproc_sync); it is not the timestamp source — timestamps come from the preprocessor’s own timestamp unit (ct_L23_preproc_ts, built with CT_EN_TIMESTAMP), whose source is selected by trTsControl: none, a prescaled internal counter in the tip_clk domain, or the core’s own tip._time.

+
+
+

The module naming encodes the layer:

+
+ ++++ + + + + + + + + + + + + + + + + + + + + +
PrefixMeaning

ct_L23_*

Layer 2/3 preprocessing, tip_clk domain (rtl/ct_L23_preproc.sv and rtl/preproc/*).

ct_L2_*

Layer 2 message generation, formatting and egress, proc_clk/atb_atclk domains.

ct_L1_*

Layer 1 transport-level aggregation — the trace funnel (rtl/ct_L1_funnel.sv), see Chapter 11.

+
+

The design is deliberately built from small, self-contained stages with explicit interfaces, so individual blocks can be modified, replaced or added without disturbing the rest of the encoder.

+
+
+
+

5.3. Two Back Ends, One Front End

+
+

CTTE implements two output protocols. Which one is built is a synthesis choice, not a runtime one:

+
+ +++++ + + + + + + + + + + + + + + + + + + + +
Back endGeneratorEgress

N-Trace

ct_L2_msg_gen (rtl/ct_L2_msg_gen.sv) — Nexus messages per the RISC-V N-Trace specification.

ct_L2_nexus_formatter + ct_L2_mseo_mdo_formatter, or ct_L2_compact_packer in CF-only profiles.

E-Trace

ct_L2_te_inst_gen (rtl/ct_L2_te_inst_gen.sv) — te_inst packets per the RISC-V Efficient Trace specification.

ct_L2_te_packetizer (rtl/ct_L2_te_packetizer.sv), reference-raw framed te_inst bytes.

+
+

Everything upstream of the back end is protocol-agnostic: ct_L23_preproc turns TIP beats into the eTIP event stream that both generators consume.

+
+
+

The selection is per instance, through the parameters EN_NTRACE / EN_ETRACE (defaulting to ct_pkg::CT_EN_NTRACE / ct_pkg::CT_EN_ETRACE). Exactly one of the two must be set; an elaboration guard in rtl/ct_encoder.sv rejects both-zero and both-one builds. Because the choice is per instance, a multi-encoder SoC can build one encoder as N-Trace and the next as E-Trace out of the same netlist sources. The output port atb_te_raw advertises the framing this instance produces (0 = Nexus MSEO/MDO chunks, 1 = E-Trace reference-raw te_inst bytes) so a downstream funnel or sink parses what the netlist actually emits rather than a second, software-programmed copy of that fact. The read-only discovery mirrors trTeProtocolSel.Protocol and trTeImpl.ProtocolMajor report the same truth to software.

+
+
+ + + + + +
+
Note
+		 +The historical dual build with a runtime protocol select has been retired; the protocol is a synthesis parameter (rtl/ct_encoder.sv, genDualBackend guard). +
+
+
+
+

5.4. Clock Domains

+
+

ct_encoder spans five clock domains, crossed internally by explicit CDC logic (rtl/ct_encoder.sv module header).

+
+ +++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
ClockResetRole

tip_clk

tip_rst

TIP ingress — the core’s retirement rate. The whole preprocessor runs here.

proc_clk

proc_rst

Internal processing pipeline: message generation and formatting.

atb_atclk

atb_atresetn

ATB trace output.

wb_clk

wb_rst

Wishbone CSR access.

wall_clk

wall_clk_rst

Free-running cadence reference for periodic synchronization (ct_L23_preproc_sync). Not the timestamp source — see the note under the element diagram.

+
+

An additional input ct_cs_rst provides a soft reset of the CSR shim independent of the functional resets. A single-clock build is possible (ct_pkg::CT_SINGLE_CLOCK), which shrinks the CDC FIFO depths accordingly (ETIP_CDC_FIFO_DEPTH in rtl/pkg/ct_pkg.sv).

+
+
+

The clocking, reset and CDC contract that an integrator has to satisfy is stated in the interface chapter; this chapter only names the domains.

+
+
+
+

5.5. Top-Level Ports

+
+

The module connects through SystemVerilog interfaces rather than flat port lists:

+
+ +++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
InterfaceDirectionCarries

tip (tip_if.slave)

in

Instruction and data retirement from the core: itype, ecause, iaddr, priv, _context, iretire, ilastsize, and for data trace dretire, dtype, daddr, dsize, data (or, in split-load mode, sdata / lresp / ldata). Field set defined in rtl/pkg/tip_if.sv and rtl/pkg/tip_pkg.sv.

wb (wb_if.slave)

in

Wishbone control/status register access. The register layout is defined in rdl/ct_cs_cpuif.rdl.

atb (atb_if.master)

out

32-bit ATB trace stream (atdata, atbytes, atvalid/atready, flush handshake afvalid/syncreq).

axis (axis_if.master)

out

AXI-Stream instrumentation / DAQ export. The payload width is ct_pkg::ACT_CAP_AXIS_TDATA_WIDTH = 3 x ACT_CAP_INT_ELEMENT_WIDTH (32 bit), i.e. three 32-bit elements per beat.

atb_te_raw

out

Constant framing advertisement of this instance (see above).

+
+

The detailed signal-level contract — timing, valid/ready rules, CDC requirements — belongs to the interface chapter and is not repeated here.

+
+
+
+

5.6. Elaboration Guards

+
+

ct_encoder refuses to build configurations whose failure mode would be silent, i.e. would produce a well-formed trace stream that is nevertheless wrong. This is a deliberate design decision: each of the guards below covers a case in which no capture, no assertion and no decoder could recover the lost information after the fact.

+
+ ++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Guard (generate label)Rejected configuration

genNoBackend / genDualBackend

Neither or both of EN_NTRACE / EN_ETRACE set.

genEtraceNoSideband

EN_ETRACE = 1 in a netlist built with ct_pkg::CT_EN_ETRACE = 0. The eTIP sideband widths (privilege, ecause, tval, last-instruction size) are sized by the package, so such a build would emit te_inst format 3.x messages assembled from 1-bit stubs.

genBadXlen

ct_pkg::CT_XLEN other than 32 or 64. The configuration message advertises the address width as a single boolean capability bit (ADDR64), so no other value can be described on the wire.

genCoreXlenUndeclared / genCoreXlenMismatch

The integration parameter CORE_XLEN is 0 (undeclared) or disagrees with ct_pkg::CT_XLEN. A 64-bit hart on a 32-bit ingress loses its upper address bits inside the adapter, before the encoder sees anything.

genBadCtxWidth

ct_pkg::CT_CONTEXT_WIDTH outside 1 .. nexus_vendor::NEXUS_MSG_PROCESS_WIDTH (44). A wider context bus would be truncated into the Ownership PROCESS field without a warning.

genBadIretireWidth

ct_pkg::CT_IRETIRE_WIDTH outside 2 .. nexus_vendor::NEXUS_MSG_I_CNT_WIDTH (8) while CT_EN_BLOCK_TIP = 1. A single beat that alone reaches the I-CNT pre-drain threshold would wedge the indirect-branch history hold.

genEtrace64

EN_ETRACE = 1 together with ct_pkg::CT_ADDR64. The te_inst address fields are sized by CT_ETRACE_ADDR_BITS = 31 and would truncate silently. A 64-bit E-Trace build is not implemented.

+
+

The CORE_XLEN and EN_ETRACE guards are each present twice in the RTL — once as a bare elaboration $fatal and once as an initial $fatal. The duplication is intentional: the repository’s simulation back end runs Verilator through abc-flow with -Wno-fatal, under which an elaboration $fatal is demoted to a warning and the run continues. The initial twin stops the simulation at time 0, before the first TIP beat. A guard that only prints is exactly the state these guards exist to end.

+
+
+
+

5.7. Instance Attributes

+
+

Three parameters are integration declarations rather than netlist knobs. They describe the environment the instance is wired into and are advertised on the wire, so that a decoder does not have to be told out of band.

+
+ ++++ + + + + + + + + + + + + + + + + + + + + + + + + +
ParameterMeaning

CT_SIJUMP

The attached core’s ingress uses the sequentially-implicit-jump convention. Advertised as configuration-message capability bit CAPS.6. The MicroBlaze™ V adapter sets it to 1; see Chapter 6.

CT_DEVICE_ID

Device identity of this encoder instance, width nexus_vendor::NEXUS_MSG_DEVID_WIDTH = 32 bit, layout per IEEE-ISTO 5001-2012 Table B-5 (RN | PN | MID). Default 0 = no device ID assigned. Nothing reaches the wire until software sets trTeControl.SendDeviceId; the value is sampled only at the emission site.

CORE_XLEN

The architectural address width (RISC-V XLEN) of the hart this instance’s TIP is wired to. Not a knob of the netlist — the netlist’s own width is ct_pkg::CT_XLEN — but the integrator’s declaration of what the adapter feeds in. See the elaboration guards above.

SPLIT_DATA_ACCESS

Selects the data-trace path. 0 = dretire-combined mode (data value on tip.data at retirement). 1 = split-load mode: store data on tip.sdata, load data and response on tip.ldata / tip.lresp. Propagated to the data-flow qualifier and the eTIP composer.

+
+

Feature toggles proper (instruction versus data tracing, sync modes, filter and comparator counts, timestamp source, and the entire compression suite) are not top-level parameters: they are compile-time switches in rtl/pkg/ct_pkg.sv paired — for the compression suite — with runtime enables in the register map. See Chapter 9 and the register-model chapter.

+
+
+
+

5.8. Pipeline Stages

+ ++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Stage (module)Responsibility

ct_L23_preproc
+rtl/ct_L23_preproc.sv

TIP delay and path alignment, CDC tip_clk → proc_clk, control-/data-flow filtering and range watchpoints, periodic / trace-enable / quota synchronization generation, performance counters, timestamp selection, ACT-CAP / ACT-ST / ACT-Proc instrumentation processing, composition of the eTIP streams (etip_q, next_iaddr_q) and of the AXI-Stream instrumentation output. See Chapter 7.

ct_L2_msg_gen
+rtl/ct_L2_msg_gen.sv

N-Trace: generates generic trace messages from the eTIP, accumulates I-CNT and branch history, emits synchronizing, resource-full and correlation messages, and hosts the compression suite. Drives trace_msg. See Chapter 8 and Chapter 9.

ct_L2_te_inst_gen
+rtl/ct_L2_te_inst_gen.sv

E-Trace: generates te_inst packets from the same eTIP stream. Drives the packet payload/length/type handshake toward the packetizer.

ct_L2_nexus_formatter
+rtl/ct_L2_nexus_formatter.sv

Maps a generic trace message to a concrete Nexus message: a TCODE plus an ordered field list of up to nexus_vendor::NEXUS_MAX_FIELDS = 10 fields. Drives nexus_msg.

ct_L2_mseo_mdo_formatter
+rtl/ct_L2_mseo_mdo_formatter.sv

CDC proc_clk → atb_atclk; serializes the field list into MDO/MSEO chunks with leading-zero suppression and packs them into 32-bit ATB beats. See Chapter 10.

ct_L2_compact_packer
+rtl/ct_L2_compact_packer.sv

Alternative single-module egress for CF-only profiles (ct_pkg::CT_COMPACT_PACKER): produces the MDO/MSEO chunks directly from a per-TCODE layout table, bypassing the ten-field array. The wire stream is byte-identical to the historical chain.

ct_L2_te_packetizer
+rtl/ct_L2_te_packetizer.sv

E-Trace egress: frames te_inst packets onto ATB and crosses into atb_atclk.

ct_L1_funnel (optional)
+rtl/ct_L1_funnel.sv

Packet-aware merge of several ATB streams into one, without switching mid-packet. See Chapter 11.

+
+
+

5.9. Backpressure, Ordering and Flush

+
+

Backpressure flows strictly upstream through per-stage ready handshakes. In the N-Trace chain the nets are mseo_mdo_formatter_ready → nexus_formatter_ready → ct_L2_msg_gen; in the compact-packer configuration the packer drives nexus_formatter_ready directly. No stage buffers speculatively: a stage that cannot hand its output on holds it stable and stalls its own input. Message order is therefore preserved by construction, and no message can be dropped by backpressure alone.

+
+
+

Two signals run against the data flow and are declared at the top of ct_encoder:

+
+
+
    +
  • +

    synq_req_trace_byte_count and synq_req_trace_msg_count — held trace-quota overflow levels reported by the egress module back to the preprocessor’s synchronization generator, so that quota-based resynchronization is driven by what actually left the encoder.

    +
    • +
  • +

    quota_cnt_clr — the crossed SyncCntClr rearm from the preprocessor back to the egress quota counters.

    +
    • +
+
+
+

The trTeControl.Empty status is likewise a chain rather than a single flag: the upstream term covers the preprocessor’s CDC FIFOs plus whatever the generator still holds back (!etip_q.valid && !next_iaddr_q.valid && msg_gen_idle, respectively te_gen_idle), and the ATB tail module appends its own stages before producing the ATB-domain verdict on cs_atb.trTeEmpty. An integrator polling Empty therefore observes the whole pipeline, not one stage of it.

+
+
+

Flush is a side-channel, not a message class of its own: on atb_afvalid the preprocessor stops feeding the TIP FIFO and raises the TIP side-channel do_flush, which propagates through the downstream stages so the ATB receiver can align to a packet boundary. The idle-core case — a flush request with no further tip.iretire — is covered by the eTIP composer’s per-cycle flush path (rtl/ct_L23_preproc.sv module header).

+
+
+
+

5.10. Global Determinism Guarantees

+
+

All CTTE modules operate deterministically with respect to the TIP input stream and the configuration register state. No arbitration mechanism depends on metastable, timing-dependent or random conditions. Given identical RTL configuration and identical TIP stimulus, the generated trace stream is cycle-accurately reproducible. This property is what makes trace-based safety validation and post-mortem analysis possible at all, and it is enforced by four concrete design rules:

+
+
+
    +
  1. +

    Retire-qualified emission. An output that represents an architectural event is emitted only on a cycle that retires an instruction or a retired data access, so message boundaries line up with the core’s architectural stream.

    +
    2. +
  2. +

    Fixed base latency. Every preprocessing block has a fixed intrinsic latency, and reports it, so that the encoder-wide alignment can be computed rather than tuned.

    +
    3. +
  3. +

    Selectable alignment latency. Parallel preprocessing paths are aligned through a common extra_delay shift-pipeline pattern rather than by re-timing internal logic. ct_L23_preproc computes the maximum path delay across all blocks and derives each block’s extra_delay from it; the bound is ct_pkg::EXTRA_DELAY_MAX (= PREPROC_DELAY_MAX, 44 when CT_EN_ACT = 1). See Chapter 7.

    +
    4. +
  4. +

    Order-preserving backpressure. Stalls delay emission but never reorder or drop events (see above).

    +
    5. +
+
+
+

Determinism is a property of the encoder given its inputs. It does not extend across a change of configuration mid-stream, and it does not claim anything about the core’s determinism: if the hart retires a different instruction sequence, the trace differs accordingly.

+
+
+
+

5.11. What This Chapter Does Not Cover

+
+ +
+
+
+
+
+

6. Trace Sources and Core Adapters

+
+
+

6.1. The Trace Ingress Port as the Contract

+
+

CTTE supports any RISC-V hart that presents a compliant Trace Ingress Port (TIP). Integration is independent of the microarchitecture as long as the hart supplies the required instruction-trace signals — and, where data tracing is wanted, the data-trace signals — on the TIP. The signal-level contract is stated in the interface chapter of this manual and defined in rtl/pkg/tip_if.sv and rtl/pkg/tip_pkg.sv; this chapter is about what it takes to drive that port from a given core.

+
+
+

Most cores do not present a TIP directly. Between the core’s own trace or retirement interface and the TIP sits an ingress adapter, and the adapter is where the interesting work is: the core’s interface is usually a truthful description of that core’s pipeline rather than of the abstract retirement stream a trace encoder needs.

+
+
+

The adapters shipped with CTTE live under rtl/adapters/, and each one has a specification-level document under doc/adapters/. Those documents are deliberately truth tables — empirically measured signal semantics of a specific core and tool version — rather than architecture prose. That distinction matters for an integrator: a rule marked as measured holds for the named version and needs re-measuring when the version changes.

+
+
+

6.1.1. The itype Vocabulary

+
+

The TIP carries a 4-bit instruction type per retirement beat (tip_itype_e, rtl/pkg/tip_pkg.sv), which is the full E-Trace vocabulary:

+
+ ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
CodeMeaningCodeMeaning

0

OTHER

8

UNINFERABLE_CALL

1

EXCEPTION_TRAP

9

INFERRABLE_CALL

2

INTERRUPT

10

UNINFERABLE_TAIL_CALL

3

EXCEPTION_IR (trap return)

11

INFERRABLE_TAIL_CALL

4

NOT_TAKEN_BRANCH

12

CO_ROUTINE_SWAP

5

TAKEN_BRANCH

13

RETURN

6

UNINFERABLE_JUMP (only populated at a 3-bit itype width)

14

OTHER_UNINFERABLE_JUMP

7

reserved

15

OTHER_INFERABLE_JUMP

+
+

A core that exports only the 3-bit subset (codes 0..6) is usable, but the encoder then cannot distinguish calls from returns, and the implicit-return compression (Chapter 9) has nothing to work with. Two of the adapters therefore reconstruct the missing codes from the instruction word; see the CVA6 and MicroBlaze™ V sections below.

+
+
+

The exception cause enum tip_ecause_e follows the RISC-V mcause exception codes. Its "no exception" sentinel deliberately sits at code 14 — a code the architecture reserves — rather than at 15, which is a real cause (store/AMO page fault). On a bare-metal RV32 build without paging the collision was invisible; under Sv39 Linux it is one of the most frequent traps there is, and a waveform, a filter bitmap or a dump reader would have read the most common store trap as "no exception".

+
+
+
+

6.1.2. Four Rules Every Adapter Has to Get Right

+
+

The three shipped adapters were each characterized by measurement, and the same four issues came up every time. They are stated here once, because they are what an integrator writing a new adapter will meet.

+
+
+

1. A trap beat must not retire. Several cores mark the faulting instruction as retired on their trace interface. The encoder counts instruction halfwords on iretire, so a trap beat with iretire = 1 makes the faulting instruction count towards the instruction count and shifts the decoder. Every adapter therefore forces iretire = 0 on exception and interrupt beats.

+
+
+

2. itype must only be driven on a real event. The encoder evaluates itype for control flow without gating it on iretire — iretire only steers the halfword count. A core whose trace bus holds the last instruction’s classification through idle cycles therefore produces ghost control-flow events. This is not cosmetic: it produces extra indirect-branch messages, the message stream derails, and the decoder aborts. The adapter rule is: on a trap indication, drive the trap itype; otherwise, on a valid retirement, drive the decoded itype; otherwise drive OTHER.

+
+
+

3. ilastsize is the halfword count of the last instruction, and it is what the encoder’s instruction count advances by. Where a core’s trace bus carries the raw instruction word, the value follows directly from the low two bits of that word (compressed versus 32-bit encoding) and needs no extra source.

+
+
+

4. The adapter is an observer and never applies backpressure. No shipped adapter can stall its core. If the encoder cannot keep up, the loss is made visible through the encoder’s own error and resynchronization path (Chapter 10), not by holding up the core.

+
+
+

A fifth item is a declaration rather than a rule: the address width of the attached hart must be declared at the encoder instantiation (CORE_XLEN, Chapter 5). A 64-bit hart wired into a 32-bit ingress loses its upper address bits inside the adapter, before the encoder sees anything, and the resulting stream is well-formed and wrong. The declaration is the only place where both widths are known at once.

+
+
+
+

6.1.3. What Each Core’s Ingress Can Carry

+
+

The four cores documented in this chapter do not offer the encoder the same ingress, and the difference stays invisible until a feature that needs the data channel silently produces nothing. The table states it per core, read from the adapters rather than inferred (examples/kv260/README.md):

+
+ ++++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
CoreAdapterData channel (dretire/dtype/daddr/sdata)CSR writes visibleACT-STACT-CAP

MINRES TGC5B

examples/kv260/common/tgc5b/rtl/ct_tip_adapter.sv

yes — from the H2E port

no

yes

the only core on which it is reachable at all

CVA6

rtl/adapters/cva6/cva6_iti_to_ctte_tip.sv

no — dretire tied to 0

no

yes

no

Rocket

rtl/adapters/rocket/rocket_tci_to_ctte_tip.sv

no — dretire tied to 0

no

yes

no

AMD MicroBlaze™ V

rtl/adapters/amd_microblaze_v/mbv_to_ctte_tip.sv

no — dretire tied to 0

no

yes

no

+
+

Three consequences follow, and they are worth keeping apart.

+
+
+

ACT-ST works everywhere. It triggers on a retired instruction address and needs nothing beyond iaddr, which every one of the four adapters delivers.

+
+
+

Everything that needs the data channel works on the TGC5B only. That covers data trace, the data-flow range filter and the DAQ_DATA, DAQ_DADDR and DAQ_DATA_DADDR commands. On the other three cores those commands are not less precise — they carry no useful payload at all, because the encoder never receives a data beat.

+
+
+

No shipped core reports CSR writes, which is what ACT-CAP decodes (dretire && dtype == CSR_READ_WRITE && daddr == 0x0B10, rtl/preproc/ct_L23_preproc_act_cap.sv). The reason differs between the TGC5B and the rest: the TGC5B does decode the vendor CSR window 0xB10-0xB9F and raises no exception for it, but its H2E port derives dtype from the data bus alone (0 = load, 1 = store), so the write never reaches the trace port; on CVA6, Rocket and MicroBlaze™ V there is no store beat at all. For CVA6 in particular, RVFI is not an escape route: the wrapper ties its RVFI outputs off, and the CVA6 RVFI CSR structure is a fixed list of named architectural CSRs with no field for an arbitrary address/value pair.

+
+
+

Because the TGC5B adapter does see stores, an integration can close the gap locally: a store to a chosen doorbell address is converted into the CSR beat the encoder expects. That is an adapter-level change and needs no core change; examples/kv260/tgc5b2_rvcfi/rtl/ct_tip_adapter_actcap.sv builds exactly this, together with the doorbell in examples/kv260/tgc5b2_rvcfi/rtl/ct_soc_doorbell.sv.

+
+
+ + + + + +
+
Important
+		 +On the documented cores' native ingress ACT-CAP has consequently no silicon history; there its coverage comes from tests/lib/cpu_model.sv, which synthesizes the beat directly (scenario sim-hsi-csr-cap). The doorbell route above has been exercised on silicon: on 2026-08-26 the tgc5b2_rvcfi testbed ran doorbell-converted ACT-CAP commands on the KV260 with board verdicts (Chapter 28, and the details in Chapter 20). +
+
+
+
+
+

6.2. MINRES TGC

+
+

The MINRES TGC family (TGC5B in the shipped examples) drives the TIP natively — it was developed with a trace ingress port and needs no adapter.

+
+
+

The shared TGC5B building blocks live in examples/kv260/common/tgc5b/. That directory is not an example but the library eight KV260 examples build on: the vendored core, the AXI-Lite-to-Wishbone bridge, SoC RAM, CLINT and interrupt controller with their SystemRDL sources, and the hello_trace program. It carries its own SoC bench, which is the entry point that needs no board (make sim-tgc5b-soc). A two-core variant with the watchpoint and DAQ testbed is examples/kv260/tgc5b2_axis_wp/, board-gated on 2026-08-17 with 851 of 851 watchpoint records per core on the KV260 and a monotone cross-core merge. TGC5B is also one of the two cores in the duo funnel demonstrator.

+
+
+ + + + + +
+
Note
+		 +Some integration collateral for the TGC core is exchanged through partner and internal channels and is therefore not publicly linked from this documentation. +
+
+
+
+

6.3. Fraunhofer IPMS EMSA5

+
+

The EMSA5 core provides the instruction-trace ingress signals directly, plus the optional data-trace signals when data tracing is enabled in the system. The signal set, timing requirements and configuration rules are those of the TIP contract and apply unchanged; see the interface chapter.

+
+
+ + + + + +
+
Note
+		 +Some EMSA5 integration collateral and the corresponding internal repository links are not publicly accessible. +
+
+
+
+

6.4. CV32E4

+
+

The CV32E4 core family is not supported at present. The reason is not a property of the encoder: no TIP-compatible instruction-trace interface instance is currently available for it that meets the ingress requirements. Should such an instance become available, the integration follows the same pattern as the others — either a native TIP or a thin adapter.

+
+
+
+

6.5. CVA6

+
+

CVA6 is supported through the ingress adapter rtl/adapters/cva6/, and it is the most thoroughly characterized of the three: the CVA6 Instruction Trace Interface (ITI) truth table in doc/adapters/cva6_iti_semantics.adoc covers RV32, RV32 with Sv32 and S-mode, and RV64.

+
+
+
+ + + + + + + + + + +
+
+
+ CVA6 core +
+
+
+ + + CVA6 core + + + + + + + + + + + +
+
+
+ ITI +
+ instruction-trace interface +
+
+
+
+ + + ITI... + + + + + + + + + + + +
+
+
+ itype refinement +
+ from the instruction word +
+
+
+
+ + + itype refinement... + + + + + + + + + + + +
+
+
+ TIP ingress +
+ (encoder contract) +
+
+
+
+ + + TIP ingress... + + + + + + + + + + + + +
+
+
+ JALR rule table shared with the MicroBlaze V decoder -  one source of truth +
+
+
+ + + JALR rule table shared wit... + + + + + + + + + + + + +
+
+
+ retired +
+ instructions +
+
+
+
+ + + retired... + + + + + + + + + + + + +
+
+
+ itype + + codes 0 + +
+ + and 6 only + +
+
+
+
+ + + itype codes 0... + + + + + + + + + + + + +
+
+
+ call / +
+ return / +
+
+ co-routine swap +
+
+
+
+ + + call /... + + + + + + + + + + + + + + Text is not SVG - cannot display + + + + +
+
Figure 6. CVA6 adapter (ITI)
+
+
+

The core exports only itype codes 0 and 6; the adapter reconstructs calls and returns from the instruction word.

+
+
+

The JALR rule table is shared with the MicroBlaze™ V decoder.

+
+
+

6.5.1. Maturity

+
+

CVA6 is not a prospect. It runs.

+
+ ++++ + + + + + + + + + + + + + + + + + + + + + + + + +
EvidenceResult

Board run, KV260, 2026-08-18 (c-trace commit 2664bb5c, demonstrator pin cva6_linux_ctrace_kv260, bitstream 4dec7b54)

OpenSBI and Linux boot with tracing active; the captured stream decodes as 4 619 090 instructions with 0 error messages over the trace-encoder port. Raw artefact: decode.log of the run directory examples/kv260/cva6_linux/board/board_run_cva6_linux/ (local to the measurement host — run directories are excluded from the published tree) — 890 412 bytes, 117 543 messages, 7.58 bytes per message, 1.542 bits per instruction.

Characterization RV32 (cv32a60x, single retirement, 2026-07-24)

68 ITI beats against 68 RVFI retirements, 1:1.

Characterization RV32 + Sv32 + S-mode (cv32a6_ima_sv32_fpga, 2026-07-26)

104 retirements against 104 ITI beats, 1:1, including page faults.

Characterization RV64 (cv64a6_imac_sv39_ctrace, 2026-08-03)

106 retirements against 106 ITI beats, 1:1.

+
+

Further CVA6 material in the example tree: examples/kv260/cva6_linux64/ (RV64 Linux) and examples/kv260/cva6_2/ (an asymmetric double-CVA6 pair; bitstream flow migrated, board leg pending).

+
+
+
+

6.5.2. Measured ITI Beat Semantics

+
+

One ITI beat per event; iretire is constant 1 and is an instruction flag, not a halfword count — the halfword count lives in ilastsize, which is exactly the CTTE contract (the instruction count advances by 1 << ilastsize per beat with iretire = 1). Idle cycles carry no beat.

+
+ +++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
EventITI itypeNote

ALU, load, store, jal, CSR write, …​

0 STANDARD

jal is not classified as a call — the ITI’s detector only marks jalr as an uninferable discontinuity.

mret

3 ERET

 — 

Branch not taken

4 NON_TAKEN_BR

 — 

Branch taken

5 TAKEN_BR

 — 

jalr (call or return)

6 UNINF_JMP

Calls, returns and co-routine swaps are indistinguishable at the ITI.

ecall

1 EXC

Beat carries iretire = 1 — clamped by the adapter.

Illegal instruction

1 EXC

Beat carries iretire = 1; tval is 0 on RV32 and the instruction word on RV64.

Timer interrupt

2 INT

Beat carries iretire = 1; iaddr is the interrupted instruction.

+
+

Under Sv32 with S-mode, three additional cases were measured and matter for a kernel trace:

+
+
+
    +
  • +

    an instruction page fault beat carries the target virtual address, not the address of the jump that triggered it. That is the right information for a trace — execution would have continued there — but a consumer that reads iaddr as "PC of the retiring instruction" must know the case. The adapter forces iretire = 0, so the never-executed instruction never enters the instruction count.

    +
    • +
  • +

    tval carries the faulting virtual address on load, store and instruction page faults. It never reaches the N-Trace wire; in the E-Trace format it is visible, and it is the most valuable addition for a kernel trace.

    +
    • +
  • +

    the privilege change from M-mode to S-mode is visible in the beat and is passed through. The context or address-space identifier is a separate, optional path (see below).

    +
    • +
+
+
+

On RV64 the beat semantics are identical. Addresses and tval arrive as full 64-bit values. Not exercised: program counters with bit 31 or 63 set — they are not representable in the measurement window, so the ITI’s sign-extension behaviour above 231 remains an open point.

+
+
+
+

6.5.3. Adapter Behaviour

+
+

cva6_iti_to_ctte_tip is a thin shim, because the ITI vocabulary is the E-Trace chapter-4 vocabulary that the TIP also speaks: the 3-bit codes 0..6 are value-identical to the lower TIP codes and zero extension is the correct mapping. What the shim adds are the convention adjustments:

+
+
+
    +
  1. +

    Trap beats drive iretire = 0 (rule 1 above).

    +
    2. +
  2. +

    Idle cycles drive itype = OTHER and iretire = 0 (rule 2 above).

    +
    3. +
  3. +

    The exception cause carries the exception cause on an exception beat and the interrupt cause on an interrupt beat, both without the mcause most significant bit; otherwise the "no exception" sentinel.

    +
    4. +
  4. +

    Every unused TIP signal is explicitly tied off, so no undefined value can propagate into the encoder.

    +
    5. +
+
+
+

Width. The address ports follow the encoder netlist (ct_pkg::CT_XLEN); the ITI_XLEN parameter names the width of the core side and is checked against it at elaboration, for the reason given in rule 5 above.

+
+
+

Context (optional). ITI_CONTEXT_WIDTH defaults to 0, which is exactly the previous behaviour: the context is fixed at 0 and the encoder emits no ownership message. When a width is named, the context input carries the core’s context identifier — for RISC-V, satp.ASID — and the shim produces what the ownership contract needs.

+
+
+
+

6.5.4. itype Refinement

+
+

The ITI’s coarse classification is a limit of the interface, not of the adapter. Since 2026-08-09 the module cva6_riscv_itype_refine reconstructs the missing 4-bit codes from the instruction word, which the trace wrapper delivers cycle-exact with the ITI beat (both are registered from the same pipeline entry in the same clocked block). No modification of the vendored CVA6 tree is required for this.

+
+ ++++ + + + + + + + + + + + + + + + + + + + + + + + + +
AspectDetail

Switch

ITI_ITYPE_REFINE, default 0 = the previous behaviour, bit-identical.

Port

The instruction word input defaults to zero, and a runtime assertion fires if it is left unconnected while refinement is on — an all-zero word is not a legal RISC-V encoding, and a forgotten connection would otherwise be the most expensive kind of silent failure: folding would simply keep doing nothing.

Rules

Only ITI codes 0 (where jal hides) and 6 (the catch-all for every jalr) are refined, following the E-Trace JALR table: jal with a link destination becomes an inferable call; jalr with a link destination and a non-link source becomes an uninferable call; both link with equal registers, an uninferable call; both link with different registers, a co-routine swap; destination x0 with a link source, a return. The rule table is shared with the MicroBlaze™ V decoder — deliberately one source of truth, not two.

Link set

ITI_LINK_REG_MASK, default {x1, x5}. Clamped to {x1} where decoder conformance is required: the reference converter knows only x1 as a return base, and eight jr t0 divergences were measured across a complete OpenSBI-plus-Linux image.

+
+

Two operating pitfalls belong with this feature, both measured:

+
+
+
    +
  • +

    A disassembly listing generated with ABI register names makes the reference converter read every return as a call (its number parser accepts only xNN form) — measured as 17 calls and 0 returns on a call-dense test. Listings for implicit-return decoding must be generated with numeric register names and no aliases.

    +
    • +
  • +

    The reset default of the periodic synchronization maximum forces a full synchronization every 16 instructions and chokes call-dense runs. Implicit-return measurements run at a larger value.

    +
    • +
+
+
+

The end-to-end effect on a deliberately call-dense program (24 413 instructions, 3 200 calls and 3 200 returns) is worth quoting with its caveat:

+
+ ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
ConfigurationATB bytesMessagesBits per instruction

Refinement off, implicit return on (baseline)

27 560

3 433

9.031

Refinement on, implicit return on

2 092

248

0.686

Refinement on, implicit return off

27 560

3 433

9.031

+
+

The decoded PC sequence is identical in all three legs. Refinement alone changes nothing — the first and third legs are byte-identical — and only refinement together with implicit return produces the reduction. On this program that is 92.4 % fewer bytes, but the program is one call or return every 7.6 instructions and is not a general ratio: on a real board window of 883 577 instructions the same measurement gives 5.25 %.

+
+
+
+

6.5.5. Upstream Defects

+
+

Two defects in the pinned CVA6 tree had to be patched for the ITI to be usable at all, and both are candidates for upstream. Neither file ships with this repository: the reference core is pinned by commit and fetched (examples/kv260/third_party/fetch.sh, pin in CVA6_PIN.md), and the patches are applied to the fetched tree. The files are named here rather than the patch series' delta identifiers, because those identifiers are not unique — two of them denote different changes in the list and in the patch text, and the repository’s own pin document asks readers to cite the file.

+
+ ++++ + + + + + + + + + + + + + + + + +
File in the pinned treeDefect

core/cva6_rvfi.sv

The ITI valid signal is tied to the commit acknowledge, so exceptions and interrupts never reach the ITI at all — zero trap beats.

corev_apu/instr_tracing/ITI/cva6_iti/itype_detector.sv

The exception condition is checked before the interrupt condition while the exception-valid signal is also asserted on interrupts, so every interrupt is classified as an exception.

+
+

Two further configuration defects surfaced during the Sv32 gate, both previously invisible because the smaller configuration generates the MMU away: a direction-reversed subrange in the MMU at a 32-bit width, and an FPGA configuration whose address regions pointed at a different board so that the test memory was not executable.

+
+
+
+
+

6.6. MicroBlaze™ V

+
+

The AMD MicroBlaze™ V soft core is supported through the ingress adapter rtl/adapters/amd_microblaze_v/, which consumes the core’s TRACE bus. It is the core of the examples/kv260/mbv/ demonstrator and one of the two cores in the duo funnel demonstrator.

+
+
+
+
MicroBlaze™ V 
soft core
MicroBlaze™ V...
TRACE bus
proprietary, not version-stable
TRACE bus...
Bit-order normaliser
(VHDL-ascending ports)
Bit-order normaliser...
Retirement gate
iretire = valid AND NOT trap-entry
Retirement gate...
itype decode
from Trace_Instruction
itype decode...
TIP ingress
TIP ingress
Ghost-event hazard:
the bus holds PC and instruction
for ~2 cycles after retirement —
ungated, one mret becomes three events
Ghost-event hazard:...
Version fingerprint
mismatch = error, not a silent pass
Version fingerprint...
Trace_PC, 
Trace_Instruction, 
…
Trace_PC,...
iretire, iaddr
iretire, iaddr
itype, ilastsize
itype, ilastsize
the reason the gate exists
the reason the gate exists
checks the IP version
checks the IP versionText is not SVG - cannot display +
+
Figure 7. MicroBlaze™ V adapter (TRACE bus)
+
+
+

The TRACE bus is proprietary and not version-stable; every statement holds for the named IP and tool version only.

+
+
+

Ghost events: the bus holds PC and instruction for about two cycles after retirement. Without the gate, one mret is reported as three events and the decoder aborts.

+
+
+

Port names are the vendor’s; the semantics beside them are Accemic measurements.

+
+
+ + + + + +
+
Important
+		 +The TRACE bus is a proprietary, non-standardized and not version-stable interface. Every statement below holds for the named IP and tool version only, and must be re-measured on a version change. The adapter carries a version fingerprint; a mismatch at elaboration or run time is an error, not a silent pass. +
+
+
+ + + + + +
+
Note
+		 +Where the information in this section comes from. The port names and widths are those of the vendor’s own interface; the authoritative description is AMD’s MicroBlaze™ V product guide, which this manual references rather than reproduces. Everything under Measured Semantics below is Accemic’s own measurement on the delivered IP — behaviour the vendor documentation does not state — and is what the adapter had to be built against. +
+
+
+

6.6.1. Verified Configuration

+ ++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
ItemValue

IP

xilinx.com:ip:microblaze_riscv:1.0, Vivado™ 2026.1, CONFIG.C_TRACE = 1

Part

Kria™ KR260, xck26-sfvc784-2LV-c

Core

RV32, C extension off, M extension on, machine mode, MMU off, trace bus on, the core’s own native trace encoder off

Adapter

32-bit addresses and data, no compressed instructions, no data trace

Encoder

One-instruction-per-beat ingress, 32-bit addresses, history mode, combined data path, ATB output, reference decoder

+
+

Board status: gated on the KV260 on 2026-07-21/22 with 7 of 7 programs green on silicon — trace, branch, sequentially-inferable jump, trap, illegal instruction and misaligned access each with an exact reference prefix of 26.6 to 26.8 thousand program counters, plus an interrupt test with a hardware interrupt pulse generator. Re-gated from the consolidated example tree on 2026-08-17 with 26 772 of 26 772 program counters prefix-identical.

+
+
+
+

6.6.2. Confirmed Port List

+
+

The port list below was confirmed by block-design introspection on 2026-07-15 and corrects an earlier integration report that had been written from documentation.

+
+ ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
TRACE portWidthTIP fieldNote

Trace_PC

32

iaddr

All multi-bit TRACE ports are VHDL-ascending, so the adapter’s normalizer establishes the bit mapping explicitly.

Trace_Instruction

32

decoded into itype

Also the source of ilastsize for compressed instructions.

Trace_Valid_Instr

1

iretire, plus the trap rules

 — 

Trace_Jump_Taken

1

conditional-branch outcome

 — 

Trace_Exception_Taken

1

trap-entry flag

 — 

Trace_Exception_Kind

6

ecause

Bit 5 distinguishes an interrupt (1) from a synchronous exception (0); bits 4..0 carry the RISC-V cause directly. Measured: ecall = 0x0b, ebreak = 0x03, machine external interrupt = 0x2b.

Trace_OF_PipeRun, Trace_EX_PipeRun, Trace_MEM_PipeRun

1 each

 — 

Pipeline-stage run indicators. Diagnostic only.

Trace_Halted

1

 — 

Core halted for debug.

+
+

Two ports that the earlier report assumed do not exist on this IP version: a privilege-mode output and a process-identifier output. Consequently the privilege field is a constant machine mode and the context is 0 in this configuration. Should privilege or context tracing be needed, another source has to be found — instruction-decode of CSR accesses, or an IP configuration option.

+
+
+

The data-flow ports (Trace_Data_Access, Trace_Data_Address, Trace_Data_Read/_Write, Trace_Data_Write_Value, Trace_Data_Byte_Enable, Trace_Reg_Write, Trace_Reg_Addr, Trace_New_Reg_Value) exist but are not part of the supported configuration: the store value is directly derivable, the load value is not — the register-write port is ambiguous, so a full load trace would need a bus monitor.

+
+
+
+

6.6.3. Measured Semantics

+
+

The retirement and trap truth table was established in eight measurement rounds. Four findings shape the adapter:

+
+
+

Retirement and traps. iretire is the valid-instruction flag minus trap entries. A trap entry maps to an interrupt or an exception according to bit 5 of the cause port and carries iretire = 0; mret and sret map to a trap return and do retire. Both branches are confirmed across rounds covering six causes and 69 interrupt events.

+
+
+

Pipeline-run signals are not retirement signals. In a full-cycle measurement the operand-fetch run indicator was low for 26.8 % of cycles (295 single-cycle fetch stalls), while the execute and memory indicators stayed constant. Decisively, a valid instruction was signalled 68 times while the fetch indicator was low. These signals are usable as a debug sideband and must never enter the retirement path.

+
+
+

Trap entry never collides with a taken branch. In 69 interrupt events, the trap flag and the jump-taken flag never occurred together — a preempted branch does not resolve. The adapter still implements the priority defensively, but it is uncontested in hardware.

+
+
+

The trace bus holds its value after a retirement — the ghost-event finding. Measured at an mret: the program counter and the instruction word stayed stable for about two further cycles after the retirement while the valid flag was already low. Those cycles describe nothing. Because the encoder evaluates itype without an iretire gate, an ungated adapter reports one mret as three events, the message stream derails and the decoder aborts. This is rule 2 above, and it is where the rule came from.

+
+
+ + + + + +
+
Note
+		 +The adapter’s own unit testbench had let this defect through. Its idle-cycle vector used a nop, which decodes to OTHER anyway — green without checking anything. An idle-cycle vector needs a control-flow word sitting on the bus, which is the constellation that actually occurs. +
+
+
+
+

6.6.4. itype Decoding

+
+

The classification priority is: reset or idle, then trap entry, then trap return (mret/sret by instruction decode), then conditional branch (taken or not, from the jump-taken flag), then jal, then jalr, then everything else. The jal and jalr rules follow the standard link-register conventions — a jal with a link destination is an inferable call, a jalr resolves to an uninferable call, a return or a co-routine swap depending on the destination and source register relationship.

+
+
+

The non-trap rules are captured as a reference vector set: doc/adapters/itype_decoder_vectors.csv is the source data for the decoder testbench’s vector file. It covers all six conditional branches in both outcomes, jal with destinations x0, x1, x5 and x8, the full jalr matrix including the co-routine-swap case, mret and sret, and two non-control instructions — 32 vectors in all, each naming the encoding, the expected itype and the expected ilastsize.

+
+
+

ilastsize is constant in the supported configuration (no compressed instructions). For a build with compressed instructions the rule was measured and is available directly from the instruction word’s low two bits — the trace bus carries the original compressed encoding, which was the open risk of that gate and is now resolved.

+
+
+
+

6.6.5. Sequentially Inferable Jumps

+
+

The adapter implements the sequentially-inferable-jump idea as an optional promotion: a jalr whose target is statically computable from an immediately preceding auipc or lui is folded, and the pair is detected in the retirement stream. The switch is sijump_en, default 0 = the previous behaviour, byte-identical. It is a paired convention: the static side of the decoder must be told to pair the same way, and the encoder advertises the convention in its configuration message through the CT_SIJUMP instance parameter (Chapter 5). The committed demonstrator configuration runs with the promotion off.

+
+
+
+
+

6.7. Rocket

+
+

The Rocket core is supported through the ingress adapter rtl/adapters/rocket/, which consumes the rocket-chip TraceCoreInterface. Example designs are examples/kv260/rocket_linux/ and examples/kv260/rocket2/ (RV64, two-hart SMP Linux); both have their bitstream flows migrated with the board leg still pending.

+
+
+
+ + + + + + + + + + +
+
+
+ Rocket core +
+ (rocket-chip generator) +
+
+
+ + + Rocket core... + + + + + + + + + + + +
+
+
+ Trace port +
+
+
+ + + Trace port + + + + + + + + + + + +
+
+
+ Signal mapping +
+ to the TIP contract +
+
+
+ + + Signal mapping... + + + + + + + + + + + +
+
+
+ TIP ingress +
+
+
+ + + TIP ingress + + + + + + + + + + + + +
+
+
+ retired +
+ instructions +
+
+
+
+ + + retired... + + + + + + + + + + + + + + + + + + Text is not SVG - cannot display + + + + +
+
Figure 8. Rocket adapter (TCI semantics)
+
+
+

The simplest of the three adapters: signal mapping only, no reconstruction.

+
+
+

The truth table in doc/adapters/rocket_tci_semantics.adoc was measured against the generated netlist standalone — without the encoder and without the adapter — so that the interface’s behaviour and the adapter’s compensation for it stay separable.

+
+
+

6.7.1. Measured Semantics

+
+

The interface is a combinational tap of the writeback stage with one retirement per cycle. Three properties are decisive:

+
+
+

Trap beats retire. iretire is tied to the writeback valid signal, which includes the exception case, so all trap beats carry iretire = 1. The adapter’s clamp to 0 is therefore mandatory.

+
+
+

Trap returns are classified as ordinary returns. Every mret beat carries the return code rather than the trap-return code, and that code appears only at mret program counters — jalr returns carry a different code. The adapter’s remap is therefore unambiguous and lossless, and it is enabled by default.

+
+
+

Idle cycles are not neutral. The classification holds the decode of the last instruction while iretire is low. In a 432-cycle characterization run this produced 161 hanging classification lines — 37 taken branches, 71 uninferable and 53 inferable jumps. A consumer must gate the classification with iretire; Rocket’s own encoder chain does exactly that internally. Not a single hanging beat carried a trap classification, so the clamp swallows no traps.

+
+
+

Further measured properties: the privilege field is constant machine mode in the characterized configuration, with the debug flag not exercised; the time field is the free-running CSR cycle counter (measured ratio exactly 1.0 against the cycle count), not the platform timer, which ticks a hundred times slower; and there is no context port at all on this netlist — the address-space-identifier path that an earlier report assumed does not exist at this pin’s interface export.

+
+
+

ilastsize distinguishes compressed from 32-bit encodings and was measured against the disassembly’s encoding length over 10 compressed and 94 full-width retirements with zero errors.

+
+
+
+

6.7.2. Upstream Defects

+ +++++ + + + + + + + + + + + + + + + + + + + + + + + + +
#DefectConsequence

U1

Trap beats carry iretire = 1.

The adapter’s clamp is mandatory; without it the encoder counts the faulting instruction.

U2

A trap return is classified as an ordinary return rather than as a trap return.

The adapter’s remap is unambiguous and lossless, and covers sret and dret as well, because the underlying condition is the CSR decode of any trap-return instruction.

U3

The trace cause is taken from a memory-stage multiplexer whenever the writeback exception flag is low. For traps the CSR raises internally — ecall and ebreak — the beat therefore carries a data-path leftover value instead of the architectural cause. Illegal instructions (correct cause and the instruction word in tval) and interrupts are unaffected.

The cause field is not trustworthy for ecall and ebreak, and the adapter cannot fix it: the interface carries no discriminating information. The N-Trace wire is unaffected, since the cause never leaves the encoder; a consumer of the E-Trace trap format must know the case.

+
+

The defect was confirmed structurally rather than only observationally: the CSR raises those two traps internally, and the value list of the trace-cause multiplexer does not contain the architectural codes at all — the defect sits exclusively in the trace path.

+
+
+
+

6.7.3. Adapter Behaviour

+
+

The Rocket adapter maps the interface’s 4-bit instruction type to the TIP type one to one; the TIP enum already carries the full E-Trace vocabulary that the interface follows. Only two clamps are active: trap beats forced to non-retiring, and the trap-return remap. The 3-bit down-mapping that an early design note proposed does not apply — it targeted the 3-bit ITI vocabulary, not the 4-bit interface.

+
+
+

The characterization run had to redirect the platform’s boot ROM, because the reset vector jumps into an SD-card bootloader that is a dead path in simulation. This is done by compiling a work-local netlist copy with one patched ROM word, which is simulator-independent; a conditional force on the ROM data bus did not take effect under the simulator used. The vendored file itself stays untouched, and the same patched image is the oracle basis.

+
+
+
+
+

6.8. Multi-Core and Mixed-Protocol Integration

+
+

Several harts share one trace port through the funnel (Chapter 11). The shipped demonstrators are:

+
+ +++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
ExampleCoresStatus

examples/kv260/duo/

MicroBlaze™ V + TGC5B

Board-gated 2026-08-18: both streams decoded on the KV260, WNS +2.188 ns.

examples/kv260/trio/

MicroBlaze™ V + TGC5B + CVA6

Adds the per-instance protocol mix — a Nexus stream next to an E-Trace reference-raw stream in one merged container, with the demultiplexing tool vendored. Board leg pending.

examples/kv260/cva6_2/

Two CVA6 harts (RV32 and RV64 scenarios)

Bitstream flow migrated, board leg pending.

examples/kv260/rocket2/

Two Rocket harts, SMP Linux

Bitstream flow migrated, board leg pending.

+
+

The trio design is also where the funnel’s per-channel arbitration priority becomes software-visible, through a SoC-level register (Chapter 11).

+
+
+
+

6.9. Peripherals

+
+

6.9.1. Bus Trace

+
+

Not implemented. References for the intended scope:

+
+
+
    +
  • +

    AMBA™ AHB Trace Macrocell (HTM) Technical Reference Manual, revision r0p4 (Arm DDI0328E)

    +
    • +
  • +

    Gaisler GRLIB IP Core User’s Manual (GRIP): AHB trace buffer (p. 94)

    +
    • +
+
+
+
+

6.9.2. DDR4 Trace

+
+

Not implemented. The intended functional scope is: transaction address; transaction attributes (direction, speculative read, read-modify-write, row state); forced page closings due to bank and sub-bank collisions, counted in total and excluding refresh-caused closings; and refresh events.

+
+
+
+
+
+
+

7. Preprocessor Stage

+
+
+

7.1. Overview

+
+

The layer 2/3 preprocessor (ct_L23_preproc, rtl/ct_L23_preproc.sv) is the front end of the encoder. It runs in the tip_clk domain, observes the core’s retirement stream, and turns it into the internal extended TIP (eTIP) event stream plus the AXI-Stream instrumentation output. Both trace back ends — N-Trace and E-Trace — consume the same eTIP stream (Chapter 5), so everything in this chapter is protocol-agnostic.

+
+
+

Its tasks are:

+
+
+
    +
  • +

    observe the TIP retire events (tip.iretire, tip.dretire) and the associated context: program counter, data address, data, privilege and trap state;

    +
    • +
  • +

    derive the next program counter for control-flow discontinuities;

    +
    • +
  • +

    qualify retire cycles into control-flow (CF) and data-flow (DF) hits through a comparator/filter engine and address range searches;

    +
    • +
  • +

    generate periodic, event-driven and requested synchronization reasons;

    +
    • +
  • +

    pre-aggregate performance statistics;

    +
    • +
  • +

    decode and synthesize instrumentation commands (ACT-CAP, ACT-ST, ACT-Proc);

    +
    • +
  • +

    select and provide the timestamp;

    +
    • +
  • +

    compose the time-aligned CF/DF/DAQ sub-messages into the eTIP stream and cross it into proc_clk.

    +
    • +
+
+
+

All blocks are fully synchronous to tip_clk. State transitions occur exclusively on its rising edge; no internally derived clocks are used. Where another clock is involved — wall-clock counting, the crossing into proc_clk, or the write side of a configuration memory — explicit CDC modules and dual-clock FIFOs are instantiated.

+
+
+
+

7.2. Determinism and Path Alignment

+
+

Determinism is guaranteed for a given TIP input sequence and configuration register state: identical inputs produce identical outputs, cycle-accurately. There is no hidden state, no randomization and no timing-dependent arbitration. Three design rules carry this property:

+
+
+

Retire-qualified emission. Anything that represents an architectural event is emitted only on a cycle that retires an instruction or a retired data access.

+
+
+

Reported fixed latency. Every block reports its intrinsic latency on an internal_delay output rather than documenting it in prose. Most blocks report one cycle (the register stage that captures the event); the blocks that contain a binary search report 1 + vbs_delay, and ACT-ST reports 2, including its match checker.

+
+
+

Computed alignment. ct_L23_preproc collects all internal_delay values, computes the maximum path delay, and derives each block’s extra_delay from it. Each block implements the same pattern — a shift pipeline of depth EXTRA_DELAY_MAX whose output is tapped at extra_delay — so an integrator changes alignment without re-timing any internal logic and without re-synthesis. The bound is ct_pkg::EXTRA_DELAY_MAX = ct_pkg::PREPROC_DELAY_MAX, which is 44 with the instrumentation feature compiled in (CT_EN_ACT = 1) and smaller otherwise.

+
+
+

There is a consequence of this alignment that is easy to get wrong, and the RTL calls it out explicitly: a control level must be sampled with the same delay as the beats it gates. The trace-enable levels are therefore staged through their own shift pipelines (ItaPipe for trTeEnable && trTeInstTracing, DtaPipe for trTeDataControl.DataTracing) and tapped at the delay of the TIP copy that the consuming stage sees, instead of being read live from the CSR interface. Qualifying delayed beats with the live level breaks in both directions, and both were measured on 2026-08-04 in tests/data/03_addr_compress:

+
+
+
    +
  • +

    at the off edge, an access that retired up to max_delay - 1 cycles before the edge is silently dropped — a traced access lost with no error indication;

    +
    • +
  • +

    at the on edge, an access that retired before the edge is emitted although data tracing was off at its retirement — a data-filter violation, and worse, it becomes the re-anchor point that the decoder subsequently computes differential addresses against.

    +
    • +
+
+
+

Both directions are gated by that test. Where a build profile compiles data tracing out, the staging registers are hard-gated to a constant rather than left for synthesis to trim.

+
+
+
+

7.3. Next Program Counter Evaluation

+
+

Many control-flow messages need an explicit target address. The TIP input carries the address of the retired instruction (iaddr) and does not always carry the target of a taken control-flow change, so the preprocessor derives the next PC:

+
+ ++++ + + + + + + + + + + + + + + + + + + + + + + + + +
CaseNext PC

Sequential retirement

iaddr + ilastsize, where ilastsize counts halfwords: 1 for a 16-bit instruction, 2 for a 32-bit instruction.

Direct PC-relative jump or call

Computable from the instruction encoding (offset immediate) and iaddr.

Not-taken conditional branch

iaddr + ilastsize.

Taken conditional branch, indirect jump, return

Not known at retirement. The next retired iaddr is the effective target; the preprocessor captures it as next_iaddr and forwards it on the companion stream next_iaddr_q.

+
+

Because next_iaddr becomes available one TIP cycle later, the encoder may have to buffer the discontinuity information briefly while independent trace elements — data retire events, for instance — continue to pass. The classification into inferable and uninferable PC discontinuities follows the itype and updiscon concepts of the RISC-V trace specifications; the per-core mapping of itype is described in Chapter 6.

+
+
+
+

7.4. Branch History Accumulation

+
+

In the history modes, conditional-branch outcomes are accumulated into the HIST field until either the buffer is full or a synchronization boundary forces emission. Overflow is signalled with a ResourceFull message rather than silently truncated, which bounds the decoder’s state error (see Chapter 8). The compression schemes that operate on the accumulated history — repeated history, repeat-branch, branch prediction — are described in Chapter 9.

+
+
+
+

7.5. Synchronization Generator

+
+

Module: ct_L23_preproc_sync (rtl/preproc/ct_L23_preproc_sync.sv).

+
+
+

The generator produces a synchronization reason (nexus_sync_reason_e) that the eTIP composer later injects into the stream and that the formatter maps into the SYNC field of a synchronizing message. Sync generation is retire-qualified: a reason is only produced on a cycle with tip.iretire, so synchronization aligns to an architectural boundary.

+
+ + ++++ + + + + + + + + + + + + + + + + + + + + +
Table 3. Sources of a synchronization request
SourceDescription

Periodic counters

Programmable counters over cycles, retired instructions, retired halfwords, wall-clock ticks, and the trace-output quota (emitted bytes or messages).

One-shot on reset exit

The first retired instruction after reset deassertion emits a non-periodic "exit from system reset" reason, then arms the periodic generator.

External request

The ATB synchronization request input, and the register field trTeControl.InstSyncReq. Each has its own lock/acknowledge handshake, and both are emitted as the explicit-request code.

+
+

All counters share one overflow threshold derived from a CSR field as 1 << (trTeInstSyncMax + 4) and run in saturation mode. The cycle counter increments every tip_clk, the instruction counter on tip.iretire, the halfword counter by tip.ilastsize at retirement, and the wall-clock counter in its own clock domain with CDC for its overflow and clear. The counter width is ct_pkg::SYNCCNT_WIDTH = 21, chosen to exceed the maximum trTeInstSyncMax plus four.

+
+
+

The trace-output quota deserves a note: the byte and message counters do not live here but in the L2 egress modules, because only there is it known what actually left the encoder. Their held overflow levels are crossed back into the preprocessor as synq_req_trace_byte_count / synq_req_trace_msg_count, and the rearm (SyncCntClr) is crossed forward as quota_cnt_clr (Chapter 5).

+
+
+

When a condition matches, SyncCntClr clears all counters and rearms them for the next period. After a sync, the design waits for all involved overflow flags to deassert before accepting new triggers, so a lingering overflow cannot immediately retrigger. If several conditions coincide, exactly one synchronization message is emitted per cycle, with a priority fixed in the RTL.

+
+
+

7.5.1. Request Pacing

+
+

The register-based sync request (trTeControl.InstSyncReq) is a self-clearing field, i.e. a one-cycle pulse — and a pulse is the wrong thing to hand to a clock-domain crossing: two pulses closer together than one destination clock period cancel in a toggle synchronizer and both requests are lost. ct_sync_req_pacer (rtl/pkg/ct_sync_req_pacer.sv) solves this by pacing:

+
+
+
    +
  • +

    a request is raised only while no other one is outstanding;

    +
    • +
  • +

    the consumer acknowledges when it has served the request;

    +
    • +
  • +

    two requests are therefore always a full round trip apart, which is what makes the crossing lossless.

    +
    • +
+
+
+

The depth is one plus one. A write that arrives while a request is outstanding is not dropped but remembered in a queued slot and raised the moment the handshake closes, so it becomes its own request and gets its own synchronization message. Only a write arriving while a request is already queued collapses into that queued one — it asks for exactly what is about to be asked for anyway.

+
+
+

What crosses the domain boundary is a level, not a strobe. An earlier version paced strobes across two toggle synchronizers, which is not survivable here: the two halves of one request live in two reset domains — the launch side in wb_rst, the pending latch in the consumer in tip_rst — and ct_encoder carries both as independent inputs. A consumer reset would then clear the pending latch without an acknowledgement while the strobe that carried the request is long gone; the request is silently lost, and depending on how the two toggle pairs come out of reset the launch side can be left waiting for an acknowledgement that never arrives.

+
+
+
+
+

7.6. TIP Delay

+
+

Module: ct_L23_preproc_tip_delay (rtl/preproc/ct_L23_preproc_tip_delay.sv).

+
+
+

This stage provides a configurable pipeline delay for the entire TIP context, so that downstream stages can be time-aligned without re-timing their internal logic. Every TIP field is delayed uniformly — timestamp, instruction and data retire qualifiers, addresses, sizes, data payload and context — so that a consumer always observes a self-consistent snapshot of one original cycle. The module does not alter semantics and generates no events; it re-times the stream and reports its intrinsic latency of one cycle.

+
+
+

The instance provides two independently tapped delayed outputs from one shared shift register: ct_L23_preproc uses tip_delayed_composer for the AXIS and eTIP composers and tip_delayed_cfdf for the control-flow and data-flow stages, since those two groups sit at different points of the alignment tree. On reset every pipeline stage is cleared, so no spurious event can appear after start-up.

+
+
+
+

7.7. Comparator and Filter Engine

+
+

Module: ct_L23_preproc_comp_filters (rtl/preproc/ct_L23_preproc_comp_filters.sv).

+
+
+

One shared engine evaluates up to NUM_TRACE_FILTER filter entries per cycle and produces the consolidated hits for both the instruction and the data path (cf_filter, df_filter). It follows the filter and comparator model of the RISC-V trace control interface.

+
+
+

Comparators. Each comparator selects a primary and a secondary 32-bit operand from the TIP fields (iaddr, context, tval, daddr) and evaluates a configurable comparison function: equal, not equal, greater or equal, less or equal, greater, less, always true, always false. Four match modes combine the two results:

+
+ ++++ + + + + + + + + + + + + + + + + + + + + + + + + +
ModeMeaning

0

Primary result true.

1

Primary AND secondary true.

2

NOT (primary AND secondary).

3

Latched: set on the primary result, cleared on the secondary result after retirement.

+
+

Mode 3 latches are synchronized to retire boundaries (tip.iretire or tip.dretire) so a latch cannot open or close on a pipeline bubble.

+
+
+

Per-filter predicates. Beyond the comparators, each filter is gated by its enable bit, a privilege bitmap, data-type and data-size selectors, and the comparator selection mask. If the filter selection mask is zero, tracing is unconditional — the "trace all" policy of the specification.

+
+
+

Trap windows. Two window predicates implement the trap-scoped filtering of the Trace Control Interface specification, section 6.3, Table 24: "start matching from the exception or interrupt, stop matching upon return from the first matching trap". The obvious counter implementation cannot do this correctly, because the return-from-exception indication carries no information about which trap is returning: with a nested non-matching trap inside a matching one, a plain counter decrements on the wrong return, closes the window early, and then underflows on the real return.

+
+
+

The implementation therefore does not use a plain counter but a stack with a match marker: the depth is tracked in a shift register whose marker bits record which entries matched the filter, so a return can be attributed to the correct trap. Overflow and underflow are detected (hot start, attaching to a running system) and checked by simulation assertions. Saturating counters track the window depth for the CSR view.

+
+
+ + + + + +
+
Note
+		 +The predecessor manual carried a design note describing the counter-based limitation as an accepted approximation of the specification. That note is superseded: the stack-based implementation resolves the nesting case it described. The remaining bound is the stack depth, ct_pkg::EXCEPTION_STACK_DEPTH. +
+
+
+
+

7.8. Control-Flow Qualifier

+
+

Module: ct_L23_preproc_cf (rtl/preproc/ct_L23_preproc_cf.sv).

+
+
+

For each retire cycle, the stage consumes the filter engine’s instruction-side hit, performs a binary search over the configured instruction address ranges, and produces:

+
+
+
    +
  • +

    cf_hit — the qualified control-flow hit that the eTIP composer uses to emit control-flow messages,

    +
    • +
  • +

    cf_region_entered / cf_region_exited — region transitions, and the region index.

    +
    • +
+
+
+

A region entry is asserted when the winning range index changes relative to the last valid one; an exit is asserted on a no-hit or on entry into a different region. The last valid index is updated only on hit cycles, which is what prevents spurious toggling on bubbles. The stage also supplies the conditional-branch outcomes that are accumulated into the HIST field in the history modes. Outputs are registered and pass through the shared extra_delay tap.

+
+
+
+

7.9. Data-Flow Qualifier and Range Filter

+
+

Modules: ct_L23_preproc_df and ct_L23_preproc_df_range (rtl/preproc/).

+
+
+

ct_L23_preproc_df_range performs the range lookup on the retired data address. On every cycle with tip.dretire it looks tip.daddr up in a programmable range set using vector_binary_search_2clk in RANGE mode; the range memory is populated through a separate write interface (df_range_wext) in the wb_clk domain. The tree depth parameter DIM (default 4) bounds the number of ranges at 2^DIM - 1, i.e. 15 ranges at the default. Throughput is one lookup per cycle after pipeline fill; the reported latency is 1 + vbs_delay, plus the configured extra_delay.

+
+
+

ct_L23_preproc_df consolidates the results. A data-flow event is qualified by tip.dretire, the aligned data-tracing level (see above), and a data type of LOAD or STORE; the filter hit and the range hit are then combined into the single df_hit output. Its intrinsic latency is one cycle before the delay tap.

+
+
+ + + + + +
+
Note
+		 +The header comment of ct_L23_preproc_df_range.sv refers to instruction addresses in a few places for historical reasons. The implementation operates on tip.daddr / tip.dretire; the description here follows the implementation. +
+
+
+
+

7.10. Timestamp Unit

+
+

Module: ct_L23_preproc_ts (rtl/preproc/ct_L23_preproc_ts.sv).

+
+
+

The timestamp unit provides the value that messages carry in their TSTAMP field, selected by the trTsControl CSR:

+
+ ++++ + + + + + + + + + + + + + + + + + + + + +
SelectionSource

TR_TS_NONE

Zero.

TR_TS_SYSTEM

A free-running internal counter in the tip_clk domain, prescaled.

TR_TS_CORE

Pass-through of tip._time from the core.

+
+

trTsActive is the primary enable of the counter, trTsCount runs and stops it, trTsReset resets it synchronously, and trTsPrescale divides by 2^(2n), i.e. 1, 4, 16 or 64. The counter width is ct_pkg::CT_TS_WIDTH = 64. Where a build profile compiles the timestamp unit out (CT_EN_TIMESTAMP = 0), the TSTAMP fields disappear from the wire and the trTs* registers read as zero rather than reporting a unit that is not there.

+
+
+
+

7.11. Performance Counters

+
+

Module: ct_L23_preproc_perfcnt (rtl/preproc/ct_L23_preproc_perfcnt.sv), with perfcnt_range_unit as the reusable range classifier.

+
+
+

The performance counter block pre-aggregates statistics in hardware so that they do not have to be reconstructed from the trace stream. It observes three access classes independently — data reads, data writes and instruction fetches — and maintains separate counter banks for plain events and for threshold-qualified events.

+
+
+

Range classification. For each class the retired address is compared against a vector of ranges, producing a one-hot hit plus a no-hit flag. The counter of the matching range increments on a hit; a dedicated no-hit counter increments when the access falls outside every configured range, so the total is conserved and a mis-configured range set is visible rather than silent. All counters saturate; they never wrap. Clearing is per bank and per source, so software can snapshot and reset one class without disturbing the others.

+
+
+

Threshold measurement. In addition to event counts, the block measures per-event latency in cycles. Small state machines accumulate the cycles between key retire events and raise an overflow when an 8-bit threshold (ct_pkg::PERFCNT_TH_WIDTH = 8) rolls over, which qualifies a thresholded count update on the next matching retire. Separate paths exist for instruction-fetch and data-read thresholding, each gated by its own threshold value and aligned to the corresponding retire signal so that one event window cannot produce several updates.

+
+
+

Uniformity. The range classification is not re-implemented per class: perfcnt_range_unit wraps vector_range_checker and is instantiated per access class and per thresholded variant, which gives identical behaviour and identical latency on all measurement paths and keeps timing closure to a single EXTRA_DELAY parameter.

+
+
+

Counter width is ct_pkg::PERFCNT_WIDTH = 32. Updates are strictly retire-qualified and registered; the block reports a fixed internal latency of one cycle.

+
+
+
+

7.12. Instrumentation: ACT-CAP, ACT-ST, ACT-Proc

+
+

The instrumentation path is described in full in the features part of this manual; this section covers only what the preprocessor contributes.

+
+
+

7.12.1. ACT-CAP

+
+

Module: ct_L23_preproc_act_cap (rtl/preproc/ct_L23_preproc_act_cap.sv).

+
+
+

ACT-CAP — the Accemic CEDARtools CSR Access Protocol — lets the encoder observe CPU writes to designated virtual CSRs through the TIP, without any modification to the core: such CSR writes are functional no-ops with no system-bus side effects, and only the trace encoder reacts to them. To address many virtual control registers, ACT-CAP uses a two-stage access: a target register index is written to a selector CSR, then the selected register is written through a second CSR access.

+
+
+

The module filters retired CSR read-write transactions for the ACT-CAP command address, captures the command fields, and asserts a one-cycle valid strobe that advances through the shared extra_delay shift pipeline. Relative command ordering is preserved. Writes to other CSR addresses are ignored; on reset the whole valid pipeline is cleared so no spurious command can escape. Intrinsic latency is one cycle.

+
+
+
+

7.12.2. ACT-ST

+
+

Module: ct_L23_preproc_act_st (rtl/preproc/ct_L23_preproc_act_st.sv).

+
+
+

ACT-ST — the Accemic CEDARtools Smart Trigger — extends ACT-CAP by generating the same virtual operations from hardware when a preconfigured runtime event occurs, with no CPU involvement at all. The supported trigger conditions are a match of a retired instruction address and a match of a configured interrupt identifier.

+
+
+

The retired instruction address is compared against an array of key addresses with vector_binary_search; on a match the associated command word is fetched from the control/status memory and injected into the alignment pipeline, formatted exactly like an ACT-CAP CSR write so that everything downstream is unaware of the difference. Several trigger addresses are monitored in parallel; multiple matches are serialized by the pipeline with their order preserved. The key/command memory is written through act_st_wext in the wb_clk domain. Intrinsic latency is fixed at 2 cycles, including the match checker.

+
+
+
+

7.12.3. ACT-Proc

+
+

Module: ct_L23_preproc_act_proc (rtl/preproc/ct_L23_preproc_act_proc.sv).

+
+
+

ACT-Proc merges the two command sources into one ordered stream and executes the side effects. Priority is fixed: ACT-ST overrides ACT-CAP when both are valid in the same retired instruction, which neutralizes the software-inserted instrumentation in favour of the hardware trigger.

+
+
+

Depending on the command encoding, the processor can:

+
+
+
    +
  • +

    emit a configurable DAQ message,

    +
    • +
  • +

    request an extra synchronization message,

    +
    • +
  • +

    perform writes to selected trace-encoder CSRs through the tip_clk-domain control interface — including setting and clearing the instruction and data trace enables, which is how tracing can be activated dynamically without CPU involvement.

    +
    • +
+
+
+

Temporal ordering as observed at the TIP is preserved; no reordering of trace-relevant events takes place. The added latency is fixed and bounded, does not depend on runtime data values or message types, and is documented in the module header of the RTL file. Downstream backpressure may delay emission but never changes ordering.

+
+
+
+
+

7.13. AXIS Composer

+
+

Module: ct_L23_preproc_composer_axis (rtl/preproc/ct_L23_preproc_composer_axis.sv).

+
+
+

The AXIS composer converts selected ACT-CAP/ACT-ST DAQ commands into wide AXI-Stream payloads — an internal trace and instrumentation sink that bypasses the trace format entirely, for example toward a watchdog CPU. It samples the most recent retired instruction and data context (addresses, data, type and size) and, when a valid ACT command targets the AXIS sink, asserts tvalid for one cycle and fills the data elements according to the command opcode: current PC; PC plus the last PC before an exception; immediate data from the command; last retired data with size and type; last data address; or combinations of these.

+
+
+

For commands that request performance statistics, the composer reads the addressed counter through the perfcnt interface, places it into the first element and atomically asserts the matching clear bit, giving read-and-clear semantics without a software race.

+
+
+

Framing: one AXI beat of TDATA_WIDTH = ct_pkg::ACT_CAP_AXIS_TDATA_WIDTH bits, carrying MAX_DAQ_DATA_ELEMENTS = 3 elements of ACT_CAP_INT_ELEMENT_WIDTH = 32 bits; tstrb marks which element slots the issued command actually filled, and tid carries a command-derived identifier. The path from command acceptance to AXI emission is single-cycle and applies no backpressure — the producer must throttle the ACT DAQ rate if the sink cannot drain the stream in time.

+
+
+
+

7.14. eTIP Composer

+
+

Module: ct_L23_preproc_composer_etip (rtl/preproc/ct_L23_preproc_composer_etip.sv).

+
+
+

The eTIP composer is the last stage of the preprocessor and the widest one. It collects the time-aligned CF, DF and DAQ sub-messages, stamps them with a common context, and serializes them through a FIFO into the proc_clk domain.

+
+
+

Sub-message capture. On each cycle the composer samples the CF hit together with an instruction-count accumulation that behaves like the Nexus I-CNT field (retired instruction halfwords), the DF hit with its data-side payload and size/type, and any DAQ command output, into one parallel composite record with per-slot validity bits and a shared timestamp and I-CNT snapshot. If a synchronization reason is pending, an I-Sync sub-message is injected and the instruction counter is reset, so subsequent distances are measured from the new synchronization point.

+
+
+

I-CNT pre-drain. The accumulator is drained before it can exceed the field width: the pre-drain fires when the accumulated halfword count plus the current beat’s halfwords reaches 2^NEXUS_MSG_I_CNT_WIDTH and then restarts the accumulator at this beat’s halfwords. This is only sound while a single beat stays below the threshold, which is exactly why the block-ingress width is bounded at elaboration (Chapter 5, genBadIretireWidth): a beat that alone reached the threshold would leave the accumulator above it and wedge the downstream history hold.

+
+
+

Implicit-return stack. The composer maintains the return-address stack used by the implicit-return compression scheme: a call pushes the address after the call site, a return pops it, and a return whose actual target equals the predicted one needs no target on the wire. The depth is ct_pkg::CT_RET_STACK_DEPTH = 16. The stack is cleared at a trace pause edge and is not modified by a gap re-anchor — both properties are checked by simulation assertions, because a stale stack entry would make a later return "implicit" against a frame the decoder does not have, and the decoder would then pop the wrong address. The scheme itself is described in Chapter 9.

+
+
+

Serialization and CDC. The composite vector is written into a compact-vector FIFO and then crossed into proc_clk. The read side emits at most one sub-message per beat, prioritizing CF, then DF, then DAQ, so the parallel per-cycle record is flattened into a serial stream with per-cycle ordering preserved. ct_pkg::ETIP_SLOT_SITES = 13 slot sites feed the record; the FIFO depth is ETIP_CVS_FIFO_DEPTH (128 when data trace, ACT or DAQ is built, else 32) and the CDC stage depth is ETIP_CDC_FIFO_DEPTH.

+
+
+

Two structural options affect this stage and are the main footprint levers of the preprocessor:

+
+
+
    +
  • +

    CT_ETIP_SERIALIZE presents eTIP slots one per cycle through a small skid queue instead of in parallel, so the FIFO stores one entry per slot rather than one per slot and parallel site. Message order, per-message timestamps and the resulting byte stream are unchanged.

    +
    • +
  • +

    CT_EN_FIFO_HIST adds a fill-level histogram over the composer FIFO — see Chapter 10, where the readout is described.

    +
    • +
+
+
+

Flush. An ATB flush request, or a trace-off, raises do_flush. This is emitted as a standalone flush eTIP element even when the core is idle and no further tip.iretire arrives, so a flush can always terminate message composition cleanly (Chapter 5).

+
+
+

Trace-off correlation. When tracing is paused, a correlation message has to be pushed out before the pipeline goes quiet, and the implicit-return stack is cleared at the same edge; an assertion checks that the stack is indeed empty at the pause edge.

+
+
+
+

7.15. Interfaces Between the Blocks

+
+

The preprocessor uses SystemVerilog interfaces rather than flat signal bundles, which is what keeps the alignment scheme uniform:

+
+ ++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
InterfaceUse

tip_if

The TIP context, also used for the two delayed copies tip_delayed_composer and tip_delayed_cfdf.

ct_hit_if

Hit/valid pairs from the filter engine and the qualifiers (cf_filter, df_filter, df_range, cf_qualifier, df_qualifier).

ct_sync_if

The synchronization reason.

ct_act_cap_if

ACT command streams (act_cap, act_st, and the merged act_cap_st).

ct_perfcnt_if

Counter values and their clear controls.

ct_cs_tipclk_if

The tip_clk-domain view of the control/status registers.

ocram_write_if

Write ports for the ACT-ST key/command memory and the DF range memory, in the wb_clk domain.

source_if

The outgoing eTIP streams etip_q and next_iaddr_q, in the proc_clk domain.

+
+
+
+
+

8. Processing Stage

+
+
+

8.1. Overview

+
+

The processing stage runs in the proc_clk domain and turns the protocol-agnostic eTIP event stream into protocol messages. Which generator is built is a synthesis choice (Chapter 5):

+
+
+
    +
  • +

    ct_L2_msg_gen produces generic trace messages for the N-Trace back end, which ct_L2_nexus_formatter then expands into a Nexus field list;

    +
    • +
  • +

    ct_L2_te_inst_gen produces E-Trace te_inst packets directly.

    +
    • +
+
+
+

Both consume the same two streams from the preprocessor: etip_q, carrying the eTIP elements with their sub-type (CF, DF, DAQ, other) and payload, and next_iaddr_q, supplying the next instruction address whenever the control-flow type requires an explicit target (Chapter 7).

+
+
+

This chapter describes message construction. The compression schemes that decide which message is emitted — and which is suppressed — are the subject of Chapter 9; the complete list of TCODEs and their fields belongs to the message catalog.

+
+
+
+

8.2. Generic Message Generator

+
+

Module: ct_L2_msg_gen (rtl/ct_L2_msg_gen.sv).

+
+
+

For each non-empty eTIP element the generator produces one or more generic trace messages (nexus::nexus_msg_struct_t) by

+
+
+
    +
  • +

    selecting the TCODE,

    +
    • +
  • +

    mapping the eTIP fields into the generic CF, DF or DAQ sub-structures,

    +
    • +
  • +

    maintaining the accumulator state (I-CNT, branch history) that the messages consume, and

    +
    • +
  • +

    optionally emitting a non-Nexus flush message when the TIP side channel signals an ATB flush.

    +
    • +
+
+
+

One eTIP element can produce several messages, emitted consecutively. The initial element after enable, for example, forces a synchronizing message followed by an ownership message; an element that overflows an accumulator forces a ResourceFull message ahead of the message it belongs to.

+
+
+

The generator covers the program-trace subset of the Nexus standard and the CTTE vendor extensions, using the TCODE, SRC, I-CNT, F-ADDR / U-ADDR, HIST, SYNC, RCODE/RDATA and TSTAMP fields as defined there.

+
+
+

8.2.1. I-CNT Accounting

+
+

The instruction count is accumulated in CurrICnt, whose width is NEXUS_MSG_I_CNT_WIDTH_WIDE + 2 = 18 bits — bounded by construction rather than by hope, since the value is drained long before that.

+
+
+

The cap at which a drain fires is CSR-selectable. With the wide-I-CNT option compiled in and enabled (trTeInstFeatures.InstEnWideIcnt) the cap is 2^16 - 1, otherwise 2^8 - 1 (NEXUS_MSG_I_CNT_WIDTH = 8). Because the on-wire I-CNT field is variable-length, widening the cap does not change the field encoding; it only changes when a drain occurs. With the default narrow cap the byte stream is identical to the original fixed-8-bit behaviour.

+
+
+

A drain is a ResourceFull message with RCODE = 0 (NEXUS_RCODE_ICNT_OVERFLOW). Two values are involved and the split between them matters:

+
+ ++++ + + + + + + + + + + + + + + + + +
ValueContent

Drain value

CurrICnt — what accumulated before the current event.

Drain residue

The current event’s own halfword count, carried forward into the fresh accumulator.

+
+

Both are capped, and the cap is checked rather than argued. CurrICnt is set to zero, to the event’s count, or to a sum the guard has found small enough — but that guard sits behind other drains and can be skipped, so the inductive reading of it is incomplete (see below). The event’s own count is bounded by the composer’s tip-side pre-drain (Chapter 7). Assertions check the emitted field value, which is what caught both breaches described next.

+
+
+

The cap has been broken twice, by two independent mechanisms, and the second one is the more instructive.

+
+
+

First cause, corrected 2026-08-12. The eight inline drain arms emitted the sum of accumulator and current event and zeroed the accumulator. By the very condition that triggers such an arm, that sum always exceeds the cap, so every one of those drains carried an over-cap field value. It decoded — the field is variable-length and the reference decoder reads it — which is why it stayed invisible; it was found as RCODE-0 RDATA values of 256, 258 and 260 on the committed artefacts of four testbenches, including the one written for this very path (tests/instruction/20_icnt_overflow, which produced the stream but judged no field value). The correction is a re-split of one number across two messages, not a change of accounting: the decoder’s total is unchanged, because the RCODE-0 payload feeds the same adjustment accumulator that the next message’s I-CNT adds to.

+
+
+

Second cause, corrected 2026-08-20. The same field values kept appearing after that. The accumulation CurrICnt ⇐ CurrICnt + etip_cf.icnt runs unconditionally, while the cap guard sits in an else if behind the branch-history drain. When both conditions fire in the same beat, history wins and the I-CNT drain is skipped — correctly, since only one message can leave per beat — but the accumulation above it has already happened, so the excess is carried on silently and the next drain puts it on the wire. Measured: 252 + 6 = 258. The fix splits rather than clamps, for the same reason as the first: discarding the excess would lose halfwords and desynchronize the decoder.

+
+
+ + + + + +
+
Caution
+		 +The inductive argument in the source comment at that line asserted the opposite — that CurrICnt is only ever set to zero, to the event’s count, or to a sum the guard has already found small enough. The third case does not hold precisely when the guard is skipped. An induction with one overlooked branch reads like a proof, and this one is the reason the second cause went unexamined for two weeks after the first was closed. tests/instruction/20_icnt_overflow now carries the red counter-proof: four legs that restore the pre-fix form in a worktree and go red with exactly the values of the real defect (260 / 260 / 256 / 258). +
+
+
+
+

8.2.2. Branch History

+
+

The HIST registers are sized to the wire field — NEXUS_MSG_RDATA_WIDTH = 30 bits including the stop bit — not to the generic maximum field width, because the window logic caps the number of data bits by construction. The valid-bit counter is 6 bits wide, bounded by the window-full drain at 29 data bits.

+
+
+

When the window fills, the generator emits ResourceFull with RCODE = 1 (NEXUS_RCODE_HIST_OVERFLOW). The repeated-history compression replaces that message with RCODE = 2 (NEXUS_RCODE_HIST_OVERFLOW_REPEATED) where it applies; see Chapter 9.

+
+
+

Bounding the accumulators this way — and signalling the bound explicitly — is what keeps a decoder’s state error bounded: the alternative, silently truncating, would leave the decoder to discover the loss later, if at all.

+
+
+
+

8.2.3. Synchronization Handling

+
+

A synchronizing message re-anchors the decoder at a full address, which makes the treatment of the pending accumulator state the delicate part.

+
+
+

Ordinary sync in history mode. A periodic or externally requested sync would clear the accumulated history bits without emitting them, leaving the decoder unable to resolve the direct branches between the previous flush and the sync point. The generator therefore holds the sync element back for one cycle and emits a ResourceFull HIST flush first.

+
+
+

IBHS. With trTeInstFeatures.InstEnIbhs set, the synchronizing message carries the pending history itself (IndirectBranchHistorySync, TCODE 29) instead of pre-flushing it as a separate ResourceFull. The hold above is then bypassed. The decoder walks the I-CNT resolving branches from the HIST field and then hard re-anchors at the full address — exactly the two-message semantics in one message.

+
+
+

FIFO overrun. A sync whose reason is a FIFO overrun is treated differently from every other sync, and the reasoning is worth stating because it is easy to get backwards. Upstream of the generator, the composer’s overflow injector has already dropped control-flow events, so the generator’s accumulators represent only the subset that reached it. Pre-flushing the residual history bits would walk the decoder through branches without the matching in-between halfwords and land it at a PC that disagrees with the sync’s own full address. The generator therefore overrides the I-CNT to zero on a FIFO-overrun sync, and the sync reset zeroes the history in the same cycle, turning the recovery sync into a pure re-anchor at the full address — the only ground truth available at that point. A decoder’s I-CNT adjustment heuristic can absorb a small over-count, but the post-overrun under-count is unbounded and would underflow as soon as the gap exceeds the in-message field; it has been observed on a hardware capture as a FIFO-overrun sync carrying a non-zero I-CNT.

+
+
+

The exit-from-reset sync never has pending history and is excluded from the hold for that reason.

+
+
+
+

8.2.4. Emission Ordering

+
+

Several accumulators may hold content that the decoder must see before the message that moves or repositions its PC. The generator enforces the order explicitly:

+
+
+
    +
  • +

    Buffered repeated-history runs are drained before any message that walks or repositions the decoder PC — an indirect-branch-history message, any sync except FIFO overrun, the trace-off correlation, and an ATB flush request. The buffered patterns are the oldest pending content, and the decoder replays them from its current PC.

    +
    • +
  • +

    ResourceFull with RCODE = 0 deliberately does not trigger that drain: its payload only accumulates into the same adjustment counter that history walks subtract from, so it commutes with the other two RCODEs, and draining would cost compression for nothing.

    +
    • +
  • +

    A FIFO-overrun sync discards the buffer instead of draining it, for the same reason the residual history is discarded.

    +
    • +
  • +

    An open repeat-instruction run and a pending repeat-branch count are closed before any state-moving consumption, so a later history bit cannot be replayed ahead of the run it belongs to.

    +
    • +
+
+
+
+

8.2.5. Idle and Empty

+
+

msg_gen_idle feeds the trTeControl.Empty chain (Chapter 5). It means: no message output is presented and no compression substance is being held back. The I-CNT and history accumulators deliberately do not count as generated trace — they are accumulator state, not a message that was produced but not yet emitted; the flush and correlation paths drain them before Empty becomes relevant.

+
+
+
+

8.2.6. Backpressure, Ordering and Determinism

+
+

The downstream formatter chain can deassert ready_in. In that case the generator holds its output stable and does not acknowledge new input from etip_q or next_iaddr_q. Concretely, the RTL

+
+
+
    +
  • +

    consumes input only while ready_in is asserted,

    +
    • +
  • +

    holds the output message stable while it is deasserted, and

    +
    • +
  • +

    acknowledges next_iaddr_q only when a control-flow message actually requires the target and the entry is valid.

    +
    • +
+
+
+

This preserves message order and makes message loss by backpressure impossible.

+
+
+
+

8.2.7. Latency

+
+

The generator is primarily a single-cycle transform in proc_clk. Observable latency is dominated by the upstream eTIP CDC FIFO and by downstream backpressure, not by the transform itself.

+
+
+
+
+

8.3. Nexus Message Formatter

+
+

Module: ct_L2_nexus_formatter (rtl/ct_L2_nexus_formatter.sv).

+
+
+

The formatter converts a generic trace message into an explicit Nexus field list (nexus_message_t) — still without MDO/MSEO packing. A Nexus message is a sequence of fields and always begins with a TCODE field; the array holds up to nexus_vendor::NEXUS_MAX_FIELDS = 10 fields, each up to NEXUS_MAX_FIELD_DATA_WIDTH bits wide.

+
+
+

For each input message the formatter:

+
+
+
    +
  • +

    emits the TCODE field,

    +
    • +
  • +

    optionally emits a SRC field, depending on configuration (trTeControl.InhibitSrc),

    +
    • +
  • +

    appends the message-specific payload fields — SYNC, ICNT, PC_FADDR, UADDR, HIST, RCODE/RDATA, DQDATA, DSZ/ELSZ and so on,

    +
    • +
  • +

    optionally appends a TSTAMP field when timestamping is enabled, and

    +
    • +
  • +

    clears or initializes unused field slots so that simulation cannot read stale content.

    +
    • +
+
+
+

Timestamps follow the standard’s two-mode scheme: a synchronizing message carries an absolute timestamp, a non-synchronizing message a relative one that a decoder adds to the last absolute or relative value.

+
+
+

The formatter also maintains the protocol state that spans messages, in particular the reference address used for address compression — the value against which the next differential address is computed. That state is mirrored bit for bit in the compression logic of the generator (Chapter 9), because both sides must agree on what the decoder’s reference will be.

+
+
+

No buffering. The module accepts a new message only while its own ready_in is asserted. When downstream stalls, it holds nexus_msg stable and deasserts ready_out to stall upstream. This is what makes the ordering guarantee of the chain hold end to end.

+
+
+

In the compact-packer profiles this module is not built at all: ct_L2_compact_packer produces the MDO/MSEO chunks directly from a per-TCODE layout table, and the wire stream is byte-identical (Chapter 10).

+
+
+
+

8.4. E-Trace te_inst Generator

+
+

Module: ct_L2_te_inst_gen (rtl/ct_L2_te_inst_gen.sv).

+
+
+

The E-Trace generator consumes the same eTIP stream and produces te_inst packets of the RISC-V Efficient Trace specification, baseline algorithm, instruction trace only. Its event mapping mirrors the reference encoder model shipped with the specification:

+
+ ++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
eTIP eventte_inst output

Plain taken / not-taken branch

One branch_map bit (0 = taken, least significant bit oldest). The 31st bit forces a Format 1 packet without an address.

Uninferable discontinuity

Format 1 with the pending branches, or Format 2 with the differential address of the jump target.

Trap (exception or interrupt)

A Format 1/2 flush at the trap point, then a deferred Format 3.1 carrying the handler address. The deferral by one event is what allows the synchronization "branch" bit to be resolved when the anchor instruction is itself a branch.

Enable sync (first beat)

Format 3.3 SUPPORT with ienable = 1, followed by a Format 3.0 full-address anchor.

FIFO-overrun sync

Format 3.3 SUPPORT with the trace-lost qualifier, followed by Format 3.0.

Trace-off / correlation

Format 1/2 flush, then Format 3.3 SUPPORT with ienable = 0 and the ended-reporting qualifier.

Composer I-CNT drain

Consumed silently — E-Trace has no I-CNT field.

+
+

Mid-trace synchronizations from the composer — periodic, explicit request, external trigger, sequential — re-anchor through a deferred Format 3.0. The sideband values ecause, tval, priv and ilastsize ride the eTIP sideband, which is why an E-Trace instance requires those fields to be built at full width (Chapter 5, genEtraceNoSideband).

+
+
+

This implementation is a control-flow-only profile; the restriction is enforced by an elaboration guard in the module.

+
+
+

The packets are framed onto ATB by ct_L2_te_packetizer (rtl/ct_L2_te_packetizer.sv), which emits the reference-raw byte framing — one byte per beat, a header byte {0, msg_type[1:0], payload_len[4:0]} followed by the payload — and crosses into the ATB clock domain. That framing is what the funnel’s dual-protocol mode consumes (Chapter 11).

+
+
+
+
+
+

9. Compression Suite

+
+
+

9.1. Principle

+
+
+ + + + + + + + + + +
+
+
+ Control-flow event +
+ from the preprocessor +
+
+
+ + + Control-flow event... + + + + + + + + + + + +
+
+
+ Return matching +
+ the call stack? +
+
+
+ + + Return matching... + + + + + + + + + + + +
+
+
+ Implicit Return - +
+ no address on the wire +
+
+
+
+ + + Implicit Return -... + + + + + + + + + + + +
+
+
+ Single-instruction +
+ spin loop? +
+
+
+ + + Single-instruction... + + + + + + + + + + + +
+
+
+ RepeatInstruction (31/32) - counted, not one bit per iteration +
+
+
+ + + RepeatInstruction (31/3... + + + + + + + + + + + +
+
+
+ History pattern +
+ repeats? +
+
+
+ + + History pattern... + + + + + + + + + + + +
+
+
+ Repeated History - collapses into a repeat count +
+
+
+ + + Repeated History - coll... + + + + + + + + + + + +
+
+
+ Indirect branch +
+ to a known target? +
+
+
+ + + Indirect branch... + + + + + + + + + + + +
+
+
+ JumpTargetCache (57) +
+ - cache index instead of address +
+
+
+ + + JumpTargetCache (57)... + + + + + + + + + + + +
+
+
+ BranchPredict (56) +
+ - run length to the next mispredict +
+
+
+ + + BranchPredict (56)... + + + + + + + + + + + +
+
+
+ Ordinary message +
+ (DirectBranch, IndirectBranch, …) +
+
+
+ + + Ordinary message... + + + + + + + + + + + + + + + + +
+
+
+ yes +
+
+
+ + + yes + + + + + + + + + + + + +
+
+
+ no +
+
+
+ + + no + + + + + + + + + + + + +
+
+
+ yes +
+
+
+ + + yes + + + + + + + + + + + + +
+
+
+ no +
+
+
+ + + no + + + + + + + + + + + + +
+
+
+ yes +
+
+
+ + + yes + + + + + + + + + + + + +
+
+
+ no +
+
+
+ + + no + + + + + + + + + + + + +
+
+
+ yes +
+
+
+ + + yes + + + + + + + + + + + + +
+
+
+ no +
+
+
+ + + no + + + + + + + + + + + + +
+
+
+ predictable run +
+
+
+ + + predictable run + + + + + + + + + + + +
+
+
+ Branch +
+ repeats? +
+
+
+ + + Branch... + + + + + + + + + + + +
+
+
+ Repeat Branch +
+ (TCODE 30) +
+
+
+ + + Repeat Branch... + + + + + + + + + + + + +
+
+
+ no +
+
+
+ + + no + + + + + + + + + + + + +
+
+
+ yes +
+
+
+ + + yes + + + + + + + + + + Text is not SVG - cannot display + + + + +
+
Figure 9. Which compression feature applies, and in which order
+
+
+

Every feature is individually switchable, and the full suite is not always the best choice: on a pointer-heavy workload it measures worse than the same build without branch prediction.

+
+
+

The order shown is the evaluation order, not a priority ranking of value.

+
+
+

CTTE bundles a set of individually switchable program-trace compression features. They reuse the standard message machinery — vendor TCODEs, reserved RCODEs, variable-length fields — so a Nexus-aware decoder can still frame every stream, whether or not it understands a particular scheme.

+
+
+

Three properties hold for the whole suite and are worth stating before the individual schemes:

+
+
+

Every feature has two switches. A compile-time switch in rtl/pkg/ct_pkg.sv (CT_EN_*) decides whether the logic exists at all, and a runtime enable field in trTeInstFeatures decides whether it is used. This pairing is a property of this suite, not of every CTTE feature: the event groups, for instance, are compile switches without a dedicated runtime enable.

+
+
+

Every feature resets to off. The runtime enables all reset to 0, so a freshly reset encoder produces the uncompressed baseline stream. This is what makes "byte-identical to the previous build" a checkable property for every feature addition.

+
+
+

Every feature is a two-sided model. The compression schemes do not remove redundancy that the decoder can find by itself — they remove information the decoder can reconstruct because it runs the same model. The return stack, the jump-target cache and the branch predictor exist twice, once in the encoder and once in the decoder, and they must agree bit for bit. A one-bit disagreement desynchronizes the two models silently. That is why the folding functions are spelled out as loops in the RTL rather than hand-unrolled, why the model state is cleared at exactly the same events on both sides, and why the capability and structure constants are advertised in the configuration message rather than configured out of band.

+
+
+

Which features are compiled in (CAPS) and which are currently enabled (ENAB) are carried in the vendor configuration message together with the structural sizes of the return stack, the jump-target cache and the branch predictor, so a decoder can configure its models from the stream itself. See the self-identification chapter.

+
+
+
+

9.2. Feature Matrix

+ ++++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
FeatureRuntime enable (trTeInstFeatures, te offset 0x008)CAPSResetFull profileMeasured cost

Implicit return

InstEnImplicitReturn [3]

0

0

1

+71 LUTs / +553 FFs — the highest FF-to-LUT ratio in the encoder: CT_RET_STACK_DEPTH (16) x 32-bit address = 512 register bits, i.e. 93 % of the flip-flops, with trivial push/pop logic.

Repeated history

InstEnRepeatedHistory [8]

1

0

1

+86 LUTs / +91 FFs

Wide instruction count

InstEnWideIcnt [12]

2

0

1

+66 LUTs / +29 FFs

Repeat branch

InstEnRepeatBranch [11]

3

0

1

+31 LUTs / +162 FFs

Jump-target cache

InstEnJumpTargetCache [5]

4

0

1

+262 LUTs / +71 FFs

Branch prediction

InstEnBranchPrediction [4]

5

0

1

+618 LUTs / +56 FFs — the most expensive of the switches measured this way.

Indirect branch history with sync (IBHS)

InstEnIbhs [13]

8

0

1

full-profile delta of -446 LUTs, not causally isolable.

Repeat instruction

InstEnRepeatInstr [14]

9

0

1

full-profile delta of -381 LUTs, not causally isolable.

+
+ + + + + +
+
Note
+		 +The cost column is quoted from the feature-flag table in the public integration guide (doc/integration.adoc). The six isolable figures are differential out-of-context syntheses on xck26-sfvc784-2LV-c measured 2026-08-11/12 with Vivado™ 2026.1 at a 5.0 ns target against base A (featparity, compact packer on: 3 552 LUTs / 3 598 FFs / 6.5 BRAM, WNS +1.196 ns). The two IBHS and repeat-instruction figures are full-profile deltas; per the interpretation rule of that table, full-profile deltas below roughly +/-300 LUTs are restructuring-affected, so a negative delta does not mean the feature is free. The consolidated profile-level resource and timing table is in the footprint-profile chapter, not here. +
+
+
+
+

9.3. Interactions and Exclusions

+
+

Branch prediction replaces the history accumulation that the history-based loop compressions buffer and replay. Mixing the two models would produce a stream neither side can walk, so the exclusion is hard-gated in the RTL rather than left to the programmer: with branch prediction enabled, repeated history, repeat branch and repeat instruction are forced off, whatever the CSR says. A misprogrammed register therefore cannot mix the models, and with branch prediction off the behaviour is bit-identical to a build without it.

+
+
+

The other interaction to know about concerns ordering, and it is described in Chapter 8: buffered compression state must reach the wire before any message that walks or repositions the decoder’s PC.

+
+
+
+

9.4. Implicit Return

+
+

Compile switch CT_EN_IMPLICIT_RETURN, enable InstEnImplicitReturn.

+
+
+

A return whose target the decoder can predict does not need to carry that target. The encoder maintains a return-address stack in the eTIP composer (rtl/preproc/ct_L23_preproc_composer_etip.sv): a call pushes the address after the call site, a return pops it. Depth is ct_pkg::CT_RET_STACK_DEPTH = 16 slots, advertised in the configuration message.

+
+
+

A return folds — is treated like an inferable branch and emits no indirect-branch message — when all of the following hold:

+
+
+
    +
  • +

    the composer’s stack produced a prediction,

    +
    • +
  • +

    that prediction equals the actual next address,

    +
    • +
  • +

    the element carries no synchronization reason, and

    +
    • +
  • +

    the runtime enable is set.

    +
    • +
+
+
+

A sentinel value means "the stack had no prediction" and never folds, because the decoder’s stack would be empty as well.

+
+
+

The comparison itself was moved into the composer during a resource pass; only the one-bit result rides the next-address sideband into the message generator.

+
+
+

Stack hygiene is the part that is easy to get wrong, and it is guarded by assertions:

+
+
+
    +
  • +

    At a trace pause the stack is cleared. A frame pushed before the pause would make a return after the resume "implicit" against a frame the decoder does not have, and the decoder would pop a wrong or empty frame. Assertion I3 checks that the stack is empty when the trace-off correlation is emitted.

    +
    • +
  • +

    A gap re-anchor must not modify the stack. Assertion I5 checks this.

    +
    • +
+
+
+

Known limitation on the E-Trace back end: with the irdepth field width at zero, an implicit-return-folded loop that crosses a positional binding point — a trap or trace-off flush, a window or resynchronization anchor — cannot express the visit count. Measured as 6 of 33 red among the implicit-return-armed runs of a free-axis calibration (efix_cal1, seed 20260806). The implicit-return bit is therefore masked from the E-Trace soak draw until an irdepth field exists; every other compression bit is drawn.

+
+
+
+

9.5. Repeated History

+
+

Compile switch CT_EN_REPEATED_HISTORY, enable InstEnRepeatedHistory.

+
+
+

A full history window that would be emitted as ResourceFull RCODE = 1 is instead buffered. An identical follow-up pattern only increments a counter. The buffered run is emitted as a single ResourceFull with RCODE = 2 (HIST_OVERFLOW_REPEATED, first payload = the pattern, second = the count) — or as a plain RCODE = 1 when the pattern occurred exactly once — as soon as the pattern changes or a PC-walking message has to go out.

+
+
+

The scheme matches the behaviour of the reference software encoder, including its partial-pattern trim.

+
+
+

9.5.1. Partial Match

+
+

The exact-window match alone is weaker than it looks. The window carries NEXUS_MSG_RDATA_WIDTH - 1 = 29 data bits, and 29 is prime — so every non-uniform periodic branch pattern phase-drifts against the window boundary and never matches exactly. Loop bodies whose period does not divide 29 would therefore never compress, which is most of them.

+
+
+

The partial-match conversion fixes this by trimming the window. For a trim by s bits, the branch stream is periodic with a period dividing W - s if and only if

+
+
+
    +
  1. +

    the previous pattern closes across the trimmed-window boundary (its lowest s bits equal its highest s bits), and

    +
    2. +
  2. +

    the current window continues the previous one, shifted by the s-bit drift.

    +
    3. +
+
+
+

Two shifts are implemented: s = 1 gives a 28-bit window, which covers periods 2, 4, 7, 14 and 28 — the if/else-in-a-loop shape — and s = 2 gives a 27-bit window, covering periods 3, 9 and 27, the three-way unrolls. The check runs only on the second window of a run, matching the reference encoder. A run with shift 0 is an exact full-window run; a run with shift s carries a pattern of 29 - s data bits, and the s least significant bits of each window are carried into the next accumulation.

+
+
+
+
+

9.6. Wide Instruction Count

+
+

Compile switch CT_EN_WIDE_ICNT, enable InstEnWideIcnt.

+
+
+

This raises the internal cap on the accumulated instruction count from 8 to 16 bits, which reduces how often a ResourceFull RCODE = 0 drain has to be emitted. The on-wire I-CNT field is variable-length either way, so an enabled wide cap changes when drains occur, not how a field is encoded. With the narrow cap the byte stream is identical to the original fixed-8-bit behaviour. The details of the drain accounting are in Chapter 8.

+
+
+
+

9.7. Repeat Branch

+
+

Compile switch CT_EN_REPEAT_BRANCH, enable InstEnRepeatBranch, wire message TCODE 30.

+
+
+

An indirect-branch-history message identical to the last emitted one — same history, same instruction count, same target — is suppressed and counted. The run is closed by a repeat-branch message carrying the suppression count, and the decoder replays its saved previous message that many times.

+
+
+

Two hard constraints follow from how the decoder implements the replay, and both shape the encoder:

+
+
+

The count must be drained before every other emission. The reference decoder saves only the first two message fields across the parse of a repeat-branch message, so any intervening message clobbers the remembered fields. This drain is stricter than the repeated-history one: it applies even to RCODE = 0 drains, and the "last message was an indirect-branch-history" flag is cleared whenever any other message goes out.

+
+
+

Only byte-identical messages may collapse. The decoder replays the saved message verbatim, so a replayed indirect-branch-history message re-applies its differential address against the moved address reference. That is correct only if the differential address was zero — then the reference already sits at the target and stays there through every replay. A jump-target-cache message replays soundly in every case, because its cache index resolves the absolute target and no cache install can happen between the message and its replays (any other emission clears the flag).

+
+
+ + + + + +
+
Note
+		 +The earlier match criterion — same history, count and target — collapsed two different calls that happened to share a target into one repeat whose head message carried a non-zero differential address. The decoder then walked a stale loop iteration and derailed. Found as soak finding S-7 (seed 1317011359) and fixed by adding the replayability condition. The encoder mirrors the packer’s address-compression reference (the last transmitted program-trace address) for exactly this test, updated centrally at the output handshake because the differential address of the message being emitted is computed one stage downstream. +
+
+
+
+

9.8. Jump-Target Cache

+
+

Compile switch CT_EN_JTC, enable InstEnJumpTargetCache, wire message vendor TCODE 57.

+
+
+

An indirect branch whose target is already installed in a direct-mapped cache is emitted with a 6-bit cache index instead of the differential address. The cache holds ct_pkg::CT_JTC_ENTRIES = 64 entries, advertised in the configuration message.

+
+
+

Install rule. The cache installs on every emitted plain indirect-branch-history message, i.e. on a cache miss. The decoder mirrors exactly that rule — learn on a plain indirect-branch-history message, read-only on a cache-index message — so both models stay bit-identical without any explicit synchronization.

+
+
+

Index function. The index is an XOR fold over 6-bit slices of the target address, not a simple bit slice. The reason is empirical: the targets where the cache wins most are far apart and typically have zero low bytes, so a plain [7:2] index would make them all collide.

+
+
+

The highest address bit the fold consumes is a knob, not simply "all bits":

+
+ ++++ + + + + + + + + + + + + + + + + +
Address widthFolded bits

32-bit

Up to bit 25 — the four slices [7:2], [13:8], [19:14], [25:20]. The fold has to stay bit-identical here, which is why the bound is explicit rather than derived from the address width.

64-bit

The remaining eleven slices join in. Leaving them out would make the index blind above bit 25, and under Sv39 the kernel/user split lives entirely above it — every kernel target would hash as if its high half were zero and collide with the user-space target sharing its low bits. The last slice is short (bits 63:62) and enters zero-extended.

+
+

The decoder’s fold must switch the same way, driven by the address-width capability bit it reads from the configuration message.

+
+
+

Clearing. The cache is cleared at trace-off (the correlation message), so a decoder starting at the next session can never see an index it could not have learned.

+
+
+
+

9.9. Branch Prediction

+
+

Compile switch CT_EN_BP, enable InstEnBranchPrediction, wire message vendor TCODE 56.

+
+
+

With branch prediction enabled, direct branches do not accumulate history bits at all. Both sides run a bit-identical predictor:

+
+ ++++ + + + + + + + + + + + + + + + + + + + + + + + + +
PropertyValue

Structure

Direct-mapped table of ct_pkg::CT_BP_ENTRIES = 512 two-bit saturating counters, advertised in the configuration message.

Index

iaddr[10:2] (9 bits).

Init

Weakly not-taken.

Update

With the actual outcome of every processed direct branch.

+
+

A correctly predicted branch is silent — the encoder only counts it. The decoder resolves it from its own predictor while walking the instruction count of whatever message eventually covers it. Only a mispredict emits a message: TCODE 56 carrying the number of correctly predicted branches since the last PC-walking emission. The decoder then eagerly walks that many branches predictor-resolved, plus one more inverted. The message carries no instruction-count field; it follows the same walking convention as the history-overflow RCODEs.

+
+
+

The prediction counter therefore resets on every PC-walking emission — an indirect-branch-history message, a cache-index message, a sync, a correlation, or a mispredict message — and not on ResourceFull drains, because an RCODE = 0 drain does not walk and RCODE = 1/2 walk only carried-over seed bits. Branches carried by a synchronizing message keep the existing one-bit history seed path: the decoder consumes pending history bits before consulting its predictor, and updates the predictor either way.

+
+
+

Storage. A clear loop over 512 entries would force the table into flip-flops. Instead each entry carries a 16-bit epoch tag: clearing the model — at trace-off, on FIFO-overrun recovery, at reset — bumps the epoch, and an entry with a stale tag simply reads as the initial value, bit-identically to a real clear. A background scrubber rewrites one stale entry per idle cycle, so a tag value can never alias even after a full wrap of the epoch counter. The table maps into LUTRAM rather than registers.

+
+
+

Model synchrony under loss. The table is cleared at trace-off and on FIFO-overrun recovery, and the decoder mirrors both. Branches dropped by an overrun are never seen by the message generator and never walked by the decoder, so the two models stay in lockstep across a gap.

+
+
+
+

9.10. Indirect Branch History with Sync (IBHS)

+
+

Compile switch CT_EN_IBHS, enable InstEnIbhs, wire message TCODE 29.

+
+
+

Without this feature, a synchronizing message in history mode has to be preceded by a ResourceFull history flush, because the sync would otherwise clear the accumulated history bits without emitting them and leave the decoder unable to resolve the direct branches before the sync point. With IBHS enabled, the synchronizing message carries the pending history itself, and the pre-flush is skipped: one message where two went before.

+
+
+

The decoder semantics are unchanged — it walks the instruction count resolving branches from the history field, then hard re-anchors at the full address. That is exactly the two-message semantics in one message.

+
+
+

Two synchronization reasons stay outside the feature: a FIFO-overrun sync, whose history is discarded rather than carried (see Chapter 8), and the exit-from-reset sync, which never has pending history.

+
+
+
+

9.11. Repeat Instruction

+
+

Compile switch CT_EN_REPEAT_INSTR, enable InstEnRepeatInstr, wire messages TCODE 31 and 32.

+
+
+

A single-instruction spin loop — a taken branch whose target is its own address — is compressed into a count instead of one history bit per iteration. The first execution is accounted normally (a history bit and its halfwords); every following identical iteration is silently counted. An iteration counts only when the address and the per-iteration halfword count match the armed run, which is a defensive match rather than a necessary one.

+
+
+

The run closes in one of two ways:

+
+ ++++ + + + + + + + + + + + + + + + + +
MessageDecoder contract

TCODE 31 (repeat instruction)

Emitted before any other message. The decoder walks the instruction count with the history — which ends back at the loop PC after the first execution’s taken bit — and then re-emits the loop PC as many times as the repeat count says. The replays touch no instruction-count accounting; the count restarts at zero after this message.

TCODE 32 (repeat instruction with sync)

Emitted when a synchronization lands on the armed loop branch mid-run. The decoder walks the instruction count with the history, then performs repeat-count-plus-one replays — the counted iterations plus the sync-carrying iteration itself, whose halfwords the encoder deliberately drops so that neither the count nor the replays carry them — and then hard re-anchors at the full address, which is the loop PC.

+
+

The counter is 18 bits wide and saturates; an iteration at the cap does not extend the run, it starts a new one. A FIFO-overrun sync discards the count, like the other buffered compressions, because it belongs to the pre-gap stream.

+
+
+

The feature is excluded under branch prediction, whose predictor already absorbs spin loops.

+
+
+
+

9.12. How much the suite actually saves

+
+

The honest answer is: it depends on the code, far more than on the encoder. A single figure per feature would be misleading, and the predecessor manual’s per-feature percentages could not be traced to any workload, configuration or artefact and are therefore not carried forward.

+
+
+

What can be shown is a measured spectrum. One core, one encoder netlist, one configuration, synchronization every 1024 instructions, PC-range filtered, two windows per point — the only difference between the rows is the code being executed:

+
+ + ++++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 4. Bits per retired instruction by compression feature set (measurement series BM1, 2026-08-09)
Workloadnoneno BPfull suitebestdominant structural property

loop

0.661

0.406

0.206

−69 %

97.5 % predictable branches, no indirect jumps

coremark

0.860

0.643

0.726

−25 %

92.2 % predictable, 0.6 % indirect

sqlite

2.084

1.710

1.784

−18 %

87.3 % predictable, 2.9 % indirect

ptr

4.627

4.129

4.900

−11 %

73.3 % predictable, 8.1 % indirect, 99.4 % new history patterns

+
+

Three things in that table matter more than any single number:

+
+
+
    +
  • +

    The range is a factor of 23.8 (0.206 to 4.900 bits per instruction) on an unchanged encoder. Bandwidth sizing therefore has to start from the workload, not from an encoder datasheet figure — Chapter 26 gives the sizing procedure.

    +
    • +
  • +

    The full suite is not always the best choice. On ptr it is measurably worse than the same build with branch prediction disabled (4.900 against 4.129), because a workload whose history patterns are 99.4 % new defeats a predictor and pays its message overhead without the benefit. The features are individually switchable for exactly this reason.

    +
    • +
  • +

    The benefit correlates with predictability, not with the number of features enabled.

    +
    • +
+
+
+ + + + + +
+
Note
+		 +The series was produced for the CTTE publication; the raw data live outside this repository. The figures are reproduced here for orientation and carry the same reproducibility caveat as the coverage figure in Chapter 31 — see the note at the end of this chapter. +
+
+
+
+

9.13. Standards Positioning

+
+

CTTE’s reset configuration produces a stream that is within N-Trace 1.0, with the single exception of the configuration message. Switching on a compression feature can leave that envelope, and the public trace-format documentation states per feature why:

+
+ ++++ + + + + + + + + + + + + + + + + + + + + + + + + +
FeaturePosition

Branch prediction (56), jump-target cache (57)

Vendor TCODEs in the Nexus vendor range 56-62. Both sides must run the bit-identical model; a decoder without it cannot reconstruct the flow.

Repeat instruction (31/32)

IEEE-ISTO 5001-2012 sections 4.3.14 and 4.3.15 messages; N-Trace 1.0 Table 9 marks TCODEs 31/32 as reserved for future extensions. Enabling the feature therefore makes the stream an Accemic/ISTO extension rather than a strict N-Trace 1.0 stream.

Wide instruction count

Internal accounting only. The on-wire field stays variable-length per Nexus, so an enabled wide cap is not a wire-format extension — it only changes how often ResourceFull (I-CNT) messages appear.

Implicit return, repeated history (RCODE 2), repeat branch (30), IBHS (29)

Standard message types and RCODEs; the compression lies in the encoder/decoder model agreement, not in a new field.

+
+

Sequential-jump inference is not a runtime switch at all but an ingress convention of the attached core, fixed at build time by the CT_SIJUMP parameter and advertised in the configuration message (Chapter 6).

+
+
+
+

9.14. The E-Trace Back End

+
+

The E-Trace generator implements the equivalent schemes in the forms the Efficient Trace specification provides for them: branch prediction as Format 0.0 and the jump-target cache as Format 0.1, plus the optional implicit-return and sequential-jump modes. The models and their clearing rules are the same; only the packet form differs. The E-Trace-specific tests are tests/instruction/25_etrace_jtc, 26_etrace_bp, 21_etrace_ir and 34_etrace_resync_ir.

+
+
+
+

9.15. Verification

+
+

Each compression feature has its own directed test:

+
+ ++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
TestFeature

tests/instruction/06_implicit_return

Implicit return

tests/instruction/07_repeated_history

Repeated history, including the partial-match trims

tests/instruction/08_repeat_branch

Repeat branch

tests/instruction/09_jtc

Jump-target cache

tests/instruction/10_branch_predict

Branch prediction

tests/instruction/13_ibhs

IBHS

tests/instruction/14_repeat_instr

Repeat instruction

tests/instruction/19_feature_matrix

Feature combinations

tests/instruction/20_icnt_overflow

Instruction-count drains, including the wide cap

+
+

Beyond the per-feature tests, the suite carries byte-identity legs (cli_bp_test.sh, cli_ir_test.sh, cli_jtc_test.sh, cli_rh_test.sh, cli_rb_test.sh): the same stimulus is run with the feature off and on. The off run’s prefix must equal the reference stream, and the on run must decode to the same PC sequence at a strictly smaller byte count. These legs pin the wire format: any by-product byte change in an unrelated fix turns them red.

+
+
+

That is also the exact claim the suite supports, and it is worth being precise about it: each feature is proven lossless — the decoded PC sequence is identical with the feature off and on — and proven to reduce the byte count on its dedicated stimulus. How much it reduces depends entirely on the workload, and a figure without a named workload, profile and comparison baseline would not be reproducible.

+
+
+
+
+
+

10. Output Stage

+
+
+

10.1. Overview

+
+

The output stage turns a message into bytes on the ATB and crosses from proc_clk into atb_atclk. Three paths exist, and exactly one is built:

+
+ ++++ + + + + + + + + + + + + + + + + + + + + +
BuildPath

N-Trace, historical (default)

ct_L2_nexus_formatter → ct_L2_mseo_mdo_formatter (message buffer, bit slicer, MSEO controller, ATB chunk packer, CDC FIFO, flush detect).

N-Trace, compact (ct_pkg::CT_COMPACT_PACKER = 1)

ct_L2_compact_packer replaces formatter, message buffer, bit slicer and MSEO controller with one module; the ATB tail is reused unchanged.

E-Trace (EN_ETRACE)

ct_L2_te_packetizer, reference-raw te_inst framing (Chapter 8).

+
+

An essential property of all N-Trace variants: the wire bytes are invariant against assembly timing. Only the number of cycles spent assembling a message differs between the variants; the byte stream does not.

+
+
+
+

10.2. MSEO/MDO Formatter

+
+

Module: ct_L2_mseo_mdo_formatter (rtl/ct_L2_mseo_mdo_formatter.sv) with the submodules in rtl/mseo_mdo/.

+
+
+

The formatter accepts one nexus_message_t whenever ready_out is high, slices and encodes it into MDO/MSEO chunks, packs the chunks into ATB beats, and crosses into the ATB clock domain. The message formatting follows the Nexus standard.

+
+ ++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
SubmoduleResponsibility

ct_L2_mseo_mdo_formatter_msg_buffer

Single-entry message buffer with valid/ready handshake.

ct_L2_mseo_mdo_formatter_bit_slicer

Slices the field list into MDO-width data slices. It is a dispatch wrapper: the supported MDO widths are bound as hard-wired modules through generate (_mdo6, _mdo14), each pinning its width at the module boundary and sharing one tuned core so the slice algorithm cannot drift between widths. An unsupported width fails elaboration.

ct_L2_mseo_mdo_formatter_mseo_controller

Generates the MSEO patterns and stalls data slices during control-only cycles.

ct_L2_mseo_mdo_formatter_atb_chunk_packer

Packs MDO/MSEO chunks into ATB-width payloads, inserts alignment padding at end of message, and emits flush payload beats on request.

ct_L2_mseo_mdo_formatter_atb_flush_detect

ATB-domain flush detector: watches the transmitted chunks for the flush marker and holds afready high until the external flush request is released.

+
+

10.2.1. MSEO Sequencing

+
+

The MSEO controller implements the single-pin and dual-pin sequences of the Nexus standard, Section 5:

+
+ +++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
EventSingle-pinDual-pin

Idle

1

11

Start of message

1, 1, 0

11 → 00

End of variable-length packet

0, 1, 0

00 → 01

End of message

0, 1, 1, 1, …​

00 or 01 → 11

+
+

The chunk packer’s end-of-message alignment padding is what allows a downstream funnel to detect packet boundaries from the chunk-local MSEO bits alone: after an end-of-message chunk the rest of the beat is padding, so a beat never carries the end of one message together with the start of the next (Chapter 11).

+
+
+
+

10.2.2. MDO Width

+
+

nexus_vendor::NEXUS_MDO_WIDTH selects the chunk width; the default is 6, giving the classic 8-bit chunk {MDO[5:0], MSEO[1:0]} — four chunks per 32-bit ATB beat. Width 14 gives two chunks per beat. The historical generic width 30 has been removed from the slicer; it survives only as a parsing configuration on the funnel side.

+
+
+
+

10.2.3. Assembly Throughput

+
+

ct_pkg::CT_SLICER_STEPS trades slicer area against sustained assembly rate. At 2 an output slice may cross one field boundary per cycle, which sustains roughly one slice per cycle even across many short fields. At 1 the field-multiplexer and shift datapath is halved, and a boundary-crossing slice then needs two cycles — a lower sustained wire rate on short-field messages, which is acceptable where the profile is bandwidth-uncritical. The wire bytes are identical either way; only assembly timing changes.

+
+
+
+

10.2.4. Backpressure, Framing and Latency

+
+

The formatter is part of the ready_in / ready_out chain and must neither drop nor reorder packets under stall conditions; messages are buffered and managed through an internal stall signal. When a flush request is propagated from the TIP side channel, the chain emits an explicit flush marker so that the ATB receiver can align to a packet boundary.

+
+
+

Packing and emission are pipelined in proc_clk. The base latency is fixed for a given configuration; variable latency comes only from ATB-sink backpressure.

+
+
+

Three figures are worth keeping in mind when sizing the ATB tail: ct_pkg::ATB_MAX_CHUNKS = 4 (chunks per beat at the 8-bit chunk width), ATB_CVS_FIFO_DEPTH = 8 and ATB_CDC_FIFO_DEPTH = 8.

+
+
+
+
+

10.3. Compact Packer

+
+

Module: ct_L2_compact_packer (rtl/ct_L2_compact_packer.sv), selected by ct_pkg::CT_COMPACT_PACKER.

+
+
+

The compact packer produces the MDO/MSEO chunk stream directly from a per-TCODE layout table, replacing the generic ten-field array of the Nexus formatter, the message buffer and the barrel bit slicer with a single module. The downstream ATB tail — chunk packer, CDC FIFO, flush detect — is reused unchanged.

+
+
+

Wire contract (byte-identical to the historical path):

+
+
+
    +
  • +

    Fields in per-TCODE order, transmitted least significant bit first.

    +
    • +
  • +

    All fixed fields of a message form one contiguous bit string — TCODE, optional SRC, and the per-TCODE subfields. Dual-pin MSEO marks no fixed-field boundaries, so pre-merging them changes no byte.

    +
    • +
  • +

    Every variable field is emitted with leading-zero suppression, at least one bit wide, and ends its MDO slice: the last slice holding its bits is zero-padded to the slice boundary.

    +
    • +
  • +

    MSEO per chunk: end-of-message on the message’s last slice, end-of-variable-field on a slice that ends a variable field mid-message, normal otherwise.

    +
    • +
  • +

    A flush message emits no data chunks; it pulses the chunk packer’s flush start, exactly as the historical message-buffer flush detect does.

    +
    • +
  • +

    The address-compression reference state and the timestamp delta/absolute handling replicate the Nexus formatter exactly — including the rule that a repeat-branch message carries no timestamp, and the historical truncation quirk when the SRC width is configured as zero.

    +
    • +
+
+
+

Scope. The layout table covers the program-trace path, ERROR and FLUSH — everything the message generator can emit in a control-flow-only profile. Data-trace and data-acquisition formats stay on the historical path, and elaboration fails for a profile that could emit them. The switch therefore requires the DAQ, data-trace and instrumentation features to be compiled out.

+
+
+

Cost. Replacing the formatter, slicer and MSEO controller is the cheaper of the two output paths in the control-flow-only profile; the sourced differential measurement is in Chapter 24. The compact pair tests report 12 of 12 verdicts and 14 of 14 message-identical streams.

+
+
+
+

10.4. eTIP Serialization

+
+

Switch: ct_pkg::CT_ETIP_SERIALIZE.

+
+
+

Strictly speaking this lever sits in the preprocessor’s eTIP composer (Chapter 7), but it belongs here because it is one of the two structural levers between the footprint profiles and because its effect is measured on the same artefacts as the packer.

+
+
+

With serialization on, the eTIP slots are presented one per cycle through a small skid queue instead of in parallel, so the composer FIFO stores one entry per slot rather than one entry per slot and parallel site. Message order and per-message timestamps are unchanged, and the byte stream is identical. A multi-slot beat that exceeds the skid drops whole into the designed overflow-to-resynchronization path — structurally unreachable for control flow plus data flow at at most one event per instruction; DAQ-dense workloads are gated by a budget analysis instead.

+
+
+

Cost. Serialization is the full-profile default, with the full test suite passing and a manifest of 15 of 15 byte-identical reference streams. On the slim and compact profiles the skid costs more than it saves, so those profiles set the switch to 0 explicitly (ct_pkg.sv). The resource figures per profile are in Chapter 24.

+
+
+

Two related switches diet the same interface: CT_ETIP_CDC_SLIM shrinks the decouple stage behind the composer FIFO in single-clock builds from depth 4 to a minimal register pair — removing the stage entirely was measured and halved the peak delivery rate, so it keeps the prefetch the consumer needs. CT_EN_ETIP_WATERMARK controls whether the trTeTipFifoMaxFill watermark chain exists in hardware; with it off the CSR reads zero and the tracking logic trims away, while the end-of-simulation watermark report remains as a simulation-only shadow, so depth-tuning evidence is unchanged.

+
+
+
+

10.5. eTIP FIFO Fill-Level Histogram

+
+

Switch: ct_pkg::CT_EN_FIFO_HIST, bin count ct_pkg::CT_FIFO_HIST_BINS (default 16).

+
+
+

The maximum-fill watermark answers "how close did we get". The histogram answers the question an integrator actually has when sizing a FIFO: how is the fill distributed. It is a set of saturating 16-bit counters, one per fill threshold, where counter b increments on the upward crossing of the level (b+1) * ETIP_CVS_FIFO_DEPTH / BINS.

+
+
+

Constraints on the bin count, checked at elaboration: even (two 16-bit bins are read per access), between 2 and 64, and a divisor of the FIFO depth, so that the thresholds are exact integers.

+
+
+

Serial readout. The read-out is deliberately serial rather than random access: one data register trTeTipFifoHistData (te offset 0xE14) returns the bin pair [2*RdIdx, 2*RdIdx+1] and auto-increments the pointer, wrapping after BINS/2 reads. The CSR map is therefore independent of the bin count — changing CT_FIFO_HIST_BINS needs no RDL regeneration — and the expensive per-register readback is avoided. The control register trTeTipFifoHistCtrl (0xE10) carries HistClear (level: clear counters and pointer, hold at 0; write 0 to re-arm), the self-clearing RdRewind (rewind the pointer without clearing, to re-read the histogram) and the read-only RdIdx.

+
+
+

Read contract. There is deliberately no CDC: the counters live in tip_clk and are wired straight to the register read path. They are therefore valid only while the trace is quiescent (trTeControl.Enable = 0); a read during tracing may tear. This is a pure diagnostic feature — the on-wire stream is identical with and without it.

+
+
+

Cost. The counter arithmetic carries a synthesis attribute that maps it into otherwise unused DSP slices rather than fabric LUTs. Compiled out, the registers are omitted from the register block entirely — no address decode, no readback, no counters — so a slim profile is exactly neutral. The feature is covered by test 18 including a smoke run at 8 bins (ct_implementation_status.adoc).

+
+
+
+

10.6. Split-Load Data Trace

+
+

Elaboration parameter: SPLIT_DATA_ACCESS on ct_encoder; discovery bit trTeDataControl.DataSplitLoad.

+
+
+

A core that reports a load’s address at retirement but its data later, when the memory response arrives, cannot be traced by the combined dretire path without either stalling or guessing. Split-load mode handles this case:

+
+ ++++ + + + + + + + + + + + + + + + + +
AccessBehaviour

Store

Data taken from tip.sdata at dretire.

Load

Address and size captured at dretire; the data-flow message is emitted later, at the load response (tip.lresp) using tip.ldata together with the saved address and size.

+
+

The pending-load state lives in the data-flow qualifier (PendingLoadHit) and in the eTIP composer, which holds the captured address and size until the response arrives, and which handles the case of a second load overwriting a still-pending one.

+
+
+

trTeDataControl.DataSplitLoad is a read-only discovery bit, not a control: it reads 1 exactly when the netlist was built with SPLIT_DATA_ACCESS = 1. Software cannot switch the path at run time, because the two paths need different signals from the core.

+
+
+

The mode is implemented but not the default. It is covered by tests/data/02_split_load, which elaborates with the parameter set and exercises the store, load, response and pending-overwrite paths.

+
+
+
+

10.7. Overflow and Overrun Handling

+
+

When the eTIP path cannot accept an event, the loss is made explicit rather than silent. An overflow injector on both the serialized and the parallel path turns the drop into an in-band ERROR message and a subsequent resynchronization, so the decoder learns of the gap and re-anchors at a full address instead of drifting (the resynchronization semantics are described in Chapter 8).

+
+
+

Three defects on this path were found and fixed on 2026-07-20: a counter truncation in the parallel configuration, a wrong resynchronization anchor (full address plus instruction count instead of the address alone), and level-triggered pending clears. The path is covered by tests/overflow/01_overrun_recovery, whose gates check three ERROR messages under the overflow stimulus, the correlation messages under the disable stimulus, decoding to the end of the stream and the data verdict; the reference stream is byte-neutral (ct_implementation_status.adoc).

+
+
+
+
+
+

11. Trace Funnel

+
+
+

11.1. Purpose

+
+

The CTTE funnel (ct_L1_funnel, rtl/ct_L1_funnel.sv) merges several ATB trace streams into one downstream ATB stream. It is the component that lets multiple encoders — in a multi-hart SoC, one encoder per hart — share a single trace sink such as an on-chip ring buffer, an ATB bridge, an Aurora link or the parallel trace output described in Chapter 12.

+
+
+

The funnel is a transport and arbitration component. It does not interpret the trace payload beyond what packet-boundary detection requires, and it never rewrites a message. Its guarantees are:

+
+
+
    +
  • +

    whole messages only — a channel is never switched in the middle of a packet, so messages from different sources are never interleaved,

    +
    • +
  • +

    order preservation within each input stream,

    +
    • +
  • +

    transparent forwarding of ATDATA and ATID,

    +
    • +
  • +

    deterministic arbitration (strict priority across levels, round-robin within a level),

    +
    • +
  • +

    propagation of ATB backpressure to exactly the selected channel,

    +
    • +
  • +

    per-channel and global flush coordination.

    +
    • +
+
+
+
Block diagram
+
+
ATB IN[0] --+
+ATB IN[1] --+
+ATB IN[2] --+--> ct_L1_funnel --> ATB OUT
+ATB IN[N-1]-+
+
+
+
+
+

11.2. Parameters

+
+

The parameters are those of the RTL module (rtl/ct_L1_funnel.sv); there are no others.

+
+ +++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
ParameterDefaultMeaning

N_STREAMS

4

Number of ATB input channels instantiated.

MAX_PRIO

3

Highest priority level. The per-channel priority input is $clog2(MAX_PRIO+1) bits wide; priority 0 disables a channel.

MSEO_WIDTH

2

Nexus MSEO field width. Fixed: an elaboration check rejects any other value.

MDO_WIDTH

30

Nexus MDO field width of the incoming chunks. 30 = one 32-bit chunk per beat (the historical fixed-width reference); 6 and 14 are the byte and halfword chunk configurations of the MSEO/MDO formatter, giving four respectively two chunks per beat. The chunk width is MDO_WIDTH + MSEO_WIDTH and must divide the ATB data width exactly.

EN_TE_RAW

0

Elaboration switch for E-Trace reference-raw framing support (see Section 11.9). At 0 every te_raw input tie is constant-folded away and the netlist is identical to the Nexus-only funnel.

+
+

The ATB widths are not parameters of the funnel: ATB_DATA_WIDTH, ATB_BYTES_WIDTH and ATB_ID_WIDTH are taken from atb_pkg. The fixed-width reference implementation requires ATDATA_WIDTH == 32 and enforces it at elaboration.

+
+ + ++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 5. Elaboration checks
ConditionRejected because

MSEO_WIDTH != 2

The packet-boundary parser decodes Nexus MSEO, which is two bits.

ATDATA_WIDTH != 32

The fixed-width reference funnel emits whole 4-byte beats.

(1 << ATB_BYTES_WIDTH) < 4

ATBYTES must be able to encode a full beat.

ATDATA_WIDTH % (MDO_WIDTH + MSEO_WIDTH) != 0

A beat must carry an integer number of chunks.

EN_TE_RAW && N_STREAMS > 128

The source tag byte encodes at most 128 channels.

+
+
+

11.3. Control and Status

+
+

The funnel is configured through ports, not through a register block of its own:

+
+ +++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
PortDirectionMeaning

chan_prio[N_STREAMS]

in

Per-channel arbitration priority. 0 disables the channel.

chan_flush_participate[]

in

Whether the channel takes part in a global flush.

chan_flush_req[]

in

Per-channel flush request.

chan_flush_done[]

out

Per-channel flush completion (request still asserted and the source has acknowledged).

global_flush_req

in

Global flush request from the system side.

global_flush_done

out

All participating channels have acknowledged.

chan_te_raw[]

in

Per-channel framing select (quasi-static mirror of that source’s trTeProtocolSel).

te_tag_always, te_tag_resync

in

Source-tag policy of the merged container (see Section 11.9).

atclk, atresetn

in

Single ATB clock domain and active-low reset.

+
+

All input channels and the output channel are synchronous to the same atclk; the funnel contains no clock crossing.

+
+
+

Where software-visible control is wanted, the integration provides it. In the KV260 Trio demonstrator the SoC control region carries a FUNNEL_CTRL register at offset 0x34 whose per-channel fields drive chan_prio and are live-writable, taking effect at the next message boundary (examples/dashboard/gen_regmap.py, entry soc.FUNNEL_CTRL; examples/kv260/trio/rtl/trio_soc_top.sv).

+
+
+ + + + + +
+
Note
+		 +The reference-PIB funnel CSRs (trFunnelArbMode, trFunnelShed*) described in Chapter 12 belong to the PIB implementation and are not part of this build — examples/dashboard/gen_regmap.py states this explicitly. Consequently the funnel has no trFunnelActive bit and does not follow the Trace-Control-Interface component reset/discovery pattern; it is reset by atresetn and disabled by setting every channel priority to 0. +
+
+
+
+

11.4. Packet Detection

+
+

For a Nexus channel, packet boundaries are derived from the chunk-local MSEO bits only.

+
+ ++++ + + + + + + + + + + + + + + + + + + + + +
MSEO valueMeaning for the funnel

START_TRANSMISSION

Start of a packet; the channel enters the in-packet state.

(variable / continuation)

Payload continuation; the beat carries data only while the channel is in a packet.

END_IDLE

End of packet, but only if the channel was in a packet. Outside a packet an END_IDLE chunk is idle, not data.

+
+

The parser folds the chunk states across all chunks of one beat, chunk 0 being the lowest bits and therefore the first chunk on the wire. It relies on the chunk packer’s end-of-message alignment padding (Chapter 10): after an END_IDLE chunk the rest of the beat is padding, so a beat never carries the end of one message together with the start of the next. For MDO_WIDTH = 30 this degenerates to the original single-chunk classification.

+
+
+

Idle beats are consumed and dropped. A beat whose chunks carry no in-packet data — flush padding, repeated END_IDLE outside a packet — is acknowledged on every active channel, not only on the selected one, and is not forwarded. Without this, an unselected source’s ATB queue would wedge behind padding it can never hand on.

+
+
+
+

11.5. Arbitration

+
+

Arbitration is evaluated only between packets. While the selected channel is inside a packet, or has just presented a beat that starts one, the selection is locked (current_locked in the RTL), regardless of what higher-priority channels do in the meantime.

+
+
+

The rules are:

+
+
+
    +
  • +

    A channel is eligible when its priority is non-zero, ATVALID is asserted, and the previewed beat carries data.

    +
    • +
  • +

    Priority levels are scanned from MAX_PRIO down to 1; the first level with an eligible channel wins outright.

    +
    • +
  • +

    Within a level, selection is round-robin. Each level keeps its own round-robin head pointer, which advances past the channel that just completed a packet.

    +
    • +
  • +

    Priority 0 disables the channel entirely — it is neither eligible nor served, though idle-beat dropping still applies.

    +
    • +
+
+
+

This yields deterministic scheduling and prevents starvation between channels of equal priority. A simulation assertion in the RTL checks the invariant that a selected channel never has priority 0 outside an ongoing packet continuation.

+
+
+

In the default configuration all channels carry the same non-zero priority; the funnel then behaves as a plain round-robin, message-atomic funnel and nothing about it is visible to trace tools.

+
+
+
+

11.6. Backpressure

+
+

Only the selected channel observes the downstream ATREADY. All other channels see ATREADY deasserted — except for the idle-beat drop described above, which is the one case in which an unselected channel is acknowledged. Because a channel is only ever switched on a packet boundary, backpressure can delay a packet but can neither fragment it nor reorder it against another packet of the same source.

+
+
+

The output always presents whole beats: ATBYTES is driven to 4 - 1 for a Nexus channel and to 0 (one valid byte) for a reference-raw channel. ATDATA and ATID are forwarded unmodified from the selected input; the funnel inserts no channel markers into a Nexus stream.

+
+
+
+

11.7. Flush

+
+

Flush uses the ATB flush handshake. Because the funnel is an ATB slave toward its sources and an ATB master toward the sink, the signal roles differ on the two sides:

+
+ +++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
SignalSideRole

afvalid

input channel

Driven by the funnel toward the source: flush request to source.

afready

input channel

Driven by the source toward the funnel: flush acknowledge / completion.

afvalid

output

Observed from downstream: external global flush request.

afready

output

Driven by the funnel: global flush completion.

+
+

Semantics:

+
+
+
    +
  • +

    A per-channel flush request (chan_flush_req[i]) raises afvalid toward that source until the source acknowledges with afready; chan_flush_done[i] then reports completion while the request is still asserted. Clearing the request re-arms the channel.

    +
    • +
  • +

    A global flush is raised either by global_flush_req or by the downstream side asserting afvalid. It is propagated to every channel that is both active (priority non-zero) and marked as a participant.

    +
    • +
  • +

    Non-participating channels are treated as immediately done and therefore never block completion. A disabled channel cannot block a global flush.

    +
    • +
  • +

    global_flush_done — and hence the output-side afready — asserts only once all participating channels have acknowledged. A simulation assertion guards this.

    +
    • +
  • +

    Flush never interrupts a packet: switching still happens on packet boundaries only.

    +
    • +
+
+
+
+

11.8. Synchronization Request

+
+

syncreq is broadcast from the output side to all input channels: the funnel drives each channel’s syncreq with the value it observes on atb_out.syncreq. A sink that asks for resynchronization therefore reaches every attached encoder, and each encoder decides for itself how to answer — synchronization remains an encoder-level function (see Chapter 7, synchronization generator). The funnel neither combines nor generates synchronization requests of its own.

+
+
+
+

11.9. Dual-Protocol Operation (E-Trace Reference-Raw Channels)

+
+

With EN_TE_RAW = 1 a channel may be marked chan_te_raw[i] = 1, which tells the funnel that this source emits the E-Trace reference-raw framing produced by ct_L2_te_packetizer: one byte per beat (ATBYTES = 0), a packet being a header byte {1’b0, msg_type[1:0], payload_len[4:0]} followed by payload_len payload bytes. Packet boundaries come from that length field rather than from MSEO, and the framing has no idle beats. A zero-length packet is a complete packet consisting of the header byte alone.

+
+
+

The reference-raw framing carries no source field, and an on-chip ring that stores ATDATA only loses ATID as well. The funnel therefore makes the merged byte stream self-describing by inserting a source tag byte 8’h80 | channel index ahead of a packet. The container is called CTMX. Splitting it yields per-source byte streams that are byte-identical to a single-core capture and are therefore consumable by an unmodified E-Trace reference decoder; the demultiplexer is examples/kv260/trio/tools/etrace_trio_demux.py.

+
+
+

Tag policy:

+
+
+
    +
  • +

    By default a tag is emitted on every source change.

    +
    • +
  • +

    te_tag_always emits a tag before every packet — more overhead, but resynchronizable at any packet boundary.

    +
    • +
  • +

    te_tag_resync is a level input that forgets which source was tagged last, so the next packet carries a tag again. It should be wired to whatever re-arms the capture, otherwise a capture started mid-stream begins without a source tag.

    +
    • +
+
+
+

Payload bytes may themselves have bit 7 set, so the tag is unambiguous only to a state machine that starts at a packet boundary — which is exactly what the demultiplexer does. A tag occupies one output beat during which the input beat is not consumed; the selection stays locked because the pending header beat still asserts start_seen, and the tag is not duplicated if the sink applies backpressure.

+
+
+

Mixed operation is legal: a Nexus MSEO channel and a reference-raw channel may be merged in the same session — the tag disambiguates the reference-raw part, and ATBYTES distinguishes the two framings beat by beat.

+
+
+
+

11.10. Determinism and Ordering

+
+

Packets from one input stream keep their order. Packets from different channels are interleaved according to the arbitration policy, but a packet is never fragmented, never reordered against another packet of the same source, and never altered. Backpressure delays transmission without changing content or order. The merged stream is therefore reconstructible by a decoder that knows the arbitration policy only in the weak sense of "some order" — it does not need to know it at all, because every packet is self-contained and attributed by ATID (Nexus) or by the source tag (reference-raw).

+
+
+
+

11.11. Verification

+
+

Three directed testbenches cover the funnel (rtl/test/):

+
+ ++++ + + + + + + + + + + + + + + + + + + + + +
TestbenchCovers

ct_L1_funnel_tb.sv

Fixed-width reference (MDO_WIDTH = 30, N_STREAMS = 4): packet switching, strict priority, round-robin, ATID/ATBYTES propagation, backpressure, repeated-END_IDLE ignore behaviour, flush handling.

ct_L1_funnel_mdo6_tb.sv

Byte-chunk configuration (MDO_WIDTH = 6, four chunks per beat, N_STREAMS = 2): multi-chunk beat parsing including mid-beat end-of-message with alignment padding, message-atomic round-robin switching, idle-beat drop, switch locking under backpressure.

ct_L1_funnel_teraw_tb.sv

Dual framing (EN_TE_RAW = 1, N_STREAMS = 3): length-prefixed packet parsing, source-tag insertion on source change and in tag-always mode, zero-length packets, packet atomicity across sources, tag beats under backpressure, mixed MSEO/reference-raw operation.

+
+

In addition, the RTL carries non-synthesis assertions for the selected-channel priority invariant, ATREADY exposure on unselected channels, ATDATA/ATBYTES/ATID agreement with the selected input, the source-tag bit-7 property, no channel switch during a packet continuation, the one-byte-per-beat contract of a reference-raw source, and the global-flush completion condition.

+
+
+
+
+
+

12. Parallel Trace Output (PIB)

+
+
+

12.1. Scope

+
+

A Pin Interface Block (PIB) serializes an ATB trace byte stream onto chip pins. It is the Trace PIB Sink component of the RISC-V Trace Control Interface specification (reference 148, Chapter 9), and in either form it is an additive output path: it sits downstream of the encoder’s 32-bit ATB output and changes neither the encoder, nor the core netlist, nor an existing Ethernet/TSN or Aurora datapath.

+
+
+

Two implementations are in play, and a reader building an example needs to know which one is in front of them.

+
+
+
    +
  • +

    The PIB that ships with the examples is examples/kv260/common/ct_soc_pib.sv, a small sink used by eight of the KV260 designs. It is described first, in Section 12.2, because it is what a reader building from this repository gets.

    +
    • +
  • +

    The reference PIB implementation is a fuller component with its own trace funnel, packet-shedding stage and register model. It is not part of this repository and lives in a separate internal engineering project; the rest of this chapter describes it as the design the shipped sink deliberately matches on the wire, so that its hardware adapter fits both.

    +
    • +
+
+
+ + + + + +
+
Important
+		 +The reference implementation brings its own trace funnel (a Trace Control Interface Chapter 8 component with a trFunnel* register block). It is a different implementation from the encoder-side funnel described in Chapter 11, which is port-configured and has no register block. The two should not be confused: trFunnelArbMode and the trFunnelShed* registers described below belong to the reference PIB funnel only, and to no build of this repository. +
+
+
+
+

12.2. The PIB that ships with the examples

+
+

examples/kv260/common/ct_soc_pib.sv is the parallel off-chip trace port of the KV260 examples. Eight designs instantiate it — mbv, duo, trio, rocket_linux, rocket2, cva6_linux, cva6_linux64 and cva6_2 — each with its own pin constraints (examples/kv260/<name>/fpga/*_pib_pmod.xdc).

+
+
+

Four properties define it, and each is stated in its own header:

+
+
+
    +
  • +

    Additive observer. Like the DDR sink, it never back-pressures the trace path. When its small internal FIFO overflows it drops whole beats, and it counts them. A dropped beat is therefore visible as a number, not as a corrupted stream.

    +
    • +
  • +

    Wire format: five pins, a subset of the reference. It implements exactly the reference mode trPibMode = PIB_PAR_4 ("4-bit DDR"), so the existing KR260 PMOD adapter of the reference implementation can be used unchanged. pib_data carries TRC_DATA[3:0] LSB first: the low nibble of each byte is stable around the rising port-clock edge, the high nibble around the falling edge. The forwarded source-synchronous pib_clk has a period of 2^(div_i+1) core clocks — at 75 MHz with div_i = 1 that is 18.75 MHz. div_i = 0 is clamped to 1, so the port clock is at most a quarter of the core clock.

    +
    • +
  • +

    No frame pin. Receivers align on the all-ones idle between messages, using the Nexus MSEO structure — exactly as the reference does. While enable_i is high the port clock keeps running so a receiver can stay locked, and the data lines hold 0xF.

    +
    • +
  • +

    Byte order is capture order. Bytes leave in ATB beat order, byte 0 (bits [7:0]) first — the same order the reference decoder consumes from the on-chip ring. A captured PIB stream is therefore byte-identical to the ring content of the same run, which is what makes the two comparable at all.

    +
    • +
+
+
+

It also implements the three calibration patterns of the reference (STANDARD = AA 55 00 FF per specification table 55 for 4 bits, MOVING_ONE, MOVING_ZERO); while calibration is active the trace input is not consumed. What it does not have is the reference’s funnel, its shedding stage or its register block: the control it needs — enable, clear, divider, calibration — arrives as ports from the example’s own control window (Section 35.3).

+
+
+
+

12.3. The reference PIB implementation

+
+

The remainder of this chapter describes the reference implementation. It is the fuller component — funnel, packet-shedding under overload, a complete register model, further output modes — and it is the design whose wire format the shipped sink matches in one mode.

+
+
+ + + + + +
+
Caution
+		 +None of what follows is part of this repository or of any build produced from it. It is documented here because it is the contract the shipped sink was built against, and because an integrator evaluating the parallel port needs to know what the full component offers beyond the subset. Where a register, a mode or a behaviour below has no counterpart in Section 12.2, it is not available in the examples. +
+
+
+

12.3.1. Block Overview

+
+
+
  N ATB sources --> Trace Funnel --> Packet-Shedding --> PIB Sink --> { PMOD pins | Aurora }
+                    (round-robin /     (overload QoS)     (unpack,
+                     static /                              serialize,
+                     dynamic priority)                     calibrate,
+                                                           DDR/SDR out)
+
+
+
+

The PIB receives trace via ATB (32-bit ATDATA, ATBYTES, ATID, ATVALID/ATREADY backpressure, AFVALID/AFREADY flush, SYNCREQ), transmits least-significant bit and byte first (TRC_DATA[0] = LSB of each beat) and holds the line in the all-ones idle state between messages.

+
+
+

Module decomposition of the reference implementation: pib_pkg, the generated APB3 register block pib_regs, pib_funnel_input / pib_funnel_arb / pib_funnel, pib_atb_unpack, pib_byte_serializer, pib_calib_gen, pib_timebase, pib_ddr_out, pib_sink and the glue level pib_top.

+
+
+
+

12.3.2. Output Modes

+
+

The WARL register field trPibMode selects the pin configuration.

+
+ +++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
trPibModePinsDescription

PIB_OFF (0)

 — 

Outputs held idle.

PIB_PAR_1 (8)

TRC_CLK + 1 TRC_DATA

1-bit parallel.

PIB_PAR_2 (9)

TRC_CLK + 2 TRC_DATA

2-bit parallel.

PIB_PAR_4 (10)

TRC_CLK + 4 TRC_DATA

4-bit DDR, MIPI / Cortex-M parallel-trace style: low nibble on the rising edge of TRC_CLK, high nibble on the falling edge.

PIB_PAR_8 (11)

TRC_CLK + 8 TRC_DATA

Nexus 8-bit direct: TRC_DATA[1:0] = MSEO, TRC_DATA[7:2] = MDO[5:0], one byte per beat. No funnel required on a single-source path.

PIB_PAR_16 (12)

 — 

Encoding reserved; not pinned on the KR260 and rejected by WARL.

+
+

The serial SWT protocols of the specification (Manchester, UART) reserve their mode encodings but are not implemented in this iteration.

+
+
+

Two further fields shape the timing: trPibDivider divides the serialization timebase (input clock / (trPibDivider + 1)), and trPibClkCenter places a TRC_CLK edge at the centre of each TRC_DATA bit period, which halves the effective data rate.

+
+
+

The programming sequence is: set trPibActive, then trPibMode / trPibDivider / trPibClkCenter / trPibCalibrate — at which point TRC_CLK starts while the data stays quiescent — and finally trPibEnable.

+
+
+
+

12.3.3. Clocking and Data Rate

+ ++++ + + + + + + + + + + + + + + + + + + + + +
ClockRole

atb_clk (100 MHz)

ATB ingress, funnel, ingress FIFO and byte-stream formatting. Equal to the encoder’s ATB clock.

pib_clk (200 MHz)

DDR generation clock; clocks the ODDRE1 output stage. One pib_clk period emits two bits per lane.

pib_clk_4x (400 MHz)

Optional, reserved for the fine-grained serializer / phase state machine (sub-byte modes, ClkCenter phase steps). The default build derives all phases from pib_clk.

+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + +
Table 6. Data rate on PMOD #3, LVCMOS33 (source: the reference implementation’s requirements document, "Data-rate summary" — an internal engineering document outside this delivery)
ModeTRC_CLKLane rateGross rate

PIB_PAR_4 (4-bit DDR)

100 MHz

200 Mb/s

800 Mb/s

PIB_PAR_8 (8-bit SDR)

100 MHz

100 Mb/s

800 Mb/s

+
+

These figures are the design targets of the KR260 integration and stay inside the 250 Mb/s per pin limit of the HDIO bank stated in the Kria™ K26 SOM data sheet. They are simulation and constraint figures, not measured link rates (see Section 12.3.12).

+
+
+
+

12.3.4. Calibration Patterns

+
+

With trPibCalibrate = 1 the PIB stops consuming ingress data and emits a repeating pattern selected by trPibCalibPattern:

+
+ ++++ + + + + + + + + + + + + + + + + + + + + +
PatternContent

STANDARD (0)

The pattern the Trace Control Interface specification defines for the active mode (Table 55): AA 55 00 FF for the 1/2/4-bit modes, 66 66 CC 33 for the 8-bit mode.

MOVING_ONE (1)

A walking "1": one set lane stepping across the active TRC_DATA width, all other lanes 0, advancing one lane per beat and wrapping. Recorded as a vendor pattern (FR-CAL-03).

MOVING_ZERO (2)

A walking "0": one cleared lane stepping across the active width, all other lanes 1. Vendor pattern (FR-CAL-04).

+
+

The two moving patterns exist to bring up and de-skew a parallel link on a scope or logic analyzer: a walking bit makes lane order, lane skew and a stuck or swapped lane visible without a decoder.

+
+
+
+

12.3.5. Egress Selection

+
+

trPibEgress routes the trace stream at run time to either the parallel PIB pins (PINS) or an existing Aurora serial link (AURORA). In Aurora egress the parallel pins are held idle. Egress selection is an additive output multiplexer at the PIB stage and does not modify a legacy build-time datapath selection.

+
+
+
+

12.3.6. PIB Sink Status and Overflow

+
+

The sink applies backpressure by deasserting ATREADY when its ingress FIFO cannot accept a full beat; it never accepts a partial beat. If a beat nevertheless arrives while the FIFO is full and not draining, the beat is dropped and the saturating counter trPibNumOverflows increments. trPibFifoMaxFill tracks the maximum fill level in beats. Both counters have a write-1-clear / write-0-rearm bit (trPibFifoMaxFillClear, trPibNumOverflowsClear). trPibEmpty reads 1 when the internal buffers are empty.

+
+
+
+

12.3.7. PIB Funnel: Arbitration

+
+

The PIB funnel aggregates up to NUM_FUNNEL_INPUTS (default 4) ATB sources into one stream. It switches inputs only on a message boundary, so packets from different sources are never interleaved, and a continuous stream on one input does not starve the others. trFunnelArbMode selects between three modes:

+
+
+
    +
  • +

    Round-robin (0) — one whole message per ready input in turn.

    +
    • +
  • +

    Static priority (1) — the input indexed by trFunnelArbPrioInput is served first; the others are served round-robin only while it has nothing pending.

    +
    • +
  • +

    Dynamic priority (2) — at each message boundary the ready input with the highest ingress-FIFO fill wins; ties are resolved round-robin.

    +
    • +
+
+
+

trFunnelDisInput[n] causes input n's data to be read and discarded and excludes it from arbitration. Clearing trFunnelEnable flushes queued trace to the output; trFunnelEmpty reads 1 once all internal buffers are empty. trFunnelGrant reports the currently granted input, and trFunnelFillLevel the fill of the input selected by trFunnelFillSel.

+
+
+
+

12.3.8. PIB Funnel: Overload Packet-Shedding

+
+

Packet-shedding is a graceful-degradation QoS layer: under overload it drops whole low-value messages instead of arbitrary ATB beats, so the stream stays decodable. It works with a single trace source as well as with several — it is a stream filter, not a funnel feature.

+
+
+

Classification. Each message is classified by its Nexus TCODE, taken from the six MDO bits of the message’s first chunk, into the coarse classes SYNC, CF, DF, DAQ and OTHER. trFunnelShedClassMask enables shedding per class (bit 0 = SYNC …​ bit 4 = OTHER); the recommended overload setting sheds CF and DF while keeping SYNC and DAQ. ERROR messages (TCODE 8) are never shed, and ERROR messages from different sources pass independently, distinguished by their SRC field.

+
+
+

Modes and hysteresis. trFunnelShedMode is OFF (nothing is shed), FORCED (always shed per class mask, regardless of fill) or OVERLOAD (shed only while the downstream ingress fill is high). OVERLOAD is a Schmitt trigger on the fill level: shedding starts at trFunnelShedEnterWatermark, stops at trFunnelShedExitWatermark (which must be less than or equal to the enter level) and holds its state in between.

+
+
+

Gap signalling. Every gap is announced in band with a Nexus ERROR message built in exactly the format the encoder uses for its own queue-overrun message — TCODE 8, SRC, ETYPE = QUEUE_OVERRUN, ECODE = the OR of the lost class bits — so a decoder that already handles the encoder’s overflow message handles this one too. trFunnelShedMarkerSrc attributes the gap to the funnel. A gap-open marker is emitted once at the start of each contiguous gap; an optional gap-close marker (trFunnelShedGapCloseEnable) carries ECODE = 0.

+
+
+ + + + + +
+
Caution
+		 +The presence of the SRC field must match the encoder’s trTeControl.InhibitSrc setting — SRC present versus omitted changes the byte layout of the marker. The shedding block builds the marker for the configured layout; a marker built for the wrong layout is not decodable. +
+
+
+

Resume semantics. The classes resume differently, because they differ in how self-contained they are:

+
+
+
    +
  • +

    Control flow is broken by any dropped CF message, so CF non-sync messages stay dropped until a forwarded I-Sync re-establishes the PC. The flag is kept per source (cf_resync_pending[SRC]), so each hart resumes on its own I-Sync while another may still be waiting.

    +
    • +
  • +

    DF, DAQ and OTHER messages are self-contained and resume the instant shedding clears, optionally with a gap-close marker.

    +
    • +
+
+
+

Counters. trFunnelShedDropped (messages, saturating), trFunnelShedGaps (episodes, saturating) and the sticky trFunnelShedOccurred, with a common write-1-clear bit.

+
+
+
+

12.3.9. Register Map Overview

+
+

The PIB block has its own base address in the integration (0xA0A00000 in the KR260 design, APB decode paddr[23:20] == 0xA) and is split into two Trace-Control-Interface components:

+
+ +++++ + + + + + + + + + + + + + + + + + + + +
OffsetComponentCompType

0x0000

Trace Funnel

0x8

0x1000

Trace PIB Sink

0xA

+
+

Both follow the specification’s two-register discovery header (tr??Control at 0x000 with the Active bit, tr??Impl at 0x004 with VerMajor/VerMinor/CompType); the CTTE-specific registers live in the vendor range from 0xE00 upwards. The reference register model is generated from its own SystemRDL by PeakRDL and is never hand-edited; that RDL is authoritative for the reference implementation and the tables in this chapter are a human-readable mirror of it. It is not a source of this repository, and none of these registers exists in a build produced from it.

+
+
+
+

12.3.10. KR260 PMOD #3 Pinout

+
+

For the KR260, the 4-bit DDR output uses PMOD #3 (J19, HDIO bank 46). The Digilent I2C-convention pins (physical pins 3 and 4) are deliberately left reserved so an I2C peripheral can run in parallel.

+
+ +++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
PMOD pinFunctionSOM signalFPGA pinUse

1

GPIO/INT

som240_2_d44

AE12

TRC_CLK, forwarded clock (ODDRE1)

2

GPIO/RST

som240_2_d49

AF11

TRC_DATA[0]

3

SCL

som240_2_d45

AF12

RESERVED — I2C SCL

4

SDA

som240_2_d50

AG11

RESERVED — I2C SDA

7

GPIO

som240_2_d46

AG10

TRC_DATA[1]

8

GPIO

som240_2_c46

AH12

TRC_DATA[2]

9

GPIO

som240_2_d48

AH10

TRC_DATA[3]

10

GPIO

som240_2_c47

AH11

Reserve

+
+

I/O standard LVCMOS33, SLEW FAST, DRIVE 8; the reference implementation carries its own PMOD constraint file; the shipped sink’s constraints are the per-example *_pib_pmod.xdc files named in Section 12.2. DDR data and the forwarded clock both leave through ODDRE1 output registers — the trace clock is never routed to the pin directly from the clock tree. For a TRC_CLK at or above 100 MHz in DDR mode, source-series termination of about 33 Ohm and a cable or adapter shorter than 10 cm are recommended.

+
+
+

The 8-bit Nexus output needs eight data lanes and therefore spans a second PMOD or a Mictor/Samtec adapter; the 4-bit DDR mode fits on PMOD #3 alone with I2C still reserved.

+
+
+
+

12.3.11. Integration

+
+

The block is added as an additional APB slave and taps the encoder’s ATB stream. Funnel input 0 is wired to the encoder’s ATB master; inputs 1..3 are available for further trace encoders and are tied idle on a single-core design. trPibEgress = AURORA routes the PIB’s Aurora ATB master into the existing datapath, = PINS drives the PMOD outputs. The integration is additive: no change to the encoder, the core netlist or the existing datapath, and no change to the carrier card.

+
+
+
+

12.3.12. Implementation and Verification Status

+
+

The reference RTL is verified by self-checking SystemVerilog testbenches under xsim: funnel round-robin fairness, static and dynamic priority, starvation, input disable, flush/empty; serializer bit and byte order for all four widths; idle behaviour; the standard and both moving calibration patterns; 4-bit DDR nibble/edge order and the ClkCenter phase; the 8-bit lane mapping; divider scaling; backpressure, overflow counting and max-fill tracking; the programming sequence; a top-level APB-program-to-pins scoreboard with a DDR sampler model; and corner cases such as partial ATBYTES, back-to-back messages without idle, single-byte messages, odd divider values, a mode change while active, and a flush mid-stream.

+
+ +++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
ItemStatusEvidence

SystemRDL register model

done

the reference implementation’s own RDL and its generated register block

Trace Funnel RTL

done

pib_funnel*, tb_pib_funnel green

PIB Sink RTL

done

pib_sink + unpack / serializer / calib / timebase, tb_pib_sink, tb_pib_serializer green

DDR output stage

done

pib_ddr_out, tb_pib_ddr_out green; ODDRE1 for synthesis

Overload packet-shedding

done

pib_shed, tb_pib_shed green

Top integration

done

pib_top, tb_pib_top green (APB + datapath + pins)

PMOD #3 constraints

done

the reference implementation’s own constraint file

kr260_top integration hook

documented

additive APB slave + ATB tap

Bitstream / hardware bring-up

out of scope of that iteration

 — 

+
+ + + + + +
+
Important
+		 +Simulation is functional evidence only. DDR signal integrity and the 3.3 V LVCMOS timing on the PMOD connector are modelled and constrained, not measured; no on-hardware claim is made for this output path until a bring-up has been logged. A behavioural DDR fallback exists for portable simulation and is not the synthesis path. +
+
+
+
+
+
+
+

13. Trace Format

+
+
+

This chapter describes how execution becomes bytes. Because the encoder can be built with either of two wire formats, the chapter states the protocol split first, then describes each format: for N-Trace the framing that delimits messages on the trace port, the compression applied to program addresses, the meaning of the instruction count and the branch history, and the mapping from a core event to a message; for E-Trace the packet framing and the properties in which it deviates from everything the N-Trace section says. The catalogue of N-Trace message types and their field orders is the next chapter, Chapter 14; this one explains the machinery those messages are built from.

+
+
+

13.1. One Encoder, Two Wire Formats

+
+

CTTE emits one of two on-wire trace formats. Which one a given instance emits is fixed at synthesis, not selected at run time (Section 5.3); the output port atb_te_raw advertises the choice to the downstream transport.

+
+
+
    +
  • +

    N-Trace — Nexus messages per the RISC-V N-Trace specification, framed by the MSEO/MDO scheme. This is the full-featured format: program trace, data trace, instrumentation (Data Acquisition), ownership, error and correlation messages, the vendor configuration message, and the entire compression suite.

    +
    • +
  • +

    E-Trace — te_inst packets per the RISC-V Efficient Trace specification, framed by that specification’s reference-raw byte framing. CTTE’s E-Trace profile is control-flow-only.

    +
    • +
+
+
+

Everything upstream of the back end is shared: filtering, watchpoints, synchronization requests, instrumentation capture and the AXI-Stream export behave identically in both builds. The split concerns only how events become bytes — and therefore which parts of this manual’s format documentation apply:

+
+ +++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
TopicN-Trace buildE-Trace build

Wire-format machinery

Section 13.2 (this chapter)

Section 13.3 (this chapter)

Message / TCODE catalog

Chapter 14

not applicable — packet formats are defined by the E-Trace specification, not by a TCODE catalog

Data Acquisition payload

Chapter 15

not emitted (control-flow-only profile)

In-stream self-identification

Chapter 18 (Vendor Config and Device ID messages)

none — the decoder is configured out of band

Message construction from eTIP events

Chapter 8, generic message generator

Chapter 8, te_inst generator

+
+
+

13.2. N-Trace Wire Format

+
+

Every statement in this section describes the N-Trace back end. One property has to be stated before the format itself, because every statement below is meant to hold for both implementations of it: the N-Trace back end has two serialization paths, and they must produce the same bytes.

+
+
+

13.2.1. Two Serializations, One Format

+
+
    +
  • +

    The historical formatter path (rtl/ct_L2_nexus_formatter.sv into rtl/ct_L2_mseo_mdo_formatter.sv) handles the full message set, including data trace and instrumentation.

    +
    • +
  • +

    The compact packer (rtl/ct_L2_compact_packer.sv) is a lean alternative for control-flow-only builds. Elaboration rejects it in any profile that has data trace or the instrumentation blocks enabled: the lean egress path and the data-flow message formats are mutually exclusive by construction (rtl/ct_L2_compact_packer.sv:85).

    +
    • +
+
+
+

The two paths are not two formats. They are two implementations of one format, and their byte-for-byte equivalence in the profiles where both elaborate is a verification obligation, not an assumption.

+
+
+
+

13.2.2. Framing: MSEO and MDO

+
+

A Nexus trace is a stream of messages, each a sequence of fields. Framing is carried out of band from the payload, in two dedicated bits per chunk:

+
+
+
    +
  • +

    MDO — message data output, the payload bits.

    +
    • +
  • +

    MSEO — message start/end/other, the framing bits.

    +
    • +
+
+
+

A chunk is MDO_WIDTH payload bits plus 2 framing bits. The committed configuration uses a 6-bit MDO, so a chunk is one byte (nexus_vendor_riscv_pkg.sv:136). Multiple chunks are packed into one egress beat; leftover bits of a beat are padded with all ones.

+
+ +++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
MSEONameMeaning

00

start of transmission

First byte of a message. Also every byte occupied by a fixed-length field, and every interior byte of a longer variable-length field.

01

end of variable-length field

The last byte of a variable-length field, with the message continuing.

10

reserved

Reserved for future extensions. Not produced.

11

end of message / idle

The last byte of a message. The same code with all payload bits set — a full 0xFF byte — is an idle byte between messages or a padding byte.

+
+

Source: nexus_vendor_riscv_pkg.sv:450; the generator is
+rtl/mseo_mdo/ct_L2_mseo_mdo_formatter_mseo_controller.sv:63.

+
+
+ + + + + +
+
Note
+		 +On the final chunk of a message the encoder emits the end-of-message code 11 rather than the end-of-field code 01, even when that chunk also ends a variable-length field. This is deliberate compatibility with the decoders in circulation, which terminate the current packet as soon as they see the end-of-message code after a variable field (ct_L2_mseo_mdo_formatter_mseo_controller.sv:73). +
+
+
+

Two MDO widths are implemented: 6 and 14. Any other width aborts
+elaboration in both egress paths
+(rtl/mseo_mdo/ct_L2_mseo_mdo_formatter_bit_slicer.sv:104,
+rtl/ct_L2_compact_packer.sv:88).

+
+
+
+

13.2.3. Field Types and Leading-Zero Suppression

+
+

Every field is one of four kinds, and the distinction is what a decoder needs to know how to read the next bits. The vocabulary is the Nexus standard’s; IEEE-ISTO 5001-2012 Table 4-2 defines variable, vendor-fixed and vendor-variable. The encoder’s own enumeration is nexus_field_type_e (nexus_vendor_riscv_pkg.sv:396); the per-message field lists are in Chapter 14.

+
+
+

Leading-zero suppression applies to every variable-length field. The encoder transmits a field from its least significant bit up to and including its highest set bit, with a minimum length of one bit — an all-zero value therefore occupies one bit, not zero (LengthWoLeadingZeros, nexus_vendor_riscv_pkg.sv:471). A variable-length field ends on a chunk boundary; if the payload does not fill the last chunk, the remaining slice bits are zero-padded and the next field starts in the following chunk.

+
+
+

Two consequences for a consumer:

+
+
+
    +
  1. +

    A field’s transmitted length carries no information about the width of the underlying value. A 12-bit value and a 32-bit value whose upper 20 bits are zero occupy the same bytes. Where that distinction matters — the architectural address width — the fact is transmitted explicitly rather than inferred; see Chapter 18.

    +
    2. +
  2. +

    The value must be zero-extended back to its declared width before being interpreted. This matters most for the instrumentation payload, where a short field is evidence of leading zeros, never of fewer payload elements; see Chapter 15.

    +
    3. +
+
+
+
+

13.2.4. Program Address Compression

+
+

Program addresses on the wire are compressed in two steps, and both are lossless for RISC-V code.

+
+
+

Shift. Instructions are at least half-word aligned, so bit 0 of an
+instruction address is always zero. Every program-trace address is
+right-shifted by one before encoding
+(NEXUS_MSG_PC_ADDR_SHIFT = 1, nexus_vendor_riscv_pkg.sv:36). A
+decoder shifts back.

+
+
+

Exclusive-or against a rolling reference. A non-synchronizing message carries U-ADDR, the exclusive-or of the shifted target address with the shifted address of the previous address-bearing program-trace message. Combined with leading-zero suppression, a branch that stays near the previous one costs very few bits (GetUaddr, nexus_vendor_riscv_pkg.sv:483). A synchronizing message carries F-ADDR, the full shifted address, which re-seats the reference on both sides.

+
+
+

The reference register is kept in shifted coordinates so that the exclusive-or and the emitted values live in the same space (ct_L2_nexus_formatter.sv:196). It is re-anchored by every address-bearing message:

+
+ +++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
TCODEMessageNew reference

9

ProgramTraceSync

current instruction address

11

DirectBranchSync

branch target

4

IndirectBranch

branch target

12

IndirectBranchSync

branch target

29

IndirectBranchHistorySync

anchor address

32

RepeatInstructionSync

loop address

57

Vendor JumpTargetCache

branch target

28

IndirectBranchHistory

branch target

+
+

Source: the per-message arms of ct_L2_nexus_formatter.sv:391-568.

+
+
+

Two messages deliberately do not move the reference, and a decoder must match that: TCODE 3 carries no address at all, and TCODE 56 carries only a count — the decoder resolves the branch targets of a predicted run by walking the code (ct_L2_nexus_formatter.sv:517).

+
+
+ + + + + +
+
Tip
+		 +This is one rolling reference for the whole program-trace stream, not one per message type. Data-trace addresses use a separate reference, with its own re-anchor contract — see below. +
+
+
+
+

13.2.5. Instruction Count

+
+

I-CNT is the field that lets a decoder walk from one message to the next. It counts retired 16-bit instruction units since the last transmitted count: a compressed instruction counts as one, a standard 32-bit instruction as two, and a longer instruction as its number of half-units. The retiring control-transfer instruction is included in the count of the message that reports it. An exception or interrupt is counted only if it occurred after the retirement of the instruction it is attached to.

+
+
+ + + + + +
+
Note
+		 +IEEE-ISTO 5001-2012 Table 4-3 leaves the unit to the architecture: "the actual number of instructions" for fixed-size architectures, or "the number of instruction units" where instructions vary in size. The RISC-V profile fixes that choice to half-words, which is what the encoder implements and what a decoder must assume. +
+
+
+

The internal accumulator has a cap, and the cap is selectable. The default is 8 bits; the wide-count feature raises it to 16 (ct_L2_msg_gen.sv:332). This is an internal cap, not a wire format. The field on the wire is variable-length either way, so raising the cap changes only how often the accumulator has to be drained — long linear code with the narrow cap produces frequent Resource Full messages with the instruction-count reason. That is legal and decodes correctly; it costs bandwidth.

+
+
+

A drain emits Resource Full (TCODE 27) with reason code 0 and the accumulated count, and it emits the accumulated count, not the count plus the pending event. The difference matters: the sum that triggers the drain is by construction larger than the cap, so emitting it would put an over-cap value into a field the specification bounds.

+
+
+
+

13.2.6. Branch History

+
+

In history mode the encoder does not emit a message per conditional branch. It accumulates their outcomes into HIST and transmits the accumulated field with the next message that carries an address.

+
+
+

The accumulation follows IEEE-ISTO 5001-2012 Table 4-3: the register is pre-loaded with a single 1 that acts as a stop bit, a taken branch shifts in a 1, a not-taken branch shifts in a 0 (ct_L2_msg_gen.sv:1371). The stop bit is not part of the history; it tells the decoder where the recorded bits end. An empty history is therefore transmitted as the value 0x1, never as zero.

+
+
+

The field is 30 bits wide including the stop bit (NEXUS_MSG_HIST_WIDTH, nexus_vendor_riscv_pkg.sv:90). When it fills, it is drained by a Resource Full message with reason code 1. The instruction count is deliberately not reset by that drain: it keeps accumulating across the flush, and the next history-bearing message reports the whole span. The decoder subtracts what it walks while resolving the flushed history, so the span is counted exactly once (ct_L2_msg_gen.sv:1383).

+
+
+

Reason code 2 is the repeated-history compression: when the same full history window recurs, the run is closed as one Resource Full carrying the pattern and a repeat count in a second data field, instead of one message per repetition.

+
+
+

One special case is worth naming because it looks like an inconsistency in a capture: when the history holds nothing but the stop bit, a reason-1 drain would transmit the payload 0x1, which the reference decoder discards. The encoder substitutes a reason-0 instruction-count drain instead (ct_L2_msg_gen.sv:857).

+
+
+
+

13.2.7. From Core Event to Message

+
+

The mapping depends on the instruction-trace mode. History mode is the reset value and the bandwidth-lean choice; branch mode exists for decoders and workflows that require a message per branch. The mode is selected at run time through trTeControl.InstMode, and the compression suite is history-mode only — it is inert in branch mode by construction.

+
+ +++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Core eventHistory mode (InstMode = 6)Branch mode (InstMode = 3)

Taken conditional branch

one history bit, no message

DirectBranch (3)

Not-taken conditional branch

one history bit, no message

silent, count accumulates

Inferable jump or call

silent, count accumulates

silent, count accumulates

Return, predicted by the return stack

silent, count accumulates

silent, count accumulates

Return, not predicted

IndirectBranchHistory (28), or JumpTargetCache (57) on a cache hit

IndirectBranch (4)

Uninferable jump or call

IndirectBranchHistory (28) / JumpTargetCache (57)

IndirectBranch (4)

Interrupt

as above, branch type "interrupt"

IndirectBranch (4), branch type "interrupt"

Trap

as above, branch type "exception"

IndirectBranch (4), branch type "exception"

Return from trap

as above, branch type "indirect"

IndirectBranch (4), branch type "indirect"

Synchronization

ProgramTraceSync (9), DirectBranchSync (11), IndirectBranchSync (12), or IndirectBranchHistorySync (29)

9 / 11 / 12, all history-free

Trace off

Correlation (33) with the trace-disabled event

same

Trace on

next message upgraded to a synchronization with the trace-enable reason

same

+
+

Source: the mode arms of ct_L2_msg_gen.sv:1236 (branch mode) and :1332 (history mode).

+
+
+

Two substitutions in history mode replace a message rather than add one, and both require the decoder to run a model in lockstep with the encoder:

+
+
+
    +
  • +

    Jump-target cache. An indirect branch whose target is already in the cache is emitted as TCODE 57 with a cache index in place of the differential address. The reference address still advances to the real target, so later differential addresses stay correct.

    +
    • +
  • +

    Branch prediction. With prediction enabled, direct branches do not accumulate history at all. Both sides run a bit-identical predictor; only a misprediction emits a message, carrying the number of correctly predicted branches before it.

    +
    • +
+
+
+

Return from a trap is mapped to the indirect branch type rather than to the interrupt type. That is deliberate: the interrupt type would attach the handler body’s half-words to a branch type that a consumer reads as "an interrupt happened here" (ct_L2_msg_gen.sv:1616).

+
+
+
+

13.2.8. Data-Flow Mapping

+
+

A retired data access produces a Data Trace message: a read produces TCODE 6, a write TCODE 5 (ct_L2_msg_gen.sv:1843). Each carries the access size in two fields — the total access size and the element size within it — followed by the address and the value.

+
+
+ + + + + +
+
Caution
+		 +The data-trace size fields use the Nexus byte-count code (1, 2, 4, 8 as distinct code points). They are not the same encoding as the size field inside the instrumentation payload, which is a base-two logarithm. The two are easy to confuse and a decoder that swaps them produces plausible-looking nonsense. See Chapter 15. +
+
+
+

Data addresses have their own compression mode and their own reference register, independent of the program-trace reference:

+
+
+
    +
  • +

    Full (the reset value): the address is transmitted unmodified. This is byte-identical to the historical stream.

    +
    • +
  • +

    Exclusive-or: the address is exclusive-ored against the previous data-trace message’s address (GetDaddrXor, nexus_vendor_riscv_pkg.sv:493). No shift is applied — data accesses carry no alignment guarantee.

    +
    • +
+
+
+

In the compressed mode the reference has to be re-seated whenever the decoder may have lost track. The first data-trace message after such an event is emitted as the synchronizing form, TCODE 13 or 14, carrying the full address. The re-anchor events are: any synchronizing control-flow message, the rising edge of data tracing, and any Error message (ct_L2_nexus_formatter.sv:278). The last one is decoder symmetry: the reference decoder invalidates its data-address reference on an Error, so the encoder must re-seat rather than assume.

+
+
+

The upgrade is a substitution at the emission site: the message generator always selects TCODE 5 or 6, and the formatter overwrites the transfer code when the re-anchor condition holds.

+
+
+
+

13.2.9. Timestamps

+
+

When timestamping is enabled, every message carries a timestamp as its last field. Synchronizing messages carry the absolute value; every other message carries the delta since the previously emitted timestamp. The baseline is updated on every emission, so a decoder reconstructs the absolute time by accumulating (ct_L2_nexus_formatter.sv:228).

+
+
+

The set of messages treated as synchronizing for the timestamp is TCODE 9, 11, 12, 29 and 32; the data-trace synchronizing forms 13 and 14 are added by their own condition, because the message generator never selects them directly.

+
+
+

Two messages carry no timestamp at all:

+
+
+
    +
  • +

    The internal flush token, which never reaches the wire anyway.

    +
    • +
  • +

    TCODE 30, the repeat-branch message. This is a decoder constraint rather than an encoder limitation: the reference decoder preserves only the first two fields of the preceding message across a TCODE-30 parse, so a third field would overwrite the saved instruction count of the repeated message and the replay would walk zero instructions (ct_L2_nexus_formatter.sv:692).

    +
    • +
+
+
+

The contrast with TCODE 56 is instructive: it also carries a single count field, but it may carry a timestamp, because to the decoder it is a regular message rather than a replay instruction.

+
+
+

Timestamp width is a build parameter; the field is variable-length and leading-zero-suppressed like every other, so the width bounds the value, not the bytes.

+
+
+
+

13.2.10. Bandwidth Optimizations Not Implemented

+
+

One optimization of the applicable standard chapter is deliberately not implemented: virtual-address most-significant-bit elision. The control field is stubbed and commented out in the SystemRDL. The reason is measurement rather than effort: at 32-bit addresses leading-zero suppression is already byte-minimal, so the elision has no benefit to capture. It becomes relevant with 64-bit addresses.

+
+
+
+
+

13.3. E-Trace Wire Format (te_inst)

+
+

The E-Trace back end emits te_inst packets of the RISC-V Efficient Trace specification — baseline algorithm, instruction trace only. The packet payload formats themselves (format 1 branch map, format 2 differential address, format 3 synchronization and support) are defined by that specification and are not repeated here; Chapter 8 describes how CTTE maps eTIP events onto them. What a consumer of the byte stream needs to know about this implementation is:

+
+
+
    +
  • +

    Framing. ct_L2_te_packetizer (rtl/ct_L2_te_packetizer.sv) applies the specification’s reference-flow raw framing: one header byte {0, msg_type[1:0], payload_len[4:0]} followed by payload_len payload bytes, emitted one byte per ATB beat. A capture of the ATB stream is therefore directly consumable as a raw te_inst file by the reference decoder flow.

    +
    • +
  • +

    Addresses. Address fields are sized by ct_pkg::CT_ETRACE_ADDR_BITS = 31 — a 32-bit instruction address after the specification’s one-bit shift. A 64-bit E-Trace build is rejected at elaboration rather than truncated silently (Chapter 5, genEtrace64).

    +
    • +
  • +

    No instruction count, no MSEO/MDO. E-Trace counts conditional branches in the branch map and re-anchors with full addresses; nothing from the N-Trace section above — I-CNT, HIST, TCODEs, MSEO/MDO framing, the rolling address reference — applies to an E-Trace stream. A composer instruction-count drain arriving on the eTIP is consumed silently (Chapter 8).

    +
    • +
  • +

    No timestamps. The specification’s optional time field is not implemented; te_inst packets carry no time information in this release.

    +
    • +
  • +

    No in-stream self-identification. There is no E-Trace counterpart to the N-Trace Vendor Config message (Chapter 18). A format 3.3 SUPPORT packet reports the qualification status — trace enable, the trace-lost qualifier on a FIFO-overrun recovery, the ended-reporting qualifier at trace-off — but not the build capabilities; an E-Trace decoder is configured out of band.

    +
    • +
  • +

    Sideband requirement. An E-Trace instance requires the eTIP sideband fields (ecause, tval, priv, ilastsize) at full width; a netlist built without them is rejected at elaboration (Chapter 5, genEtraceNoSideband).

    +
    • +
+
+
+

The funnel’s dual-protocol mode transports both framings side by side and keeps them apart by the per-source atb_te_raw advertisement (Chapter 11).

+
+
+
+
+
+

14. N-Trace Message Catalog

+
+
+

This chapter is the complete reference for every transfer code (TCODE) the CEDARtools.TraceEncoder knows. TCODEs exist only on the N-Trace wire; an E-Trace stream carries te_inst packets instead and has no message catalog of its own (Section 13.3). The chapter answers two different questions that the previous revisions of this manual answered only partly, and never in one place:

+
+
+
    +
  1. +

    Decoding. Given a TCODE observed in a captured stream, what is it, which specification defines it, and which fields follow it?

    +
    2. +
  2. +

    Expectation. Given a build and a runtime configuration, which TCODEs can appear at all? A TCODE that never occurs is as much a property of the configuration as one that does.

    +
    3. +
+
+
+
+ + + + + + + + + + +
+
+
+ IEEE-ISTO 5001-2012 +
+ TCODEs 0…63 assigned +
+
+
+ + + IEEE-ISTO 5001-2012... + + + + + + + + + + + +
+
+
+ N-Trace 1.0 profile +
+ Table 9: adopted subset +
+
+
+ + + N-Trace 1.0 profile... + + + + + + + + + + + +
+
+
+ Emitted by CTTE +
+ 16 of 38 enum values +
+
+
+ + + Emitted by CTTE... + + + + + + + + + + + +
+
+
+ Public messages CTTE emits +
+ outside the N-Trace profile: +
+ DeviceID (1), Watchpoint (15), +
+ DataAcquisition (7) +
+
+
+ + + Public messages CTTE emits... + + + + + + + + + + + +
+
+
+ Vendor range 56…62: +
+ BranchPredict (56), +
+ JumpTargetCache (57), +
+ Config (58) +
+
+
+ + + Vendor range 56…62:... + + + + + + + + + + + + +
+
+
+ Present in the enum, +
+ never emitted: +
+ Aux access, Port replacement, +
+ Flush (internal marker) +
+
+
+ + + Present in the enum,... + + + + + + + + + + + + +
+
+
+ profiles +
+
+
+ + + profiles + + + + + + + + + + + + +
+
+
+ implements +
+
+
+ + + implements + + + + + + + + + + + + +
+
+
+ also emitted +
+
+
+ + + also emitted + + + + + + + + + + + + +
+
+
+ extensions +
+
+
+ + + extensions + + + + + + + + + + + + +
+
+
+ assigned, +
+ never emitted +
+
+
+
+ + + assigned,... + + + + + + + + + + Text is not SVG - cannot display + + + + +
+
Figure 10. Message space: Nexus, N-Trace profile and vendor range
+
+
+

A TCODE can be a fully defined Nexus public message and still be Reserved from an N-Trace decoder’s point of view. Values present in the enumeration are not evidence of emission: the Auxiliary Access and Port Replacement range and the internal flush marker are never sent.

+
+
+

Both answers are derived from the register-transfer sources, not from prose. The authoritative places are:

+
+
+
    +
  • +

    rtl/pkg/nexus_vendor_riscv_pkg.sv:168 — the nexus_tcode_e enumeration: the complete set of TCODE constants the design knows.

    +
    • +
  • +

    rtl/ct_L2_nexus_formatter.sv:390 — the per-TCODE field composition of the historical egress path; this is where the on-wire field order is decided.

    +
    • +
  • +

    rtl/ct_L2_compact_packer.sv:255 — the same layouts in the lean control-flow-only egress path. Both paths must produce identical bytes; the equivalence is a verification obligation, not an assumption.

    +
    • +
  • +

    rtl/ct_L2_msg_gen.sv — the message selection: which core event becomes which TCODE.

    +
    • +
+
+
+ + + + + +
+
Note
+		 +The existence of a constant in nexus_tcode_e is not evidence that the encoder emits it. The enumeration also carries values that exist for completeness (the Auxiliary Access and Port Replacement range), values used as internal markers only (NEXUS_MSG_FLUSH), and the two range delimiters of the Nexus vendor space. The Emitted by CTTE column below is derived from the message-generation and formatter arms, not from the enumeration. +
+
+
+

14.1. Specification baseline used in this chapter

+
+

Three primary documents are cited by section and table number:

+
+ +++++ + + + + + + + + + + + + + + + + + + + + + + + + +
Short formDocumentUse in this chapter

IEEE-ISTO 5001-2012

IEEE-ISTO 5001™-2012 v3.0.1, The Nexus 5001 Forum™ Standard for a Global Embedded Processor Debug Interface

Table 4-5 (p. 35) assigns every TCODE value; sections 4.3.1 — 4.3.29 define the message formats; Table 4-3 (p. 31) defines the shared fields (TCODE, SRC, I-CNT, HIST, F-ADDR, U-ADDR, TSTAMP).

N-Trace 1.0

RISC-V N-Trace (Nexus-based Trace) Specification v1.0, ratified 2024-11-21

Table 9 (p. 18) lists the message subset the N-Trace profile adopts; every TCODE not listed there is "Reserved for future extensions of N-Trace specification". Table 24 (p. 33) defines the Correlation message, Table 25 (p. 41) the SYNC field values.

TCI 1.0

RISC-V Trace Control Interface v1.0

The control-register semantics referenced from the Emitted by CTTE column; see Chapter 16.

+
+

The N-Trace profile is deliberately narrower than the Nexus standard it profiles. A TCODE can therefore be a fully defined Nexus Public Message and be Reserved from an N-Trace decoder’s point of view — Device ID (1) and Watchpoint (15) are the two cases where CTTE implements exactly such a message. N-Trace 1.0 Table 9 (p. 18) instructs decoders to ignore Reserved and Vendor Defined messages for program-flow reconstruction and to offer an option to display them or raise a warning; because the MSEO framing is self-delimiting, such a message never breaks the parse.

+
+
+
+

14.2. Complete TCODE catalog

+
+

The table lists all 38 constants of nexus_tcode_e
+(rtl/pkg/nexus_vendor_riscv_pkg.sv:168-219) in numerical order.

+
+
+

Reading the last column. yes = emitted in every build, no runtime knob. conditional = the named compile switch (rtl/pkg/ct_pkg.sv) and, where one exists, the named runtime control must both be set; the runtime reset value is given because it decides what an unconfigured encoder does. no = the design contains no generation arm for this TCODE.

+
+ ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
TCODEName (nexus_tcode_e)Defined inEmitted by CTTE

0

NEXUS_MSG_DEBUG_STATUS

IEEE-ISTO 5001-2012 Table 4-5, section 4.3.1.
+ N-Trace 1.0 Table 9: not listed.

no. No generation arm exists. The message carries a 16-bit status register describing the core’s debug state, and the ingress interface has no source for those bits — all three core adapters tie the debug-related inputs to 0. See Chapter 17 and doc/trace-format.adoc (section "Not yet implemented").

1

NEXUS_MSG_DEVICE_ID

IEEE-ISTO 5001-2012 Table 4-5, section 4.3.2.
+ N-Trace 1.0 Table 9: not listed.

conditional — CT_EN_DEVICE_ID (ct_pkg.sv:187) and trTeControl.SendDeviceId = DID_ONCE (reset DID_NONE, Enable-locked WARL). Emitted on every trace-on edge, ahead of TCODE 58 (ct_L23_preproc_composer_etip.sv:582, ordering assertion a_p4_devid_before_cfg at :2172).

2

NEXUS_MSG_OWNERSHIP_TRACE

IEEE-ISTO 5001-2012 Table 4-5, section 4.3.3.
+ N-Trace 1.0 Table 9: adopted ("Ownership").

conditional — CT_EN_OWNERSHIP (ct_pkg.sv:119) and trTeControl.Context = 1 (reset 0).

3

NEXUS_MSG_PROGRAM_TRACE_DIRECT_BRANCH

IEEE-ISTO 5001-2012 Table 4-5, section 4.3.4.
+ N-Trace 1.0 Table 9: adopted ("DirectBranch").

conditional — branch-trace mode only: CT_EN_BTM (ct_pkg.sv:225) and trTeControl.InstMode = 3 (reset 6 = history mode). ct_L2_msg_gen.sv:1247.

4

NEXUS_MSG_PROGRAM_TRACE_INDIRECT_BRANCH

IEEE-ISTO 5001-2012 Table 4-5, section 4.3.5.
+ N-Trace 1.0 Table 9: adopted ("IndirectBranch").

conditional — branch-trace mode only, same gate as TCODE 3. ct_L2_msg_gen.sv:1299 and :1309.

5

NEXUS_MSG_DATA_TRACE_WRITE

IEEE-ISTO 5001-2012 Table 4-5, section 4.3.17.
+ N-Trace 1.0 Table 9: not listed (data trace is outside the N-Trace program-trace profile).

conditional — CT_EN_DATA_TRACE (ct_pkg.sv:48) and trTeDataControl.DataTracing = 1 (reset 0). ct_L2_msg_gen.sv:1846.

6

NEXUS_MSG_DATA_TRACE_READ

IEEE-ISTO 5001-2012 Table 4-5, section 4.3.17.
+ N-Trace 1.0 Table 9: not listed.

conditional — same gate as TCODE 5. ct_L2_msg_gen.sv:1843.

7

NEXUS_MSG_DATA_ACQUISITION

IEEE-ISTO 5001-2012 Table 4-5, section 4.3.21 — a Public Message, not a vendor extension.

conditional — CT_EN_DAQ (ct_pkg.sv:47). No enable bit: emission is command-driven through the ACT-CAP / ACT-ST command CSR at core CSR address 0x0B10. ct_L2_msg_gen.sv:1865; payload see Chapter 15.

8

NEXUS_MSG_ERROR

IEEE-ISTO 5001-2012 Table 4-5, section 4.3.22.
+ N-Trace 1.0 Table 9: adopted ("Error", ETYPE [4] + ECODE [Var]).

yes — no compile switch, no runtime enable. Used for queue overrun and for the data-trace drop announcement. ct_L23_preproc_composer_etip.sv:1012 and :1514.

9

NEXUS_MSG_PROGRAM_TRACE_SYNC

IEEE-ISTO 5001-2012 Table 4-5, section 4.3.11.
+ N-Trace 1.0 Table 9: adopted ("ProgTraceSync"), and required.

yes. ct_L2_msg_gen.sv:1187 / :1214. The cadence is configurable (trTeControl.InstSyncMode / InstSyncMax); the message itself is unconditional.

10

NEXUS_MSG_PROGRAM_TRACE_CORRECTION

IEEE-ISTO 5001-2012 Table 4-5, section 4.3.12.
+ N-Trace 1.0 Table 9: not listed.

no. No generation arm. The encoder does not emit speculative trace, so there is nothing to correct.

11

NEXUS_MSG_PROGRAM_TRACE_DIRECT_BRANCH_SYNC

IEEE-ISTO 5001-2012 Table 4-5, section 4.3.6.
+ N-Trace 1.0 Table 9: adopted ("DirectBranchSync").

yes — selected when a synchronization coincides with a direct control-flow event. ct_L2_msg_gen.sv:1192.

12

NEXUS_MSG_PROGRAM_TRACE_INDIRECT_BRANCH_SYNC

IEEE-ISTO 5001-2012 Table 4-5, section 4.3.7.
+ N-Trace 1.0 Table 9: adopted ("IndirectBranchSync").

yes — selected when a synchronization coincides with an indirect control-flow event. ct_L2_msg_gen.sv:1195.

13

NEXUS_MSG_DATA_TRACE_WRITE_SYNC

IEEE-ISTO 5001-2012 Table 4-5, section 4.3.18.
+ N-Trace 1.0 Table 9: not listed.

conditional — CT_EN_DF_ADDR_COMPRESS (ct_pkg.sv:164), trTeDataControl.DataAddrCompress = 1 (XOR; reset 0), plus the TCODE-5 gate. Produced by TCODE substitution in the formatter, not by the message generator: ct_L2_nexus_formatter.sv:222 and :569.

14

NEXUS_MSG_DATA_TRACE_READ_SYNC

IEEE-ISTO 5001-2012 Table 4-5, section 4.3.18.
+ N-Trace 1.0 Table 9: not listed.

conditional — same gate as TCODE 13, on the read side.

15

NEXUS_MSG_WATCHPOINT

IEEE-ISTO 5001-2012 Table 4-5, section 4.3.23.
+ N-Trace 1.0 Table 9: not listed.

conditional — CT_EN_WATCHPOINT_MSG (ct_pkg.sv:205; requires CT_EN_ACT), a non-zero trWpMask.WEM (reset 0, Enable-locked) and an ACT-ST command ACT_CAP_ST_WATCHPOINT (command code 14) whose masked result is non-zero. ct_L23_preproc_composer_etip.sv:1040, ct_L2_nexus_formatter.sv:638. See Section 14.3.4.

20

NEXUS_MSG_PORT_REPLACEMENT_OUT

IEEE-ISTO 5001-2012 Table 4-5, section 4.3.24.
+ N-Trace 1.0 Table 9: not listed.

no. Enumeration constant only; no generation arm anywhere in the design.

21

NEXUS_MSG_PORT_REPLACEMENT_IN

IEEE-ISTO 5001-2012 Table 4-5, section 4.3.25.

no. Enumeration constant only.

22

NEXUS_MSG_AUX_READ

IEEE-ISTO 5001-2012 Table 4-5, section 4.3.26.

no. Enumeration constant only. CTTE is a trace source; it does not implement the Nexus read/write-access service.

23

NEXUS_MSG_AUX_WRITE

IEEE-ISTO 5001-2012 Table 4-5, section 4.3.27.

no. Enumeration constant only.

24

NEXUS_MSG_AUX_READ_NEXT

IEEE-ISTO 5001-2012 Table 4-5, section 4.3.28.

no. Enumeration constant only.

25

NEXUS_MSG_AUX_WRITE_NEXT

IEEE-ISTO 5001-2012 Table 4-5, section 4.3.28.

no. Enumeration constant only.

26

NEXUS_MSG_AUX_RESPONSE

IEEE-ISTO 5001-2012 Table 4-5, section 4.3.29.

no. Enumeration constant only.

27

NEXUS_MSG_PROGRAM_TRACE_RESOURCE_FULL

IEEE-ISTO 5001-2012 Table 4-5, section 4.3.8.
+ N-Trace 1.0 Table 9: adopted ("ResourceFull", RCODE [4] + RDATA [Var]).

yes — no switch. Drains a full instruction counter (RCODE 0) or a full history buffer (RCODE 1, and RCODE 2 with a repeat count). Twelve generation sites in ct_L2_msg_gen.sv, the most of any message.

28

NEXUS_MSG_PROGRAM_TRACE_INDIRECT_BRANCH_HISTORY

IEEE-ISTO 5001-2012 Table 4-5, section 4.3.9.
+ N-Trace 1.0 Table 9: adopted ("IndirectBranchHist").

conditional — history mode: trTeControl.InstMode = 6 (the reset value). The workhorse message of the default configuration. ct_L2_msg_gen.sv:1529 / :1580.

29

NEXUS_MSG_PROGRAM_TRACE_INDIRECT_BRANCH_HISTORY_SYNC

IEEE-ISTO 5001-2012 Table 4-5, section 4.3.10.
+ N-Trace 1.0 Table 9: adopted ("IndirectBranchHistSync").

conditional — CT_EN_IBHS (ct_pkg.sv:393) and trTeInstFeatures.InstEnIbhs (reset 0). Without it a synchronization in history mode is carried by TCODE 9 / 11 / 12 and the pending history drains separately. ct_L2_msg_gen.sv:1172.

30

NEXUS_MSG_PROGRAM_TRACE_REPEAT_BRANCH

IEEE-ISTO 5001-2012 Table 4-5, section 4.3.13.
+ N-Trace 1.0 Table 9: adopted ("RepeatBranch", B-CNT [Var]).

conditional — CT_EN_REPEAT_BRANCH (ct_pkg.sv:385) and trTeInstFeatures.InstEnRepeatBranch (reset 0). ct_L2_msg_gen.sv:1759.

31

NEXUS_MSG_PROGRAM_TRACE_REPEAT_INSTRUCTION

IEEE-ISTO 5001-2012 Table 4-5, section 4.3.14.
+ N-Trace 1.0 Table 9: not listed — Reserved for future extensions.

conditional — CT_EN_REPEAT_INSTR (ct_pkg.sv:403) and trTeInstFeatures.InstEnRepeatInstr (reset 0). Enabling it takes the stream outside the N-Trace 1.0 message set; see Section 14.2.1. ct_L2_msg_gen.sv:1786.

32

NEXUS_MSG_PROGRAM_TRACE_REPEAT_INSTRUCTION_SYNC

IEEE-ISTO 5001-2012 Table 4-5, section 4.3.15.
+ N-Trace 1.0 Table 9: not listed — Reserved for future extensions.

conditional — same gate as TCODE 31. ct_L2_msg_gen.sv:1145.

33

NEXUS_MSG_PROGRAM_TRACE_CORRELATION

IEEE-ISTO 5001-2012 Table 4-5, section 4.3.16.
+ N-Trace 1.0 Table 9: adopted ("ProgTraceCorrelation", EVCODE [4]
+ CDF [2]); field detail in N-Trace 1.0 Table 24.

yes for the trace-off event (EVCODE = 4); conditional for the two other events — EVCODE = 0 (debug entry) needs CT_EN_DEBUG_EVENTS (ct_pkg.sv:99), EVCODE = 1 (low-power entry) needs CT_EN_POWER_EVENTS (ct_pkg.sv:100). ct_L2_msg_gen.sv:993, ct_L23_preproc_composer_etip.sv:638.

34

NEXUS_MSG_INCIRCUIT_TRACE

IEEE-ISTO 5001-2012 Table 4-5, section 4.3.19.

no. Enumeration constant only.

35

NEXUS_MSG_INCIRCUIT_TRACE_SYNC

IEEE-ISTO 5001-2012 Table 4-5, section 4.3.20.

no. Enumeration constant only.

36

NEXUS_MSG_FLUSH

IEEE-ISTO 5001-2012 Table 4-5: TCODE 36 falls in the Reserved range 36 — 55.

no — internal marker, never on the wire. The message generator produces it (ct_L2_msg_gen.sv:1874) as a pipeline token; both egress paths recognise it and drop it before serialization (ct_L2_mseo_mdo_formatter.sv:174 and :213, ct_L2_compact_packer.sv:199). It triggers the ATB flush handshake; no byte of it reaches the trace port.

56

NEXUS_MSG_VENDOR_BRANCH_PREDICT

IEEE-ISTO 5001-2012 Table 4-5: Vendor-Defined Message range 56 — 62.
+ N-Trace 1.0 Table 9: "56..62 Designated for use by Vendor Defined messages".

conditional — CT_EN_BP (ct_pkg.sv:387) and trTeInstFeatures.InstEnBranchPrediction (reset 0). Requires a decoder running the bit-identical predictor model. ct_L2_msg_gen.sv:1820.

57

NEXUS_MSG_VENDOR_JUMP_TARGET_CACHE

Vendor-Defined Message range 56 — 62 (as above).

conditional — CT_EN_JTC (ct_pkg.sv:386) and trTeInstFeatures.InstEnJumpTargetCache (reset 0). Requires a decoder mirroring the cache. ct_L2_msg_gen.sv:1525 / :1576.

58

NEXUS_MSG_VENDOR_CONFIG

Vendor-Defined Message range 56 — 62 (as above).

conditional — CT_EN_CONFIG_MSG (ct_pkg.sv:120) and trTeControl.SendConfig other than CFG_NONE. This is the one message whose full-profile reset is not "off": SendConfig resets to CFG_ONCE. See Chapter 18.

62

NEXUS_MSG_VENDOR_1_END

Upper bound of the Vendor-Defined Message range (IEEE-ISTO 5001-2012 Table 4-5).

no. Range delimiter, not a message.

63

NEXUS_MSG_VENDOR_EXT

IEEE-ISTO 5001-2012 Table 4-5: Vendor-Defined Extension Message, TCODE 63 (0x3F).

no. Enumeration constant only.

+
+

14.2.1. What the reset configuration produces

+
+

Read down the Emitted by CTTE column with every runtime control at its reset value and the committed full build profile. The message set that can occur is then TCODE 8, 9, 11, 12, 27, 28, 33 and 58 — and nothing else. Every one of those except 58 is adopted by N-Trace 1.0 Table 9; TCODE 58 is a Vendor-Defined message and therefore conformant use of the vendor range, but a decoder that ignores it loses the self-description. Set SendConfig = CFG_NONE for a stream that contains adopted TCODEs only.

+
+
+

That is the point of the reset values: an encoder nobody configured produces a stream a stock N-Trace decoder can read. Every message type that leaves that envelope has to be switched on deliberately, twice — once at build time and once at run time.

+
+
+

The messages that leave the N-Trace 1.0 message set when enabled are TCODE 5/6/13/14 (data trace), 7 (Data Acquisition), 15 (Watchpoint), 1 (Device ID), 31/32 (Repeat Instruction) and the vendor TCODEs 56/57/58. For 5/6/7/13/14/15/1/31/32 the relevant statement is narrow and checkable: they are defined Nexus Public Messages (IEEE-ISTO 5001-2012 Table 4-5) that N-Trace 1.0 Table 9 does not list. Only 56/57/58 are Accemic-defined message formats, and they sit in the range the Nexus standard reserves for exactly that purpose.

+
+
+
+
+

14.3. On-wire field order

+
+

The tables below give the field sequence as the formatter emits it, first field first. All messages are transmitted least significant bit first (IEEE-ISTO 5001-2012 Table 4-2, "Message Transmission Order").

+
+
+

Two fields are governed globally and are therefore not repeated in every row:

+
+
+

SRC. Inserted as the second field of every message unless
+trTeControl.InhibitSrc is set, and never for the internal flush token
+(ct_L2_nexus_formatter.sv:380). Its value is
+trTeInstFeatures.SrcID, its width trTeInstFeatures.SrcBits.

+
+
+

TSTAMP. Appended as the last field of every message when trTsControl.Enable is set, with two exceptions: the internal flush token, and TCODE 30 (ct_L2_nexus_formatter.sv:698). Synchronizing messages carry the absolute timestamp, every other message the delta to the previously emitted TSTAMP; the baseline is updated on every emission. The set of TCODEs treated as synchronizing for this purpose is 9, 11, 12, 29 and 32 (ct_L2_nexus_formatter.sv:253); TCODE 13/14 are additionally synchronizing for the data-address reference (nexus_vendor_riscv_pkg.sv:544).

+
+
+

The reason TCODE 30 carries no timestamp is a decoder constraint, not an encoder limitation: the reference decoder preserves only the first two fields of the preceding message across a TCODE-30 parse, so a third field would overwrite the saved instruction count of the repeated message (ct_L2_nexus_formatter.sv:692).

+
+
+

14.3.1. Program-trace messages

+ +++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
TCODEMessageField sequence after TCODE and SRC

3

DirectBranch

ICNT

4

IndirectBranch

BTYPE, ICNT, UADDR

9

ProgramTraceSync

SYNC, ICNT, F-ADDR (current address)

11

DirectBranchSync

SYNC, ICNT, F-ADDR (next address)

12

IndirectBranchSync

SYNC, BTYPE, ICNT, F-ADDR (next address)

27

ResourceFull

RCODE, RDATA0; plus RDATA1 if and only if RCODE = 2

28

IndirectBranchHist

BTYPE, ICNT, UADDR, HIST

29

IndirectBranchHistSync

SYNC, BTYPE, ICNT, F-ADDR, HIST

30

RepeatBranch

B-CNT (no TSTAMP — see above)

31

RepeatInstruction

R-CNT, ICNT, HIST

32

RepeatInstructionSync

SYNC, R-CNT, ICNT, F-ADDR, HIST

33

ProgramTraceCorrelation

EVCODE (4 bit), CDF (2 bit, always 1), ICNT, HIST

56

Vendor BranchPredict

B-CNT (count of correctly predicted direct branches)

57

Vendor JumpTargetCache

BTYPE, ICNT, cache index, HIST

+
+

Source: ct_L2_nexus_formatter.sv:391-568. The HIST and B-CNT payloads travel in the internal rdata0 / rdata1 slots of the control-flow message structure; the debug field names of nexus_field_name_e therefore read RDATA0 / RDATA1 where the specification says HIST / B-CNT / R-CNT.

+
+
+

For TCODE 33 the CDF field is emitted as the constant 2’b01 and the HIST field is always present, encoded as 0x1 when the history is empty.

+
+
+

In history mode (HTM) this matches the specification. N-Trace 1.0 Table 24 requires CDF = 1 in history mode "even if HIST field is empty, encoded as 0x1", so a decoder need not read CDF to know the field exists.

+
+
+ + + + + +
+
Caution
+		 +In branch mode (BTM) this is a deviation. Table 24 specifies CDF = 0 there, and the encoder emits 2’b01 regardless of mode (verified in the RTL). A third-party decoder that dispatches on CDF will misread the correlation message in BTM. Because the HIST field is present in either case, a decoder that reads the field unconditionally — as the reference decoder does — is unaffected. The deviation is listed in Chapter 33. +
+
+
+

For TCODE 57 the cache index replaces the differential UADDR of TCODE
+28. The address reference still advances to the real branch target, so subsequent UADDR differences remain correct; a decoder must mirror the cache to follow (ct_L2_nexus_formatter.sv:526).

+
+
+
+

14.3.2. Data-trace and instrumentation messages

+ +++++ + + + + + + + + + + + + + + + + + + + + + + + + +
TCODEMessageField sequence after TCODE and SRC

5 / 6

DataTraceWrite / Read

DSZ, ELSZ, address slot, DQDATA

13 / 14

DataTraceWrite / ReadSync

DSZ, ELSZ, ADDR (full address), DQDATA

7

DataAcquisition

IDTAG (12 bit, fixed), DQDATA

+
+

Source: ct_L2_nexus_formatter.sv:569-607. The address slot of TCODE 5/6 carries the unmodified address while trTeDataControl.DataAddrCompress is FULL (the reset value), and the exclusive-OR against the previous data-trace address in mode XOR. The first data-trace message after a re-anchor event is upgraded to TCODE 13/14 carrying the full address, which re-seeds the reference on both sides. The DAQ payload layout is described in Chapter 15.

+
+
+
+

14.3.3. Context, identification and error messages

+ +++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
TCODEMessageField sequence after TCODE and SRC

1

DeviceID

DEVID

2

OwnershipTrace

PROCESS

8

Error

ETYPE (4 bit), ECODE (8 bit)

15

Watchpoint

WPHIT

58

Vendor Config

CFGVER (4 bit, fixed), CAPS, ENAB, PARAM0, PARAM1, PARAM2, PARAM3

+
+

Source: ct_L2_nexus_formatter.sv:609-682. The PROCESS payload is the
+packed structure {CONTEXT, V, PRV, FORMAT}, least significant field
+first, per nexus_process_t
+(nexus_vendor_riscv_pkg.sv:297). The TCODE-58 payload is documented
+field by field in Chapter 18.

+
+
+
+

14.3.4. Watchpoint (TCODE 15) — the bridge from ACT-ST into the stream

+
+

TCODE 15 is the message that makes a hardware watchpoint hit visible in the trace stream by identity rather than by mere occurrence. The distinction matters for a consumer:

+
+
+
    +
  • +

    The trigger path (trTeControl.InstTrigEnable, and the Trace Control Interface action 4) marks that something fired, by upgrading the next synchronization to SYNC = 6 (Trace Event).

    +
    • +
  • +

    TCODE 15 names which watchpoint fired, in a bitmap.

    +
    • +
+
+
+

The WPHIT payload is the bitwise AND of the command’s DirectData[15:0] and the mask trWpMask.WEM, computed in the composer so that the formatter receives the already reportable set (ct_L2_nexus_formatter.sv:638). Two consequences follow:

+
+
+
    +
  1. +

    The bit-to-slot assignment is a software convention. Software gives each watchpoint table entry the DirectData bit it wants to see and enables that bit in WEM. The hardware imposes no mapping.

    +
    2. +
  2. +

    A command whose masked result is zero emits nothing. With the reset value WEM = 0 the feature is byte-neutral until software opts in.

    +
    3. +
+
+
+

The internal payload width is 16 bits
+(NEXUS_MSG_WPHIT_IMPL_WIDTH, nexus_vendor_riscv_pkg.sv:76),
+matching the 16 mask bits of trWpMask.WEM. The on-wire field is
+variable-length with leading zeros stripped, so the width bounds the
+internal payload, not the wire.

+
+
+ + + + + +
+
Note
+		 +IEEE-ISTO 5001-2012 contains a conflict in its own description of this message: the prose of section 4.3.23 describes the WPHIT field as "masked by 1", which reads as an inverted mask, while Table B-26 defines WEM as "1 = enabled". CTTE follows Table B-26 — a 1 enables reporting. A consumer written against the prose reading would invert the mask. +
+
+
+
+
+

14.4. Enumerated field values

+
+

14.4.1. SYNC — synchronization reason

+
+

nexus_sync_reason_e, rtl/pkg/nexus_vendor_riscv_pkg.sv:246. Reference: N-Trace 1.0 Table 25 (p. 41).

+
+ ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
ValueNameEmittedMeaning / gate

0

External Trace Trigger

conditional

CT_EN_EVTI; a pulse on the external-trigger input while tracing.

1

Exit from Reset

yes

First synchronization after a reset that did not stop the core.

2

Periodic Synchronization

yes

The cadence configured by trTeControl.InstSyncMode / InstSyncMax. Required by N-Trace 1.0 Table 25.

3

Exit from Debug Mode

conditional

CT_EN_DEBUG_EVENTS. Required by N-Trace 1.0 Table 25 where debug mode is observable.

4

Sequential Instruction Counter

conditional

CT_EN_SEQ_SYNC and trTeControl.InstSeqSyncEnable (reset 0). N-Trace 1.0 Table 25 marks this code "Not required"; the binding to branch-trace mode is stated in the instruction-count section, not in the table itself. using it in history mode as a full synchronization, instead of the leaner instruction-count drain, is a deliberate deviation — see Chapter 4.

5

Trace Enable

yes

Re-anchor after a trace gap — software pause, filter region entry.

6

Trace Event

conditional

CT_EN_TRIG_SYNC and trTeControl.InstTrigEnable.

7

Restart from FIFO overrun

yes

First synchronization after an announced loss. Required by N-Trace 1.0 Table 25.

8

Reserved

no

Reserved for future standard use (N-Trace 1.0 Table 25).

9

Exit from Powerdown

conditional

CT_EN_POWER_EVENTS.

10, 11

Reserved / Message Contention

no

11 is defined in the enumeration but has no generation site; 10 is reserved for future standard use.

12, 13

Reserved

no

Reserved for future standard use (N-Trace 1.0 Table 25). Earlier CTTE revisions used these two codes for vendor sync requests; that was corrected — see the note below.

14

Explicit sync request

conditional

CT_EN_INST_SYNC_REQ. Vendor-defined code (N-Trace 1.0 Table 25 assigns 14..15 to vendor codes). Covers all request sources — control register, ACT-CAP command, trace-port request; the source is read back from trTeSyncStatus.SyncReqSource.

15

(no sync)

no

Internal marker, never on the wire.

+
+ + + + + +
+
Note
+		 +The collapse of the three former CTTE request codes into the single vendor code 14 was a deliberate correction: N-Trace 1.0 Table 25 reserves 10..13 for future standard use and assigns only 14..15 to vendors, and the request source is irrelevant to a decoder because every synchronization is a full re-anchor. The source remains readable for diagnosis in trTeSyncStatus.SyncReqSource (nexus_vendor_riscv_pkg.sv:238). +
+
+
+
+

14.4.2. RCODE — Resource Full reason

+
+

nexus_rcode_e, rtl/pkg/nexus_vendor_riscv_pkg.sv:262.

+
+ +++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
ValueNameOn the wire

0

I-CNT overflow

yes — RDATA0 carries the drained instruction count.

1

HIST overflow

yes — RDATA0 carries the drained history.

2

HIST overflow, repeated

yes — RDATA0 carries the history, RDATA1 the repeat count. This is the only RCODE that adds a second data field.

3, 4, 5

internal correlation markers

no. Composer-to-generator markers that request a Correlation message (TCODE 33) with a specific EVCODE; they are consumed by the message generator and never leave it.

15

none

no. Debug value.

+
+

Only RCODE 0, 1 and 2 occur on the wire
+(nexus_vendor_riscv_pkg.sv:252).

+
+
+
+

14.4.3. EVCODE — Correlation event

+
+

rtl/pkg/nexus_vendor_riscv_pkg.sv:268. Reference: N-Trace 1.0 Table 24 (p. 33).

+
+ +++++ + + + + + + + + + + + + + + + + + + + + + + + + +
ValueNameEmitted

0

Entry into Debug Mode

conditional — CT_EN_DEBUG_EVENTS. N-Trace 1.0 Table 24 marks this "Required (do not send 4 instead!)".

1

Entry into Low-power Mode

conditional — CT_EN_POWER_EVENTS. Optional per Table 24.

4

Program Trace Disabled

yes — the trace-off event. Optional per Table 24.

+
+
+

14.4.4. BTYPE — branch type

+
+

nexus_btype_e, rtl/pkg/nexus_vendor_riscv_pkg.sv:277:
+0 = indirect branch, 1 = exception or interrupt, 2 = exception,
+3 = interrupt. The message generator maps interrupt-class retirements to
+3 and trap-class retirements to 2
+(ct_L2_msg_gen.sv:1177).

+
+
+

For a non-control-flow synchronization the encoder emits BTYPE = 0. N-Trace 1.0 section 8.4 sanctions this explicitly ("B-TYPE=0 …​ will not mean indirect flow change").

+
+
+
+

14.4.5. ETYPE and ECODE — error message

+
+

nexus_etype_e and the NEXUS_ECODE_* constants,
+rtl/pkg/nexus_vendor_riscv_pkg.sv:319 and :321.

+
+
+

ETYPE is 4 bits: 0 = queue overrun caused one or more messages to be lost, 1 = contention with higher-priority messages caused loss.

+
+
+

ECODE is an 8-bit bitmap naming the class of message that was lost:

+
+ ++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Bit valueLost message class

0x01

Watchpoint message

0x02

Data-trace message

0x04

Control-flow message

0x08

Ownership message

0x10

Status message

0x20

Data-acquisition message

0x40

In-circuit-trace message

0x80

Vendor message

+
+ + + + + +
+
Important
+		 +ECODE = 0x02 is used twice with different consequences. As part of the generic overflow path it announces lost data-trace messages and is followed by a SYNC = 7 re-anchor. As the data-drop policy announcement it is emitted without a re-anchor, because the instruction trace was not lost and must not be forced to re-anchor for a shed data-trace message. A consumer that treats every Error message as a full desynchronization discards exactly the instruction trace this marker promises is intact. Scope the reaction to the data-trace reference. +
+
+
+
+

14.4.6. DSZ and ELSZ — data-trace access size

+
+

nexus_dsz_e and nexus_elsz_e, rtl/pkg/nexus_vendor_riscv_pkg.sv:306 and :314. Both are derived from the ingress access-size code by GetDsz() / GetElsz() (:499 and :516), which map the log2 size 0..3 to 1, 2, 4 and 8 bytes. Access sizes above 8 bytes are not supported by the regular Nexus data-trace messages and are rejected in simulation.

+
+
+
+
+

14.5. Field type vocabulary

+
+

nexus_field_type_e (rtl/pkg/nexus_vendor_riscv_pkg.sv:396) distinguishes four field kinds that a decoder must treat differently. The vocabulary is the Nexus standard’s; IEEE-ISTO 5001-2012 Table 4-2 defines variable, vendor-fixed and vendor-variable.

+
+ ++++ + + + + + + + + + + + + + + + + + + + + + + + + +
KindDecoder consequence

FIXED

Fixed width defined by the standard; always present.

VENDOR_FIXED

Fixed width chosen by the vendor; may be zero-length, in which case it is absent. A tool must learn the width out of band or from the device identification. CTTE transmits the widths it chose in the Config message (Chapter 18), which removes the out-of-band dependency.

VARIABLE

At least one bit; ends on a packet boundary signalled by the framing. Leading zeros are suppressed.

VENDOR_VARIABLE

Variable-length field whose existence is vendor-determined. Normally reserved for the end of a message.

+
+

Leading-zero suppression applies to every variable-length field. A decoder therefore cannot infer a value’s width from the field: a 12-bit value and a 32-bit value whose upper 20 bits are zero occupy the same bytes. Where that distinction matters — the address width — the information is transmitted explicitly, as bit 23 of the CAPS map.

+
+
+
+

14.6. Notes and findings

+ +
+
+
+
+

15. Data Acquisition Payload (DQDATA)

+
+
+

The Data Acquisition message (TCODE 7) is an N-Trace message: CTTE’s E-Trace profile is control-flow-only and has no counterpart to it (Section 13.3). It is how hardware-supported instrumentation reaches the trace stream. A single command from the instrumented program produces one message whose payload carries what the command asked for — a program counter, a data value, a data address, a performance counter, a caller-supplied tag — packed into the DQDATA field.

+
+
+

This chapter defines that packing. It is the one message whose payload a decoder cannot parse from the message alone: the number and meaning of the payload elements follow from the command, and the command is identified by the IDTAG field. Everything a decoder needs to build that table is here.

+
+
+ + + + + +
+
Note
+		 +Which commands carry a payload at all is a property of the core, not of this format. The three data-context commands — DAQ_DATA, DAQ_DADDR and DAQ_DATA_DADDR — need a data beat on the trace ingress port, which only the MINRES TGC5B among the four documented cores delivers; on CVA6, Rocket and MicroBlaze™ V they produce no useful payload, because the encoder never receives one (Section 6.1.3). The commands that report a program counter, a performance counter or a caller-supplied tag are unaffected: their payload comes from the encoder itself. +
+
+
+

15.1. What the standard defines and what CTTE fills in

+
+

The Data Acquisition message is a Nexus Public Message, not a vendor extension. IEEE-ISTO 5001-2012 Table 4-5 assigns it TCODE 7; section 4.3.21 and its Table 4-33 define the format:

+
+ +++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
FieldType per Table 4-33Standard’s description

TCODE

fixed, 6 bits

Value 7.

SRC

vendor-fixed

Client that is the source of the message; may be omitted on single-client targets.

IDTAG

vendor-fixed

"Data ID tag. This specifies which group of data is included in the Data Acquisition Message."

DQDATA

variable

"One or more packets of data values."

TSTAMP

vendor-variable

Timestamp; may be omitted.

+
+

The standard deliberately leaves the payload semantics open: section 4.3.21 states that "usage of the IDTAG is left to the discretion of the instrumentation software and external development tool", and that messages "may also be generated through vendor-defined mechanisms for instrumenting software".

+
+
+

CTTE fills that discretion in as follows, and this is the whole of the CEDARtools-specific part of this message:

+
+
+
    +
  • +

    IDTAG carries the command code of the instrumentation command that produced the message.

    +
    • +
  • +

    DQDATA carries up to three 64-bit elements, whose count and meaning are determined by that command code.

    +
    • +
  • +

    The mechanism that generates the message is the ACT-CAP / ACT-ST command register, reachable from the instrumented program through a core control-and-status register.

    +
    • +
+
+
+

The message is otherwise an ordinary Nexus message: it is framed, timestamped and source-tagged like every other, and a decoder that does not know the command table still parses past it correctly.

+
+
+ + + + + +
+
Note
+		 +N-Trace 1.0 Table 9 does not list TCODE 7, so a strict N-Trace decoder treats it as reserved and skips it by framing. That is a property of the profile, not a defect of the message — data acquisition sits outside the N-Trace program-trace profile in the same way data trace does. +
+
+
+
+

15.2. IDTAG

+
+

IDTAG is a fixed 12-bit field (NEXUS_IDTAG_WIDTH, rtl/pkg/nexus_vendor_riscv_pkg.sv:107), emitted as vendor-fixed (ct_L2_nexus_formatter.sv:599). Being fixed, it is not subject to leading-zero suppression: it always occupies its full 12 bits, whatever the value.

+
+
+

Its value is the command code, taken directly from the command register’s command field (ct_L23_preproc_composer_etip.sv:1062). Software does not set IDTAG separately; it selects a command, and the command code becomes the tag. A caller-supplied identifier does exist, but it rides inside the payload as the direct-data element — see below.

+
+
+
+

15.3. Payload structure

+
+

The payload is a fixed-size vector of three elements, packed least significant element first:

+
+ +++++ + + + + + + + + + + + + + + + + + + + + + + + + +
ElementBit rangeNote

el0

[63:0]

Present in every command that produces a message.

el1

[127:64]

Present in commands with two or three elements.

el2

[191:128]

Present in three-element commands.

+
+

The maximum payload width is 192 bits: three elements of 64 bits
+(MAX_DAQ_DATA_ELEMENTS = 3, rtl/pkg/ct_pkg.sv:906;
+NEXUS_DQDATA_WIDTH = NEXUS_MSG_DATA_WIDTH = 192 when the
+instrumentation or acquisition blocks are built in,
+rtl/pkg/nexus_vendor_riscv_pkg.sv:46 and :106).

+
+
+

Elements the command does not use are zero: the composer clears the whole vector before filling it (ct_L23_preproc_composer_etip.sv:1063).

+
+
+

15.3.1. Leading-zero suppression across the whole payload

+
+

DQDATA is a variable-length field, and the encoder applies leading-zero suppression to the entire concatenated 192-bit vector, not per element (ct_L2_nexus_formatter.sv:600). This has a consequence a decoder must get right:

+
+
+ + + + + +
+
Important
+		 +A short received DQDATA field is evidence of leading zeros, never of fewer elements. A decoder determines the element count from the IDTAG command code, zero-extends the received bits to count x 64, and only then splits the vector into elements. Treating the received length as the payload length produces silently wrong values for any command whose upper elements happen to be small. +
+
+
+

The reverse also holds: a command that uses only el0 still produces a field whose length is decided by the highest set bit of el0, so a zero-valued single-element payload occupies one bit.

+
+
+
+
+

15.4. Layout per command

+
+

The command codes are the enumeration trActCapStCmd_e in rdl/ct_cs_cpuif.rdl. The table gives, for every command that produces a Data Acquisition message, the element assignment as the composer builds it (ct_L23_preproc_composer_etip.sv:1064-1110).

+
+
+

"Direct data" throughout is the 24-bit caller-supplied field of the command word. Its role is the caller’s tag; the value 0 means "no tag" and costs nothing on the wire, because leading-zero suppression removes it.

+
+ ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
CodeCommandElementsPayload

1

DAQ_PC_CURR

2

el0 = current program counter. el1 = direct data.

2

DAQ_PC_CURR_LAST

3

el0 = current program counter. el1 = the last program counter before the most recent exception or interrupt. el2 = direct data.

3

DAQ_DIRECT_DATA

1

el0 = direct data, zero-extended. The minimal command: it records that a point in the program was reached, with a caller-chosen value.

4

DAQ_DATA

3

el0 = the value of the next data access. el1 = its access context (type and size, see below). el2 = direct data. The address is not reported.

5

DAQ_DADDR

3

el0 = the address of the next data access. el1 = its access context. el2 = direct data. The value is not reported.

6

DAQ_DATA_DADDR

3

el0 = value. el1 = address. el2 = context and direct data packed together — the only command whose element carries two things; see the packing below.

8

DAQ_IFETCH_TH

1

el0 = the instruction-fetch threshold counter of the region selected by the low 8 bits of direct data. The counter is cleared afterwards.

9

DAQ_DATA_RD_TH

1

el0 = the read-threshold counter of the selected region, then cleared.

10

DAQ_DATA_WR

1

el0 = the write counter of the selected region, then cleared.

11

DAQ_DATA_RD

1

el0 = the read counter of the selected region, then cleared.

+
+

Three command codes of the same enumeration produce no Data Acquisition message and are listed here only so the table is not read as exhaustive: code 12 requests a synchronization message, code 14 produces a Watchpoint message (see Section 14.3.4), and code 13 sets an encoder control field. All three are excluded from the acquisition arm explicitly (ct_L23_preproc_composer_etip.sv:1057).

+
+
+

15.4.1. The packed context element of command 6

+
+

Command 6 is the only one that needs two payloads in one element, because it already spends el0 and el1 on the value and the address:

+
+ +++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsContentNote

[5:0]

access size

Base-two logarithm of the byte count.

[9:6]

access type

See the type encoding below.

[33:10]

direct data

The caller’s 24-bit tag.

[63:34]

reserved

Zero. A decoder ignores these bits but must tolerate them being set by a future revision.

+
+

Source: pack_daq_context_direct,
+rtl/preproc/ct_L23_preproc_composer_etip.sv:187.

+
+
+

For commands 4 and 5 the same access context occupies its own element, zero-extended: bits [9:0] as above, bits [63:10] reserved.

+
+
+
+

15.4.2. Access type and size

+
+

The access-size field is a base-two logarithm of the byte count: 0 is
+one byte, 1 is two, 2 is four, 3 is eight
+(rtl/pkg/tip_pkg.sv:243).

+
+
+ + + + + +
+
Caution
+		 +This is not the encoding of the DSZ and ELSZ fields of the data-trace messages, which are Nexus byte-count codes where the value is the byte count itself. The two fields describe the same physical property with different encodings, they appear in neighbouring messages of the same stream, and confusing them yields values that look plausible. See Chapter 13. +
+
+
+

The access-type field is four bits, from the ingress type enumeration (rtl/pkg/tip_pkg.sv:200): 0 = load, 1 = store, 4 — 6 = the three control-register access forms, 8 — 14 = the atomic operations, 15 = failed conditional store. Values 2, 3 and 7 are unused.

+
+
+

For a consumer that only needs the direction, the rule is: type 0 is a read, every other value is a write-class access.

+
+
+
+
+

15.5. What a decoder needs

+
+

The message is not self-describing. A decoder needs:

+
+
+
    +
  1. +

    The command table above, keyed by IDTAG, to know the element count and the element meanings. There is no element-count field on the wire; the message consists of exactly TCODE, SRC, IDTAG, DQDATA and TSTAMP (verified against the formatter unit test, which asserts a five-field message, rtl/test/ct_L2_nexus_formatter_tb.sv:574).

    +
    2. +
  2. +

    Zero-extension before splitting — see the suppression rule above.

    +
    3. +
  3. +

    The access-size distinction from the data-trace size fields.

    +
    4. +
  4. +

    Tolerance for reserved bits: a set reserved bit is a newer encoder, not a corrupt message.

    +
    5. +
  5. +

    The convention that direct data 0 means "no tag", so a tag-less event is not reported as a tagged event with tag zero.

    +
    6. +
+
+
+
+

15.6. The same event on the AXI-Stream path

+
+

A command can be routed to the trace port, to the on-chip AXI-Stream egress, or to both. The same event looks different on the two paths, and the difference is not cosmetic:

+
+ +++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Trace port (TCODE 7)AXI-Stream

Payload width

up to 3 x 64 bit

3 x 32 bit (96-bit beat)

Compression

leading-zero-suppressed, variable-length

none; fixed-format beat

Framing

Nexus chunks, interleaved with the trace stream

one beat, no framing

Command identification

IDTAG field

tid signal

Element validity

implied by the command

tstrb: 0xF, 0xFF or 0xFFF for one, two or three elements

Timestamp

TSTAMP field, per the timestamp rules

optional third element on the current-program-counter command, when the corresponding build switch is set

+
+

The AXI-Stream path exists for consumers that process instrumentation inside the fabric, where the bandwidth saved by compression is not worth the decode. See Chapter 17.

+
+
+
+
+
+

16. Register Model

+
+
+

This chapter is the control- and status-register reference of the CEDARtools.TraceEncoder. It returned to this manual in revision 2.0: it had been removed in revision 1.2 on the grounds that the register map was maintained in the public repository, which left three chapters of this manual pointing at an interface description that the manual no longer contained.

+
+
+
+ + + + + + + + + + +
+
+
+ trTe* - trace encoder TCI standard component layout +
+
+
+ + + trTe* - trace encoder TCI stand... + + + + + + + + + + + +
+
+
+ trAtb* - output bridge TCI standard component layout +
+
+
+ + + trAtb* - output bridge TCI standa... + + + + + + + + + + + +
+
+
+ trWp* - watchpoints 1023 slots, indirect access +
+
+
+ + + trWp* - watchpoints 1023 slots, i... + + + + + + + + + + + +
+
+
+ trPerfCnt* - performance counters four banks, range engine +
+
+
+ + + trPerfCnt* - performance counte... + + + + + + + + + + + +
+
+
+ trTeFilter* / trTeComp* +
+ data-flow range filters, comparators +
+
+
+
+ + + trTeFilter* / trTeComp*... + + + + + + + + + + + +
+
+
+ CAPS +
+ what this build contains +
+ (read-only, set at elaboration) +
+
+
+
+
+ + + CAPS... + + + + + + + + + + + +
+
+
+ ENAB - what is switched on +
+ (read/write, resets to 0) +
+
+
+
+ + + ENAB - what is switched on... + + + + + + + + + + + +
+
+
+ Debug IP / software +
+ (integrator-supplied) +
+
+
+
+ + + Debug IP / software... + + + + + + + + + + + + +
+
+
+ configures +
+
+
+ + + configures + + + + + + + + + + + + +
+
+
+ discovery: read before write +
+
+
+ + + discovery: read before write + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+
+
+ gates +
+
+
+ + + gates + + + + + + + + + + Text is not SVG - cannot display + + + + +
+
Figure 11. Register space: components and capability gating
+
+
+

Notation: an asterisk denotes the whole register group with that prefix — trTe* means every register whose name begins with trTe, not a single register called trTe.

+
+
+

CAPS is read-only and fixed at elaboration; ENAB is writable and resets to 0. Software reads CAPS before it writes ENAB.

+
+
+

A feature that was not built has no registers at all — reading zero is not how software detects it.

+
+
+

It returns in a different form. The tables are not written by hand. They are generated from the SystemRDL source that the hardware itself is generated from, so a register that changes in the hardware changes in this manual in the same step or the build fails. The prose around the tables — address spaces, the capability principle, WARL behaviour, the programming order — is written; the numbers are not.

+
+
+

16.1. Source of truth and generation

+
+

rdl/ct_cs_cpuif.rdl in the CEDARtools.TraceEncoder repository is the single source of truth for the register layout. From it, make rdl generates the SystemVerilog register block (rtl/pkg/ct_cs_cpuif.sv, ct_cs_cpuif_pkg.sv, ct_cs_cpuif_types_pkg.sv, ct_cs_cpuif_wb_pkg.sv) and the simulation helper (tests/lib/ct_cs_cpuif_wb_helper.sv); the generated SystemVerilog is committed next to the RDL so the repository builds without the RDL toolchain (rdl/README.md).

+
+
+

The tables in Section 16.7 come from the same file, through scripts/gen_ctte_regs.py in this documentation repository:

+
+
+
+
1
+2
+
make check-generated                   # the gate the documentation build runs
+python3 scripts/gen_ctte_regs.py       # regenerate the fragment
+
+
+
+
+

On Windows the interpreter is called py; make check-generated selects whichever of the two the build host provides.

+
+
+

The generator elaborates the SystemRDL with the systemrdl-compiler, walks the elaborated map in address order and writes src/product_internal/ctte/_generated/registers.adoc. Two runs over the same input produce byte-identical output: nothing time-, host- or path-dependent enters the file. The only provenance stamp is the SHA-256 of the RDL source text, which the generated fragment carries in its header comment — so a reader can tell which revision of the register map a given printed manual describes.

+
+
+ + + + + +
+
Warning
+		 +The --check mode is wired into the documentation build as the check-generated prerequisite of pre-build: a stale fragment breaks the build. The check needs both the RDL source and the systemrdl-compiler package. Where neither is in reach — on a build agent without a working copy of the encoder repository, for instance — the generator exits with code 3 and the build records the check as skipped, with the reason in the log; a missing prerequisite is never reported as drift. The gate therefore holds on the workstations where the fragment is regenerated. Without it, the fragment can fall behind the RDL silently, which is exactly the failure this chapter exists to prevent. +
+
+
+ + + + + +
+
Note
+		 +The first thing this mechanism actually found was not drift. Regenerating the KV260 example tables on 2026-08-24 produced a field with an empty value list, and the cause was a defect in the SystemRDL itself: sink_ctrl.pib_pattern declared the enumeration pib_pattern_e and never assigned it, and in SystemRDL it is the field’s own encode property that binds a type to a field. The defect is invisible everywhere one would look for it — the file compiles, the field reads and writes unchanged, every simulation stays green and the RTL is not affected at all. It shows up only as a missing value list in generated documentation, which is why a documentation generator found it (4feabc2b77c; the same run, with only that one line changed, turns "none of six enumeration strings rendered" into "all six"). The encoder repository now guards the class with make check-rdl-encode (scripts/check_rdl_encode.py). This is also the argument for generating these tables rather than transcribing them, made with a finding instead of a principle: a transcription would have carried the same missing list and nothing would have contradicted it. +
+
+
+
+

16.2. What the generated tables do and do not tell you

+
+

The generated tables state, per field: offset, register, field name, bit range, software access with its qualifiers, reset value, and the description carried in the RDL itself. Four things they deliberately do not state, because the RDL is not where those live:

+
+
+

WARL legalization. Several fields are WARL — write any value, read a legal one. The legalization is not in the generated register block; it lives in the Wishbone adapter rtl/pkg/ct_cs_cpuif_wb.sv, which is hand-written. The RDL descriptions name the rule for each affected field (trTeControl.InstMode, trTeDataControl.DataAddrCompress, trTeControl.SendDeviceId, trTeTrigExtInControl.ExtInAction0), and the rule usually depends on a compile switch: a value is legal if and only if the corresponding feature was built in, otherwise the write is legalized to the safe default. That is the register map’s honest way of reporting an absent option — writing it and reading back tells you whether the netlist has it.

+
+
+

Build-profile omission. The tables show the committed full profile. A slim build regenerates the register block with the profile defines of rdl/ct_profile.inc.rdl (produced from the CT_EN_* switches by scripts/gen_rdl_profile.py). A CT_PROFILE_NO_<X> define turns that feature group’s configuration fields into sw=r constants: storage and write decode vanish, the hardware interface keeps its member with the constant reset value, and reads return the reset value. Two profiles go further and remove registers from the map entirely — CT_PROFILE_NO_SYNC_STATUS omits te.trTeSyncStatus, and CT_PROFILE_NO_FIFO_HIST omits te.trTeTipFifoHistCtrl and te.trTeTipFifoHistData. What a profile does not change is where anything sits: offsets are fixed by the address map, not by the profile, so a slim build has the same addresses as the full one and software compiled against these tables addresses a slim netlist correctly. The difference it sees is the answer, not the address — a compiled-out configuration field reads its reset value and ignores writes.

+
+
+

The Enable lock as a mechanism. The tables mark an Enable-locked field as such, but the lock is a single RDL construct applied in one place: a block of →swwel = te.trTeControl.Enable assignments at the end of rdl/ct_cs_cpuif.rdl. That block is the authoritative list of what may not be written while the encoder is armed. It is census-checked: scripts/check_swwel_census.py counts the write gates in the generated register block against the list, and make lint fails if a field leaves the list without either a lock or a documented reason.

+
+
+

Which register a feature belongs to. The mapping from compile switch to runtime control to capability bit is a separate table, and it lives in Chapter 17 — one row per CT_EN_* switch.

+
+
+
+

16.3. Address spaces and components

+
+

The map is 32-bit-register-wide throughout (default regwidth = 32) and its default access is read-only, so every writable field states its access explicitly. The control interface decodes 15 address bits, i.e. a 32 KiB window (rtl/pkg/ct_cs_cpuif_wb.sv).

+
+
+

It is divided into components, each following the RISC-V Trace Control Interface convention that a component carries a trXxControl register with an Active bit at offset 0x000 of its base and a trXxImpl register with version and component type at 0x004:

+
+ ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
RangeComponentTypeContent

0x0000 — 0x0FFF

te — Trace Encoder

0x1 (N-Trace)

Session control, instruction and data trace configuration, timestamp unit, trigger registers, instruction and data filters, comparators, and the diagnostic status registers.

0x1000 — 0x1FFF

atb — Trace ATB Bridge

0xE (N-Trace)

The egress bridge’s control and implementation pair.

0x3000 — 0x3FFF

pc — Performance Counters

0x3 (vendor)

The performance-counter block and its region registers.

0x4000 — 0x4FFF

wp — Watchpoints (ACT-ST)

0x4 (vendor)

The watchpoint-message mask and the indirect watchpoint-table access window.

0x5000 — 0x7FFF

df — Data-flow range filter

0x5 (vendor)

The range-filter control pair and the external range memory.

+
+

Source: the address-map description in rdl/ct_cs_cpuif.rdl. Components pc, wp and df are CEDARtools extensions and say so in their component type; te and atb follow the Trace Control Interface component numbering.

+
+
+ + + + + +
+
Note
+		 +wp and df appear in the generated tables as registers of the address map rather than of a named group. That is a SystemRDL restriction, not a layout choice: a mem instantiation may not live inside a regfile, and both components own an external memory, so their registers sit as siblings of that memory in the same window. The generator groups them back together by name prefix. +
+
+
+

The convention for reading a component description: a register, field or enumeration value whose description ends in a [CTTE …​] marker — [CTTE specific], or a qualified form such as [CTTE container] — is a CEDARtools extension. Everything else follows the RISC-V N-Trace control interface.

+
+
+
+

16.4. The capability principle: CAPS and ENAB

+
+

A register map alone cannot tell a decoder what the encoder can do, because the decoder sits at the far end of a one-way trace port and never sees the registers. The encoder therefore transmits the same information on the wire, in the Vendor Config message: CAPS is the compiled-in capability map, ENAB the currently enabled subset, one bit per feature at identical bit positions.

+
+
+

The relationship to this chapter is exact and worth stating once:

+
+
+
    +
  • +

    A CAPS bit reports a compile switch — whether the netlist contains the feature at all. Its register-map counterpart is whether the field is writable or a read-only constant.

    +
    • +
  • +

    An ENAB bit reports a runtime control — the value of the field in this chapter’s tables. It is computed as the runtime term ANDed with the CAPS bit, so a feature that is enabled in a register but not built into the netlist can never appear as enabled on the wire.

    +
    • +
  • +

    Six positions have no separate runtime enable and therefore mirror CAPS. Four more use mode selection as the enable: the bit is set when the corresponding field holds a non-default mode rather than by a dedicated enable bit.

    +
    • +
+
+
+

The bit-by-bit definition, the mapping to the register fields of this chapter, and the parameter words P0--P3 are in Chapter 18.

+
+
+
+

16.5. Programming order and the Enable lock

+
+

The register model has a bootstrap order, and it is not a style preference: most configuration fields are locked while the encoder is armed, so a program that arms first and configures afterwards silently loses its configuration writes.

+
+
+
    +
  1. +

    trTeControl.Active = 1. Active gates the encoder’s clock enables. It must stay set for the entire session, including the shutdown polling described in Chapter 17.

    +
    2. +
  2. +

    Configure. Write everything that is Enable-locked: instruction mode, source identification, synchronization cadence, timestamp type and prescale, the compression feature bits of te.trTeInstFeatures, the filters and comparators, the watchpoint mask, the trigger action. All of these are writable only while trTeControl.Enable = 0. Writes after arming are void, and they are void silently — there is no error response.

    +
    3. +
  3. +

    Arm. Set trTeControl.Enable, then trTeControl.InstTracing (and trTeDataControl.DataTracing for data trace).

    +
    4. +
+
+
+

What remains writable while the trace runs is a deliberately short list: the session handles (Active, Enable, InstTracing, DataTracing, InstSyncReq), the status-clear bits (the RW1C overflow flags, the FIFO-histogram controls), the message-class enables (SendConfig, Context, InstSeqSyncEnable, InstTrigEnable), the timestamp run control te.trTsControl, the data-drop policy trTeDataControl.DataDropEna, and the two performance-counter stall thresholds. The performance-counter address ranges next to those thresholds are locked, because a range spans two registers and a mid-trace update would be observable as a nonsense interval.

+
+
+ + + + + +
+
Caution
+		 +Until 2026-08-16 the eight te.trTeInstFeatures.InstEn* bits were not Enable-locked — an omission in the swwel list found by an external register-access audit. They are locked now. Software written against the earlier behaviour, which configured compression features after arming, stops taking effect against a current netlist. This is the one place where the register contract changed in a way a caller can notice. +
+
+
+

trTeControl.Enable also gates tracing implicitly: effective instruction tracing is Enable AND InstTracing. Clearing Enable therefore disables instruction tracing without rewriting InstTracing, and the resulting trace-off edge produces the Correlation message described in Chapter 14. Raising it again is a trace-on edge, which re-triggers the one-shot Device ID and Config messages.

+
+
+
+

16.6. The indirect watchpoint table

+
+

The wp component is the one place where the register model is not a flat map. The ACT-ST watchpoint table has 1023 slots in the committed elaboration — far too many to expose as a register window — so it is reached indirectly through a staging protocol:

+
+
+
    +
  1. +

    Write the slot number to trWpIndex.Idx.

    +
    2. +
  2. +

    Stage the entry through trWpDataLow (address) and trWpDataHigh (command); the write to trWpDataHigh commits the pair.

    +
    3. +
  3. +

    Read the entry back through trWpReadLow and trWpReadHigh.

    +
    4. +
+
+
+

trWpCap reports the implemented capacity, so software discovers the table size rather than assuming it. The staging registers are Enable-locked like the rest of the configuration.

+
+
+

The separate register trWpMask.WEM decides which slots may report a hit as a Watchpoint message; it is a 16-bit mask, and its reset value 0 means no hit is reported until software opts in. The bit-to-slot assignment is a software convention — see Section 14.3.4.

+
+
+ + + + + +
+
Note
+		 +This indirect window replaced a direct 64-bit memory window at 0x4100 and is a breaking change against pre-2026-08 software. The direct window did not scale past the historical 15-slot table. +
+
+
+
+

16.7. Register tables

+
+

The tables below are generated. Do not edit them in this document; edit the SystemRDL and regenerate.

+
+
+

The last generated section, "Declared but not addressable", is not part of the address map. It lists the one register the SystemRDL declares and then hides with ispresent = false: the ACT-CAP command word trActCapStCmd, which exists as a type anchor for the RTL and for the watchpoint table’s command word, and which the encoder does not decode on its control bus at all. It is listed rather than dropped because a reader searching this chapter for that name has to find out why it is missing; its full contract, including the CPU-side CSR address it is reachable at, is in Chapter 20.

+
+
+

The register maps of the example designs are not in this chapter. They are separate SystemRDL sources, generated the same way and under the same drift gate, in Chapter 35.

+
+
+

Register, field and enumeration descriptions in the tables below are reproduced verbatim from the SystemRDL source. For the components that the RISC-V N-Trace specification and the RISC-V Trace Control Interface specification (TCI) define, that description follows the specification’s own text; both specifications are CC BY 4.0 and are credited in the legal appendix. CEDARtools extensions carry a [CTTE …​] marker.

+
+
+
+

16.8. Elaboration parameters

+
+

The register map is parameterised. The values below are the ones the committed SystemRDL elaborates with; a build that overrides a parameter changes the corresponding array length.

+
+ ++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
ParameterValue

NUM_TRACE_FILTER

16

NUM_TRACE_COMPARATORS

8

NUM_PERFCNT_IFETCH_TH_RANGES

3

NUM_PERFCNT_DATA_RD_TH_RANGES

3

NUM_PERFCNT_DATA_RD_RANGES

7

NUM_PERFCNT_DATA_WR_RANGES

7

NUM_ACT_ST

1023

NUM_DF_RANGE

15

MAX_I_FILTER

8

MAX_J_FILTER

8

CSC_COUNTER_DATA_RANGE_COUNT

2

+
+
+

16.9. Component overview

+ +++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BaseComponentRegisters

0

te

32

0x1000

atb

2

0x3000

pc

12

0x4000

wp

9

0x5000

df

2

0x6000

mem1

2

+
+
+

16.10. Component te (base 0)

+
+

Trace Encoder sub-component (N-Trace compliant, CompType=0x1). See RISC-V N-Trace Control Interface spec Table 4.

+
+ +++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
OffsetRegisterFields

0x000

te.trTeControl

16

0x004

te.trTeImpl

5

0x008

te.trTeInstFeatures

10

0x00C

te.trTeInstFilters

1

0x010

te.trTeDataControl

7

0x01C

te.trTeDataFilters

1

0x030

te.trTeProtocolSel

1

0x040

te.trTsControl

7

0x048

te.trTsCounterLow

1

0x04C

te.trTsCounterHigh

1

0x050

te.trTeTrigDbgControl

1

0x054

te.trTeTrigExtInControl

2

0x058

te.trTeTrigExtOutControl

2

0x400

te.trTeFilter[].Control

13

0x404

te.trTeFilter[].Match

2

0x408

te.trTeFilter[].MatchChoiceEcauseLow

1

0x40C

te.trTeFilter[].MatchChoiceEcauseHigh

1

0x410

te.trTeFilter[].MatchValueImpdef

1

0x414

te.trTeFilter[].MatchMaskImpdef

1

0x418

te.trTeFilter[].MatchChoiceData

2

0x600

te.trTeComp[].Control

7

0x608

te.trTeComp[].SMaskLow

1

0x60C

te.trTeComp[].SMaskHigh

1

0x610

te.trTeComp[].PMatchLow

1

0x614

te.trTeComp[].PMatchHigh

1

0x618

te.trTeComp[].SMatchLow

1

0x61C

te.trTeComp[].SMatchHigh

1

0xE00

te.trTeCsrControl

4

0xE04

te.trTeTipFifoStatus

4

0xE08

te.trTeSyncStatus

1

0xE10

te.trTeTipFifoHistCtrl

3

0xE14

te.trTeTipFifoHistData

2

+
+

16.10.1. te.trTeControl — offset 0x000

+
+

Primary control register for the CTTE Encoder

+
+
+
+te.trTeControl bit layout +
+
+ +++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsFieldAccessResetDescription (SystemRDL, N-Trace/TCI)

29:28

SendDeviceId

RW (Enable-locked)

0

Send a Device ID message (Nexus TCODE 1, IEEE-ISTO 5001 4.3.2) carrying the encoder instance’s static identifier (elaboration parameter CT_DEVICE_ID of ct_encoder; layout per ISTO Table B-5 RN | PN | MID), so a stock Nexus decoder learns which device produced the stream without out-of-band setup. Resets to DID_NONE — deliberately UNLIKE SendConfig: N-Trace 1.0 does not adopt TCODE 1 (Table 9), so the default stream stays strictly N-Trace 1.0 and byte-identical to the pre-P4 reference. Requires the CT_EN_DEVICE_ID build switch; profiles without the feature read DID_NONE. Bit position: the CTTE-vendor area above InstSyncReq — bits [13:12] are reserved for the standard TE status/stall fields (trTeInstStallOrOverflow / trTeInstStallEna, see the commented stubs above). [CTTE specific] Values: 0 = DID_NONE; 1 = DID_ONCE.

27

InstSyncReq

WO (self-clearing)

0

Explicit instruction-trace synchronization request (TCI trTeInstSyncReq). Write-1 semantics: the write raises ONE request and the field clears itself in the next cycle, so it always reads back 0. The request is served by the sync generator on the first qualifying retired instruction and appears on the wire as the explicit-request code SYNC = 14 — the same code the ACT-CAP CF_SYNC command and the ATB sync-request input produce, because the source is irrelevant to a decoder (every synchronization message is a full re-anchor). For diagnosis the source is recorded in trTeSyncStatus.SyncReqSource (value 4, SYNC_REQ_TE). Deliberately NOT gated on trTeInstSyncMode: unlike the ATB request (mode 7) this field is itself the trigger and works in every cadence mode. A request written while instruction tracing is paused is DEFERRED, not dropped: it is served after the resume anchor. Request depth is one in flight plus one remembered: a write arriving while a request is still outstanding is NOT swallowed — it is launched as its own request as soon as the outstanding one has been served and produces its OWN synchronization message. Only a write that arrives when a request is already waiting to be launched collapses into it (it asks for what is about to be asked anyway). Measured on the system test (scripts/cli_tesyncreq_test.sh, legs req/req2/req3): one write → 1 SYNC = 14, two writes back to back → 2, three writes back to back → 2. Requires the CT_EN_INST_SYNC_REQ build switch; without it the write is still accepted and still auto-clears, but nothing consumes it (the pre-2026-08 behaviour). [CTTE specific]

26:24

Format

RO

1

Trace recording format. Only accessible on trTeControl. Enable=0 Values: 1 = TR_FORMAT_N.

23:20

InstSyncMax

RW (Enable-locked)

6

Maximum interval between sync messages (2\^(trTeInstSyncMax+4)). The unit follows InstSyncMode: on-wire trace messages (mode 1), hart clock cycles (2), instruction half-words (3), emitted ATB trace bytes (4), wallclock cycles (5) or instructions (6). Resets to 6, i.e. a period of 2\^(6+4) = 1024 units in whichever unit InstSyncMode selects. The reset value matters because the natural programming path is ONE write to trTeControl ('periodic sync, counted in X'), which takes the mode from software and the period from here. 1024 is the knee of the measured cost curve: the periodic sync then costs 2.5 % of the trace stream, while every wider period can save at most those 2.5 % and doubles the blind window of a consumer that attaches mid-stream. The minimum period (0 = every 16 units) costs a factor 2.4 on the same workload and loses trace against a finite sink — it remains available as an explicit stress configuration, but it is not a product default (P0-02; gate tests/instruction/37_sync_cadence — the raw measurement behind those numbers is not part of this repository). Only accessible on trTeControl. Enable=0

19:16

InstSyncMode

RW (Enable-locked)

0

Periodic instruction trace synchronization mode. This field combines bits 17 and 16 (standard trTeInstSyncMode) with the two reserved bits 19 and 18. Only accessible on trTeControl. Enable=0 Values: 0 = ITR_SYNC_OFF; 1 = ITR_SYNC_TRACE_MSG; 2 = ITR_SYNC_CLK_CYCLES; 3 = ITR_SYNC_HALFWORDS; 4 = ITR_SYNC_TRACE_BYTES; 5 = ITR_SYNC_WALL_CLK; 6 = ITR_SYNC_INSTRUCTIONS; 7 = ITR_SYNC_ATB.

15

InhibitSrc

RW (Enable-locked)

1

Add source field to trace message. Only accessible on trTeControl. Enable=0

12

InstStallOrOverflow

RW (WOCLR, hwset, hwclr)

0

Sticky status: set when the encoder generated an OVERFLOW message, i.e. when the eTIP drop path discarded messages and injected the Error(QueueOverrun) marker (N-Trace Required status bit). Write 1 to clear (RW1C); additionally cleared by hardware while trTeControl.Enable = 0, so every trace session starts from a known-clear bit. Pure status — setting or clearing it has NO effect on the wire stream. STALL HALF NOT IMPLEMENTED: the second half of the standard semantics ('or TE requests hart stall') needs a back channel to the hart. The CTTE ingress port (rtl/pkg/tip_if.sv) is UNIDIRECTIONAL — there is no stall/ready signal towards the core — so no CTTE adapter can stall a hart and the companion control bit trTeControl.InstStallEna [13] stays unimplemented (see the commented stub below). The bit therefore reports overflow only. [N-Trace Required, overflow half]

11

InstTrigEnable

RW

0

Enable instruction trace trigger: while set, a pulse on the generic tip.trigger event input upgrades the next retire to a synchronization message with SYNC=6 (Trace Event / watchpoint marker, N-Trace Table 25). Integrators wire tip.trigger to a core watchpoint unit or external trigger fabric; the MBV adapter ties it 0 (integration requirement, see doc/supported_configurations.md).

10

InstSeqSyncEnable

RW

0

Emit a full synchronization message with SYNC=4 (Sequential Instruction Counter) when the internal instruction-count accumulator reaches its cap, instead of the bandwidth-lean ResourceFull(RCODE=0) drain. CAUTION: N-Trace 1.0 allows SYNC=4 only in BTM mode; enabling it in the HTM-only CTTE is a documented Accemic extension (any decoder still treats it as a full re-anchor). Reset 0 = RCODE-0 drains (strictly N-Trace). Applies to the composer-side pre-drain (the dominant path for long linear runs); msg_gen-internal drains stay RCODE-0. [CTTE specific]

9

Context

RW

0

Send Ownership messages (TCODE 2) to indicate processor context: emitted on a context-report ingress event (ctype != 0), on a privilege-level change between retires, and after every synchronizing message (N-Trace 7.1). PROCESS payload = {CONTEXT, V, PRV, FORMAT} per Table 13. [CTTE granularity; TCODE 2 itself is N-Trace standard]

8:7

SendConfig

RW

1

Send NEXUS_MSG_VENDOR_CONFIG (TCODE 58) messages: the encoder describes its compiled-in capabilities and runtime configuration on-wire so a decoder can configure itself from the stream (self-describing trace; payload layout in rtl/pkg/ct_pkg.sv). Resets to CFG_ONCE in the full profile (AW E6, seq 24); profiles without the feature read CFG_NONE. [CTTE specific] Values: 0 = CFG_NONE; 1 = CFG_ONCE; 2 = CFG_ON_SYNC.

6:4

InstMode

RW (Enable-locked)

6

Instruction trace generation mode. Only accessible on trTeControl. Enable=0. WARL: legal values are 6 (ITR_BRANCH_HIST, HTM) always, and 3 (ITR_BRANCH, BTM) iff the CT_EN_BTM build switch is set. With both modes settable, N-Trace Table 8 ('3 OR 6 settable') is fully met. A write of any illegal value is legalized to 6 before it reaches the register; when CT_EN_BTM=0 a write of 3 is likewise legalized to 6 (honest 'BTM unsupported' read-back). Legalization lives in ct_cs_cpuif_wb.sv (the Wishbone adapter), not in this generated block. [CTTE specific] Values: 3 = ITR_BRANCH; 6 = ITR_BRANCH_HIST.

3

Empty

RO (hw-written)

1

Reads as 1 when all generated trace has been emitted

2

InstTracing

RW (hwset, hwclr)

0

Instruction trace generation. Effective instruction tracing is (trTeControl.Enable AND this bit). The 1→0 edge of effective instruction tracing (this bit cleared, or Enable cleared) makes the encoder emit a Program Trace Correlation Message (TCODE 33, EVCODE=Program Trace Disabled) carrying the residual instruction count and branch history, so a decoder can resolve the final instructions up to the trace-off point; the 0→1 edge emits a TRACE_ENABLE synchronization message to re-anchor the decoder. [CTTE specific]

1

Enable

RW

0

1: Trace Encoder is enabled. Allows trTeInstTracing and trTeDataTracing to turn tracing on and off. Setting trTeEnable to 0 flushes any queued trace data to the sink or funnel attached to this encoder. This bit can be set to 1 only by direct writing to it. This write of 1 should be done after all other settings are done. Enable gates instruction and data tracing: effective instruction tracing is (Enable AND trTeInstTracing). Clearing Enable therefore implicitly disables instruction (and data) tracing without rewriting those bits; the resulting instruction-tracing-disabled edge generates the trace-off Program Trace Correlation Message (see trTeInstTracing). [CTTE: the implicit-disable gating is RTL, not an RDL auto-clear.]

0

Active

RW

0

Primary enable/reset for the Trace Encoder

+
+
+

16.10.2. te.trTeImpl — offset 0x004

+
+

Contains version and protocol information for the CTTE Encoder

+
+
+
+te.trTeImpl bit layout +
+
+ +++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsFieldAccessResetDescription (SystemRDL, N-Trace/TCI)

23:20

ProtocolMinor

RO

0

Trace Protocol Minor Version

19:16

ProtocolMajor

RO (hw-written)

1

Trace Protocol Major Version (1 = N-Trace, 2 = E-Trace; driven by the compiled-in back end)

11:8

CompType

RO

1

Trace Encoder Component Type

7:4

VerMinor

RO

0

Trace Encoder Component Minor Version

3:0

VerMajor

RO

1

Trace Encoder Component Major Version

+
+
+

16.10.3. te.trTeInstFeatures — offset 0x008

+
+

Defines the trace instruction features configuration for the CTTE Encoder. Only accessible on trTeControl. Enable=0

+
+
+
+te.trTeInstFeatures bit layout +
+
+ +++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsFieldAccessResetDescription (SystemRDL, N-Trace/TCI)

31:28

SrcBits

RW (Enable-locked)

4

Number of bits in the trace source field Writable only while trTeControl.Enable=0.

27:16

SrcID

RW (Enable-locked)

0xA

TE source ID Writable only while trTeControl.Enable=0.

14

InstEnRepeatInstr

RW (Enable-locked)

0

Emit RepeatInstruction messages (TCODE 31/32) for single-instruction spin loops (a taken branch targeting its own address): iterations after the first are counted and the run closes as ONE message with R-CNT instead of one HIST bit per iteration. CAUTION: TCODE 31/32 are IEEE-ISTO-5001-2012 (4.3.14/15); N-Trace 1.0 keeps them reserved — enabling this makes the stream an Accemic/ISTO extension. Reset 0 keeps the stream strictly N-Trace 1.0. Writable only while trTeControl.Enable=0. [CTTE specific]

13

InstEnIbhs

RW (Enable-locked)

0

Emit IndirectBranchHistorySync messages (TCODE 29): synchronizing messages carry the pending branch history instead of pre-flushing it as a separate ResourceFull(RCODE=1) — one message where two went before (bandwidth win). 0 = historical two-message form. Writable only while trTeControl.Enable=0. [CTTE granularity; TCODE 29 itself is N-Trace standard]

12

InstEnWideIcnt

RW (Enable-locked)

0

Widen the internal ICNT cap from 8 to 16 bit (fewer ResourceFull ICNT drains; wire ICNT stays variable-length per Nexus). Writable only while trTeControl.Enable=0.

11

InstEnRepeatBranch

RW (Enable-locked)

0

Enable RepeatBranch messages (TCODE 30) for identical repeated IndirectBranchHistory messages. Writable only while trTeControl.Enable=0.

8

InstEnRepeatedHistory

RW (Enable-locked)

0

Enable repeated branch history. Writable only while trTeControl.Enable=0.

5

InstEnJumpTargetCache

RW (Enable-locked)

0

Enable jump target cache (vendor TCODE 57: target as cache index instead of UADDR). Writable only while trTeControl.Enable=0.

4

InstEnBranchPrediction

RW (Enable-locked)

0

Enable branch prediction (vendor TCODE 56: mispredict count instead of HIST bits; excludes InstEnRepeatedHistory/InstEnRepeatBranch). Writable only while trTeControl.Enable=0.

3

InstEnImplicitReturn

RW (Enable-locked)

0

Treat returns as inferable PC discontinuities when returning from a recent call on a stack. Writable only while trTeControl.Enable=0.

+
+
+

16.10.4. te.trTeInstFilters — offset 0x00C

+
+

Defines filters for qualifying control flow CTTE generation. Only accessible on trTeControl. Enable=0

+
+
+
+te.trTeInstFilters bit layout +
+
+ +++++++ + + + + + + + + + + + + + + + + + + +
BitsFieldAccessResetDescription (SystemRDL, N-Trace/TCI)

15:0

Filters

RW (Enable-locked)

0

Determine which filters qualify an instruction trace Writable only while trTeControl.Enable=0.

+
+
+

16.10.5. te.trTeDataControl — offset 0x010

+
+

Controls data trace behavior

+
+
+
+te.trTeDataControl bit layout +
+
+ +++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsFieldAccessResetDescription (SystemRDL, N-Trace/TCI)

20

DataSplitLoad

RO (hw-written)

0

Read as 1 if split-load tracing is implemented (sdata/lresp/ldata path). Force to 1 in generated RTL when SPLIT_DATA_ACCESS parameter=1 (see ct_cs_cpuif.sv). [CTTE specific]

19:18

DataAddrCompress

RW (Enable-locked)

0

Data trace address compression mode. 0 = full addresses (reset; byte-identical legacy stream). 1 = XOR against the previous data-trace message’s address; the first DF after a re-anchor event (any synchronizing message, a DataTracing rising edge, any ERROR message, reset) is emitted as the synchronizing TCODE 13/14 form carrying the full address. Modes 2/3 are not implemented (sign/encodability, see the reference manual) — WARL: writes of 2/3 (and of 1 when the CT_EN_DF_ADDR_COMPRESS build switch is 0) legalize to 0. Writable only while trTeControl.Enable=0. Values: 0 = DTR_ADDR_FULL; 1 = DTR_ADDR_XOR.

6

DataDropEna

RW

0

Allow dropping data trace to avoid instruction trace overflows. While set, the encoder suppresses data-trace messages as soon as the eTIP queue fill reaches the drop watermark (ct_pkg::CT_DF_DROP_WATERMARK = 3/4 of the queue depth), so the remaining capacity stays available for the instruction trace. Each drop episode is announced ON THE WIRE by ONE Error message (TCODE 8) with ETYPE = QueueOverrun and ECODE = 0x02 (DataMessageLost) — deliberately WITHOUT the ProgramTraceSync (SYNC=7) re-anchor of the generic overflow path: forcing an instruction re-anchor for every dropped data message would defeat the purpose of the policy. RUNTIME policy, therefore NOT gated by trTeControl.Enable (unlike the configuration fields): software may arm or disarm the drop while the trace is running. Reset 0 = never drop (byte-identical legacy behaviour); reads 0 and is not writable in a build without CT_EN_DF_DROP. Advertised in the vendor config message as CAPS/ENAB bit 22 (DF_DROP).

5

DataDrop

RW (WOCLR, hwset, hwclr)

0

Sticky status: set when the DataDropEna policy actually dropped data-trace messages (one set event per drop episode). Write 1 to clear (RW1C); additionally cleared by hardware while trTeControl.Enable = 0. Reads 0 in a build without the CT_EN_DF_DROP switch (nothing can set it).

3

DataStallOrOverflow

RW (WOCLR, hwset, hwclr)

0

Sticky status: set when data-trace messages were LOST — either because the generic eTIP drop path discarded a beat (the same event that sets trTeControl.InstStallOrOverflow) or because the DataDropEna policy suppressed data-trace messages at the watermark. Write 1 to clear (RW1C); additionally cleared by hardware while trTeControl.Enable = 0. STALL HALF NOT IMPLEMENTED — same reason as trTeControl.InstStallOrOverflow: the ingress port is unidirectional, so the encoder cannot stall a hart and DataStallEna [4] stays unimplemented. [CTTE specific]

1

DataTracing

RW (hwset, hwclr)

0

Data trace is being generated

0

DataImplemented

RO

1

Read as 1 if data trace is implemented

+
+
+

16.10.6. te.trTeDataFilters — offset 0x01C

+
+

Defines filters for qualifying data trace generation. Only accessible on trTeControl. Enable=0

+
+
+
+te.trTeDataFilters bit layout +
+
+ +++++++ + + + + + + + + + + + + + + + + + + +
BitsFieldAccessResetDescription (SystemRDL, N-Trace/TCI)

15:0

Filters

RW (Enable-locked)

0

Determine which filters qualify a data trace Writable only while trTeControl.Enable=0.

+
+
+

16.10.7. te.trTeProtocolSel — offset 0x030

+
+

Active trace protocol: 0 = N-Trace 1.0 (Nexus), 1 = E-Trace 2.0 (te_inst). Read-only discovery of the compiled-in back end (synthesis parameter, per encoder instance).

+
+
+
+te.trTeProtocolSel bit layout +
+
+ +++++++ + + + + + + + + + + + + + + + + + + +
BitsFieldAccessResetDescription (SystemRDL, N-Trace/TCI)

0

Protocol

RO (hw-written)

0

Compiled-in trace protocol of this encoder instance

+
+
+

16.10.8. te.trTsControl — offset 0x040

+
+

Controls the behavior of the timestamp unit

+
+
+
+te.trTsControl bit layout +
+
+ +++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsFieldAccessResetDescription (SystemRDL, N-Trace/TCI)

29:24

Width

RO

0x3F

Width of timestamp in bits (0..63). Only accessible on trTeControl. Enable=0

15

Enable

RW

1

Global enable for timestamp field in trace messages/packets

9:8

Prescale

RW (Enable-locked)

0

Internal timestamp only. Prescale timestamp clock by 2^2n (1, 4, 16, 64). Only accessible on trTeControl. Enable=0

6:4

Type

RW (Enable-locked)

0

Type of Timestamp unit. Only accessible on trTeControl. Enable=0 Values: 0 = TR_TS_NONE; 2 = TR_TS_SYSTEM; 3 = TR_TS_CORE.

2

Reset

RW

0

Internal timestamp only. Write 1 to reset the timestamp counter

1

Count

RW

0

Internal timestamp only. 1: counter runs, 0: counter stopped

0

Active

RW

0

Primary reset/enable for timestamp unit

+
+
+

16.10.9. te.trTsCounterLow — offset 0x048

+
+

Stores the lower 32 bits (bits [31:0]) of the current 64-bit timestamp counter.

+
+
+
+te.trTsCounterLow bit layout +
+
+ +++++++ + + + + + + + + + + + + + + + + + + +
BitsFieldAccessResetDescription (SystemRDL, N-Trace/TCI)

31:0

Value

RO (hw-written)

0

Lower 32 bits (bits [31:0]) of the timestamp counter

+
+
+

16.10.10. te.trTsCounterHigh — offset 0x04C

+
+

Stores the upper 32 bits (bits [63:32]) of the current 64-bit timestamp counter.

+
+
+
+te.trTsCounterHigh bit layout +
+
+ +++++++ + + + + + + + + + + + + + + + + + + +
BitsFieldAccessResetDescription (SystemRDL, N-Trace/TCI)

31:0

Value

RO (hw-written)

0

Upper 32 bits (bits [63:32]) of the timestamp counter

+
+
+

16.10.11. te.trTeTrigDbgControl — offset 0x050

+
+

Vendor-specific setup for RISC-V Debug-Module triggers whose action is a trace action (TCI Table 19). CTTE has no debug-trigger interface: the ingress port carries no mcontrol trigger-hit sideband, so there is nothing to configure. Read-only 0 in every profile; writes are ignored. The register is kept in the map (rather than left unmapped) so a TCI tool gets a defined 'no vendor trigger setup' answer instead of a bus error. [TCI Table 19]

+
+
+
+te.trTeTrigDbgControl bit layout +
+
+ +++++++ + + + + + + + + + + + + + + + + + + +
BitsFieldAccessResetDescription (SystemRDL, N-Trace/TCI)

31:0

TrigDbgSetup

RO

0

Vendor-specific trigger setup. Fixed at 0 (no debug-trigger interface).

+
+
+

16.10.12. te.trTeTrigExtInControl — offset 0x054

+
+

Selects the action performed when an external trigger input fires (TCI Table 20). CTTE implements external trigger input \#0 = the generic tip.trigger event port; inputs \#1..7 do not exist and their action fields are fixed at 0 as the spec prescribes.

+
+
+
+te.trTeTrigExtInControl bit layout +
+
+ +++++++ + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsFieldAccessResetDescription (SystemRDL, N-Trace/TCI)

31:4

ExtInActionN

RO

0

Actions for external trigger inputs #1..7 (4 bits each, same encoding as ExtInAction0). These inputs do not exist in CTTE, so per TCI Table 20 their action fields are fixed at 0.

3:0

ExtInAction0

RW (Enable-locked)

0

Select action to perform when external trigger input \#0 fires. External trigger input \#0 is the generic tip.trigger event port of the ingress interface — the same pulse that the historical trTeControl.InstTrigEnable path consumes. WARL: legal values are 0 (no action), 2 (trace-on), 3 (trace-off) and — only with the CT_EN_TRIG_SYNC build switch — 4 (trace-notify); every other value, and any value at all in a build without CT_EN_TRIG_REGS, is legalized to 0 before it reaches the register (legalization lives in ct_cs_cpuif_wb.sv, not in this generated block). RELATION TO InstTrigEnable (documented deviation): CTTE used InstTrigEnable as the enable of the SYNC=6 notify marker long before this register existed, and that behaviour is UNCHANGED — action 4 is an ADDITIONAL source of the same one-shot, so a configuration with InstTrigEnable = 1 AND Action0 = 4 still produces exactly ONE marker per trigger pulse. Writable only while trTeControl.Enable = 0. Values: 0 = TRIG_ACT_NONE; 2 = TRIG_ACT_ON; 3 = TRIG_ACT_OFF; 4 = TRIG_ACT_NOTIFY.

+
+
+

16.10.13. te.trTeTrigExtOutControl — offset 0x058

+
+

Bitmap selecting which events fire an external trigger OUTPUT (TCI Table 21). CTTE has no trigger output port — adding one would change the encoder’s top-level signal contract — so per TCI Table 21 all event bits are fixed at 0 ('If external trigger output #0 does not exist, then all bits are fixed at 0'). Writes are ignored.

+
+
+
+te.trTeTrigExtOutControl bit layout +
+
+ +++++++ + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsFieldAccessResetDescription (SystemRDL, N-Trace/TCI)

31:4

ExtOutEventN

RO

0

Event bitmaps for external trigger outputs #1..7. Fixed at 0 (outputs do not exist).

3:0

ExtOutEvent0

RO

0

Event bitmap for external trigger output #0. Fixed at 0 (output does not exist).

+
+
+

16.10.14. te.trTeFilter[].Control — offset 0x400

+
+

Enable, input select, function, match mode, inversion and latching

+
+
+
+te.trTeFilter[].Control bit layout +
+
+ +++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsFieldAccessResetDescription (SystemRDL, N-Trace/TCI)

25

Dsize

RW (Enable-locked)

0

When set, match dsize values as specified by trTeFilterMatchChoiceDsize field for filter #i) Writable only while trTeControl.Enable=0.

24

Dtype

RW (Enable-locked)

0

When set, match dtype values as specified by trTeFilterMatchChoiceDtype field for filter #i. Writable only while trTeControl.Enable=0.

16

Impdef

RW (Enable-locked)

0

When set, match impdef values as specified by trTeFilterMatchValueImpdef and trTeFilterMatchMaskImpdef fields for filter #i. Writable only while trTeControl.Enable=0.

15:13

Comp3

RW (Enable-locked)

0

Specifies the comparator unit to use for the 3rd comparison Writable only while trTeControl.Enable=0.

12

MatchComp3

RW (Enable-locked)

0

When set, the output of the comparator selected by trTeFilterComp3 must be true for the filter to match Writable only while trTeControl.Enable=0.

11:9

Comp2

RW (Enable-locked)

0

Specifies the comparator unit to use for the 2nd comparison. Writable only while trTeControl.Enable=0.

8

MatchComp2

RW (Enable-locked)

0

When set, the output of the comparator selected by trTeFilterComp2 must be true for the filter to match Writable only while trTeControl.Enable=0.

7:5

Comp1

RW (Enable-locked)

0

Specifies the comparator unit to use for the 1st comparison. Writable only while trTeControl.Enable=0.

4

MatchComp1

RW (Enable-locked)

0

When set, the output of the comparator selected by trTeFilterComp1 must be true for the filter to match Writable only while trTeControl.Enable=0.

3

MatchInterrupt

RW (Enable-locked)

0

When set, start matching from either an interrupt or exception as specified by trTeFilterMatchValueInterrupt field for filter #i, and stop matching upon return from the 1st matching trap. Writable only while trTeControl.Enable=0.

2

MatchEcause

RW (Enable-locked)

0

When set, start matching from exception cause codes specified by trTeFilterMatchChoiceEcause field for filter #i, and stop matching upon return from the 1st matching exception. Writable only while trTeControl.Enable=0.

1

MatchPrivilege

RW (Enable-locked)

0

When set, match privilege levels specified by trTeFilterMatchChoicePrivilege field for filter #i Writable only while trTeControl.Enable=0.

0

Enable

RW (Enable-locked)

0

Overall filter enable for filter #i Writable only while trTeControl.Enable=0.

+
+
+

16.10.15. te.trTeFilter[].Match — offset 0x404

+
+

Privilege bitmap and interrupt/exception selector. Only accessible on trTeControl. Enable=0

+
+
+
+te.trTeFilter[].Match bit layout +
+
+ +++++++ + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsFieldAccessResetDescription (SystemRDL, N-Trace/TCI)

8

ValueInterrupt

RW (Enable-locked)

0

Interrupt/exception selector for start condition. 0: EXCEPTION_TRAP, 1: INTERRUPT Writable only while trTeControl.Enable=0. Values: 0 = TR_FILTER_MATCHVALUE_EXCEPTION_TRAP; 1 = TR_FILTER_MATCHVALUE_INTERRUPT.

7:0

ChoicePrivilege

RW (Enable-locked)

0

Privilege bitmap; bit N=1 matches priv=N Writable only while trTeControl.Enable=0.

+
+
+

16.10.16. te.trTeFilter[].MatchChoiceEcauseLow — offset 0x408

+
+

Bits 31:0 of Ecause bitmap. Only accessible on trTeControl. Enable=0. Default configuration: Only Bits 0…​15 are used.

+
+
+
+te.trTeFilter[].MatchChoiceEcauseLow bit layout +
+
+ +++++++ + + + + + + + + + + + + + + + + + + +
BitsFieldAccessResetDescription (SystemRDL, N-Trace/TCI)

31:0

Value

RW (Enable-locked)

0

Bitmap for ecause codes 0..31; bit N=1 matches ecause=N Writable only while trTeControl.Enable=0.

+
+
+

16.10.17. te.trTeFilter[].MatchChoiceEcauseHigh — offset 0x40C

+
+

Bits 63:32 of Ecause bitmap. Only accessible on trTeControl. Enable=0. Not used in default configuration

+
+
+
+te.trTeFilter[].MatchChoiceEcauseHigh bit layout +
+
+ +++++++ + + + + + + + + + + + + + + + + + + +
BitsFieldAccessResetDescription (SystemRDL, N-Trace/TCI)

31:0

Value

RW (Enable-locked)

0

Bitmap for ecause codes 32..63; bit N=1 matches ecause=N+32 Writable only while trTeControl.Enable=0.

+
+
+

16.10.18. te.trTeFilter[].MatchValueImpdef — offset 0x410

+
+

Implementation-defined value (used with mask). Only accessible on trTeControl. Enable=0

+
+
+
+te.trTeFilter[].MatchValueImpdef bit layout +
+
+ +++++++ + + + + + + + + + + + + + + + + + + +
BitsFieldAccessResetDescription (SystemRDL, N-Trace/TCI)

31:0

Value

RW (Enable-locked)

0

Value compared with (impdef & mask) Writable only while trTeControl.Enable=0.

+
+
+

16.10.19. te.trTeFilter[].MatchMaskImpdef — offset 0x414

+
+

Implementation-defined mask. Only accessible on trTeControl. Enable=0

+
+
+
+te.trTeFilter[].MatchMaskImpdef bit layout +
+
+ +++++++ + + + + + + + + + + + + + + + + + + +
BitsFieldAccessResetDescription (SystemRDL, N-Trace/TCI)

31:0

Value

RW (Enable-locked)

0

Mask for implementation-defined compare Writable only while trTeControl.Enable=0.

+
+
+

16.10.20. te.trTeFilter[].MatchChoiceData — offset 0x418

+
+

dtype/dsize selection bitmaps. Only accessible on trTeControl. Enable=0

+
+
+
+te.trTeFilter[].MatchChoiceData bit layout +
+
+ +++++++ + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsFieldAccessResetDescription (SystemRDL, N-Trace/TCI)

23:16

Dsize

RW (Enable-locked)

0

Bitmap for dsize; bit N=1 matches dsize=N Writable only while trTeControl.Enable=0.

15:0

Dtype

RW (Enable-locked)

0

Bitmap for dtype; bit N=1 matches dtype=N Writable only while trTeControl.Enable=0.

+
+
+

16.10.21. te.trTeComp[].Control — offset 0x600

+
+

Input select, compare functions, mode, notify

+
+
+
+te.trTeComp[].Control bit layout +
+
+ +++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsFieldAccessResetDescription (SystemRDL, N-Trace/TCI)

15

SNotify

RW (Enable-locked)

0

Generate a trace packet explicitly reporting the address of the final instruction in a block that causes a SECONDARY match. This is also known as a watchpoint. Writable only while trTeControl.Enable=0.

14

PNotify

RW (Enable-locked)

0

Generate a trace packet explicitly reporting the address of the final instruction in a block that causes a PRIMARY match. This is also known as a watchpoint. Writable only while trTeControl.Enable=0.

13:12

MatchMode

RW (Enable-locked)

0

Match mode (0..3, see desc) Writable only while trTeControl.Enable=0. Values: 0 = TR_COMP_MATCH_MODE0; 1 = TR_COMP_INPUT_MODE1; 2 = TR_COMP_INPUT_MODE2; 3 = TR_COMP_INPUT_MODE3.

10:8

SFunction

RW (Enable-locked)

0

Secondary function Writable only while trTeControl.Enable=0. Values: 0 = TR_COMP_SFUNC_EQUAL; 1 = TR_COMP_SFUNC_NOT_EQUAL; 2 = TR_COMP_SFUNC_LESS; 3 = TR_COMP_SFUNC_LESS_EQUAL; 4 = TR_COMP_SFUNC_GREATER; 5 = TR_COMP_SFUNC_GREATER_EQUAL; 6 = TR_COMP_SFUNC_PMASK; 7 = TR_COMP_SFUNC_ALWAYS_MATCH.

6:4

PFunction

RW (Enable-locked)

0

Primary function Writable only while trTeControl.Enable=0. Values: 0 = TR_COMP_PFUNC_EQUAL; 1 = TR_COMP_PFUNC_NOT_EQUAL; 2 = TR_COMP_PFUNC_LESS; 3 = TR_COMP_PFUNC_LESS_EQUAL; 4 = TR_COMP_PFUNC_GREATER; 5 = TR_COMP_PFUNC_GREATER_EQUAL; 6 = TR_COMP_PFUNC_RESERVED_MATCH; 7 = TR_COMP_PFUNC_ALWAYS_MATCH.

3:2

SInput

RW (Enable-locked)

0

Secondary input select Writable only while trTeControl.Enable=0. Values: 0 = TR_COMP_INPUT_IADDR; 1 = TR_COMP_INPUT_CONTEXT; 2 = TR_COMP_INPUT_TVAL; 3 = TR_COMP_INPUT_DADDR.

1:0

PInput

RW (Enable-locked)

0

Primary input select Writable only while trTeControl.Enable=0. Values: 0 = TR_COMP_INPUT_IADDR; 1 = TR_COMP_INPUT_CONTEXT; 2 = TR_COMP_INPUT_TVAL; 3 = TR_COMP_INPUT_DADDR.

+
+
+

16.10.22. te.trTeComp[].SMaskLow — offset 0x608

+
+

Bits 31:0 of the PMASK mask. Only accessible on trTeControl. Enable=0. [CTTE specific] Used ONLY by SFunction = TR_COMP_SFUNC_PMASK, which matches (value AND mask) == SMatch. Until X2a this mask was read out of SMatchHigh, which made the high half of the secondary bound unusable — with 64-bit addresses SMatch{High,Low} IS the bound, so the mask needs its own register.

+
+
+
+te.trTeComp[].SMaskLow bit layout +
+
+ +++++++ + + + + + + + + + + + + + + + + + + +
BitsFieldAccessResetDescription (SystemRDL, N-Trace/TCI)

31:0

Value

RW (Enable-locked)

0

Secondary mask value, bits [31:0]. Writable only while trTeControl.Enable=0.

+
+
+

16.10.23. te.trTeComp[].SMaskHigh — offset 0x60C

+
+

Bits 63:32 of the PMASK mask. Only accessible on trTeControl. Enable=0. Not used in a 32-bit address configuration.

+
+
+
+te.trTeComp[].SMaskHigh bit layout +
+
+ +++++++ + + + + + + + + + + + + + + + + + + +
BitsFieldAccessResetDescription (SystemRDL, N-Trace/TCI)

31:0

Value

RW (Enable-locked)

0

Secondary mask value, bits [63:32]. Writable only while trTeControl.Enable=0.

+
+
+

16.10.24. te.trTeComp[].PMatchLow — offset 0x610

+
+

Bits 31:0. Only accessible on trTeControl. Enable=0

+
+
+
+te.trTeComp[].PMatchLow bit layout +
+
+ +++++++ + + + + + + + + + + + + + + + + + + +
BitsFieldAccessResetDescription (SystemRDL, N-Trace/TCI)

31:0

Value

RW (Enable-locked)

0

Primary match value, bits [31:0]. Writable only while trTeControl.Enable=0.

+
+
+

16.10.25. te.trTeComp[].PMatchHigh — offset 0x614

+
+

Bits 63:32. Only accessible on trTeControl. Enable=0

+
+
+
+te.trTeComp[].PMatchHigh bit layout +
+
+ +++++++ + + + + + + + + + + + + + + + + + + +
BitsFieldAccessResetDescription (SystemRDL, N-Trace/TCI)

31:0

Value

RW (Enable-locked)

0

Primary match value, bits [63:32]. Writable only while trTeControl.Enable=0.

+
+
+

16.10.26. te.trTeComp[].SMatchLow — offset 0x618

+
+

Bits 31:0. Only accessible on trTeControl. Enable=0

+
+
+
+te.trTeComp[].SMatchLow bit layout +
+
+ +++++++ + + + + + + + + + + + + + + + + + + +
BitsFieldAccessResetDescription (SystemRDL, N-Trace/TCI)

31:0

Value

RW (Enable-locked)

0

Secondary match value, bits [31:0]. Writable only while trTeControl.Enable=0.

+
+
+

16.10.27. te.trTeComp[].SMatchHigh — offset 0x61C

+
+

Bits 63:32. Only accessible on trTeControl. Enable=0

+
+
+
+te.trTeComp[].SMatchHigh bit layout +
+
+ +++++++ + + + + + + + + + + + + + + + + + + +
BitsFieldAccessResetDescription (SystemRDL, N-Trace/TCI)

31:0

Value

RW (Enable-locked)

0

Secondary match value, bits [63:32]. Writable only while trTeControl.Enable=0.

+
+
+

16.10.28. te.trTeCsrControl — offset 0xE00

+
+

TE control via CSR. [CTTE specific]

+
+
+
+te.trTeCsrControl bit layout +
+
+ +++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsFieldAccessResetDescription (SystemRDL, N-Trace/TCI)

3

trTeCsrSendCC

RO (hw-written)

0

Do send Clock Cycle

2

trTeCsrSendTS

RO (hw-written)

0

Do send TS

1

trTeCsrSendPC

RO (hw-written)

0

Do send PC

0

trTeCsrSendSync

RO (hw-written)

0

Do send Sync

+
+
+

16.10.29. te.trTeTipFifoStatus — offset 0xE04

+
+

Provides TIP FIFO statistics. [CTTE specific]

+
+
+
+te.trTeTipFifoStatus bit layout +
+
+ +++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsFieldAccessResetDescription (SystemRDL, N-Trace/TCI)

31

trTeTipFifoNumOverflowsClear

RW

0

Write 1 to clear trTeTipFifoNumOverflows and hold it at 0, write 0 to re-arm.

30:16

trTeTipFifoNumOverflows

RO (hw-written)

0

Count of discard events (dropped message beats) since the last clear. Saturates at 0x7FFF.

15

trTeTipFifoMaxFillClear

RW

0

Write 1 to clear trTeTipFifoMaxFill and hold it at 0, write 0 to re-arm.

14:0

trTeTipFifoMaxFill

RO (hw-written)

0

Max fill level of internal buffering fifo since the last clear. Saturates at 0x7FFF.

+
+
+

16.10.30. te.trTeSyncStatus — offset 0xE08

+
+

Diagnostic status for explicit synchronization requests. On the wire every explicit sync request is emitted with the single vendor SYNC code 14 (explicit sync request) — N-Trace 1.0 Table 25 reserves codes 10-13 for future standard use, so the former per-source codes 12 (CSR) and 13 (ATB) are no longer used. The request source does not matter to a decoder (every synchronization message is a full re-anchor); it is kept readable here for diagnosis. [CTTE specific]

+
+
+
+te.trTeSyncStatus bit layout +
+
+ +++++++ + + + + + + + + + + + + + + + + + + +
BitsFieldAccessResetDescription (SystemRDL, N-Trace/TCI)

2:0

SyncReqSource

RO (hw-written)

0

Source of the most recent explicit synchronization request. [CTTE specific] Values: 0 = SYNC_REQ_NONE; 1 = SYNC_REQ_CSR; 2 = SYNC_REQ_ATB; 3 = SYNC_REQ_QUOTA; 4 = SYNC_REQ_TE.

+
+
+

16.10.31. te.trTeTipFifoHistCtrl — offset 0xE10

+
+

Control for the SERIAL fill-level histogram read-out via trTeTipFifoHistData. The number of bins (CT_FIFO_HIST_BINS, default 16) is an RTL parameter — the CSR map is independent of it (one data register, serial pointer). [CTTE specific]

+
+
+
+te.trTeTipFifoHistCtrl bit layout +
+
+ +++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsFieldAccessResetDescription (SystemRDL, N-Trace/TCI)

12:8

RdIdx

RO (hw-written)

0

Current serial read pointer (bin-pair index the next trTeTipFifoHistData read will return). [CTTE specific]

1

RdRewind

WO (self-clearing)

0

Write 1 to rewind the serial read pointer to bin pair 0 WITHOUT clearing the counters (re-read the histogram). Self-clearing. [CTTE specific]

0

HistClear

RW

0

Write 1 to clear all histogram counters AND the read pointer and hold them at 0, write 0 to re-arm. Level, no CDC — change only while the trace is quiescent (trTeControl.Enable=0). [CTTE specific]

+
+
+

16.10.32. te.trTeTipFifoHistData — offset 0xE14

+
+

SERIAL window into the CT_FIFO_HIST_BINS saturating 16-bit upward-crossing counters (AW: not random access — one register, DSP-backed counters, minimal readback). Each read returns bin pair [2*RdIdx (Lo), 2*RdIdx+1 (Hi)] and auto-increments RdIdx (wraps after BINS/2). Bin b counts crossings of fill level (b+1)*DEPTH/BINS, DEPTH = ETIP_CVS_FIFO_DEPTH. Read protocol: HistClear or RdRewind, then BINS/2 consecutive reads. No CDC — read only while the trace is quiescent (trTeControl.Enable=0). [CTTE specific]

+
+
+
+te.trTeTipFifoHistData bit layout +
+
+ +++++++ + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsFieldAccessResetDescription (SystemRDL, N-Trace/TCI)

31:16

Hi

RO (hw-written)

0

Bin 2*RdIdx+1 — crossings of level (2*RdIdx+2)*DEPTH/BINS. [CTTE specific]

15:0

Lo

RO (hw-written)

0

Bin 2*RdIdx — crossings of level (2*RdIdx+1)*DEPTH/BINS. [CTTE specific]

+
+
+
+

16.11. Component atb (base 0x1000)

+
+

Trace ATB Bridge sub-component (N-Trace compliant, CompType=0xE). See RISC-V N-Trace Control Interface spec Chapter 10 (Tables 56/57).

+
+ +++++ + + + + + + + + + + + + + + + + + + + +
OffsetRegisterFields

0x1000

atb.trAtbBridgeControl

4

0x1004

atb.trAtbBridgeImpl

4

+
+

16.11.1. atb.trAtbBridgeControl — offset 0x1000

+
+

Primary control register for the ATB Bridge.

+
+
+
+atb.trAtbBridgeControl bit layout +
+
+ +++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsFieldAccessResetDescription (SystemRDL, N-Trace/TCI)

14:8

ID

RW (Enable-locked)

8

ID of this node on ATB. Values 0x00 and 0x70-0x7F are reserved by the ATB specification and should not be used. Writable only while trTeControl.Enable=0.

3

Empty

RO (hw-written)

1

Reads as 1 when ATB Bridge internal buffers are empty.

1

Enable

RO

1

1: ATB Bridge enabled. Setting Enable to 0 flushes any queued trace data to ATB.

0

Active

RO

1

Primary activate/reset for the ATB Bridge. When 0, the ATB Bridge may have clocks gated off or be powered down, and other register locations may be inaccessible. [Not implemented: read-only constant 1; there is no clock-gate/power-down control behind it.]

+
+
+

16.11.2. atb.trAtbBridgeImpl — offset 0x1004

+
+

Contains version and protocol information for the ATB Bridge.

+
+
+
+atb.trAtbBridgeImpl bit layout +
+
+ +++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsFieldAccessResetDescription (SystemRDL, N-Trace/TCI)

14:12

AsyncFreq

RW (Enable-locked)

0

Async packet frequency. 0: Async disabled; 1..7: different levels of alignment synchronization. Writable only while trTeControl.Enable=0.

11:8

CompType

RO

0xE

ATB Bridge Component Type (0xE)

7:4

VerMinor

RO

0

ATB Bridge Component Minor Version

3:0

VerMajor

RO

1

ATB Bridge Component Major Version

+
+
+
+

16.12. Component pc (base 0x3000)

+
+

Performance Counter sub-component (CTTE, vendor CompType=0x3). [CTTE specific]

+
+ +++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
OffsetRegisterFields

0x3000

pc.trPcControl

1

0x3004

pc.trPcImpl

3

0x3008

pc.trTeConstants

6

0x3010

pc.trPerfCntControl

2

0x3100

pc.trTePerfCntIFetchRange[].Low

1

0x3104

pc.trTePerfCntIFetchRange[].High

1

0x3200

pc.trTePerfCntDataRdThRange[].Low

1

0x3204

pc.trTePerfCntDataRdThRange[].High

1

0x3300

pc.trTePerfCntDataRdRange[].Low

1

0x3304

pc.trTePerfCntDataRdRange[].High

1

0x3400

pc.trTePerfCntDataWrRange[].Low

1

0x3404

pc.trTePerfCntDataWrRange[].High

1

+
+

16.12.1. pc.trPcControl — offset 0x3000

+
+

Primary activate/reset for the Performance Counter component. [CTTE specific]

+
+
+
+pc.trPcControl bit layout +
+
+ +++++++ + + + + + + + + + + + + + + + + + + +
BitsFieldAccessResetDescription (SystemRDL, N-Trace/TCI)

0

Active

RO

1

Primary activate/reset bit. [Not implemented: read-only constant 1; there is no clock-gate/power-down control behind it.]

+
+
+

16.12.2. pc.trPcImpl — offset 0x3004

+
+

Version and component type information for the Performance Counter component. [CTTE specific]

+
+
+
+pc.trPcImpl bit layout +
+
+ +++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsFieldAccessResetDescription (SystemRDL, N-Trace/TCI)

11:8

CompType

RO

3

Component Type (vendor: 0x3)

7:4

VerMinor

RO

0

Component Minor Version

3:0

VerMajor

RO

1

Component Major Version

+
+
+

16.12.3. pc.trTeConstants — offset 0x3008

+
+

Implementatopn parameters for synchronization with RDL implementation. (RDL has no direct access PeakRDL parameters.) [CTTE specific]

+
+
+
+pc.trTeConstants bit layout +
+
+ +++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsFieldAccessResetDescription (SystemRDL, N-Trace/TCI)

24:21

num_perfcnt_data_wr_ranges

RO

7

NUM_PERFCNT_DATA_WR_RANGES

20:17

num_perfcnt_data_rd_ranges

RO

7

NUM_PERFCNT_DATA_RD_RANGES

16:13

num_perfcnt_data_rd_th_ranges

RO

3

NUM_PERFCNT_DATA_RD_TH_RANGES

12:9

num_perfcnt_ifetch_th_ranges

RO

3

NUM_PERFCNT_IFETCH_TH_RANGES

8:5

num_trace_comparators

RO

8

NUM_TRACE_COMPARATORS

4:0

num_trace_filter

RO

0x10

NUM_TRACE_FILTER

+
+
+

16.12.4. pc.trPerfCntControl — offset 0x3010

+
+

Control register for the encoder’s performance counter. [CTTE specific]

+
+
+
+pc.trPerfCntControl bit layout +
+
+ +++++++ + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsFieldAccessResetDescription (SystemRDL, N-Trace/TCI)

15:8

DataWrThreshold

RW

4

CPU cycles threshold. When required CPU clock cycles exceed this threshold, the respective counter increments.

7:0

IFetchThreshold

RW

4

CPU cycles threshold for instruction fetch. When required CPU clock cycles exceed this threshold, the respective counter increments.

+
+
+

16.12.5. pc.trTePerfCntIFetchRange[].Low — offset 0x3100

+
+

Inclusive low address of instruction fetch range.

+
+
+
+pc.trTePerfCntIFetchRange[].Low bit layout +
+
+ +++++++ + + + + + + + + + + + + + + + + + + +
BitsFieldAccessResetDescription (SystemRDL, N-Trace/TCI)

31:0

Value

RW (Enable-locked)

0

Start address of the range (inclusive). Writable only while trTeControl.Enable=0.

+
+
+

16.12.6. pc.trTePerfCntIFetchRange[].High — offset 0x3104

+
+

Inclusive high address of instruction fetch range.

+
+
+
+pc.trTePerfCntIFetchRange[].High bit layout +
+
+ +++++++ + + + + + + + + + + + + + + + + + + +
BitsFieldAccessResetDescription (SystemRDL, N-Trace/TCI)

31:0

Value

RW (Enable-locked)

0

End address of the range (inclusive). Writable only while trTeControl.Enable=0.

+
+
+

16.12.7. pc.trTePerfCntDataRdThRange[].Low — offset 0x3200

+
+

Inclusive low address of data read range.

+
+
+
+pc.trTePerfCntDataRdThRange[].Low bit layout +
+
+ +++++++ + + + + + + + + + + + + + + + + + + +
BitsFieldAccessResetDescription (SystemRDL, N-Trace/TCI)

31:0

Value

RW (Enable-locked)

0

Start address of the range (inclusive). Writable only while trTeControl.Enable=0.

+
+
+

16.12.8. pc.trTePerfCntDataRdThRange[].High — offset 0x3204

+
+

High address of data write threshold range.

+
+
+
+pc.trTePerfCntDataRdThRange[].High bit layout +
+
+ +++++++ + + + + + + + + + + + + + + + + + + +
BitsFieldAccessResetDescription (SystemRDL, N-Trace/TCI)

31:0

Value

RW (Enable-locked)

0

End address of the range (inclusive). Writable only while trTeControl.Enable=0.

+
+
+

16.12.9. pc.trTePerfCntDataRdRange[].Low — offset 0x3300

+
+

Low address of data read range.

+
+
+
+pc.trTePerfCntDataRdRange[].Low bit layout +
+
+ +++++++ + + + + + + + + + + + + + + + + + + +
BitsFieldAccessResetDescription (SystemRDL, N-Trace/TCI)

31:0

Value

RW (Enable-locked)

0

Start address of the range (inclusive). Writable only while trTeControl.Enable=0.

+
+
+

16.12.10. pc.trTePerfCntDataRdRange[].High — offset 0x3304

+
+

High address of data write range.

+
+
+
+pc.trTePerfCntDataRdRange[].High bit layout +
+
+ +++++++ + + + + + + + + + + + + + + + + + + +
BitsFieldAccessResetDescription (SystemRDL, N-Trace/TCI)

31:0

Value

RW (Enable-locked)

0

End address of the range (inclusive). Writable only while trTeControl.Enable=0.

+
+
+

16.12.11. pc.trTePerfCntDataWrRange[].Low — offset 0x3400

+
+

Low address of data write range.

+
+
+
+pc.trTePerfCntDataWrRange[].Low bit layout +
+
+ +++++++ + + + + + + + + + + + + + + + + + + +
BitsFieldAccessResetDescription (SystemRDL, N-Trace/TCI)

31:0

Value

RW (Enable-locked)

0

Start address of the range (inclusive). Writable only while trTeControl.Enable=0.

+
+
+

16.12.12. pc.trTePerfCntDataWrRange[].High — offset 0x3404

+
+

High address of data write range.

+
+
+
+pc.trTePerfCntDataWrRange[].High bit layout +
+
+ +++++++ + + + + + + + + + + + + + + + + + + +
BitsFieldAccessResetDescription (SystemRDL, N-Trace/TCI)

31:0

Value

RW (Enable-locked)

0

End address of the range (inclusive). Writable only while trTeControl.Enable=0.

+
+
+
+

16.13. Component wp (base 0x4000)

+
+

Registers the SystemRDL places directly into the address map: a component that owns an external memory cannot be a regfile.

+
+ +++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
OffsetRegisterFields

0x4000

trWpControl

1

0x4004

trWpImpl

3

0x4008

trWpMask

1

0x400C

trWpIndex

1

0x4010

trWpDataLow

1

0x4014

trWpDataHigh

3

0x4018

trWpReadLow

1

0x401C

trWpReadHigh

3

0x4020

trWpCap

1

+
+

16.13.1. trWpControl — offset 0x4000

+
+

Primary activate/reset for the Watchpoints component. [CTTE specific]

+
+
+
+trWpControl bit layout +
+
+ +++++++ + + + + + + + + + + + + + + + + + + +
BitsFieldAccessResetDescription (SystemRDL, N-Trace/TCI)

0

Active

RO

1

Primary activate/reset bit. [Not implemented: read-only constant 1; there is no clock-gate/power-down control behind it.]

+
+
+

16.13.2. trWpImpl — offset 0x4004

+
+

Version and component type information for the Watchpoints component. [CTTE specific]

+
+
+
+trWpImpl bit layout +
+
+ +++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsFieldAccessResetDescription (SystemRDL, N-Trace/TCI)

11:8

CompType

RO

4

Component Type (vendor: 0x4)

7:4

VerMinor

RO

0

Component Minor Version

3:0

VerMajor

RO

1

Component Major Version

+
+
+

16.13.3. trWpMask — offset 0x4008

+
+

Enable mask for Watchpoint messages (Nexus TCODE 15). [CTTE specific]

+
+
+
+trWpMask bit layout +
+
+ +++++++ + + + + + + + + + + + + + + + + + + +
BitsFieldAccessResetDescription (SystemRDL, N-Trace/TCI)

15:0

WEM

RW (Enable-locked)

0

Watchpoint Event Mask: one bit per reportable watchpoint slot. A 1 ENABLES reporting of that bit (IEEE-ISTO 5001 Table B-26, 'WEM …​ 1 = enabled'). NOTE: the prose of ISTO 4.3.23 says the WPHIT field is 'masked by 1', which reads like the inverse; CTTE follows Table B-26. The emitted WPHIT of an ACT_CAP_ST_WATCHPOINT command is Cmd.DirectData[15:0] AND WEM, so which slot owns which bit is a SOFTWARE convention: program the watchpoints[] entry with the DirectData bit you want to see and enable that bit here. A command whose masked result is 0 emits no message. Reset 0 masks every hit, so adding the feature to an existing build changes no wire byte until software opts in. Writable only while trTeControl.Enable=0. Requires the CT_EN_WATCHPOINT_MSG build switch (which itself requires CT_EN_ACT); profiles without the feature read 0.

+
+
+

16.13.4. trWpIndex — offset 0x400C

+
+

Slot index for the indirect watchpoint load/readback path. A trWpDataHigh write commits the staged entry to slot Idx and then increments Idx; a trWpReadHigh read returns the shadow entry at Idx and also increments it. Both wrap from NUM_ACT_ST-1 back to 0. Software normally writes the start slot once and streams NUM_ACT_ST Low/High pairs. Reads return the CURRENT index, so after a burst of n commits starting at i the register reads (i + n) mod NUM_ACT_ST — cheap load verification. Values >= NUM_ACT_ST are out of range: hardware uses the low address bits and the first increment normalizes to 0. The one in-window out-of-range value, Idx = NUM_ACT_ST (= 1023), addresses the physical padding slot behind the last tree node: a commit or readback there is inert for matching (the search never visits that slot) and the following increment wraps to 0. Writable only while trTeControl.Enable=0. [CTTE specific]

+
+
+
+trWpIndex bit layout +
+
+ +++++++ + + + + + + + + + + + + + + + + + + +
BitsFieldAccessResetDescription (SystemRDL, N-Trace/TCI)

15:0

Idx

RW (Enable-locked, hw-written)

0

Watchpoint slot index the next commit/readback targets. [CTTE specific]

+
+
+

16.13.5. trWpDataLow — offset 0x4010

+
+

Address (PC) that arms the watchpoint entry being staged. When the retired CPU PC matches Addr, the Cmd committed with it is dispatched through the CTTE unit. Write Low first, then trWpDataHigh — the High write commits the pair to slot trWpIndex.Idx; a Low write alone has no effect. Writable only while trTeControl.Enable=0. [CTTE specific]

+
+
+
+trWpDataLow bit layout +
+
+ +++++++ + + + + + + + + + + + + + + + + + + +
BitsFieldAccessResetDescription (SystemRDL, N-Trace/TCI)

31:0

Value

RW (Enable-locked)

0

Addr (PC) to stage. [CTTE specific]

+
+
+

16.13.6. trWpDataHigh — offset 0x4014

+
+

Command of the watchpoint entry being staged. Writing this register COMMITS {trWpDataLow, this word} to slot trWpIndex.Idx and increments Idx — identical commit semantics to the historical +0x4 write of the removed 0x4100 window. Bit layout is shared with RISC-V CSR 0x0B10 (ACT-CAP protocol), which the CPU can write directly to dispatch the same command immediately without going through the table. Writable only while trTeControl.Enable=0 (the lock also suppresses the commit). Rules for programming the table: 1. Fill ALL NUM_ACT_ST slots (trWpCap.Entries). Unused slots are not optional — leaving a slot at its reset value can mask real watchpoints. 2. Addr values across slot 0 .. slot NUM_ACT_ST-1 must be strictly ascending and unique (Addr[i] < Addr[i+1]). 3. Each slot is a pair: write trWpDataLow first, then this register. The High write is what commits the entry. 4. Update the entire table with tracing disabled (trTeControl.Enable = 0). The index/staging registers are hardware-locked while enabled; a table changed mid-trace would produce undefined matches. 5. Watchpoint messages (Cmd = ACT_CAP_ST_WATCHPOINT, Nexus TCODE 15): which BIT of the on-wire WPHIT field stands for which slot is a SOFTWARE convention, not hardware. Put the bit you want to see into that slot’s DirectData[15:0] (one-hot is the obvious choice) and enable the same bit in trWpMask.WEM; the encoder emits WPHIT = DirectData[15:0] AND WEM and stays silent when that is 0. For slots you do not need as real watchpoints, pick an Addr the CPU will never execute (odd instruction addresses are ideal — the core forces PC[0] = 0, so odd Addr values never match) and set Cmd = ACT_CAP_ST_NONE. The Addr values of such padding slots still have to satisfy rule 2. [CTTE specific]

+
+
+
+trWpDataHigh bit layout +
+
+ +++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsFieldAccessResetDescription (SystemRDL, N-Trace/TCI)

31:8

DirectData

RW (Enable-locked)

0

Direct data (24 bits). Always included in the DAQ message payload. A value of 0 is cost-free: Nexus MDO/MSEO variable-length encoding strips leading zeros, so an all-zero field adds no MDO cycles.

7:6

Sink

RW (Enable-locked)

0

Sink (trActCapStSink_e)

5:0

Cmd

RW (Enable-locked)

0

HSI command (trActCapStCmd_e). A write commits the staged pair. [CTTE specific]

+
+
+

16.13.7. trWpReadLow — offset 0x4018

+
+

Addr word of the shadow entry at trWpIndex.Idx. The shadow is zero-initialized at configuration load and NOT cleared by a soft reset — it reflects everything committed since configuration, the same persistence the search-tree memory itself has. Reading this register does not move Idx. [CTTE specific]

+
+
+
+trWpReadLow bit layout +
+
+ +++++++ + + + + + + + + + + + + + + + + + + +
BitsFieldAccessResetDescription (SystemRDL, N-Trace/TCI)

31:0

Value

RO (hw-written)

0

Shadow Addr at Idx. [CTTE specific]

+
+
+

16.13.8. trWpReadHigh — offset 0x401C

+
+

Cmd word of the shadow entry at trWpIndex.Idx. Reading this register increments Idx (wrap at NUM_ACT_ST-1) — serial readback: set Idx once, then alternate trWpReadLow / trWpReadHigh per slot. [CTTE specific]

+
+
+
+trWpReadHigh bit layout +
+
+ +++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsFieldAccessResetDescription (SystemRDL, N-Trace/TCI)

31:8

DirectData

RO (hw-written)

0

Shadow DirectData at Idx. [CTTE specific]

7:6

Sink

RO (hw-written)

0

Shadow Sink at Idx. [CTTE specific]

5:0

Cmd

RO (hw-written)

0

Shadow Cmd at Idx — reading increments Idx. [CTTE specific]

+
+
+

16.13.9. trWpCap — offset 0x4020

+
+

Number of implemented watchpoint slots (NUM_ACT_ST) — software discovery for the indirect load path. Profiles without the ACT blocks read 0. [CTTE specific]

+
+
+
+trWpCap bit layout +
+
+ +++++++ + + + + + + + + + + + + + + + + + + +
BitsFieldAccessResetDescription (SystemRDL, N-Trace/TCI)

15:0

Entries

RO

0x3FF

Implemented watchpoint slots. [CTTE specific]

+
+
+
+

16.14. Component df (base 0x5000)

+
+

Registers the SystemRDL places directly into the address map: a component that owns an external memory cannot be a regfile.

+
+ +++++ + + + + + + + + + + + + + + + + + + + +
OffsetRegisterFields

0x5000

trDfControl

1

0x5004

trDfImpl

3

+
+

16.14.1. trDfControl — offset 0x5000

+
+

Primary activate/reset for the DF RangeFilter component. [CTTE specific]

+
+
+
+trDfControl bit layout +
+
+ +++++++ + + + + + + + + + + + + + + + + + + +
BitsFieldAccessResetDescription (SystemRDL, N-Trace/TCI)

0

Active

RO

1

Primary activate/reset bit. [Not implemented: read-only constant 1; there is no clock-gate/power-down control behind it.]

+
+
+

16.14.2. trDfImpl — offset 0x5004

+
+

Version and component type information for the DF RangeFilter component. [CTTE specific]

+
+
+
+trDfImpl bit layout +
+
+ +++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsFieldAccessResetDescription (SystemRDL, N-Trace/TCI)

11:8

CompType

RO

5

Component Type (vendor: 0x5)

7:4

VerMinor

RO

0

Component Minor Version

3:0

VerMajor

RO

1

Component Major Version

+
+
+
+

16.15. Component mem1 (base 0x6000)

+
+

Read/write DF range filter memory. Each 64-bit entry is a {Key1, Key0} pair with Key0 ⇐ daddr ⇐ Key1. Software writes/reads the lower 32-bit Key0 word first, then the upper 32-bit Key1 word. Memory has NUM_DF_RANGE entries (sized to match the hardware binary-search tree depth M1_DIM; 15 entries for the current M1_DIM=4 configuration). [CTTE specific]

+
+ +++++ + + + + + + + + + + + + + + + + + + + +
OffsetRegisterFields

0x6000

mem1.Key0

1

0x6004

mem1.Key1

1

+
+

16.15.1. mem1.Key0 — offset 0x6000

+
+
+mem1.Key0 bit layout +
+
+ +++++++ + + + + + + + + + + + + + + + + + + +
BitsFieldAccessResetDescription (SystemRDL, N-Trace/TCI)

31:0

Value

RW

0

Lower 32-bit word of a 64-bit DF range-filter entry. Holds Key0, the inclusive low bound of the data-address range (Key0 ⇐ daddr ⇐ Key1). Writable only while trTeControl.Enable=0 (wrapper-enforced; keys must stay sorted and non-overlapping). [CTTE specific]

+
+
+

16.15.2. mem1.Key1 — offset 0x6004

+
+
+mem1.Key1 bit layout +
+
+ +++++++ + + + + + + + + + + + + + + + + + + +
BitsFieldAccessResetDescription (SystemRDL, N-Trace/TCI)

31:0

Value

RW

0

Upper 32-bit word of a 64-bit DF range-filter entry. Holds Key1, the inclusive high bound of the data-address range (Key0 ⇐ daddr ⇐ Key1). Writable only while trTeControl.Enable=0 (wrapper-enforced; the write of this word is what commits the pair). [CTTE specific]

+
+
+
+

16.16. Declared but not addressable

+
+

The SystemRDL declares the register below and then hides it with ispresent = false: the hardware does not decode that address on the control bus, and no exporter — register block, C header, HTML reference — offers it. It is listed because a map that silently drops a declared register is not a complete map. The chapter named in the description carries the contract.

+
+
+

16.16.1. trActCapStCmd — offset 0xB10 (not decoded)

+ +++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsFieldAccessResetDescription (SystemRDL, N-Trace/TCI)

31:8

DirectData

RW

0

Direct data (24 bits).

7:6

Sink

RW

0

Sink Values: 0 = ACT_CAP_ST_SINK_NEXUS; 1 = ACT_CAP_ST_SINK_AXIS; 2 = ACT_CAP_ST_SINK_AXIS_NEXUS; 3 = ACT_CAP_ST_SINK_TE.

5:0

Cmd

RW

0

HSI command Values: 0 = ACT_CAP_ST_NONE; 1 = ACT_CAP_ST_DAQ_PC_CURR; 2 = ACT_CAP_ST_DAQ_PC_CURR_LAST; 3 = ACT_CAP_ST_DAQ_DIRECT_DATA; 4 = ACT_CAP_ST_DAQ_DATA; 5 = ACT_CAP_ST_DAQ_DADDR; 6 = ACT_CAP_ST_DAQ_DATA_DADDR; 8 = ACT_CAP_ST_DAQ_IFETCH_TH; 9 = ACT_CAP_ST_DAQ_DATA_RD_TH; 10 = ACT_CAP_ST_DAQ_DATA_WR; 11 = ACT_CAP_ST_DAQ_DATA_RD; 12 = ACT_CAP_ST_CF_SYNC; 14 = ACT_CAP_ST_WATCHPOINT; 13 = ACT_CAP_ST_TE.

+
+
+
+
+
+

17. Interface Contract

+
+
+

This chapter is the hardware contract of the CEDARtools.TraceEncoder: the parameters and ports of the top-level module, the clock and reset domains, the clock-domain-crossing obligations, the three data interfaces (instruction ingress, trace egress, event egress), the control interface, and the shutdown sequence.

+
+
+
+ + + + + + + + + + +
+
+
+ RISC-V +
+ hart +
+
+
+
+ + + RISC-V... + + + + + + + + + + + +
+
+
+ TIP / ITI ingress (tip_clk) +
+
+
+ + + TIP / ITI ingres... + + + + + + + + + + + +
+
+
+ Preprocessor +
+ (tip_clk) +
+
+
+
+ + + Preprocessor... + + + + + + + + + + + +
+
+
+ Message generation (proc_clk) +
+
+
+ + + Message generatio... + + + + + + + + + + + +
+
+
+ Output stage (proc_clk) +
+
+
+ + + Output stage... + + + + + + + + + + + +
+
+
+ ATB egress, 32 bit (atb.atclk) +
+
+
+ + + ATB egress, 32 bit (... + + + + + + + + + + + +
+
+
+ AXI-Stream event path uncompressed +
+
+
+ + + AXI-Stream event pat... + + + + + + + + + + + +
+
+
+ Control interface Wishbone / CPUIF (wb_clk) +
+
+
+ + + Control interface Wishbone... + + + + + + + + + + + +
+
+
+ Trace sink +
+ (integrator) +
+
+
+
+ + + Trace sink... + + + + + + + + + + + +
+
+
+ On-chip consumer +
+ (watchdog, CFI checker) +
+
+
+
+ + + On-chip consumer... + + + + + + + + + + + + +
+
+
+ retired +
+ instructions +
+
+
+
+ + + retired... + + + + + + + + + + + + +
+
+
+ iaddr, +
+ itype, +
+
+ iretire +
+
+
+
+ + + iaddr,... + + + + + + + + + + + + +
+
+
+ events, +
+ aligned +
+
+
+
+ + + events,... + + + + + + + + + + + + +
+
+
+ messages +
+
+
+ + + messages + + + + + + + + + + + + +
+
+
+ MSEO/ +
+ MDO bytes +
+
+
+
+ + + MSEO/... + + + + + + + + + + + + +
+
+
+ atvalid / +
+ atready +
+
+
+
+ + + atvalid /... + + + + + + + + + + + + +
+
+
+ raw events +
+
+
+ + + raw events + + + + + + + + + + + + +
+
+
+ no backpressure +
+
+
+ + + no backpressure + + + + + + + + + + + + + + + + +
+
+
+ configuration +
+
+
+ + + configuration + + + + + + + + + + + + + + + + +
+
+
+ Register file from SystemRDL +
+
+
+ + + Register file fr... + + + + + + + + + + + +
+
+
+ Wall clock +
+ (wall_clk) +
+
+
+
+ + + Wall clock... + + + + + + + + + + + + + + Text is not SVG - cannot display + + + + +
+
Figure 12. Interface contract: clock domains and data path
+
+
+

Clock domains: tip_clk, proc_clk and atb.atclk; the control interface runs on wb_clk. CDC bridges sit at the domain boundaries.

+
+
+

The AXI-Stream path does not sample tready: a back-pressuring consumer loses beats.

+
+
+

It, too, returned in revision 2.0. Revision 1.2 removed it, and three places in the manual went on referring to a "CTTE interface chapter" that no longer existed — which made the manual unusable for the one task it is most often opened for: integrating a core.

+
+
+

The condensed form here is deliberate. The public integration guide of the CEDARtools.TraceEncoder repository (doc/integration.adoc) carries the same substance at roughly five times the length, with the full measurement apparatus behind every figure. This chapter states the contract; where a detail has a longer treatment, the anchor of the public document is named so it can be followed.

+
+
+

17.1. Top-level module

+
+

The integration unit is the module ct_encoder (rtl/ct_encoder.sv:50). Everything below is its interface.

+
+
+

17.1.1. Parameters

+ ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
ParameterTypeDefaultMeaning

SPLIT_DATA_ACCESS

bit

0

Shape of the data-trace ingress. 0 = the legacy mode in which the data value is sampled from tip.data at retirement. 1 = split-load mode: tip.sdata carries store data at retirement, tip.lresp and tip.ldata carry the load response when it arrives.

CT_SIJUMP

bit

0

Integration attribute, not a feature switch: declares that the attached core’s ingress uses the sequentially-implicit-jump convention. It has no effect inside the encoder; it is advertised to the decoder as capability bit 6 so that the decoder knows to apply the matching convention. The MicroBlaze™ V adapter sets it.

CT_DEVICE_ID

logic [31:0]

0

The static identity of this encoder instance, laid out per IEEE-ISTO 5001-2012 Table B-5. 0 means "no device ID assigned". Nothing reaches the wire until software sets trTeControl.SendDeviceId; see Chapter 18.

EN_NTRACE / EN_ETRACE

bit

build profile

Per-instance protocol back end. Exactly one must be set — elaboration aborts if both or neither are (rtl/ct_encoder.sv:220). A multi-encoder system-on-chip can therefore mix protocols out of one set of netlist sources. The historical dual build with a runtime protocol select is retired.

CORE_XLEN

int unsigned

0 (invalid)

The integrator’s declaration of the architectural address width of the hart this instance’s ingress is wired to. It must equal the netlist’s own ct_pkg::CT_XLEN or elaboration aborts (rtl/ct_encoder.sv:294). See the note below — this parameter has no useful default and the invalid default is the point.

+
+ + + + + +
+
Important
+		 +CORE_XLEN exists because nothing else can see a width mismatch. The ingress interface is parameterless; its address fields are sized by the netlist’s CT_XLEN. An adapter that drives a 64-bit program counter into a 32-bit netlist has its upper address bits truncated by SystemVerilog’s silent width adaptation before the encoder sees anything. Inside the encoder those bits never existed, so no assertion, no capture and no decoder downstream can miss them. The declaration is the only place where both widths are known at once — which is why its default is an error rather than a match: an integrator who says nothing would otherwise keep exactly the silent truncation the parameter exists to stop. +
+
+
+

The same guard is written twice, as a bare elaboration $fatal and as an initial $fatal, because one simulation backend in the tool flow runs with -Wno-fatal, which demotes the elaboration form to a warning and lets the run continue. Measured on 2026-08-12 before the fix: 15 ATB transfers were traced out of a declared 64-bit hart on a 32-bit ingress (rtl/ct_encoder.sv:294-301).

+
+
+

Four further elaboration guards enforce contracts that are otherwise silent: ct_pkg::CT_XLEN must be 32 or 64 (:256); EN_ETRACE requires the corresponding build switch, or the ingress sideband fields are one-bit stubs (:246); ct_pkg::CT_CONTEXT_WIDTH must fit the message field (:310); and with block ingress enabled, CT_IRETIRE_WIDTH must lie between 2 and the instruction-count field width (:332). The combination of the E-Trace back end with 64-bit addresses is rejected (:346).

+
+
+
+

17.1.2. Ports

+ ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
PortKindDomainRole

tip_clk, tip_rst

input

 — 

Ingress clock and its synchronous, active-high reset.

tip

tip_if.slave

tip_clk

Instruction and data ingress — see Section 17.5.

wb_clk, wb_rst

input

 — 

Control-interface clock and its synchronous, active-high reset.

wb

wb_if.slave

wb_clk

Register access — see Section 17.8.

ct_cs_rst

input

wb_clk

Additional register-block reset, logically OR-ed with wb_rst at every register in that domain.

axis

axis_if.master

tip_clk

Uncompressed instrumentation egress — see Section 17.7.

atb_atclk, atb_atresetn

input

 — 

Egress clock and its active-low reset.

atb

atb_if.master

atb_atclk

Trace egress — see Section 17.6.

atb_te_raw

output

atb_atclk

Framing advertisement: 0 = Nexus chunks, 1 = E-Trace raw bytes. Constant per instance, tied to EN_ETRACE.

proc_clk, proc_rst

input

 — 

Internal pipeline clock and its synchronous, active-high reset.

wall_clk, wall_clk_rst

input

 — 

Free-running wall-clock timestamp reference and its synchronous, active-high reset.

+
+ + + + + +
+
Note
+		 +The AXI-Stream interface carries its own aclk / aresetn in the interface definition rather than as ports of ct_encoder. The encoder drives that interface from the ingress domain, so the integrator binds them to the ingress clock and reset. It is not a sixth clock domain. +
+
+
+
+
+

17.2. Clocks

+
+

Five clock domains, each with its own reset. A fully single-clock integration — all five tied together — is supported and is the configuration the hardware robustness campaign runs on; a structural build knob removes the internal crossing logic in that case.

+
+ +++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
ClockDrivesConstraint

tip_clk

Instruction ingress and the preprocessor front end

Must be the core clock. The ingress bus is synchronous to retirement; there is no handshake to make it otherwise.

proc_clk

Message generation and formatting

May equal the ingress clock. One-to-one is the proven board profile; a faster processing clock buys headroom.

atb_atclk

Trace egress and the Empty status view

Sink-side clock. One-to-one with the ingress clock is proven on hardware. A slower drain does not lose data silently — it raises the rate of announced-loss episodes.

wb_clk

Register access

Any frequency.

wall_clk

Wall-clock timestamp source

Optional feature clock.

+
+
+

17.3. Resets

+ +++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
ResetPolarityNotes

tip_rst

active high

Synchronous to tip_clk.

proc_rst

active high

Synchronous to proc_clk.

wb_rst

active high

Synchronous to wb_clk.

ct_cs_rst

active high

Synchronous to wb_clk; always OR-ed with wb_rst.

atb_atresetn

active low

Synchronous to atb_atclk; inverted internally.

wall_clk_rst

active high

Synchronous to wall_clk.

+
+

The encoder takes its reset inputs as already synchronous to their domains; it instantiates no reset synchronizer of its own at the top level. No minimum reset-hold length is specified.

+
+
+

17.3.1. Resetting one domain without the others

+
+

This is an explicit contract, not an accident of the implementation (doc/integration.adoc, anchor independent-resets). An integrator may hold the ingress domain — and with it the whole core — in reset while the control domain keeps running. That is what makes the encoder programmable across a core reset.

+
+
+

One property is deliberate and worth knowing, because a naive design would not have it: an explicit synchronization request survives a reset of the consuming domain. The request crosses as a four-phase level handshake, so an ingress-domain reset clears the generator’s pending state without acknowledging the request; the still-standing request is simply seen again when the domain returns. The same holds for the egress-side sync request. Proven formally for a single clock (formal/preproc_sync, task tereqrst) and measured at two unrelated clocks (scripts/cli_syncreqrst_test.sh) in the CEDARtools.TraceEncoder repository; the same measurement shows that a pulse-based request would be dropped and the requesting side would wait forever.

+
+
+

Two limits belong with that guarantee:

+
+
+
    +
  • +

    The direction matters. A reset of the control domain resets the launching side, where a request has nowhere to survive: a request written but not yet served is gone, with no message, no error and no status bit. Survival is claimed for the ingress reset only.

    +
    • +
  • +

    It may cost one extra synchronization message, if the reset lands after the generator served the request but before the launching side saw the acknowledgement. A synchronization message is always safe to emit, so this is a byte, not a hazard. Exactly-once delivery across a one-sided reset is not claimed.

    +
    • +
+
+
+

Everything else resets per domain in the ordinary way: state in the reset domain is gone, and the stream re-anchors on the first qualifying retirement afterwards.

+
+
+
+
+

17.4. Clock-domain crossing

+
+

All crossings are internal. The integrator connects clocks and resets and applies the constraint fragments; there is no crossing the integrator has to build.

+
+ +++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
PrimitiveUsed forConstraint fragment

signal_cdc

A slowly changing single bit; two-flop synchronizer with the synthesis attributes that keep it from being re-timed or absorbed into a shift register.

signal_cdc.xdc

strobe_cdc

A single-cycle strobe, carried as a toggle and recovered by an edge detector.

(via signal_cdc)

vector_cdc2

A multi-bit value, carried by a four-phase request/acknowledge handshake so the receiver never samples a partially updated vector.

 — 

reset_cdc

Asynchronous-assert, synchronous-deassert reset synchronization.

reset_cdc.xdc

Gray-pointer CDC FIFO

The trace payload itself between the processing and egress domains.

fifo2clk_fwft.xdc

+
+

Two obligations fall on the integrator:

+
+
+

Include the constraint fragments. They ship next to the RTL and carry the false paths and datapath-only maximum delays the synchronizers need. The register-distribution bundles need one in particular: the control/status values that reach the ingress, processing and egress domains are pseudo-static and combinational by design, and rtl/pkg/ct_cs_cpuif_wb.xdc false-paths them as a group. Without it, a timing tool reports a large set of impossible cross-domain paths.

+
+
+

Group the clocks as asynchronous at the top level. The encoder’s own out-of-context synthesis figures assume exactly that grouping; cross-domain paths are outside that analysis by construction, which makes grouping them a system-level responsibility rather than an optional tightening.

+
+
+
+

17.5. Instruction ingress

+
+

The ingress is the interface tip_if (rtl/pkg/tip_if.sv:21), with its types in rtl/pkg/tip_pkg.sv. It is a fixed-latency retirement bus with no handshake: there is no ready signal and no backpressure toward the core. That is a deliberate property, not an omission — see the note at the end of this section.

+
+
+

17.5.1. Signals

+ +++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
SignalWidthMeaning

Instruction flow

iretire

1 or CT_IRETIRE_WIDTH

Retirement indication. One bit in the default mode; a half-word count in block mode.

iaddr

CT_XLEN

Address of the retired instruction (block mode: of the first instruction of the block).

ilastsize

2

Size of the retired instruction (block mode: of the last instruction of the block).

itype

4

Type of the retirement (block mode: how the block terminated).

ecause

4

Exception cause; meaningful only when itype is the trap type.

tval

CT_XLEN

Trap value.

priv

3

Privilege level.

_context

CT_CONTEXT_WIDTH

Context identifier.

ctype

2

Context-report type; a non-zero value is a context event.

impdef

8

Implementation-defined sideband.

_time

64

Time reference.

Data flow

dretire

1

Data access retirement.

dtype

4

Access type; the load encoding is 0, every other value is a write-class access.

daddr

CT_XLEN

Data address.

dsize

6

Access size as a base-two logarithm of the byte count.

data

64

Data value in the legacy (non-split) mode.

sdata

32

Store data, valid at dretire, in split-load mode.

lresp

2

Load response, valid when its upper bit is set; 2 = ok, 3 = error.

ldata

32

Load data, valid with the load response.

Event sideband

debug_mode

1

Level. Debug mode is active.

power_down

1

Level. The hart is powered down.

evti

1

Pulse, at least one clock wide. External trace trigger input.

trigger

1

Pulse. Watchpoint or trigger-fabric event.

+
+
+

17.5.2. Beat semantics

+
+
    +
  • +

    One beat per retirement opportunity. iretire marks a retired instruction; iaddr and ilastsize must be valid on that beat.

    +
    • +
  • +

    A synchronously faulting instruction does not retire. It is signalled with iretire = 0 and the trap type, and its program counter never appears in the decoded stream. Interrupts likewise use iretire = 0; the pre-empted instruction is re-executed after the return from the trap and appears then. This one-to-one retirement rule is what lets a consumer treat the decoded stream as an execution record rather than an attempt record.

    +
    • +
  • +

    itype must be valid whenever it is not the "other" value, even on a beat with iretire = 0 — trap markers ride non-retiring beats.

    +
    • +
  • +

    The two level signals must rise after the last retirement before the window and fall before the first retirement after it. Debug-mode entry produces a Correlation message, its exit a re-anchor with the exit-from-debug reason; power-down behaves the same way with its own reason code. While either level is high, no instruction trace is generated or counted.

    +
    • +
  • +

    An adapter that has no source for a sideband signal ties it to zero. All three current core adapters do this for the debug-related inputs, which is why the Debug Status message is not implemented — see Chapter 14.

    +
    • +
+
+
+
+

17.5.3. Block ingress

+
+

Setting the block-ingress build switch redefines the bus so that one beat can report a whole basic block, and widens the retirement field to CT_IRETIRE_WIDTH:

+
+ +++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
SignalDefault meaningBlock meaning

iretire

one instruction retired

half-words retired by the block

iaddr

that instruction’s address

address of the first instruction

ilastsize

that instruction’s size

size of the last instruction

itype

that instruction’s type

how the block terminated

+
+

The rules that follow from it:

+
+
+
    +
  1. +

    Only the last instruction of a block may be a control-flow event. The encoder derives the control-flow source address as iaddr + 2 * (iretire - 2^ilastsize) and the successor as iaddr + 2 * iretire.

    +
    2. +
  2. +

    iretire must fit CT_IRETIRE_WIDTH, which elaboration constrains to 2..8. A core whose block generator has no natural bound must have its adapter split long linear runs into several blocks that terminate with the "other" type. That is free on the wire: such a block raises no message, it only accumulates the count.

    +
    3. +
  3. +

    Trap beats are unchanged — still iretire = 0.

    +
    4. +
  4. +

    Address comparators, the watchpoint search and the performance counters compare one address per beat, which in block mode is the block start. Instruction-granular address filtering is not expressible on a block ingress. That is a property of the port, not a shortfall of the filters.

    +
    5. +
+
+
+

The switch adds no message type and no wire field, and carries no capability bit: in the reset configuration a block beat produces exactly the messages a serialized beat sequence would, with the same instruction count. That equivalence is measured, not asserted (scripts/cli_blocktip_test.sh).

+
+
+

What is not invariant: the periodic-synchronization cadence mode that counts retirement beats counts beats, not instructions, so periodic synchronization lands after a different amount of program.

+
+
+
+

17.5.4. Core adapters

+
+

The adapters that translate a specific core’s trace port into this interface live outside the encoder — for the AMD MicroBlaze™ V trace bus, for the CVA6 instruction trace interface fed from its verification interface probes, and for the Rocket trace core interface. Their port mappings and instruction-type semantics are in Chapter 6.

+
+
+ + + + + +
+
Note
+		 +The absence of backpressure is a contract in both directions. The core is expected to always be able to drive the ingress; the encoder is expected never to stall the core. When the encoder’s internal queues cannot keep up, the result is an announced loss on the egress side plus a counted overflow in the status registers — never a silent gap and never a stalled hart. The one standard feature this forecloses is the data-trace hart-stall policy: stalling a hart needs a back channel, the ingress port is unidirectional by construction, and no adapter could route one. The implemented alternative is the data-drop policy described in Chapter 14. +
+
+
+
+
+

17.6. Trace egress

+
+

The trace stream leaves through the interface atb_if
+(rtl/external/amba/atb_if.sv:14).

+
+ ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
SignalWidthDirectionMeaning

atdata

32

encoder → sink

Trace bytes.

atbytes

2

encoder → sink

Number of valid bytes on atdata.

atid

7

encoder → sink

Stream identifier.

atvalid

1

encoder → sink

Beat valid.

atready

1

sink → encoder

Beat accepted.

afvalid

1

sink → encoder

Flush request.

afready

1

encoder → sink

Flush acknowledgement.

syncreq

1

sink → encoder

Synchronization request from the sink side.

+
+

Backpressure through atready is legal at any time and for any duration. Sustained backpressure raises the rate of overflow episodes, and an overflow episode is announced: an Error message plus a recovery re-anchor tell the decoder exactly what it lost and where to resume. Nothing is dropped silently.

+
+
+

The flush handshake is: assert afvalid, wait for afready to fall, wait for it to rise, release afvalid (rtl/external/amba/atb_pkg.sv:18 carries the reference sequence as a task).

+
+
+

The framing on this port is advertised by atb_te_raw and is constant per instance. A funnel or sink downstream therefore parses the framing the netlist actually produces, rather than a second, software-programmed copy of that fact.

+
+
+
+

17.7. Event egress

+
+

Independently of the trace port, an AXI-Stream master (rtl/external/amba/axis_if.sv:12) carries instrumentation events to consumers inside the fabric. It exists for the case where the instrumentation data is processed on chip rather than exported.

+
+
+

The stream carries only the command-driven instrumentation path, and it carries it uncompressed: one fixed-format beat per command, with tid set to the command code so the beat is self-describing, and tstrb marking which of the fixed-width element slots are valid. tkeep, tlast, tdest and tuser are present in the interface but not driven.

+
+
+

The difference to the same event on the trace port is worth stating, because the two paths are easy to confuse: the trace port carries the event as a Data Acquisition message, variable-length and leading-zero-suppressed, framed into the Nexus byte stream (see Chapter 15); the AXI-Stream path carries it as one raw beat with no framing and no compression.

+
+
+
+

17.8. Control interface

+
+

Registers are reached over a Wishbone slave (wb_if, rtl/external/wishbone/wb_package.sv:75), 32 bits wide, with a 32-bit address of which 15 bits are decoded — a 32 KiB window. Internally the Wishbone transaction is adapted to the register block’s own request interface by rtl/external/wishbone/wb_to_cpuif.sv, instantiated in its combinational form; an AXI4-Lite bridge is available a level up for systems whose control fabric is AXI.

+
+
+

The control interface is its own clock domain. Every value that has to reach the ingress, processing or egress domain crosses through one of the primitives listed above, inside rtl/pkg/ct_cs_cpuif_wb.sv.

+
+
+

The register map itself, the programming order and the Enable lock are in Chapter 16.

+
+
+
+

17.9. Shutdown

+
+

Reaching a quiescent encoder is a sequence, and the order is not interchangeable:

+
+
+
    +
  1. +

    Flush — assert the flush request on the trace port, or use the sink’s flush control.

    +
    2. +
  2. +

    Stop tracing while the core is still retiring — clear trTeControl.InstTracing.

    +
    3. +
  3. +

    Stop the core.

    +
    4. +
  4. +

    Poll trTeControl.Empty until it reads 1, with trTeControl.Active still set.

    +
    5. +
+
+
+

Step 2 is the one that is easy to get wrong, and the failure is confusing rather than obvious. With instruction tracing still enabled and the core already stopped, exactly one control-flow event is permanently in flight — its successor address can never be observed, because no further instruction will retire. Empty then reads 0 forever, and that report is correct: there really is unresolvable trace in the pipeline. Closing the stream while the core still retires resolves that last event.

+
+
+

trTeControl.Empty is a conservative, crossing-safe status: it rises only after the entire chain — accumulators, formatter, packer, crossing queues, egress queue — has been observably quiet, and it falls immediately on any visible substance.

+
+
+

This sequence is contract-tested rather than merely documented; the verification chapter names the gate.

+
+
+
+

17.10. Feature switches, runtime controls and capability bits

+
+

Each optional feature of the encoder exists at three levels, and an integrator needs all three: a compile switch decides whether the netlist contains it, a register field decides whether it is active in this session, and a capability bit tells the decoder both facts over the wire. The table below is the mapping, condensed from the reference table in doc/integration.adoc (anchor feature-flags) of the CEDARtools.TraceEncoder repository.

+
+
+

Two columns need a word of reading instruction. Reset is the reset value of the runtime control, which is what an encoder does if nobody configures it — and it is 0 almost everywhere, deliberately: the unconfigured stream stays inside the standard message set. CAPS is the bit position in the capability map of the Vendor Config message (Chapter 18); a dash means the feature is not advertised, which for most of them is because it changes no wire format.

+
+ +++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Build switchRuntime controlResetCAPSSlim reference profiles

CT_EN_NTRACE / CT_EN_ETRACE

trTeProtocolSel.Protocol (read-only discovery, driven by the instance parameters)

 — 

 — 

as built

CT_EN_BLOCK_TIP

 — (build-time shape of the ingress)

 — 

 — ^(no message type, no wire field)^

off

CT_EN_BTM

trTeControl.InstMode = 3 (WARL; legal only if compiled in)

6

 — 

on

CT_EN_CONFIG_MSG

trTeControl.SendConfig

1 (CFG_ONCE)

 — ^(by design: it is the feature that transmits the map)^

on

CT_EN_OWNERSHIP

trTeControl.Context

0

7

on

CT_EN_DATA_TRACE

trTeDataControl.DataTracing

0

16

off

CT_EN_DF_ADDR_COMPRESS

trTeDataControl.DataAddrCompress (WARL; requires data trace)

0

21

off

CT_EN_DF_DROP

trTeDataControl.DataDropEna (runtime policy, not Enable-locked)

0

22

off

CT_EN_DAQ

 — (command-driven through the instrumentation command register)

 — 

17 (shared)

off

CT_EN_ACT

indirect watchpoint table, performance-counter registers (no single enable bit)

 — 

17 (shared)

off

CT_EN_FILTERS

trTeInstFilters, trTeDataFilters, trTeFilter[], trTeComp[]

0

 — 

off

CT_EN_FILTER_SYNC

none of its own — armed by a non-zero instruction filter

0

 — ^(a filter gap uses the existing pause vocabulary)^

off

CT_EN_TIMESTAMP

trTsControl.Enable (plus type, prescale, width)

1

15

on / off

CT_EN_AXIS_TS

 — (build-time shape of the event beat; requires timestamps and the instrumentation blocks)

 — 

 — ^(not a Nexus wire format)^

off

CT_EN_DEBUG_EVENTS

 — (ingress event port)

 — 

10

on

CT_EN_POWER_EVENTS

 — (ingress event port)

 — 

11

on

CT_EN_EVTI

 — (ingress event port)

 — 

12

on

CT_EN_TRIG_SYNC

trTeControl.InstTrigEnable

0

13

on

CT_EN_SEQ_SYNC

trTeControl.InstSeqSyncEnable

0

14

on

CT_EN_TRIG_REGS

trTeTrigExtInControl.ExtInAction0 (WARL)

0 (no action)

 — ^(the on-wire effect is capability bit 13)^

on

CT_EN_QUOTA_SYNC

trTeControl.InstSyncMode = 1 or 4, with InstSyncMax

0

18

on

CT_EN_DEVICE_ID

trTeControl.SendDeviceId (WARL)

0 (DID_NONE)

19

on

CT_EN_WATCHPOINT_MSG

trWpMask.WEM plus the watchpoint command (requires the instrumentation blocks)

0 (mask empty)

20

off

CT_EN_IMPLICIT_RETURN

trTeInstFeatures.InstEnImplicitReturn

0

0

off

CT_EN_REPEATED_HISTORY

trTeInstFeatures.InstEnRepeatedHistory

0

1

off

CT_EN_WIDE_ICNT

trTeInstFeatures.InstEnWideIcnt

0

2

off

CT_EN_REPEAT_BRANCH

trTeInstFeatures.InstEnRepeatBranch

0

3

off

CT_EN_JTC

trTeInstFeatures.InstEnJumpTargetCache

0

4

off

CT_EN_BP

trTeInstFeatures.InstEnBranchPrediction

0

5

off

CT_EN_IBHS

trTeInstFeatures.InstEnIbhs

0

8

on

CT_EN_REPEAT_INSTR

trTeInstFeatures.InstEnRepeatInstr

0

9

on

CT_EN_INST_SYNC_REQ

trTeControl.InstSyncReq (write-1, self-clearing, not Enable-locked)

0

 — ^(the vendor sync reason exists either way)^

on

CT_EN_SYNC_STATUS

trTeSyncStatus.SyncReqSource (read-only; the register is omitted from the map when off)

0

 — 

on

CT_EN_FIFO_HIST

trTeTipFifoHistCtrl, trTeTipFifoHistData (registers omitted when off)

0

 — 

on

CT_EN_ETIP_WATERMARK

trTeTipFifoStatus.trTeTipFifoMaxFill (reads 0 when off)

0

 — 

on / off

 — 

CT_SIJUMP (elaboration attribute, no register)

 — 

6

as built

CT_XLEN = 64

 — (a synthesis parameter, not a runtime mode)

 — 

23

as built

+
+

Two entries in the CAPS column are not features and are listed for completeness: bit 6 reports the ingress convention declared by CT_SIJUMP, and bit 23 reports the address width. Bit 23 has to be on the wire because a decoder cannot derive it from the stream — the address fields are variable-length with leading zeros stripped, so a 32-bit address and a 64-bit address whose upper bits happen to be zero occupy the same bytes.

+
+
+

The consistency of this mapping with the compile switches, the SystemRDL and the capability map is machine-checked in the source repository (scripts/check_feature_flags.py); the elaboration dependencies between switches — data-address compression and the drop policy following data trace, the watchpoint message following the instrumentation blocks — are checked separately (scripts/check_profile_deps.py).

+
+
+ + + + + +
+
Note
+		 +The measured resource cost of each switch is deliberately not in this table. Those figures are per profile and per tool version, and mixing them into a contract table invites comparing numbers that were never measured against each other. They belong with the footprint profiles; the underlying per-switch measurements and their artefact paths are in doc/integration.adoc (anchor feature-flags) of the source repository. +
+
+
+
+
+
+

18. N-Trace Self-Identification and Configuration Messages

+
+
+

A trace decoder has to know how the encoder was built and how it was configured. Every compression feature changes what the byte stream means, not just how much of it there is: a stream with the jump-target cache enabled contains cache indices where an otherwise identical stream contains addresses, and a decoder that does not know cannot tell the difference from the bytes.

+
+
+
+ + + + + + + + + + +
+
+
+ build profile +
+ elaboration, ct_pkg switches +
+
+
+ + + build profile... + + + + + + + + + + + +
+
+
+ CAPS +
+ compiled-in capability map +
+ read-only +
+
+
+ + + CAPS... + + + + + + + + + + + +
+
+
+ software +
+ reads CAPS, then enables +
+
+
+ + + software... + + + + + + + + + + + +
+
+
+ ENAB +
+ enabled subset, same bit positions +
+ read/write, resets to 0 +
+
+
+ + + ENAB... + + + + + + + + + + + +
+
+
+ Vendor Config message +
+ TCODE 58 +
+ CFGVER, CAPS, ENAB, parameters +
+
+
+ + + Vendor Config message... + + + + + + + + + + + +
+
+
+ trace stream +
+
+
+ + + trace stream + + + + + + + + + + + +
+
+
+ decoder +
+ configures itself +
+ from the message +
+
+
+ + + decoder... + + + + + + + + + + + + + + + + +
+
+
+ a set bit needs its CAPS bit +
+
+
+ + + a set bit needs its CAPS bit + + + + + + + + + + + + +
+
+
+ enable +
+ at run time +
+
+
+
+ + + enable... + + + + + + + + + + + + + + + + + + + + +
+
+
+ on trace-on +
+ edge +
+
+ (SendConfig) +
+
+
+
+ + + on trace-on... + + + + + + + + + + + + + + Text is not SVG - cannot display + + + + +
+
Figure 13. Capability and enable registers
+
+
+

There are two ways to give the decoder that knowledge. Either it is configured out of band — command-line flags, a configuration file, a convention — or the encoder puts it into the stream. CTTE’s N-Trace back end does the second: the Vendor Config message (TCODE 58) carries the compiled-in capabilities and the currently enabled subset, and the Device ID message (TCODE 1) carries the instance identity. Both are N-Trace messages; the E-Trace back end has no in-stream counterpart, so an E-Trace decoder stays with the first way (Section 13.3).

+
+
+

This chapter defines both messages, the controls that emit them, and what a decoder can and cannot do without them. The last section documents a failure mode that stays invisible until a second, unrelated setting changes.

+
+
+

18.1. The Vendor Config message (TCODE 58)

+
+

TCODE 58 sits in the vendor-defined range that IEEE-ISTO 5001-2012 Table 4-5 reserves for exactly this purpose (56 — 62); N-Trace 1.0 Table 9 confirms the same range as "designated for use by Vendor Defined messages". A decoder that does not know the message still frames it correctly through the message framing and can skip it.

+
+
+

18.1.1. Field list

+
+

After the transfer code and the source field, the message carries one
+fixed field and six variable-length ones
+(ct_L2_nexus_formatter.sv:661):

+
+ ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
FieldTypeMax bitsContent

CFGVER

vendor-fixed

4

Payload format version.

CAPS

vendor-variable

24

Compiled-in capability map.

ENAB

vendor-variable

24

Currently enabled subset, same bit positions.

PARAM0

vendor-variable

16

Source identification.

PARAM1

vendor-variable

12

Source inhibition, synchronization cadence, instruction mode.

PARAM2

vendor-variable

12

Timestamp unit configuration.

PARAM3

vendor-variable

13

Structural sizes of the compression models.

+
+

The maximum widths are upper bounds, not on-wire lengths: the six variable fields are leading-zero-suppressed like every other variable-length field, so a lightly configured encoder emits a short message.

+
+
+
+

18.1.2. Version and forward compatibility

+
+

CFGVER is currently 1 (ct_pkg.sv:377). The forward-compatibility rule is append-only: a future version may add fields after PARAM3, never reinterpret an existing one. A decoder written against version 1 therefore reads the first seven fields of any future message and ignores what follows — which is what the reference decoder does, with an informational note.

+
+
+

That rule is the reason CFGVER did not move when the address-width bit was added: the information is boolean and fitted into the existing capability map, and adding a PARAM4 would have been a structural change in the lean egress path, whose variable segments are all taken.

+
+
+
+

18.1.3. The capability map

+
+

CAPS reports what the netlist contains. One bit per feature, built directly from the compile switches (ct_cfgmsg_caps, ct_pkg.sv:723):

+
+ +++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitNameReports

0

IR

Implicit-return inference

1

RH

Repeated-history compression

2

WIDE_ICNT

Widened internal instruction-count cap

3

RB

Repeat-branch messages

4

JTC

Jump-target cache

5

BP

Branch prediction

6

SIJUMP

The attached core’s ingress uses the sequentially-implicit-jump convention — an integration attribute of the encoder instance, not a build switch

7

OWNERSHIP

Ownership messages

8

IBHS

Indirect-branch-history synchronization messages

9

REPEAT_INSTR

Repeat-instruction messages

10

DEBUG_EVENTS

Debug-mode entry and exit events

11

POWER_EVENTS

Power-down entry and exit events

12

EVTI

External trace-trigger input

13

TRIG_SYNC

Trigger-event synchronization marker

14

SEQ_SYNC

Sequential-instruction-counter synchronization

15

TIMESTAMP

Timestamp unit

16

DATA_TRACE

Data trace

17

DAQ

Data acquisition and the instrumentation blocks — one shared bit, because the two are not separable

18

QUOTA_SYNC

Trace-output quota synchronization cadence

19

DEVICE_ID

Device ID message

20

WATCHPOINT_MSG

Watchpoint message

21

DF_ADDR_COMPRESS

Data-address compression

22

DF_DROP

Data-trace drop policy

23

ADDR64

Not a feature: the architectural address width of this netlist

+
+

Bit 23 is the one entry that does not report a capability, and it has to be on the wire because a decoder cannot derive it from the stream. Address fields are variable-length with leading zeros stripped, so a 40-bit address and a 64-bit address whose upper bits happen to be zero are byte-for-byte identical. A decoder reads the bit and sizes its own program-counter state — and, critically, its jump-target-cache index fold — accordingly. A one-bit disagreement in that fold desynchronizes the two cache models silently.

+
+
+

Two features have no capability bit by design: the configuration message itself, because it is the feature that transmits the map, and the trigger registers, whose on-wire effect is already reported as bit 13.

+
+
+
+

18.1.4. The enabled map

+
+

ENAB uses identical bit positions and reports what is enabled right now. It is computed as the runtime term ANDed with CAPS (ct_L2_nexus_formatter.sv:151), so a bit set in a register of a netlist that does not contain the feature can never appear as enabled.

+
+
+

Most bits mirror a single register field:

+
+ ++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitRuntime source

0 — 5, 8, 9

The corresponding bit of te.trTeInstFeatures

7

trTeControl.Context

13

trTeControl.InstTrigEnable

14

trTeControl.InstSeqSyncEnable

15

trTsControl.Enable

16

trTeDataControl.DataTracing

22

trTeDataControl.DataDropEna

+
+

Four bits use mode selection as the enable, because the feature has no separate enable bit — selecting a non-default mode is switching it on:

+
+ ++++ + + + + + + + + + + + + + + + + + + + + + + + + +
BitCondition

18

trTeControl.InstSyncMode selects one of the two trace-output quota cadence modes

19

trTeControl.SendDeviceId is not the "none" value

20

trWpMask.WEM is non-zero

21

trTeDataControl.DataAddrCompress is not the full-address mode

+
+

Six bits have no runtime enable at all and mirror CAPS: 6 (the ingress convention), 10, 11, 12 (the three event inputs), 17 (the instrumentation group) and 23 (the address width).

+
+
+
+

18.1.5. The parameter words

+ ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
WordBitsFieldSource

PARAM0

[15:4]

source identifier

trTeInstFeatures.SrcID

[3:0]

source-field width

trTeInstFeatures.SrcBits

PARAM1

[11]

source field inhibited

trTeControl.InhibitSrc

[10:7]

synchronization interval exponent

trTeControl.InstSyncMax

[6:3]

synchronization cadence mode

trTeControl.InstSyncMode

[2:0]

instruction-trace mode

trTeControl.InstMode

PARAM2

[11:6]

timestamp width

trTsControl.Width

[5:4]

timestamp prescale

trTsControl.Prescale

[3:1]

timestamp type

trTsControl.Type

[0]

timestamp enable

trTsControl.Enable

PARAM3

[12:8]

return-stack depth

ct_pkg::CT_RET_STACK_DEPTH

[7:4]

branch-predictor size, base-two logarithm

ct_pkg::CT_BP_ENTRIES

[3:0]

jump-target-cache index width

ct_pkg::CT_JTC_ENTRIES

+
+

Source: ct_L2_nexus_formatter.sv:125 (the third word, a build-time constant) and :177 (the three runtime words).

+
+
+

PARAM3 is worth a sentence of its own. It is built from the same package constants the implementing modules consume, so the advertised model sizes cannot drift from the built hardware — a decoder that sizes its return stack, its predictor table and its cache from these three fields is by construction in step with the encoder.

+
+
+
+

18.1.6. When it is emitted

+
+

Emission is controlled by trTeControl.SendConfig:

+
+ +++++ + + + + + + + + + + + + + + + + + + + + + + + + +
ValueNameBehaviour

0

CFG_NONE

Never emitted.

1

CFG_ONCE

Once per trace-on edge — the rising edge of effective instruction tracing.

2

CFG_ON_SYNC

As above, plus one message after every periodic synchronization.

+
+

The reset value is CFG_ONCE. This is the one feature in the full build profile whose reset is not "off", and it is a deliberate trade: an unconfigured encoder produces a self-describing stream. Set CFG_NONE for a stream that contains only transfer codes the N-Trace profile adopts.

+
+
+

"Once per trace-on edge" is not "once per session". After an
+instruction-tracing pause the message is sent again — which is exactly
+what a decoder attaching during the pause needs
+(ct_L23_preproc_composer_etip.sv:610).

+
+
+

The payload is sampled at the emission site, not latched when SendConfig was written. That is safe because the fields it reports are quasi-static: they are Enable-locked and can only change while the encoder is disarmed, and every such change implies a new trace-on edge and therefore a new message. SendConfig itself is not Enable-locked and may be changed while the trace runs.

+
+
+
+
+

18.2. The Device ID message (TCODE 1)

+
+

TCODE 1 carries the static identity of the encoder instance: the value of the CT_DEVICE_ID elaboration parameter, laid out per IEEE-ISTO 5001-2012 Table B-5 (revision number, part number, manufacturer identifier). The default 0 means the integrator assigned no identity.

+
+
+

Emission is controlled by trTeControl.SendDeviceId, whose reset value is "none" — deliberately unlike SendConfig. The reason is conformance arithmetic rather than preference: N-Trace 1.0 Table 9 does not adopt TCODE 1, so leaving it off keeps the default stream inside the adopted message set. Setting it to the "once" value emits one message per trace-on edge, with the same trigger as CFG_ONCE.

+
+
+

The on-wire order is Device ID, then Config, then the first synchronizing message. This is a contract, not an ordering that happens to fall out: the Device ID slot is filled before the Config slot in the same beat, and an assertion checks the relation (ct_L23_preproc_composer_etip.sv:576 and the ordering assertion at :2172). A decoder therefore learns which device produced the stream before it learns how that device is configured, and both before it has to decode anything.

+
+
+

One documented deviation applies: IEEE-ISTO 5001-2012 Table 4-7 specifies the identifier field as "Fixed 32", and CTTE emits it as a variable-length field with leading zeros stripped. The reason is that a fixed field would need a special case in both egress paths and in the decoder’s table mechanism, for a value a decoder reads as an integer anyway. A decoder that expects 32 fixed bits must be told; the reference decoder reads the variable form.

+
+
+
+

18.3. What a decoder does with it

+
+

The reference decoder uses the configuration message to configure itself, and its rules are worth stating because they define what the message is for:

+
+
+
    +
  • +

    Enable-only. An enabled bit switches a decoder feature on; a cleared bit never switches one off that a command-line flag or an earlier message enabled. A configuration message therefore cannot break a correctly configured decoder.

    +
    • +
  • +

    The command line wins. Where an explicit flag and the message disagree, the flag is used and a warning is printed.

    +
    • +
  • +

    Some values are checked, not applied. The return-stack depth is compared against the decoder’s configured mirror and a mismatch is warned about rather than silently resized — re-initializing the mirror mid-stream would discard live entries.

    +
    • +
  • +

    The address width is applied on first sight and never narrowed. A configuration message that arrives after decoding has already started produces a warning, because the lines already printed are narrower than those that follow.

    +
    • +
+
+
+

Without the message, a decoder falls back to its command-line configuration. That works when the operator knows the encoder configuration and passes it correctly. The failure mode is that nothing checks the assumption — which is the subject of the next section.

+
+
+
+

18.4. Failure mode: a stream that never says what it is

+
+

This is the most expensive configuration mistake the encoder allows, and it is worth a section of its own because every property that makes it expensive is a property of not noticing.

+
+
+

The account below is taken from commit 7d91c2f8 of the CEDARtools.TraceEncoder repository, which fixed it; the two control words and the symptom are quoted from that commit’s message and its diff of examples/kv260/cva6_linux/board/cva6_linux_boot_trace.sh.

+
+
+

What happened. A board bring-up script programmed the control register with a constant that had SendConfig = CFG_NONE. No configuration message was emitted, so the decoder ran entirely on its command-line defaults.

+
+
+

Why nothing was visible. The same constant had the synchronization interval at its minimum, so periodic synchronization re-anchored the decoder every 16 instruction units. The branch-history buffer never filled, so the repeated-history compression never emitted a Resource Full message with the repeated-history reason — and that message class was precisely where the missing configuration would have mattered. The setup worked, repeatedly, for as long as that unrelated setting stayed at its non-default value.

+
+
+

When it broke. Raising the synchronization interval to the register’s reset value — 1024 units instead of 16 — let the history buffer overflow for the first time. At the first repeated-history message the decoder’s assumptions parted company with the encoder’s behaviour and it walked 20 million program counters into a startup hang symbol — the figure the fixing commit records. Not a decode error, not a warning: a plausible-looking, entirely wrong reconstruction.

+
+
+

The two control words, decoded field by field against
+Chapter 16:

+
+ ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
FieldBroken 0x01060067Corrected 0x016600E7Effect

Active, Enable, InstTracing

1, 1, 1

1, 1, 1

unchanged

InstMode

6 (history)

6 (history)

unchanged

SendConfig

0 — CFG_NONE

1 — CFG_ONCE

no configuration message at all

InhibitSrc

0

0

unchanged

InstSyncMode

6 (instructions)

6 (instructions)

unchanged

InstSyncMax

0 — period 16

6 — period 1024

the setting that made the first defect visible

Format

1

1

unchanged

SendDeviceId

0 (none)

0 (none)

unchanged

+
+

The two words differ in exactly three bits: bit 7, the low bit of SendConfig, and bits 21 and 22 of InstSyncMax. Everything else is identical.

+
+
+

What to take from it. Three things, in order of usefulness:

+
+
+
    +
  1. +

    A control-register constant is a configuration, and it deserves the same review as one. A hexadecimal literal in a script hides which fields it sets and, more importantly, which it leaves at zero. Prefer composing the word from named fields.

    +
    2. +
  2. +

    SendConfig = CFG_NONE should be a deliberate choice, never a leftover. There is one good reason to select it — a stream that must contain only transfer codes the N-Trace profile adopts — and it is worth writing down when it applies.

    +
    3. +
  3. +

    A defect that only manifests under a second, unrelated setting is not a rare defect; it is a latent one. The absence of a configuration message is invisible for as long as no message class needs it. That is an argument for emitting it by default, which is why the reset value is CFG_ONCE.

    +
    4. +
+
+
+

The configuration recipes that follow from this — how to compose a control word, and the other pitfalls of the same family — are in Chapter 26.

+
+
+ + + + + +
+
Note
+		 +One case cannot be fixed by SendConfig alone. A stream with instruction tracing disabled carries no configuration message, because the emission trigger is the instruction-trace-on edge. A decoder joining a data-only stream mid-stream therefore cannot auto-detect the data-address compression mode. Either keep a program-trace stream alive alongside it, or provide the mode to the decoder out of band. +
+
+
+
+
+
+

19. Hardware-Supported Instrumentation (ACT-CAP / ACT-ST / ACT-Proc)

+
+
+

CEDARtools.TraceEncoder (CTTE) carries a hardware-supported instrumentation (HSI) path that lets a traced hart — or the encoder itself — inject instrumentation events into the trace stream without a bus transaction and without a change to the CPU.

+
+
+ + + + + +
+
Important
+		 +What of this path is reachable depends on the core, and the answer is not the same for the three blocks. ACT-ST works everywhere: it triggers on a retired instruction address and needs nothing but iaddr, which all four cores documented in Chapter 6 deliver. ACT-CAP is reachable on no shipped core as delivered, because none of the four reports CSR writes on the trace ingress port — the per-core table in Section 6.1.3 states this together with the reason and with the adapter-level way out. That way out has since carried ACT-CAP onto silicon: the tgc5b2_rvcfi testbed drives doorbell-converted ACT-CAP commands on the KV260 with board verdicts of 2026-08-26 (Chapter 28). Everything that needs the data channel — data trace, the data-flow range filter and the DAQ_DATA / DAQ_DADDR / DAQ_DATA_DADDR commands — works on the MINRES TGC5B only; on CVA6, Rocket and MicroBlaze™ V those commands carry no payload at all, because the encoder never receives a data beat. This chapter describes the mechanism; the table says where it can be exercised. +
+
+
+

Three preprocessor blocks implement the path:

+
+ +++++ + + + + + + + + + + + + + + + + + + + + + + + + +
BlockLong nameRTL module

ACT-CAP

Accemic CEDARtools CSR Access Protocol — software-issued commands, observed as CSR writes on the Trace Ingress Port (TIP)

rtl/preproc/ct_L23_preproc_act_cap.sv

ACT-ST

Accemic CEDARtools Smart Trigger — hardware-synthesized commands, fired by a retired-PC match against the watchpoint table

rtl/preproc/ct_L23_preproc_act_st.sv

ACT-Proc

Accemic CEDARtools Instrumentation Processor — merge, arbitration and side-effect dispatch for both sources

rtl/preproc/ct_L23_preproc_act_proc.sv

+
+ + + + + +
+
Note
+		 +The shared ACT- prefix reads *A*ccemic *C*EDAR*T*ools; it names the house mark rather than any single product. +
+
+
+

All three blocks are instantiated behind the CT_EN_ACT build switch (rtl/ct_L23_preproc.sv, generate block genAct). With CT_EN_ACT = 0 the stub branch genActStub ties the downstream command interface to "no command" and drives the four tracing-override signals to 0, so a control-flow-only profile contains no ACT logic at all and the composer’s DAQ, watchpoint and sync-request arms are provably unreachable.

+
+
+

19.1. What the instrumentation path is for

+
+

The motivating cases, in the order they drove the design:

+
+
+
    +
  • +

    Design-time data trace — emit a chosen value, address or program counter at a chosen source line, without a data-trace configuration that would export everything around it.

    +
    • +
  • +

    Run-time reconfiguration of the trace subsystem from the traced hart — turn instruction or data tracing on and off, or request a synchronization message, without any access to the encoder’s control bus.

    +
    • +
  • +

    Branch coverage and MC/DC evidence — a marker per decision outcome, carried in the same stream as the control-flow trace and therefore ordered against it.

    +
    • +
  • +

    Timestamp control at meaningful program points — a timestamp taken where the analysis needs one, instead of a fixed cadence that is either too coarse to be useful or dense enough to push the stream into overflow.

    +
    • +
+
+
+

The last point is the reason the mechanism is a command rather than a counter setting: a synchronization or timestamp emitted every n branches ignores the structure of the control flow, and raising the rate until it does not costs bandwidth in every part of the program that did not need it.

+
+
+
+

19.2. ACT-CAP — commands observed on the TIP

+
+

ACT-CAP rests on one property of the Trace Ingress Port: every retired data access of the traced hart, including CSR accesses, is visible to the encoder. When the hart writes the command CSR, the encoder sees the write together with its target CSR number and decodes it — no CPU modification, no dedicated port, and no system-bus transaction. Functionally the write behaves like a NOP; the only requirement on the integration is that the write must be permitted at the executing privilege level, so that it does not raise an exception.

+
+
+

The decode is a single qualified comparison in
+ct_L23_preproc_act_cap.sv:

+
+
+
+
1
+2
+3
+4
+5
+6
+
if (tip.dretire && (tip.dtype == CSR_READ_WRITE)) begin
+    if (tip.daddr == ACT_CAP_CMD) begin
+        ValidPipe[0] <= 1;
+        CmdPipe  [0] <= tip_data_to_cmd(tip.data);
+    end
+end
+
+
+
+
+

ACT_CAP_CMD is CSR_ACT_CAP_BASE + 0 = 0x0B10 (rtl/pkg/nexus_vendor_riscv_pkg.sv:144); the surrounding 0x0B10--0x0B9F core-specific CSR window is reserved for the protocol but no second address is decoded in the current implementation. The write data is unpacked by tip_pkg::tip_data_to_cmd (rtl/pkg/tip_pkg.sv:457) into the {Cmd, Sink, DirectData} command word described in the chapter The trActCapStCmd Command CSR; the inverse function cmd_to_tip_data is what the verification environment uses to drive a command, so both directions come from one definition.

+
+
+

0x0B10 is a CPU-side CSR. The encoder does not decode it on its control bus; the register appears in the SystemRDL source only as a type anchor and is marked ispresent = false there, so no register exporter offers it as a memory-mapped register (rdl/ct_cs_cpuif.rdl:112-120).

+
+
+

The captured command advances through a shift pipeline whose tap is selected by extra_delay, so ACT-CAP events stay aligned with the control-flow and data-flow preprocessing paths. The block’s own latency is one cycle (internal_delay = 1); reset clears the whole valid pipeline, so no command can survive a reset.

+
+
+
+

19.3. ACT-ST — commands synthesized by the encoder

+
+

ACT-ST removes the software step. The block watches the retired instruction stream and compares the retired instruction address against the watchpoint table; on a match it fetches the 32-bit command word stored with that entry and injects it into the same pipeline an ACT-CAP write would have entered. The software under test needs no instrumentation at all, and the reaction latency is fixed and known.

+
+
+

19.3.1. Trigger source and matcher

+
+

The comparison is a RAM-backed perfect binary search tree (vector_binary_search_2clk, one on-chip RAM per level, one lookup per cycle) instantiated with the key type tip_iaddr_t and qualified by TipBeatRetires(tip.iretire) — that is, by a retiring beat, not by a raw strobe, so the block behaves identically for serialized and block TIP ingress.

+
+ +++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
PropertyValueSource

Tree dimension M0_DIM

10

rtl/pkg/ct_pkg.sv:988

Table capacity M0_N = 2M0_DIM − 1

1023 slots

rtl/pkg/ct_pkg.sv:989; software discovery via trWpCap.Entries (0x4020)

Matcher chain latency

4 × M0_DIM = 40 cycles

elaboration guard in ct_L23_preproc_act_st.sv:92; runtime guard idelay_act_st == 4*M0_DIM in ct_L23_preproc.sv:160

Preprocessor alignment budget with ACT

PREPROC_DELAY_MAX = 44

rtl/pkg/ct_pkg.sv:925 (ACT branch: act_st 41 + act_proc 1)

+
+

The alignment budget is charged to CT_EN_ACT alone: a profile with data trace but without ACT keeps the historical budget of 20, and a control-flow-only profile 4 or 2. That asymmetry is deliberate — every EXTRA_DELAY_MAX-deep alignment pipe in the preprocessor is sized by this constant, so an ACT profile pays for the ten-level tree in every one of them.

+
+
+
+

19.3.2. Programming the table

+
+

The table is loaded through an indirect register pair; the direct memory window at 0x4100 that earlier revisions used no longer exists, because 1023 entries of 8 bytes would overlap the DF range-filter component at 0x5000. The registers are defined in rdl/ct_cs_cpuif.rdl:1420-1541:

+
+ +++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
RegisterOffsetFunction

trWpIndex.Idx

0x400C

Slot index the next commit or readback targets. Wraps at NUM_ACT_ST − 1. Reads return the current pointer, so after n commits from slot i it reads (i + n) mod NUM_ACT_ST.

trWpDataLow.Value

0x4010

Staged Addr (the PC that arms the entry). A Low write alone has no effect.

trWpDataHigh.{Cmd,Sink,DirectData}

0x4014

Staged command word. Writing this register commits the staged pair to slot Idx and increments Idx. Same bit layout as CSR 0x0B10.

trWpReadLow / trWpReadHigh

0x4018 / 0x401C

Readback of the shadow copy at Idx. The High read advances Idx (serial readback); the Low read does not.

trWpCap.Entries

0x4020

Implemented slot count. Reads 0 in profiles without the ACT blocks.

+
+

Four programming rules follow from the tree layout and are stated normatively in the register description:

+
+
+
    +
  1. +

    Fill all trWpCap.Entries slots. The flat slot index is the position in the key-sorted array, which the hardware maps in order onto the tree (even indices are the leaves, an odd index takes the inner level given by its count of trailing one bits, the median index is the root). Leaving slots at their reset value can mask real watchpoints, because a lookup that reaches an empty inner node stops there.

    +
    2. +
  2. +

    Keys must be strictly ascending and unique across slot 0 to slot Entries − 1.

    +
    3. +
  3. +

    Each slot is a pair: write trWpDataLow, then trWpDataHigh.

    +
    4. +
  4. +

    Load the table only while trTeControl.Enable = 0. This is enforced in hardware: the three load registers are write-locked while enabled, and the commit pulse is suppressed as well. Readback stays live, by design, so a debugger can walk the table of a running session.

    +
    5. +
+
+
+

For slots that are not real watchpoints, choose an address the hart can never execute — an odd instruction address is the natural choice, since the core forces PC[0] = 0 — and set Cmd = ACT_CAP_ST_NONE. Padding keys still have to satisfy rule 2.

+
+
+

The shadow copy behind trWpReadLow/trWpReadHigh is zero-initialized at configuration load and is not cleared by a soft reset; it reflects everything committed since configuration, the same persistence the search tree itself has.

+
+
+
+

19.3.3. Address-width limit at XLEN = 64

+
+

The matcher key follows the architectural address width (M0_K = logic [CT_XLEN-1:0]), but the software-visible table entry keeps its 32-bit Addr word. In a 64-bit configuration the upper key half is therefore written as zero: a watchpoint can be placed anywhere in the low 4 GiB and never matches a higher address. This is a configuration limit of the load path, not a truncation in the comparison — the full-width address enters the comparison unchanged (rtl/pkg/ct_pkg.sv:992-1000).

+
+
+
+
+

19.4. ACT-Proc — merge, priority and side effects

+
+

ACT-Proc takes the two command interfaces and produces one ordered command stream for the composers, plus the direct control side effects.

+
+
+

19.4.1. Merge and priority

+
+

The arbitration is fixed and combinational: if both sources are valid in the same cycle, ACT-ST wins and the software-issued ACT-CAP command of that instruction is dropped. The intent is that a smart trigger placed on an instrumented instruction neutralizes the instrumentation it replaces, rather than producing two events for one program point.

+
+
+
+

19.4.2. Sink decode

+
+

The Sink field of the command word selects the dispatch path. ACT-Proc implements exactly two branches:

+
+ ++++ + + + + + + + + + + + + + + + + +
SinkEffect in ACT-Proc

ACT_CAP_ST_SINK_NEXUS, ACT_CAP_ST_SINK_AXIS, ACT_CAP_ST_SINK_AXIS_NEXUS

The command is admitted into the output pipeline if its Cmd is one of the ten DAQ_* commands, ACT_CAP_ST_CF_SYNC or ACT_CAP_ST_WATCHPOINT. Any other Cmd value is silently discarded — an unsupported command produces no message, which is what the register description promises.

ACT_CAP_ST_SINK_TE

No message of any kind. DirectData is reinterpreted as a TE control request and applied directly; the command is not forwarded to the composers.

+
+ + + + + +
+
Important
+		 +For a TE control request the Cmd field is not examined at all — Sink = ACT_CAP_ST_SINK_TE is what selects the behaviour (ct_L23_preproc_act_proc.sv:138-150). Conversely, Cmd = ACT_CAP_ST_TE (13) sent to a message sink matches none of the admitted command values and therefore does nothing. +
+
+
+
+

19.4.3. TE control side effects

+
+

With Sink = ACT_CAP_ST_SINK_TE the 24-bit DirectData field is cast to the packed structure ct_act_cap_te_t (rtl/pkg/ct_pkg.sv:971-979):

+
+ +++++ + + + + + + + + + + + + + + + + + + + +
Sub-fieldBits of DirectDataMeaning

ctrl

[23:16]

Selects the TE control target: 0 = ACT_CAP_TE_INSTR_TRACING (trTeControl.InstTracing), 1 = ACT_CAP_TE_DATA_TRACING (trTeDataControl.DataTracing). Any other value is ignored.

data

[15:0]

Carries the new state. For ctrl = 0 the encoder evaluates data[0]; for ctrl = 1 it evaluates data[1]. A 1 asserts the corresponding …​TracingSet strobe, a 0 the …​TracingClr strobe.

+
+

Both strobes are single-cycle pulses into the CSR shim, which is how a traced hart switches instruction or data tracing on and off without any control-bus access.

+
+
+
+

19.4.4. Ordering, latency and backpressure

+
+

ACT-Proc preserves the temporal ordering of events as observed at the TIP; no reordering of trace-relevant events takes place. Its own latency is one cycle, on top of which the selectable extra_delay tap aligns the ACT branch with the peer preprocessing paths. The latency is a function of the build configuration only — it does not depend on runtime data values or on the message type. Backpressure from downstream logic can delay emission but cannot change the order in which events were observed.

+
+
+
+
+

19.5. How an ACT-ST hit becomes visible in the trace stream

+
+

Two mechanisms make a trigger visible; they are separate and can be used independently.

+
+
+

The message the command asks for. The Cmd field decides what is emitted: a Data Acquisition message (TCODE 7) for the ten DAQ_* commands, an instruction synchronization message for ACT_CAP_ST_CF_SYNC, or a Watchpoint message for ACT_CAP_ST_WATCHPOINT.

+
+
+

The Watchpoint message, TCODE 15. This is the direct answer to the question "which watchpoint fired". The command ACT_CAP_ST_WATCHPOINT (value 14) makes the encoder raise a Watchpoint message whose WPHIT field is a bitmap of the watchpoints reported:

+
+
+
+
WPHIT = Cmd.DirectData[15:0] AND trWpMask.WEM
+
+
+
+

The slot-to-bit assignment is a software convention, not hardware: give each watchpoints[] entry the DirectData bit that should identify it — one-hot is the obvious choice — and enable the same bit in trWpMask.WEM (0x4008). A command whose masked result is zero emits nothing. The mask resets to 0, so adding the feature to an existing build changes no wire byte until software opts in.

+
+
+

The message is emitted with the field order of the Nexus standard’s Watchpoint message (TCODE, SRC, WPHIT, TSTAMP; rtl/pkg/nexus_vendor_riscv_pkg.sv:660-670, referencing IEEE-ISTO 5001-2012 §4.3.23 and Table 4-37). The internal payload width is 16 bits, one per reportable slot; on the wire WPHIT remains a variable-length MDO field with leading zeros stripped, so the internal width bounds the eTIP payload, not the wire.

+
+
+

Three properties are worth stating explicitly because they are easy to get wrong:

+
+
+
    +
  • +

    A watchpoint command produces no Data Acquisition message. The DAQ arm of the eTIP composer excludes both ACT_CAP_ST_WATCHPOINT and ACT_CAP_ST_CF_SYNC (ct_L23_preproc_composer_etip.sv:1049-1060), and an assertion checks that the two never share one beat (a_p4_wp_daq_exclusive, same file, line 2161).

    +
    • +
  • +

    The feature is compile-gated by CT_EN_WATCHPOINT_MSG, which itself requires CT_EN_ACT. In a build without it, trWpMask.WEM reads as a constant 0 and the composer raises no slot, so a forwarded watchpoint command is inert rather than an error.

    +
    • +
  • +

    On-wire capability is advertised in the vendor Config message (TCODE 58) as CAPS/ENAB bit 20 (rtl/pkg/ct_pkg.sv:728), so a decoder can discover whether the stream can contain TCODE 15 at all.

    +
    • +
+
+
+

Where the watchpoint mechanism is not used, a trigger still reaches the stream as the anonymous synchronization reason NEXUS_SYNC_WATCHPOINT (sync reason 6, "trace event"). The difference is exactly the identity of the trigger: reason 6 says that something fired, TCODE 15 says which.

+
+
+

For the full field layout of both messages see the message catalog chapter; for the DQDATA payload of the DAQ commands see the Data Acquisition payload chapter.

+
+
+
+

19.6. Synchronization requests from the traced hart

+
+

ACT_CAP_ST_CF_SYNC (12) requests an instruction synchronization message. The command rides on the retiring csrw 0x0B10 — an instruction of type OTHER — and is turned into a synchronization exactly as a periodic sync landing on a non-control-flow instruction would be. If a real synchronization reason is already present on that beat, the real reason takes precedence; a synchronization is emitted either way.

+
+
+

On the wire the reason is the single vendor code NEXUS_SYNC_REQ = 14 ("explicit sync request"). N-Trace 1.0 Table 25 reserves codes 10 to 13 for future standard use, which is why the earlier per-source codes 12 (CSR) and 13 (ATB) are no longer emitted. The source of the request stays readable for diagnosis in the read-only field trTeSyncStatus.SyncReqSource (0xE08), which reports SYNC_REQ_CSR = 1 for an ACT-CAP CF_SYNC and distinguishes it from SYNC_REQ_ATB, SYNC_REQ_QUOTA and SYNC_REQ_TE.

+
+
+

A decoder does not need the distinction: every synchronization message is a full re-anchor.

+
+
+
+

19.7. Determinism and reset behaviour

+
+

The instrumentation path is deterministic in the sense a trace-based verification argument needs:

+
+
+
    +
  • +

    Fixed, configuration-dependent latency. Each block reports its own latency to the preprocessor (internal_delay): 1 cycle for ACT-CAP, 1 + matcher for ACT-ST (40 cycles at M0_DIM = 10), 1 cycle for ACT-Proc. None of these depends on the command, the payload or the message type.

    +
    • +
  • +

    Elaboration-time budget checks. ACT-ST checks its own chain length against EXTRA_DELAY_MAX at elaboration and fails the build if the budget is too small; ct_L23_preproc repeats the check at simulation time against the reported delay. A silent misalignment between the ACT branch and the control-flow branch is therefore not a possible failure mode.

    +
    • +
  • +

    Order preservation. Multiple matches are serialized by the pipeline with per-event order preserved; ACT-Proc adds no reordering.

    +
    • +
  • +

    Clean reset. Every valid pipeline is cleared on reset, in all three blocks, so no command emitted before the reset can appear after it.

    +
    • +
+
+
+

The one state that deliberately survives is the watchpoint table and its readback shadow: both are configuration, not trace state, and are not cleared by a soft reset.

+
+
+
+

19.8. Licensing of ACT-CAP and ACT-ST

+
+

ACT-CAP and ACT-ST are implemented in the hardware IP under rtl/ and are covered by the same licence as the rest of it. The terms, and the question of whether a third-party implementation of these mechanisms carries any obligation beyond that licence, are stated once in Section 37.5 — not here.

+
+
+
+

19.9. Related mechanisms in other architectures

+
+

The idea of a software-issued marker that the trace hardware picks up without a bus transaction exists elsewhere; the table is given so an integrator can place CTTE’s mechanism against what they already know. It is not a feature comparison.

+
+ ++++ + + + + + + + + + + + + + + + + + + + + + + + + +
MechanismCharacter

Nexus Data Acquisition message, TCODE 7 (IEEE-ISTO 5001-2012 §4.3.21)

The message CTTE uses to carry the DAQ payload. It is a public message of the standard, not an Accemic extension; what is CTTE-specific is the command set that produces it and the payload layout inside DQDATA.

Arm A64 TRCIT (an alias of SYS)

A dedicated instruction that writes a value into the instruction-trace stream.

Intel PTWRITE

A dedicated instruction that writes a value into a Processor Trace packet.

Arm System Trace Macrocell (STM)

A separate trace source with memory-mapped stimulus ports and its own global timestamp, used for system-activity and trigger indication.

+
+

CTTE’s variant differs in what it costs the integration rather than in what it achieves: the command is an ordinary CSR write on an existing port, so it needs no new instruction, no new bus master and no change to the core.

+
+
+
+

19.10. Verification status

+ ++++ + + + + + + + + + + + + + + + + + + + + + + + + +
AspectEvidence

Full ACT-CAP command set, both sinks

tests/hsi/01_csr_cap/csr_cap_tb.sv — fires every command that produces output to ACT_CAP_ST_SINK_AXIS_NEXUS, self-checks the AXIS beat via ct_axis_decoder, and checks the ATB capture for the synchronization messages (>= 2: startup plus the CF_SYNC).

ACT-ST table: capacity, boundary slots, index autoincrement, readback, soft-reset persistence

tests/instruction/19_feature_matrix/feature_matrix_tb.sv, phases Ph.10 / Ph.10b / Ph.10c / Ph.11 — full 1023-slot load in ascending key order; hits proven on slot 0, slot 511 (tree root) and slot 1022 (last leaf); an unarmed PC proven silent; trWpCap.Entries checked against M0_N.

Watchpoint message (TCODE 15) and the WEM mask

tests/instruction/31_status_msgs/status_msgs_tb.sv — scenarios wp (WEM = 0xFFFF, expected WPHIT 0x1 / 0x2 / 0x8001), wpmask (WEM = 0x0002, negative control: exactly one message survives), both (device ID, config and watchpoint messages in one stream) and wpaxis (the same command on the AXIS sink). The test also asserts that a watchpoint command produces no Data Acquisition message.

Block-level behaviour of the three ACT modules

rtl/preproc/test/ct_L23_preproc_act_cap_tb.sv, ct_L23_preproc_act_st_tb.sv, ct_L23_preproc_act_proc_tb.sv

+
+
+
+
+

20. The trActCapStCmd Command CSR

+
+
+

CTTE carries every ACT-CAP and ACT-ST command in one 32-bit word. Software delivers it by writing the RISC-V CSR trActCapStCmd at CSR address 0x0B10; the ACT-ST hardware delivers the identical word from a watchpoint table entry. Downstream of the instrumentation processor the two are indistinguishable — everything is driven by the command word.

+
+
+

This chapter is the normative description of that word. The authoritative source for the layout and the enumerations is rdl/ct_cs_cpuif.rdl:56-120; the SystemVerilog typedefs the RTL uses are regenerated from it into rtl/pkg/ct_cs_cpuif_types_pkg.sv by scripts/generate_wb_pkg.py.

+
+
+

20.1. Register definition

+ +++++ + + + + + + + + + + + + + + + + + + + + + + + + +
FieldBitsDescription

Cmd

[5:0]

Instrumentation command. Encoded as trActCapStCmd_e; see Section 20.2. Reset 0.

Sink

[7:6]

Destination of the command’s effect. Encoded as trActCapStSink_e; see Section 20.3. Reset 0.

DirectData

[31:8]

24-bit command-specific payload. Reset 0.

+
+ + + + + +
+
Important
+		 +0x0B10 is a CPU-side CSR of the traced hart, not a memory-mapped register of the encoder. The encoder never decodes 0x0B10 on its control bus; it observes the write on the Trace Ingress Port. In the SystemRDL source the register carries ispresent = false and exists only as a type anchor, so no register exporter — HTML, C header or regblock — offers it as an addressable register. The same bit layout is reachable through the control bus as the watchpoint table’s command word, trWpDataHigh at 0x4014. +
+
+
+

The word is placed on the TIP data channel by tip_pkg::cmd_to_tip_data and recovered by tip_pkg::tip_data_to_cmd (rtl/pkg/tip_pkg.sv:446-467), both of which use exactly the bit positions above.

+
+
+
+

20.2. Cmd field: trActCapStCmd_e

+ +++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
EnumeratorValueMeaning

ACT_CAP_ST_NONE

0

Do nothing. The command word is ignored by the ACT processing pipeline. Use it as the "no operation" value for unused watchpoint slots.

ACT_CAP_ST_DAQ_PC_CURR

1

Transmit a DAQ message containing the current program counter plus DirectData[23:0].

ACT_CAP_ST_DAQ_PC_CURR_LAST

2

Transmit a DAQ message with the current PC, the previous PC before an exception or interrupt, plus DirectData[23:0]. Useful to correlate a trap with the instruction that caused it.

ACT_CAP_ST_DAQ_DIRECT_DATA

3

Transmit a DAQ message carrying only the 24-bit DirectData value. The cheapest marker: an application-defined event ID with no automatic address or data capture.

ACT_CAP_ST_DAQ_DATA

4

Transmit a DAQ message with the data value of the last retired data access and its context (data type and size), plus DirectData[23:0].

ACT_CAP_ST_DAQ_DADDR

5

Transmit a DAQ message with the data address of the last retired data access and its context, plus DirectData[23:0]. Traces which memory location was touched without exporting the value.

ACT_CAP_ST_DAQ_DATA_DADDR

6

Both of the above — value and address of the last retired data access, with context, plus DirectData[23:0]. The most information-rich DAQ command and correspondingly the most expensive in bandwidth.

(reserved)

7

Reserved. The RDL source carries a commented-out ACT_CAP_ST_DAQ_STALL_COUNTER at this value; it is not implemented and the value must not be used.

ACT_CAP_ST_DAQ_IFETCH_TH

8

Transmit a DAQ message with the count of instruction fetches that exceeded the cycle threshold in region DirectData[7:0], plus DirectData[23:8], and clear that counter.

ACT_CAP_ST_DAQ_DATA_RD_TH

9

As above for read accesses that exceeded the cycle threshold in region DirectData[7:0]; clears the counter.

ACT_CAP_ST_DAQ_DATA_WR

10

Transmit a DAQ message with the number of write accesses counted for region DirectData[7:0], plus DirectData[23:8], and clear that counter.

ACT_CAP_ST_DAQ_DATA_RD

11

Transmit a DAQ message with the number of read accesses counted for region DirectData[7:0], plus DirectData[23:8], and clear that counter.

ACT_CAP_ST_CF_SYNC

12

Request an instruction synchronization message. Produces a Nexus synchronization message with the vendor reason code 14 and no DAQ message.

ACT_CAP_ST_TE

13

Nominally "set a TE control field". See the note below: the effect is selected by Sink, not by this value.

ACT_CAP_ST_WATCHPOINT

14

Transmit a Watchpoint message (Nexus TCODE 15) reporting which watchpoint fired: WPHIT = DirectData[15:0] AND trWpMask.WEM. A command whose masked result is 0 emits nothing. Requires the CT_EN_WATCHPOINT_MSG build switch (which itself requires CT_EN_ACT). Unlike the DAQ commands this one produces no Data Acquisition message.

+
+

Any Cmd value not listed above is discarded by the instrumentation processor and produces no message.

+
+
+

20.2.1. Two behaviours that differ from the obvious reading

+
+

The data-context commands report the LAST retired data access, not the next one. Commands 4, 5 and 6 are served from the registers PrevData, PrevDAddr and PrevDtypeDsize, which the composers latch on every tip.dretire beat (ct_L23_preproc_composer_etip.sv:1385-1389, ct_L23_preproc_composer_axis.sv:103-107). The command therefore reports the access that has already been observed when the command retires — the usual software pattern is load or store, then command, not the reverse. There is no pending-request state and no arming step.

+
+
+

ACT_CAP_ST_TE is not what selects a TE write. The instrumentation processor branches on Sink first; for Sink = ACT_CAP_ST_SINK_TE it applies the TE control request and never looks at Cmd, and for the message sinks the value 13 matches none of the admitted commands and is discarded (ct_L23_preproc_act_proc.sv:99-155). A TE control request is therefore a command with Sink = 3; the Cmd value is free. Setting Cmd = 13 with a message sink does nothing.

+
+
+
+
+

20.3. Sink field: trActCapStSink_e

+ +++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
EnumeratorValueMeaning

ACT_CAP_ST_SINK_NEXUS

0

Emit the result as a Nexus message on the encoder’s trace output only. The classic trace-only path.

ACT_CAP_ST_SINK_AXIS

1

Emit the result as an AXI-Stream beat to an on-chip consumer only. No Nexus message is generated.

ACT_CAP_ST_SINK_AXIS_NEXUS

2

Emit both: local processing and off-chip trace visibility.

ACT_CAP_ST_SINK_TE

3

Emit nothing. DirectData is applied as a TE control request instead (instruction tracing on/off, data tracing on/off).

+
+

The two composers gate independently on the sink value: the eTIP composer accepts NEXUS and AXIS_NEXUS, the AXIS composer accepts AXIS and AXIS_NEXUS. CF_SYNC and WATCHPOINT are Nexus-side commands — the AXIS composer has no arm for them and its default branch drops the beat.

+
+
+
+

20.4. DirectData field

+
+

DirectData is a 24-bit payload with three roles, selected by the command:

+
+
+
    +
  • +

    User tag. For the PC-based and data-based DAQ commands the value is carried into the DAQ payload as an application-defined identifier, so tools can correlate a trace packet with a logical event.

    +
    • +
  • +

    Region selector. For the four counter commands (8, 9, 10, 11) DirectData[7:0] selects the region; DirectData[23:8] remains available as a tag.

    +
    • +
  • +

    Watchpoint bitmap. For ACT_CAP_ST_WATCHPOINT, DirectData[15:0] is the WPHIT bitmap before masking.

    +
    • +
  • +

    TE control request. With Sink = ACT_CAP_ST_SINK_TE, DirectData[23:16] selects the control target and DirectData[15:0] carries the new state.

    +
    • +
+
+
+ + + + + +
+
Note
+		 +There is no "non-negative" guard on DirectData and no sentinel that suppresses it. DirectData is always part of the DAQ payload; a value of 0 is free, because the Nexus MDO/MSEO variable-length field encoding strips leading zeros and an all-zero field occupies no additional MDO cycles. Callers that need no auxiliary data simply leave DirectData = 0 (rdl/ct_cs_cpuif.rdl:50-55). +
+
+
+
+

20.5. Software use via ACT-CAP

+
+

20.5.1. C helper types

+
+

The command word has no generated C header: trActCapStCmd is hidden from every PeakRDL exporter by ispresent = false, so the C-header exporter does not see it either. The definitions below are the recommended software-side declarations; they mirror rdl/ct_cs_cpuif.rdl field for field, and that file remains the normative source.

+
+
+
+
 1
+ 2
+ 3
+ 4
+ 5
+ 6
+ 7
+ 8
+ 9
+10
+11
+12
+13
+14
+15
+16
+17
+18
+19
+20
+21
+22
+23
+24
+25
+26
+27
+28
+29
+30
+31
+32
+33
+
typedef union {
+  struct {
+    uint32_t Cmd        : 6;  /* [5:0]  instrumentation command */
+    uint32_t Sink       : 2;  /* [7:6]  sink selection          */
+    uint32_t DirectData :24;  /* [31:8] command-specific payload */
+  } b;
+  uint32_t w;
+} CT_CSR_trActCapStCmd_Type;
+
+typedef enum {
+  CT_CSR_TRACTCAPSTCMD_CMD_ACT_CAP_ST_NONE             =  0,
+  CT_CSR_TRACTCAPSTCMD_CMD_ACT_CAP_ST_DAQ_PC_CURR      =  1,
+  CT_CSR_TRACTCAPSTCMD_CMD_ACT_CAP_ST_DAQ_PC_CURR_LAST =  2,
+  CT_CSR_TRACTCAPSTCMD_CMD_ACT_CAP_ST_DAQ_DIRECT_DATA  =  3,
+  CT_CSR_TRACTCAPSTCMD_CMD_ACT_CAP_ST_DAQ_DATA         =  4,
+  CT_CSR_TRACTCAPSTCMD_CMD_ACT_CAP_ST_DAQ_DADDR        =  5,
+  CT_CSR_TRACTCAPSTCMD_CMD_ACT_CAP_ST_DAQ_DATA_DADDR   =  6,
+  /* 7 reserved -- do not use */
+  CT_CSR_TRACTCAPSTCMD_CMD_ACT_CAP_ST_DAQ_IFETCH_TH    =  8,
+  CT_CSR_TRACTCAPSTCMD_CMD_ACT_CAP_ST_DAQ_DATA_RD_TH   =  9,
+  CT_CSR_TRACTCAPSTCMD_CMD_ACT_CAP_ST_DAQ_DATA_WR      = 10,
+  CT_CSR_TRACTCAPSTCMD_CMD_ACT_CAP_ST_DAQ_DATA_RD      = 11,
+  CT_CSR_TRACTCAPSTCMD_CMD_ACT_CAP_ST_CF_SYNC          = 12,
+  CT_CSR_TRACTCAPSTCMD_CMD_ACT_CAP_ST_TE               = 13,
+  CT_CSR_TRACTCAPSTCMD_CMD_ACT_CAP_ST_WATCHPOINT       = 14
+} ct_csr_trActCapStCmd_Cmd_e;
+
+typedef enum {
+  CT_CSR_TRACTCAPSTCMD_SINK_ACT_CAP_ST_SINK_NEXUS      = 0,
+  CT_CSR_TRACTCAPSTCMD_SINK_ACT_CAP_ST_SINK_AXIS       = 1,
+  CT_CSR_TRACTCAPSTCMD_SINK_ACT_CAP_ST_SINK_AXIS_NEXUS = 2,
+  CT_CSR_TRACTCAPSTCMD_SINK_ACT_CAP_ST_SINK_TE         = 3
+} ct_csr_trActCapStCmd_Sink_e;
+
+
+
+
+

A bitfield union is convenient but not portable across compilers with different bitfield packing rules. Where portability matters, build the word with shifts:

+
+
+
+
1
+2
+3
+4
+
#define CT_ACT_CMD(cmd, sink, direct) \
+    ( ((uint32_t)(cmd)    & 0x3Fu)        \
+    | (((uint32_t)(sink)  & 0x03u) << 6)  \
+    | (((uint32_t)(direct)& 0xFFFFFFu) << 8) )
+
+
+
+
+
+

20.5.2. Constructing and issuing a command

+
+
+
 1
+ 2
+ 3
+ 4
+ 5
+ 6
+ 7
+ 8
+ 9
+10
+11
+12
+13
+14
+15
+16
+17
+18
+19
+20
+21
+22
+23
+24
+25
+26
+27
+28
+29
+30
+31
+32
+33
+34
+35
+36
+
/* ACT-CAP command CSR of the traced hart. */
+static inline void ct_act_cap_write(uint32_t value)
+{
+    __asm__ volatile ("csrw 0xB10, %0" :: "r"(value));
+}
+
+/* Emit a DAQ marker carrying the current PC and an 8-bit user tag,
+   visible in the off-chip trace stream only. */
+void ct_mark_pc(uint8_t tag)
+{
+    ct_act_cap_write(CT_ACT_CMD(
+        CT_CSR_TRACTCAPSTCMD_CMD_ACT_CAP_ST_DAQ_PC_CURR,
+        CT_CSR_TRACTCAPSTCMD_SINK_ACT_CAP_ST_SINK_NEXUS,
+        tag));
+}
+
+/* Sample the value of the load or store immediately preceding this call,
+   to both sinks. */
+void ct_sample_last_access(uint32_t *p, uint8_t tag)
+{
+    volatile uint32_t v = *p;            /* the access that will be reported */
+    (void)v;
+    ct_act_cap_write(CT_ACT_CMD(
+        CT_CSR_TRACTCAPSTCMD_CMD_ACT_CAP_ST_DAQ_DATA,
+        CT_CSR_TRACTCAPSTCMD_SINK_ACT_CAP_ST_SINK_AXIS_NEXUS,
+        tag));
+}
+
+/* Turn instruction tracing off from the traced hart itself:
+   Sink = TE, ctrl = 0 (InstTracing) in DirectData[23:16], state in bit 0. */
+void ct_inst_tracing(int on)
+{
+    ct_act_cap_write(CT_ACT_CMD(
+        0, CT_CSR_TRACTCAPSTCMD_SINK_ACT_CAP_ST_SINK_TE,
+        (0u << 16) | (on ? 1u : 0u)));
+}
+
+
+
+
+ + + + + +
+
Caution
+		 +The CSR number is architecturally a core-specific CSR. Whether a given hart implements it, and at which privilege level a write is permitted, is an integration property. On a core that does not implement it, csrw 0xB10 raises an illegal-instruction exception — which is exactly how the MicroBlaze™ V demonstrator uses it as a deliberate trap stimulus (examples/kv260/mbv/sw/rob_stress.S:35-38,125). Confirm with the SoC documentation before instrumenting production code. +
+
+
+ + + + + +
+
Caution
+		 +ACT-CAP works only on cores that report CSR write accesses on the TIP as dretire with dtype = CSR_READ_WRITE. A core that retires the write without reporting it produces no command, silently. This is the first thing to check when instrumentation appears to do nothing — and on the four cores this manual documents, it is not a caveat but the present state: none of them reports CSR writes, for two different reasons (Section 6.1.3). The MINRES TGC5B decodes the vendor CSR window and raises no exception for it, but its H2E port derives dtype from the data bus alone, so the write never reaches the trace port; CVA6, Rocket and MicroBlaze™ V tie dretire to 0 and produce no data beat at all. +
+
+
+

An integration can close this locally on a core whose adapter does see stores: a store to a chosen doorbell address is converted into the CSR beat the encoder expects. That is an adapter-level change and needs no core change. The runtime-verification testbed builds exactly this pair — examples/kv260/tgc5b2_rvcfi/rtl/ct_tip_adapter_actcap.sv with the doorbell in examples/kv260/tgc5b2_rvcfi/rtl/ct_soc_doorbell.sv. On CVA6, Rocket and MicroBlaze™ V no such local fix exists, because there is no store beat to convert; for CVA6 in particular, RVFI is not an escape route, since the wrapper ties its RVFI outputs off and the CVA6 RVFI CSR structure is a fixed list of named architectural CSRs with no field for an arbitrary address/value pair.

+
+
+ + + + + +
+
Important
+		 +On the four documented cores' native ingress, ACT-CAP therefore still has no silicon history; there its coverage comes from tests/lib/cpu_model.sv, which synthesizes the beat directly (scenario sim-hsi-csr-cap). The doorbell pair above is the first silicon exercise of the mechanism: on 2026-08-26 the runtime-verification testbed drove doorbell-converted ACT-CAP commands on the KV260 with board verdicts over both of its record transports (twin table BOARD_VERDICTS_OK, ring drops 0/0 — the closing status chapter of examples/kv260/tgc5b2_rvcfi/TUTORIAL_runtime_verification.md carries the tables). Those records leave through the AXI-Stream record path; a Data Acquisition message emitted from silicon over the ATB trace port is still outstanding. +
+
+
+
+
+

20.6. Use via the Smart Trigger (ACT-ST)

+
+

With ACT-ST the hart writes nothing. The command word is stored in the watchpoint table and the encoder issues it when a retired PC matches the entry’s Addr:

+
+
+
    +
  1. +

    Decide which Cmd / Sink / DirectData combination expresses the intended action — for example "on function entry, emit DAQ_PC_CURR with tag 42".

    +
    2. +
  2. +

    Build the 32-bit word with the same helper used for ACT-CAP.

    +
    3. +
  3. +

    Write the arming PC to trWpDataLow (0x4010), then the command word to trWpDataHigh (0x4014). The High write commits the pair to slot trWpIndex.Idx and advances the index.

    +
    4. +
  4. +

    Observe the four programming rules of the table (fill all slots, strictly ascending unique keys, pair-wise writes, load only while trTeControl.Enable = 0) — see the instrumentation chapter.

    +
    5. +
+
+
+

When the entry fires, the encoder emits exactly what a csrw 0xB10, value with the same word would have produced.

+
+
+
+

20.7. How a command reaches the wire

+
+

For a message sink the instrumentation processor forwards the command to the composers, and the eTIP composer decides the message class:

+
+ ++++ + + + + + + + + + + + + + + + + + + + + +
Command classMessage

the ten DAQ_* commands

Data Acquisition, TCODE 7. The IDTAG field carries the command value itself (ct_L23_preproc_composer_etip.sv:1062), so a decoder can tell from the tag how to read the payload; the payload rides in DQDATA as up to three elements (MAX_DAQ_DATA_ELEMENTS = 3).

ACT_CAP_ST_CF_SYNC

An instruction synchronization message, on-wire reason 14. No DAQ message.

ACT_CAP_ST_WATCHPOINT

Watchpoint, TCODE 15, WPHIT = DirectData[15:0] AND trWpMask.WEM. No DAQ message; an assertion in the composer checks that a watchpoint and a DAQ message never share a beat.

+
+

The element-by-element payload layout of the DAQ message is in the Data Acquisition payload chapter; the AXIS beat layout is in the raw event path chapter.

+
+
+
+

20.8. DAQ bandwidth and backpressure

+
+

An instrumentation stream is trace bandwidth like any other. Too many DAQ messages saturate the trace interface, cause backpressure on the encoder and can lead to loss of trace elements — which the encoder reports rather than hides:

+
+
+
    +
  • +

    On sustained backpressure the composer raises a queue-overrun condition and the encoder emits an Error message (TCODE 8, ETYPE = QUEUE_OVERRUN) whose ECODE bitfield records which message classes were lost. The DAQ bit is set only in builds that can produce a DAQ message at all — (CT_EN_DAQ || CT_EN_ACT) in ct_L23_preproc_composer_etip.sv:1502 — so a profile without instrumentation never advertises a DAQ loss that could not have happened.

    +
    • +
  • +

    After the overrun the encoder re-anchors with a FIFO_OVERRUN synchronization, so a decoder regains position.

    +
    • +
+
+
+

Mitigations, in the order of effect:

+
+
+
    +
  1. +

    Reduce the number of arming points. A static analysis of the program before the run identifies the hot spots; fewer watchpoints in a hot loop is the cheapest fix by a wide margin.

    +
    2. +
  2. +

    Reduce the payload. DAQ_DIRECT_DATA (one element) costs a fraction of DAQ_DATA_DADDR (three elements plus context). A DirectData of 0 costs nothing on the wire.

    +
    3. +
  3. +

    Use the address/range and privilege filtering of the trace configuration so that the regular data trace does not compete with the instrumentation for the same interface.

    +
    4. +
  4. +

    Route very high-rate instrumentation to the AXIS sink instead of the Nexus stream (Sink = ACT_CAP_ST_SINK_AXIS). The on-chip path does not consume trace-port bandwidth at all. Note its own loss behaviour, described in the raw event path chapter.

    +
    5. +
  5. +

    Watch the FIFO fill-level histogram (trTeTipFifoHistCtrl / trTeTipFifoHistData, CT_EN_FIFO_HIST) during a pilot run rather than guessing: it reports the distribution of the internal fill level, not just the peak watermark.

    +
    6. +
+
+
+
+

20.9. Summary

+
+
    +
  • +

    trActCapStCmd is the single command word for both ACT-CAP and ACT-ST.

    +
    • +
  • +

    Cmd selects what is emitted — PC, data context, counter value, an extra synchronization, or a watchpoint report.

    +
    • +
  • +

    Sink selects where the effect goes: trace stream, on-chip AXI-Stream, both, or the TE control registers.

    +
    • +
  • +

    DirectData carries 24 bits of tag, region index, watchpoint bitmap or control value, and costs nothing on the wire when it is 0.

    +
    • +
  • +

    ACT-CAP issues the word with a CSR write; ACT-ST issues an identical word from the watchpoint table. Downstream they are the same event.

    +
    • +
+
+
+
+
+
+

21. HSI Transfer

+
+
+

"HSI transfer" is the path an instrumentation command takes from the moment it becomes visible to the encoder until the resulting message leaves the encoder. The command word itself is described in the command CSR chapter; this chapter describes the transfer — the control structure, the data sources a command can reach, the control-register access it can perform, how the resulting Nexus message is composed, and what the implementation does and does not guarantee about the ordering of a command relative to the data it reports.

+
+
+

21.1. Control structure

+
+

The control structure is the 32-bit command word {Cmd, Sink, DirectData}, delivered either by a single CSR write to 0x0B10 (ACT-CAP) or from a watchpoint table entry (ACT-ST).

+
+
+

That it is a single 32-bit write is a property worth stating explicitly, because it removes an entire class of failure. A protocol that first writes a data register and then a command register has an interruptible window between the two: an interrupt whose handler also uses those registers corrupts the transfer. CTTE has no such window for the command itself — there is one write, it is atomic by construction, and it is therefore safe to issue from any context, including an interrupt handler, without a critical section.

+
+
+

The window that does remain is a semantic one and concerns only the three data-context commands; it is described in Section 21.8.

+
+
+ + + + + +
+
Note
+		 +A command’s route into the encoder and its payload have different prerequisites, and both depend on the core. The CSR route (ACT-CAP) needs the core to report a CSR write on the ingress port, which no shipped core does as delivered; the watchpoint route (ACT-ST) needs only a retired instruction address and works on all four. Independently of the route, the three data-context commands need a data beat, which only the MINRES TGC5B supplies. The per-core table is Section 6.1.3. +
+
+
+
+

21.2. Data sources a command can reach

+
+

The Cmd field selects which of the encoder’s observation points feeds the message. All of them are values the encoder already holds from the Trace Ingress Port; no additional bus access takes place.

+
+ +++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
SourceContentReached by

Current program counter

tip.iaddr of the beat carrying the command

DAQ_PC_CURR, DAQ_PC_CURR_LAST

Program counter before the last trap

LastIAddrBeforeException, updated on an EXCEPTION_TRAP or INTERRUPT itype

DAQ_PC_CURR_LAST

Value of the last retired data access

PrevData, latched on every tip.dretire

DAQ_DATA, DAQ_DATA_DADDR

Address of the last retired data access

PrevDAddr, latched on every tip.dretire

DAQ_DADDR, DAQ_DATA_DADDR

Context of the last retired data access

PrevDtypeDsize = {tip.dtype, tip.dsize} — access type (load, store, CSR, atomic) and size

DAQ_DATA, DAQ_DADDR, DAQ_DATA_DADDR

Direct data

the 24-bit DirectData field of the command word itself

every DAQ command

Per-region access and threshold counters

the four counter banks of the performance-counter block, indexed by DirectData[7:0]

DAQ_DATA_RD, DAQ_DATA_WR, DAQ_IFETCH_TH, DAQ_DATA_RD_TH

Timestamp

the value selected by the timestamp unit (trTsControl.Type, Active, Count, Prescale)

the TSTAMP field of the message, and — with CT_EN_AXIS_TS — element 2 of a DAQ_PC_CURR AXIS beat

+
+

The four counter commands clear the counter they report. On the Nexus path the clear pulse comes from the eTIP composer (ct_L23_preproc_composer_etip.sv:1413-1433), on the AXIS path from the AXIS composer; each drives its own clear input of the counter, so the two sinks cannot clear each other’s reading.

+
+
+
+

21.3. Accessing TE control registers through HSI

+
+

A command with Sink = ACT_CAP_ST_SINK_TE performs no transfer to a sink at all; instead its DirectData field is applied to the encoder’s control registers. This is the mechanism by which a traced hart reconfigures the trace subsystem without any access to the control bus.

+
+
+

Two control targets are implemented
+(ct_pkg.sv:971-979, ct_L23_preproc_act_proc.sv:138-150):

+
+ +++++ + + + + + + + + + + + + + + + + + + + +
DirectData[23:16]TargetState taken from

0

trTeControl.InstTracing — instruction tracing on/off

DirectData[0]

1

trTeDataControl.DataTracing — data tracing on/off

DirectData[1]

+
+

The block asserts a single-cycle …​TracingSet or …​TracingClr strobe into the CSR shim, which is the same hardware path the external control bus uses. Any other value in DirectData[23:16] is ignored.

+
+
+

The same registers remain reachable over the control bus. The format of the control structure is identical either way, which is the point: a debugger and a traced hart can drive the same field, and the encoder cannot tell them apart.

+
+
+
+

21.4. Nexus message composition

+
+

21.4.1. Event triggers

+
+

Exactly two events start an HSI transfer:

+
+
+
    +
  • +

    a CSR write to 0x0B10 observed as dretire with dtype = CSR_READ_WRITE (ACT-CAP), or

    +
    • +
  • +

    a retired instruction address matching a watchpoint table entry (ACT-ST).

    +
    • +
+
+
+

Both produce the same command word, and the instrumentation processor gives the ACT-ST command priority when both occur on the same instruction.

+
+
+
+

21.4.2. Data Acquisition message (TCODE 7)

+
+

The ten DAQ_* commands produce one Data Acquisition message. Its field order and types come from the message-format table in rtl/pkg/nexus_vendor_riscv_pkg.sv:672-681:

+
+ +++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
FieldType / widthContent

TCODE

fixed, 6 bit

7

SRC

fixed, NEXUS_MSG_SOURCE_WIDTH

source identifier of the encoder instance; present only when the source field is configured

IDTAG

vendor fixed, 12 bit

the command value itself (ct_L23_preproc_composer_etip.sv:1062). A decoder reads IDTAG to know how to interpret the payload.

DQDATA

vendor variable, up to NEXUS_DQDATA_WIDTH = NEXUS_MSG_DATA_WIDTH = 192 bit in a build with DAQ messages (rtl/pkg/nexus_vendor_riscv_pkg.sv:46,106)

the payload elements, up to MAX_DAQ_DATA_ELEMENTS = 3 per message (rtl/pkg/ct_pkg.sv:906); encoded with leading zeros stripped, so unused elements and zero values cost nothing on the wire

TSTAMP

vendor variable, up to NEXUS_MSG_TSTAMP_WIDTH

present when the timestamp unit is enabled for wire fields (trTsControl.Enable)

+
+

Two consequences follow from IDTAG carrying the command:

+
+
+
    +
  • +

    One DAQ message carries one command’s complete payload. There is no grouping of several messages into a logical unit and no sequence bit that would tie them together — the three elements of, say, DAQ_DATA_DADDR ride in one DQDATA field of one message.

    +
    • +
  • +

    A decoder needs no side channel to parse DQDATA; the element layout is a function of IDTAG. That layout is tabulated in the Data Acquisition payload chapter.

    +
    • +
+
+
+

The DQDATA width is the reason DAQ is used at all for this purpose: a standard data-trace message carries fewer bits than three address-or-data elements plus context require.

+
+
+
+

21.4.3. Watchpoint message (TCODE 15)

+
+

ACT_CAP_ST_WATCHPOINT produces a Watchpoint message instead of a DAQ message: TCODE, SRC, WPHIT, TSTAMP, with WPHIT = DirectData[15:0] AND trWpMask.WEM. The internal payload is 16 bit wide; on the wire WPHIT is a variable-length field. See the instrumentation chapter for the slot-to-bit convention and the message catalog for the field table.

+
+
+
+

21.4.4. Synchronization message

+
+

ACT_CAP_ST_CF_SYNC produces an instruction synchronization message with the vendor reason code 14, and no DAQ message. The requesting actor is recorded in trTeSyncStatus.SyncReqSource for diagnosis only.

+
+
+
+
+

21.5. Region control

+
+

The "regions" the counter commands index are the address ranges of the performance-counter block at 0x3000, not a dedicated register pair. Four independent range banks exist — data read, data write, instruction fetch above threshold, data read above threshold — each with its own set of Low/High register pairs and an extra counter for accesses that fall outside every configured range. The range registers are write-locked while trTeControl.Enable = 1, deliberately: a range is two registers, and a mid-trace update would be visible for one bus cycle as a nonsense interval built from the new Low and the old High.

+
+
+

The bank sizes are elaboration parameters and are readable at runtime in trTeConstants (0x3008). The performance chapter carries the full description.

+
+
+
+

21.6. TracePoint programming

+
+

What earlier design notes called the "TracePoint register" is implemented as the ACT-ST watchpoint table: each slot is an {Addr, Cmd} pair, where Addr is the arming instruction address and Cmd the command word dispatched on a match. The table is loaded through the indirect register path (trWpIndex, trWpDataLow, trWpDataHigh) and read back through trWpReadLow/trWpReadHigh; the programming rules are in the instrumentation chapter.

+
+
+

The matching is performed by ct_L23_preproc_act_st.sv against tip.iaddr. Separate control words for an interrupt entry, an interrupt return or an interrupt-enable change — which the original concept sketch foresaw — are not implemented; see Section 21.9.

+
+
+
+

21.7. Trace destination

+
+

The destination of a transfer is the Sink field of the command word: ACT_CAP_ST_SINK_NEXUS for the external trace port, ACT_CAP_ST_SINK_AXIS for the on-chip AXI-Stream consumer, ACT_CAP_ST_SINK_AXIS_NEXUS for both, ACT_CAP_ST_SINK_TE for a control-register write with no message at all.

+
+
+

The encoder instantiates one AXI-Stream master (axis_if.master on ct_encoder), so the choice is between the two ports, not among several numbered stream destinations. The tid field of the beat carries the command value; tdest is not driven by the encoder. Fan-out to several on-chip consumers is an integration task — the shared TGC5B base (examples/kv260/common/tgc5b/) and the tgc5b2_axis_wp example show one way of doing it.

+
+
+
+

21.8. HSI sequence correctness

+
+

Three commands depend on a data access that happened before them: DAQ_DATA, DAQ_DADDR and DAQ_DATA_DADDR. They report the most recent retired data access the composer has latched. The intended pattern is therefore:

+
+
+
+
    load or store              <- the access to be reported
+    csrw 0x0B10, <command>     <- the command that reports it
+
+
+
+

Two properties follow, and both matter for a correctness argument:

+
+
+

What the implementation guarantees. The latch is updated on every tip.dretire, in the same clock domain and in the same beat order the TIP delivers. The value reported is therefore always a real, retired access of the traced hart — never a partially updated or speculative one. Ordering between the instrumentation branch and the control-flow branch is preserved by the alignment pipelines.

+
+
+

What it does not guarantee. Nothing marks the pairing. If an interrupt is taken between the access and the command, and the handler performs a data access of its own before returning, the command reports the handler’s access, because that is the most recent one. The encoder cannot detect this: there is no pending-request state, no tag linking a command to a particular access, and no sequence check.

+
+
+

Mitigations available today, in order of cost:

+
+
+
    +
  1. +

    Place the pair where it cannot be split. Inside a critical section, or in code that is not interruptible in the first place.

    +
    2. +
  2. +

    Mask interrupts around the pair if the measurement must be exact. On RISC-V this is the usual save/clear/restore of mstatus.MIE:

    +
    +
    +
    1
+2
+3
+4
+5
+6
+7
+8
+
        csrr   t0, mstatus            /* 1) save                              */
+    li     t1, 1 << 3             /* MIE                                  */
+    csrrc  x0, mstatus, t1        /* 2) disable machine interrupts        */
+
+    lw     t2, 0(a0)              /* 3a) the access to be reported        */
+    csrw   0xB10, t3              /* 3b) the reporting command            */
+
+    csrw   mstatus, t0            /* 4) restore                           */
+
    +
    +
    +
    +

    Note that this protects the pairing, not the command: the command write itself needs no protection.

    +
    +
    3. +
  3. +

    Use DAQ_DIRECT_DATA instead where the value is known to the program anyway. A tag needs no pairing at all and is the cheapest message in the set.

    +
    4. +
  4. +

    Use ACT-ST rather than ACT-CAP where the arming point is a program address. The command is then issued by the encoder on the matching instruction, so no software sequence exists that could be interrupted.

    +
    5. +
+
+
+
+

21.9. Concept elements not implemented

+
+

The HSI concept as originally sketched is wider than what is built. The following elements appear in earlier design notes and in the predecessor reference manual; none of them is present in the current RTL or register map. They are listed so that a reader of the older documents can tell concept from implementation, and so that a decoder author does not look for fields that never appear.

+
+ ++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Concept elementStatus

Two-register control structure (CSR_DATA_ADDR + CSR_CTRL_ADDR) and the "not interrupt safe" transfers built on it (CSR_WRITE1/2/4, LAST_WRITTEN_DATA, LAST_WRITTEN_ADDR, LAST_READ_ADDR)

Not implemented. One CSR address is decoded, 0x0B10, and it carries the complete command in one 32-bit write.

Special counters: wall-clock, stall, instruction-cache miss, data-cache miss, and the per-region write/read counters as a clearable special counter set with an SCNT difference-to-previous-reading field

Not implemented as special counters. A wall-clock reference exists as the timestamp unit’s source; per-region read/write and threshold counters exist in the performance-counter block and are read (and cleared) with the four counter commands. There are no stall or cache-miss counters — the TIP does not carry those events.

Counter Emit Control register (CCE, WCE, SCE, ICMCE, DCMCE, WR0CE, …​) selecting which counters ride along with every DAQ message

Not implemented. Each counter command reports exactly one counter, chosen by Cmd and DirectData[7:0].

A DAQ message group with a one-bit sequence identifier tying several messages together

Not implemented. One command produces one message; IDTAG identifies it.

Dedicated Region Control register with two fixed regions (R0L/R0H/R1L/R1H)

Superseded. The performance-counter block carries four independent range banks with several ranges each plus an outside-of-all-ranges counter.

TracePoint control words for interrupt entry (WPIC), interrupt return (WPIRC) and interrupt enable/disable

Not implemented. A watchpoint slot carries one command, dispatched on an instruction-address match.

Numbered internal AXI-Stream destinations [0..n]

Not implemented. One AXI-Stream master exists; tdest is not driven.

Encoder-side stack that assigns a pending data access to a later command by interrupt level and ownership ID

Not implemented. See Section 21.8.

Power-consumption information in the trace

Not implemented; listed in the original notes as a possible improvement.

+
+
+
+
+

22. Raw Event Path via AXI-Stream

+
+
+

Besides the encoded trace stream that leaves the encoder through the ATB port, CTTE offers a second, independent export path: an AXI4-Stream master that carries instrumentation events uncompressed to a consumer inside the same chip. It exists so that an on-chip agent can act on program events at low latency without owning a Nexus decoder and without competing for the external trace port.

+
+
+

Typical consumers:

+
+
+
    +
  • +

    a local CPU acting as a complex watchdog — for example a control-flow integrity checker,

    +
    • +
  • +

    a runtime-verification monitor evaluating properties over program events,

    +
    • +
  • +

    a just-in-time compiler that uses observed execution as optimisation input.

    +
    • +
+
+
+

The path is fed exclusively by the ACT-CAP/ACT-ST command path. Whether an event goes to this port, to the ATB port or to both is decided per command by the Sink field of the command word; the two paths are otherwise independent and can be used simultaneously.

+
+
+

22.1. Where the port sits

+
+

The AXI-Stream master is a top-level port of ct_encoder (axis_if.master axis), driven by ct_L23_preproc_composer_axis inside the preprocessor. The composer reads the same command interface as the eTIP composer and the same TIP observation registers, so an event that goes to both sinks reports the same values on both.

+
+
+

Two elaboration guards restrict the configuration
+(ct_L23_preproc_composer_axis.sv:51-63):

+
+
+
    +
  • +

    CT_EN_AXIS_TS requires CT_EN_TIMESTAMP — without the timestamp unit the timestamp element would be a constant zero marked valid.

    +
    • +
  • +

    CT_EN_AXIS_TS requires CT_EN_ACT — the sink is fed by the ACT-CAP command path and has no other producer.

    +
    • +
+
+
+

Both are structural: a violating configuration fails elaboration on every back end rather than producing a quietly wrong netlist.

+
+
+
+

22.2. Signal contract

+
+

The port is an ordinary AXI4-Stream interface (rtl/external/amba/axis_if.sv) in the preprocessor clock domain. The widths every reference design uses:

+
+ +++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
SignalWidthDriven by the encoder

tvalid

1

Yes — one cycle per emitted event.

tdata

96 bit (ACT_CAP_AXIS_TDATA_WIDTH = 3 × 32)

Yes — three 32-bit elements, element 0 in bits [31:0], packed LSB-first.

tstrb

12 bit (tdata width / 8)

Yes — four strobe bits per 32-bit element, so 0xF / 0xFF / 0xFFF mark one, two or three valid elements.

tid

8 bit (ACT_CAP_AXIS_TID_WIDTH)

Yes — the Cmd value of the command that produced the beat.

tready

1

Not sampled. See Section 22.4.

tkeep, tlast, tdest, tuser

 — 

Not driven. The beat is single-cycle, so there is no packet boundary to mark, and there is one destination.

+
+

The composer derives its element count from the interface (NUM_ELEMENTS = TDATA_WIDTH / ACT_CAP_DATA_WIDTH), so the width is nominally an integration choice; the payload layout below assumes the 96-bit configuration that every reference design, the verification environment and the dump/decode helpers use. Two of those helpers hard-code it (tests/lib/ct_axis_dump.sv writes a fixed 25-byte record and states the assumption in its header), so a different width needs them adjusted.

+
+
+
+

22.3. Packetisation and payload

+
+

One beat per command. There are no multi-beat packets and no framing. Each beat is self-describing: tid says which command produced it and therefore how to read the payload; tstrb says how many elements carry data.

+
+ ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Command (tid)Element 0Element 1Element 2

DAQ_PC_CURR

current PC

direct-data tag

timestamp[31:0] (only with CT_EN_AXIS_TS)

DAQ_PC_CURR_LAST

current PC

last PC before exception or interrupt

direct-data tag

DAQ_DIRECT_DATA

direct-data tag

 — 

 — 

DAQ_DATA

value of the last retired data access

{dtype, dsize} of that access

 — 

DAQ_DADDR

address of the last retired data access

{dtype, dsize} of that access

 — 

DAQ_DATA_DADDR

value of the last retired data access

address of that access

{dtype, dsize} of that access

DAQ_DATA_RD, DAQ_DATA_WR, DAQ_IFETCH_TH, DAQ_DATA_RD_TH

counter value of the region selected by DirectData[7:0]

 — 

 — 

+
+

Source: rtl/preproc/ct_L23_preproc_composer_axis.sv:109-202.

+
+
+

Three commands have no AXIS beat: ACT_CAP_ST_CF_SYNC and ACT_CAP_ST_WATCHPOINT are Nexus-side commands and fall into the composer’s default arm, which clears tvalid; a command with Sink = ACT_CAP_ST_SINK_TE produces no message on either sink. A counter command whose region index exceeds the bank size likewise emits nothing.

+
+
+

22.3.1. The timestamp element

+
+

With CT_EN_AXIS_TS — the full-profile default — a DAQ_PC_CURR beat carries the value the timestamp unit produces (per trTsControl.Type, Active, Count and Prescale) as element 2, and the strobe is 0xFFF instead of the historical 0xFF. This lets an in-fabric consumer order and correlate PC samples without any Nexus decoding.

+
+
+

Note the deliberate split: trTsControl.Enable gates only the TSTAMP fields of the Nexus and E-Trace messages, not this element. The AXIS sink is not a Nexus wire format, so its shape is a build-time property and the ATB byte stream is identical either way. A build without CT_EN_AXIS_TS keeps the two-element shape.

+
+
+

The verification environment checks both directions: with the switch on, element 2 must be valid and strictly monotonic across at least two beats; compiled out, it must be invalid and the strobe must be 0xFF (tests/hsi/01_csr_cap/csr_cap_tb.sv).

+
+
+
+
+

22.4. Flow control and loss behaviour

+
+

This is the property an integrator must design around, and it differs from what a plain reading of "AXI4-Stream" would suggest:

+
+
+ + + + + +
+
Important
+		 +The encoder’s AXIS master never samples tready. tvalid is driven directly from the composer’s registered valid flag (ct_L23_preproc_composer_axis.sv:207), with no dependence on the sink’s handshake. Every beat must therefore be consumed in the cycle it is presented, or it is lost — silently, as far as the encoder is concerned. +
+
+
+

The design reason is the same one that makes the whole instrumentation path deterministic: backpressure from an on-chip consumer must not be able to stall the trace pipeline, and a consumer that is too slow is a property of the consumer, not an encoder fault. The consequence is that the shim in front of the consumer owns the loss accounting.

+
+
+

22.4.1. The reference shim

+
+

examples/kv260/common/ct_axis_wp_shim.sv is the pattern to copy. It accepts every encoder beat unconditionally and converts the 96-bit single-beat stream into a fully handshaken 32-bit stream:

+
+
+
    +
  • +

    Admission. Each incoming beat is written into an internal FIFO of FIFO_DEPTH records of 116 bit (tdata + tstrb + tid). If the FIFO is full the beat is dropped.

    +
    • +
  • +

    Accounting. drop_count increments on every dropped beat and saturates at 32’hFFFF_FFFF; overflow_sticky latches and is cleared only by reset; fill_level reports the records currently held. The top level maps all three into a control window, so a host can tell a complete capture from a lossy one instead of guessing.

    +
    • +
  • +

    Serialisation. Each record leaves as four 32-bit words on a stall-safe master with a full handshake — no loss after admission, back-to-back capable:

    + ++++ + + + + + + + + + + + + + + + + + + + + + + + + +
    WordContent

    0

    tdata[31:0] — element 0

    1

    tdata[63:32] — element 1

    2

    tdata[95:64] — element 2

    3

    {8’h00, CORE_ID[3:0], tstrb[11:0], tid[7:0]}; tlast is asserted on this word, tkeep is constant 4’hF

    +
    • +
  • +

    Clocking. Single clock domain, synchronous active-high reset, no CDC — any clock crossing belongs to the downstream FIFO IP, not to the shim.

    +
    • +
+
+
+

The tgc5b2_axis_wp example on the KV260 uses one shim per core and drains the result over an axi_fifo_mm_s that a Linux host reads through /dev/mem, in parallel with an ordinary Nexus capture of the same run — which is what makes the two views cross-checkable.

+
+
+
+

22.4.2. Alternative: a passive capture buffer

+
+

Where the events only need to be inspected after the fact, examples/kv260/common/tgc5b/rtl/ct_soc_axis_buf.sv shows the simpler pattern: a passive observer that stores one 128-bit record per accepted beat into a block RAM readable from Linux with devmem. Its header states the same two cautions that apply to any consumer: decode a beat from its command in tid, not from tkeep, and treat a full buffer as evidence that beats were dropped.

+
+
+
+
+

22.5. Relationship to the ATB trace path

+ +++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
PropertyAXI-Stream pathATB (Nexus) path

Content

Instrumentation events only

Program trace, data trace, instrumentation and status messages

Encoding

Uncompressed 32-bit elements

Nexus MSEO/MDO messages, variable-length fields, leading zeros stripped

Consumer

On-chip logic or a local CPU; no decoder needed

Trace probe or on-chip sink plus a Nexus decoder

Selection

Sink = AXIS or AXIS_NEXUS

Sink = NEXUS or AXIS_NEXUS

Flow control

None towards the encoder (Section 22.4)

Backpressure-aware; overrun produces an Error message and a re-anchoring synchronization

Loss visibility

In the consumer’s own accounting (shim drop_count / overflow_sticky)

In the stream itself: TCODE 8 with the lost message classes in ECODE

Timestamp

Element 2 of a DAQ_PC_CURR beat, gated by CT_EN_AXIS_TS

TSTAMP field, gated by trTsControl.Enable

Ordering against program flow

By the order of the beats only

By message position in the stream

+
+

With Sink = ACT_CAP_ST_SINK_AXIS_NEXUS both paths carry the same event. This is the configuration to use when an on-chip monitor must react quickly and the event must remain in the off-chip record for later analysis. The two composers sample the same source registers in the same beat, and the timestamp element of the AXIS beat is taken from the same selected value the eTIP composer puts into TSTAMP, so the two views agree.

+
+
+

The counter-clearing commands are the one place where the two sinks touch shared state, and they are separated on purpose: each composer drives its own clear input of the performance counters, so a read on one sink does not consume the other sink’s measurement.

+
+
+
+

22.6. Verification support

+ ++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
HelperPurpose

tests/lib/ct_axis_decoder.sv

Simulation sink that converts one beat into a structured record — command from tid, three elements from tdata, per-element validity from tstrb — so a testbench asserts on fields instead of slicing vectors. It also flags partial element strobes as an error. Drives tready constantly high.

tests/lib/ct_axis_dump.sv

Simulation-only dump of every accepted beat to a text and a raw file. The raw record is 25 bytes: tid, tdata[95:0] as 12 little-endian bytes, and the 12 strobe bits expanded to one byte each. Instantiating the module is the gate — there is no run-time switch.

rtl/external/amba/test/axis_dump.sv

The generic AXI-Stream dump used at block level.

rtl/preproc/test/ct_L23_preproc_axis_tb.sv

Block-level testbench for the AXIS composer, driving ACT-CAP commands through the TIP.

tests/hsi/01_csr_cap/csr_cap_tb.sv

System-level check: fires every command that produces output to ACT_CAP_ST_SINK_AXIS_NEXUS, counts the beats, matches the DAQ_DIRECT_DATA beat against its expected command and payload, and checks the timestamp element in both CT_EN_AXIS_TS configurations. The beat is identical whether the sink is AXIS or AXIS_NEXUS.

tests/instruction/31_status_msgs/status_msgs_tb.sv, scenario wpaxis

Confirms that a watchpoint command issued on the AXIS sink produces the identical Nexus watchpoint message — the AXIS routing does not change what the trace stream sees.

+
+
+

22.7. Integration checklist

+
+
    +
  1. +

    Decide the consumer’s admission policy first. The encoder will not wait. Either guarantee single-cycle consumption, or put a shim with a FIFO and drop accounting in front (ct_axis_wp_shim is the reference).

    +
    2. +
  2. +

    Expose the drop accounting. A capture without a drop counter cannot be used as evidence, because a missing event and an event that never happened look the same.

    +
    3. +
  3. +

    Decode from tid, never from tkeep or tlast. Those lines are not driven by the encoder and read back as zero through most integration wrappers.

    +
    4. +
  4. +

    Match the widths. 96-bit tdata, 12-bit tstrb, 8-bit tid. The dump and shim helpers check this at elaboration and stop the build on a mismatch.

    +
    5. +
  5. +

    Check the profile. The port exists only with CT_EN_ACT; the timestamp element only with CT_EN_AXIS_TS, which additionally requires CT_EN_TIMESTAMP. In a profile without ACT the port is present but permanently idle.

    +
    6. +
  6. +

    Budget the rate. One beat per command means the beat rate equals the command rate. The AXIS path costs no trace-port bandwidth, which makes it the right sink for high-rate instrumentation — but the consumer then carries the rate instead.

    +
    7. +
+
+
+
+
+
+

23. Performance Analysis and Counters

+
+
+

Performance analysis needs detailed information about what a core actually does — which regions it fetches from, which regions it reads and writes, and how long individual accesses take. The Trace Ingress Port already carries that information, so CTTE can aggregate it in hardware without any change to the core and without an additional bus master.

+
+
+

The aggregation happens in one preprocessor block, rtl/preproc/ct_L23_preproc_perfcnt.sv, and is read out through the instrumentation commands described in the command CSR chapter. The counters are part of the ACT group and exist only in builds with CT_EN_ACT.

+
+
+

23.1. The performance-counter component

+
+

The component occupies 0x3000--0x3FFF of the control-register map and reports the vendor component type 0x3 in trPcImpl. Its registers:

+
+ +++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
RegisterOffsetFunction

trPcControl.Active

0x3000

Required component stub. Read-only constant 1 — there is no clock gate or power-down control behind it.

trPcImpl

0x3004

Component version and type; CompType = 0x3, the vendor-assigned type of the performance-counter component.

trTeConstants

0x3008

Read-only implementation parameters, so software can discover the sizes instead of assuming them: num_trace_filter, num_trace_comparators, num_perfcnt_ifetch_th_ranges, num_perfcnt_data_rd_th_ranges, num_perfcnt_data_rd_ranges, num_perfcnt_data_wr_ranges.

trPerfCntControl

0x3010

The two cycle thresholds. IFetchThreshold[7:0], reset 4, and DataWrThreshold[15:8], reset 4.

trTePerfCntIFetchRange[]

0x3100 + 8 × i

Instruction-address ranges for the fetch-threshold counters. Each entry is an inclusive Low/High pair.

trTePerfCntDataRdThRange[]

0x3200 + 8 × i

Data-address ranges for the read-threshold counters.

trTePerfCntDataRdRange[]

0x3300 + 8 × i

Data-address ranges for the plain read counters.

trTePerfCntDataWrRange[]

0x3400 + 8 × i

Data-address ranges for the plain write counters.

+
+

The committed configuration provides three instruction-fetch threshold ranges, three data-read threshold ranges, seven data-read ranges and seven data-write ranges (rtl/pkg/ct_cs_cpuif_pkg.sv:17-20). These are elaboration parameters of the register map; read trTeConstants rather than hard-coding them.

+
+
+

There is no enable bit for the counters and no register that reads a counter value. The counters run whenever the block is instantiated, and the only way to obtain a value is an instrumentation command — which is also what clears it. That is a deliberate design point: a counter read is an event in the trace stream, ordered against the control flow around it, rather than an asynchronous bus read whose position in the program is unknown.

+
+
+

23.1.1. Enable-locking, and why it is asymmetric

+
+

The range registers are write-locked while trTeControl.Enable = 1. The two thresholds in trPerfCntControl are not.

+
+
+

The asymmetry is deliberate and is argued in the register source (rdl/ct_cs_cpuif.rdl:1846-1858): a range is two registers, Low and High, so a mid-trace update is visible for one bus cycle as a nonsense interval built from the new Low and the old High. A single-field scalar cannot be torn that way. The thresholds are compared combinationally against a counter that restarts at every retire, so a new value simply applies from the next measurement window on — no cross-window state can go stale, and the counters they feed leave the encoder as instrumentation values, never as instruction-trace grammar.

+
+
+
+
+

23.2. Counter banks

+
+

Four independent banks exist, one per access class:

+
+ +++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BankCounted eventQualifier in the RTL

Data read

a retired load whose address falls in one of the configured ranges

tip.dretire && (tip.dtype == LOAD)

Data write

a retired store whose address falls in one of the configured ranges

tip.dretire && (tip.dtype == STORE)

Instruction fetch above threshold

a retiring instruction whose elapsed-cycle count has reached the instruction threshold, with the fetch address in one of the ranges

tip.iretire && (IThCnt == trPerfCntControl.IFetchThreshold)

Data read above threshold

a retired load whose elapsed-cycle count has reached the data threshold, with the address in one of the ranges

tip.dretire && (tip.dtype == LOAD) && (DThCnt == trPerfCntControl.DataWrThreshold)

+
+

Each bank holds N + 1 counters for N configured ranges: one per range, plus one that counts every qualifying access that falls outside all configured ranges. The extra counter is what makes a measurement interpretable — without it, a low count in a range cannot be told apart from a low total.

+
+
+

Counter properties:

+
+
+
    +
  • +

    Width 32 bit (PERFCNT_WIDTH, rtl/pkg/ct_pkg.sv:894).

    +
    • +
  • +

    Saturating. The counters are instantiated with MODE_SATURATION and hold at all-ones instead of wrapping, so a stale reading is visibly saturated rather than silently small.

    +
    • +
  • +

    Increment only. There is no down-count mode and no decrement path.

    +
    • +
  • +

    Two independent clear inputs, one per sink (…​_clr_etip and …​_clr_axis). The eTIP composer and the AXIS composer each drive their own, so a read on one sink does not disturb a measurement being taken on the other.

    +
    • +
+
+
+

23.2.1. Range matching

+
+

Each bank instantiates one perfcnt_range_unit, a thin wrapper around vector_range_checker. It compares the address against all Low/High pairs of the bank and returns a hit flag, a no-hit flag and the index of the matching range, in one cycle plus an optional configurable extra delay. The same unit is used for all four banks, so the classification behaviour and latency are identical across them.

+
+
+

Ranges are inclusive at both ends. Overlapping ranges are not rejected by hardware, but the unit returns exactly one index, so an address in two ranges is attributed to one of them; configure disjoint ranges if the attribution must be unambiguous.

+
+
+
+
+

23.3. Threshold measurement

+
+

The two threshold banks do not count accesses — they count accesses that were slow. The measurement is a small state machine (ct_L23_preproc_perfcnt.sv:70-128) that maintains two 8-bit cycle counters, IThCnt and DThCnt, and exists to make sure one event window produces at most one counter update:

+
+ ++++ + + + + + + + + + + + + + + + + + + + + +
StateBehaviour

TH_IDLE

On a retiring instruction both counters restart. On a retiring data access both restart and the machine moves to TH_CNT_IRETIRE. On a cycle with neither, both counters increment; when IThCnt reaches all-ones the machine moves to TH_ITH_OVERFLOW.

TH_CNT_IRETIRE

Counts the cycles between the data access and the next instruction retire. Returns to TH_IDLE on that retire, or moves to TH_ITH_OVERFLOW if the counter saturates first.

TH_ITH_OVERFLOW

Waits for the next data retire and returns to TH_IDLE. The window is discarded.

+
+

The qualifier that admits a counter update is an equality comparison against the threshold, evaluated on the retire beat — IThCnt == trPerfCntControl.IFetchThreshold for the fetch bank, DThCnt == trPerfCntControl.DataWrThreshold for the read bank. The counters are therefore a measure of how often an event took exactly the configured number of idle cycles, which for a threshold at the low end of the distribution is in practice "took at least that long, and was the first beat to reach it".

+
+
+
+

23.4. Reading the counters

+
+

A counter is read with one of four instrumentation commands. All four take the region index in DirectData[7:0], may carry a tag in DirectData[23:8], and clear the counter they report:

+
+ +++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
CommandValueReads

ACT_CAP_ST_DAQ_IFETCH_TH

8

the instruction-fetch threshold counter of the selected range

ACT_CAP_ST_DAQ_DATA_RD_TH

9

the data-read threshold counter of the selected range

ACT_CAP_ST_DAQ_DATA_WR

10

the data-write counter of the selected range

ACT_CAP_ST_DAQ_DATA_RD

11

the data-read counter of the selected range

+
+

Each produces a Data Acquisition message (TCODE 7) whose IDTAG is the command value and whose DQDATA carries the counter value; on the AXIS sink the same value appears as element 0 of a single beat with tid = command.

+
+
+

The index is range-checked before the read. On the AXIS path an index above the bank size takes the else branch and no beat is emitted; on the Nexus path the arm is likewise guarded. Both out-of-range branches are exercised by the feature-matrix test rather than left to inspection (tests/instruction/19_feature_matrix/feature_matrix_tb.sv, phases Ph.10 and Ph.10b, which drive an in-range command, an out-of-range command and an unknown command through both the ACT-ST table and the direct ACT-CAP CSR path).

+
+
+

Because the read clears, a series of reads yields deltas: the count since the previous read of the same counter. A measurement over a whole run is therefore the sum of the reported values, and a lost message — which the encoder reports as an Error message with the DAQ bit set — loses one interval rather than corrupting the total silently.

+
+
+
+

23.5. Determinism and latency

+
+

The counter block reports a fixed internal latency of one cycle (internal_delay = 1) for alignment with the adjacent preprocessing stages. Updates are qualified strictly by retire signals, and each bank’s clear handling is explicit and independent, so software can snapshot and reset one class without cross-coupling into the read, write and fetch domains of the others. The latency does not depend on the values counted or on the number of configured ranges.

+
+
+
+

23.6. Using the counters

+
+

A workable measurement procedure, given that the counters have no enable bit and no bus read path:

+
+
+
    +
  1. +

    Configure the ranges while tracing is disabled (trTeControl.Enable = 0). Set the thresholds too; they may also be changed later.

    +
    2. +
  2. +

    Decide how the read happens. Either instrument the program with ACT-CAP commands at the points where a reading is wanted, or arm ACT-ST watchpoints on those addresses and leave the program untouched. The second is preferable for production binaries and for tight loops.

    +
    3. +
  3. +

    Choose a sink. ACT_CAP_ST_SINK_NEXUS puts the readings into the trace stream, ordered against the control flow — which is what makes a reading attributable to a program phase. ACT_CAP_ST_SINK_AXIS keeps them on-chip and costs no trace-port bandwidth.

    +
    4. +
  4. +

    Read the first sample early to clear the counters, so that the first interval starts at a known point rather than at reset.

    +
    5. +
  5. +

    Watch the interval length. A counter read per iteration of a hot loop is a message per iteration; the bandwidth guidance in the command CSR chapter applies unchanged.

    +
    6. +
+
+
+
+

23.7. Related measurements documented elsewhere

+
+
    +
  • +

    Timestamps. The timestamp unit (trTsControl, 0x040, with the 64-bit counter at 0x048/0x04C) is described with the trace format; its value rides as the TSTAMP field of synchronization, data and DAQ messages, and — with CT_EN_AXIS_TS — as element 2 of a DAQ_PC_CURR AXIS beat.

    +
    • +
  • +

    Internal FIFO fill level. The fill-level histogram (trTeTipFifoHistCtrl 0xE10 / trTeTipFifoHistData 0xE14, CT_EN_FIFO_HIST) and the peak watermark (trTeTipFifoStatus.trTeTipFifoMaxFill 0xE04) measure the encoder, not the core. They are the right instrument for sizing a trace configuration; see the development-support appendix. The histogram registers carry a read contract: valid only while the trace is quiescent.

    +
    • +
  • +

    Trace-stream reduction by the compression suite. Reduction figures for the individual compression features belong with the compression chapter, together with the workload they were measured on.

    +
    • +
+
+
+
+
+
+

24. Footprint Profiles and Resource/Timing Matrix

+
+
+

CTTE is not one netlist. Which logic is built is decided at elaboration by the CT_EN_* and structural switches in rtl/pkg/ct_pkg.sv, and a profile is one named combination of them. This chapter defines the profiles the project measures, states the measured resource and timing figures for each, and names the tool version, commit and report file behind every number.

+
+
+

24.1. What a profile is, and where it is defined

+
+

A profile is a set of assignments to the switches in ct_pkg.sv. Every measurement flow applies them from one definition, scripts/ct_profiles.sh, rather than hand-editing the package — so the resource matrix below and the per-switch cost figures in the integration guide describe the same builds.

+
+
+

ct_profile_names currently yields five names: voll_gold, featparity_gold, slimfull_gold, nonly, eonly. They are built from two bases plus a fixed set of nine feature switches:

+
+ ++++ + + + + + + + + + + + + + + + + + + + + +
DefinitionContent

ct_profile_voll_base_in

The maximum configuration: data trace, DAQ/ACT, filters and the complete compression suite on; multi-clock; 64-bit timestamp; two slicer steps; Nexus formatter egress; eTIP serialization on.

ct_profile_featparity_base_in

The compact control-flow-only configuration: data trace, DAQ/ACT, filters and the compression suite compiled out; single clock; 32-bit timestamp; one slicer step; compact-packer egress; serialization off. CT_EN_WATCHPOINT_MSG and CT_EN_AXIS_TS follow CT_EN_ACT, and CT_EN_DF_DROP / CT_EN_DF_ADDR_COMPRESS follow CT_EN_DATA_TRACE — those are elaboration dependencies, not preferences (scripts/check_profile_deps.py).

CT_GOLD_FEATS (the _gold suffix)

Nine switches turned on over the base: CT_EN_DEBUG_EVENTS, CT_EN_POWER_EVENTS, CT_EN_EVTI, CT_EN_TRIG_SYNC, CT_EN_SEQ_SYNC, CT_EN_OWNERSHIP, CT_EN_CONFIG_MSG, CT_EN_IBHS, CT_EN_REPEAT_INSTR.

+ ++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
ProfileDefinition

voll_gold

voll_base + the nine gold switches, N-Trace back end. This is the committed full profile.

featparity_gold

featparity_base + the nine gold switches, N-Trace back end.

slimfull_gold

featparity_gold plus CT_ETIP_CDC_SLIM = 1, CT_EN_ETIP_WATERMARK = 0, CT_EN_TIMESTAMP = 0 (and therefore CT_EN_AXIS_TS = 0). The smallest profile the project measures.

nonly

voll_gold with the back-end selector explicitly set to N-Trace. The two definitions produce a byte-identical ct_pkg.sv, so this is the same build as voll_gold and its run serves as a control.

eonly

voll_gold with the E-Trace back end selected instead.

+
+

The _gold profiles deliberately leave CT_EN_BTM, CT_EN_SYNC_STATUS, CT_EN_FIFO_HIST, CT_EN_QUOTA_SYNC, CT_EN_DEVICE_ID, CT_EN_TRIG_REGS and CT_EN_INST_SYNC_REQ at their committed full-profile value of 1. A build that wants a smaller footprint than slimfull_gold has to switch those off as well; that build is not measured here.

+
+
+
+

24.2. Resource and timing matrix

+ + ++++++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 7. Out-of-context synthesis of ct_encoder, Vivado™ 2022.1.2, commit 7a0b7b2, device xck26-sfvc784-2LV-c, 2026-08-06 — reports under verification/evidence/P10/<profile>/
ProfileCLB LUTsRegister as FFBlock RAM tilesDSP48E2WNS @ 13.333 ns (75 MHz)WNS @ 5.0 ns (200 MHz)Derived Fmax

voll_gold — committed full profile, N-Trace back end

25 784

20 168

9.5

16

+4.175 ns

−4.158 ns

109.2 MHz

nonly — same build as voll_gold, run as a control

25 784

20 168

9.5

16

+4.175 ns

−4.158 ns

109.2 MHz

eonly — full profile, E-Trace back end

26 372

16 953

9.5

16

+1.753 ns

−6.580 ns

86.4 MHz

featparity_gold — control-flow only, compact packer, single clock

4 938

4 824

10

16

+8.672 ns

+0.339 ns

214.5 MHz

slimfull_gold — featparity_gold + slim eTIP CDC, no watermark, no timestamp unit

4 290

3 984

10

16

+8.695 ns

+0.362 ns

215.6 MHz

+
+

Provenance of every row in this table. Out-of-context synthesis of the top module ct_encoder on the device xck26-sfvc784-2LV-c, run on 2026-08-06 with Vivado™ 2022.1.2 (build 3605665, the version .abc.config pins) at commit 7a0b7b2. Reproduce with

+
+
+
+
bash scripts/p10_timing_matrix.sh
+
+
+
+

LUTs, flip-flops, block RAM and DSP are read from verification/evidence/P10/<profile>/timing_75mhz_util_flat.rpt; the two WNS columns from timing_75mhz_summary.rpt and timing_200mhz_summary.rpt in the same directory; the verdict from verification/evidence/P10/timing.log.

+
+
+

How Fmax is derived, since the derivation is otherwise invisible: critical path = budget − WNS, Fmax = 1000 / critical path in ns. For voll_gold: 13.333 − 4.175 = 9.158 ns → 109.2 MHz. The figure is a post-synthesis derivation, not a characterized maximum frequency.

+
+
+

24.2.1. How to read these numbers

+
+
    +
  • +

    At the 75 MHz board budget every profile meets timing. The smallest margin is eonly with +1.753 ns; Vivado’s own line in all five reports is "All user specified timing constraints are met", with zero failing endpoints.

    +
    • +
  • +

    At 200 MHz only the two slim profiles meet timing (+0.339 ns and +0.362 ns); the three full-profile builds miss it by 4.158 ns and 6.580 ns. 200 MHz is not a requirement of this project — the column is headroom information and is reported as measured.

    +
    • +
  • +

    This is post-synthesis, not placed-and-routed. Routing takes some of the margin back. The synthesis is out of context with one clock per clock port at the same budget and set_clock_groups -asynchronous between the five clock domains; the encoder’s CDC structures are exactly what a real SoC constraint file decouples the same way, so cross-domain paths are outside this analysis.

    +
    • +
  • +

    A budget without its slack figure says nothing, and neither does a slack figure without its budget. That is why two budgets are reported and why the constrained clock of the reference design is named.

    +
    • +
  • +

    Two controls came out of the runs themselves. nonly and voll_gold are the same netlist, and the two independent runs agree on every figure including total negative slack and failing-endpoint count. And the two budgets of each profile agree on the critical path to the picosecond, which is what makes the second run of a profile a control rather than a repetition.

    +
    • +
+
+
+
+

24.2.2. One placed-and-routed data point

+
+

The single place-and-route figure the project holds is the mbv_kv260 reference design of 2026-08-01: 23 428 LUTs / 19 065 FFs, WNS +2.679 ns at 75 MHz single-clock. It predates the P2 to P9 work and is therefore not comparable with the matrix above; it is quoted only as an order-of-magnitude check that an in-design build lands in the same region as the out-of-context one. (The value was corrected on 2026-08-14: the previously quoted +2.186 ns was Vivado’s router estimate, not the routed timing summary.)

+
+
+
+
+

24.3. The structural levers between the profiles

+
+

The distance between the full profile and the slim ones is not one switch. Four structural knobs carry most of it, and they are the ones to reach for first when a footprint target is missed.

+
+ ++++ + + + + + + + + + + + + + + + + + + + + + + + + +
KnobEffect

CT_COMPACT_PACKER

Replaces the formatter, slicer and MSEO stages of the egress path with a lean control-flow-only packer. Measured: the historical formatter path costs +1 018 LUTs / +623 FFs over the compact packer in the same profile (doc/integration.adoc, differential bases A = featparity with the packer on, 3 552 LUTs / 3 598 FFs / 6.5 BRAM, and B = featparity_noc with it off, 4 570 LUTs / 4 221 FFs / 6.5 BRAM; OOC, Vivado™ 2026.1, 5.0 ns target). The packer and the data-flow/DAQ message formats are mutually exclusive by construction — ct_L2_compact_packer stops elaboration with "`CT_COMPACT_PACKER` requires a CF-only profile".

CT_ETIP_SERIALIZE

Serializes the internal eTIP message path instead of carrying the parallel slots. Full-profile default since the E4 round; the resulting stream is byte-identical, proven on 15 of 15 reference streams. See the finding below on the cost figure.

CT_ETIP_CDC_SLIM and CT_EN_ETIP_WATERMARK

The two levers between featparity_gold and slimfull_gold, together with CT_EN_TIMESTAMP. Measured as the difference between those two rows of the matrix: −648 LUTs / −840 FFs. Of that, switching the timestamp unit off is worth about −300 LUTs / −490 FFs and the watermark about −24 LUTs / −32 FFs in the featparity context, so the slim eTIP CDC carries the remainder.

CT_SINGLE_CLOCK, CT_TS_WIDTH, CT_SLICER_STEPS, CT_MICRO_CSR, CT_ETIP_FIFO_STYLE, CT_FIFO_HIST_BINS

The remaining structural sizing knobs; each is documented at its definition in rtl/pkg/ct_pkg.sv. The base profiles set the first three; the others stay at their committed values in every measured profile.

+
+
+

24.4. What the instrumentation path costs

+
+

The material of Part D — the ACT blocks, the DAQ message path and the watchpoint message — is compiled out together in the slim profiles, so its cost does not appear as a separate row above. Two measurements bound it.

+
+
+

The group figure. CT_EN_DAQ + CT_EN_ACT + CT_EN_WATCHPOINT_MSG together measure +8 965 LUTs / +10 514 FFs / +12.5 BRAM against differential base B (OOC, Vivado™ 2026.1, 5.0 ns target; doc/integration.adoc, feature-flag table). The three switches are quoted as a group because they cannot be separated: CT_EN_DAQ alone is functionally dead — its only producer sits behind CT_EN_ACT — and CT_EN_WATCHPOINT_MSG fails elaboration without CT_EN_ACT. The group cannot be measured against base A at all, because the compact packer and the DAQ message format are mutually exclusive.

+
+
+

Five mechanisms are code-verified as the drivers, and they compound inside the same message queue: the DAQ payload (three 32-bit elements plus a 32-bit address = 128 bits) becomes the widest arm of the packed message union and is therefore paid by every queued message; the queue depth quadruples from 32 to 128; the parallel slot count grows from three to four; the watchpoint read-back shadow is an explicit block-RAM copy; and the ACT-ST engine is a pipelined binary search with 32-bit comparators per level. No bit-level accounting is claimed.

+
+
+

The watchpoint capacity step. The group figure above was measured at the historical table shape (M0_DIM = 4, a four-level tree with 15 slots). The current implementation has ten levels and 1023 slots, and the preprocessor alignment budget PREPROC_DELAY_MAX grew from 20 to 44 for CT_EN_ACT profiles with it. The 68-fold capacity step was measured as an OOC pair on the full profile (Vivado™ 2022.1.2, xck26-sfvc784-2LV-c; verdict verification/evidence/C0b/ooc_pair.log):

+
+ ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BuildCLB LUTsRegister as FFBlock RAM tiles

pre — commit 64ae043979, M0_DIM = 4 (verification/evidence/C0b/ooc_pre_util_flat.rpt)

26 307

20 743

9.5

post — commit b4cc804692, M0_DIM = 10 (verification/evidence/C0b/ooc_post_util_flat.rpt)

30 432

31 204

14.5

delta

+4 125

+10 461

+5

+
+

The flip-flop side is the alignment pipes — every EXTRA_DELAY_MAX-deep pipe in the preprocessor follows PREPROC_DELAY_MAX; the block-RAM side is the ten-level tree plus the 1024 × 64-bit read-back shadow.

+
+
+ + + + + +
+
Note
+		 +This pair is a different commit and a different build state from the matrix in the previous section. Its rows may be compared with each other — that is what a differential pair is for — but not with the matrix. +
+
+
+
+

24.5. Choosing a profile

+ ++++ + + + + + + + + + + + + + + + + + + + + + + + + +
If the requirement isStart from

Full instrumentation: DAQ, ACT-CAP/ACT-ST, watchpoint messages, data trace, filters and the complete compression suite

voll_gold. This is also the profile the register map is committed for — a slim build regenerates the map through scripts/gen_rdl_profile.py.

The E-Trace back end instead of N-Trace

eonly. The protocol is a synthesis parameter, one back end per encoder instance.

Smallest control-flow-only encoder with the gold feature set

slimfull_gold, then featparity_gold if the timestamp unit is needed.

Smaller than slimfull_gold

slimfull_gold with CT_EN_BTM, CT_EN_SYNC_STATUS, CT_EN_FIFO_HIST, CT_EN_QUOTA_SYNC, CT_EN_DEVICE_ID, CT_EN_TRIG_REGS and CT_EN_INST_SYNC_REQ switched off as well. That combination is not measured in this manual; measure it before quoting a figure for it.

+
+

Two rules apply to any profile change:

+
+
+
    +
  1. +

    Regenerate the register map. The committed ct_cs_cpuif.sv is the full profile. After editing the switches, run python3 scripts/gen_rdl_profile.py; it rewrites rdl/ct_profile.inc.rdl and the generated register block together, so a compiled-out feature’s CSR bits read as 0 instead of holding a value nothing consumes.

    +
    2. +
  2. +

    Let the dependency checks run. scripts/check_profile_deps.py and make check-flags verify that the switch combination is legal and that the feature-flag documentation still matches ct_pkg.sv, the SystemRDL source and the capability map. Several dependencies are enforced by elaboration guards rather than by convention, and an illegal combination fails the build rather than producing a quiet mis-configuration.

    +
    3. +
+
+
+
+
+
+

25. Integration Guide

+
+
+

This chapter is the contract an integrator drops ct_encoder against: clocks and resets, the instruction ingress, the control interface’s locking rules, trace egress and protocol selection, and the shutdown semantics. It condenses doc/integration.adoc (71 KB) to the decisions an integrator has to make and the guarantees they can rely on; the derivations, measured cost tables and every per-switch footnote stay in that public document, cited by section below. The pin-accurate signal-level contract (port lists, timing diagrams) is the interface contract chapter; the register-by-register reference is the register model chapter. Configuration recipes and the pitfalls found in practice are their own chapter, next.

+
+
+

25.1. Clocks and resets

+
+

ct_encoder spans five clock domains, each with its own synchronous reset. Every CDC crossing is internal (gray-pointer FIFOs plus 2-FF synchronizers) — the integrator only connects clocks (doc/integration.adoc, "Clocks and resets"):

+
+ +++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
ClockDrivesConstraint

tip_clk

Instruction ingress (tip_if), preprocessor front

Must be the core clock — the TRACE/TIP bus is synchronous to retirement.

proc_clk

Message generation, formatting

May equal tip_clk (the proven board profile, 1:1) or run faster for headroom.

atb_atclk

ATB egress, the trTeControl.Empty view

Sink-side clock; 1:1 with tip_clk is proven on hardware. A slower drain only raises the FIFO-overrun rate (announced loss, see below).

wb_clk

Wishbone CSR access

Any frequency.

wall_clk

Wall-clock timestamp source

Optional feature clock.

+
+

A fully single-clock integration (all five tied to one clock, as on the KV260 reference designs in the demonstrators chapter) is supported and is the configuration the hardware robustness campaign runs on.

+
+
+

Resetting one domain without the others is allowed, and it has a defined cost. An integrator may hold the core (and tip_rst) in reset while the CSR domain keeps running — that is what makes the encoder programmable across a core reset. Two consequences are contract, not accident:

+
+
+
    +
  • +

    An explicit sync request (trTeControl.InstSyncReq, and the ATB sync request the same way) survives a reset of the consumer’s domain: the request crosses as a four-phase LEVEL handshake (ct_sync_req_pacer) specifically so that a tip_rst clearing the generator’s pending state does not lose a request still standing on the launch side. The direction matters: a wb_rst resets the launch side, and there a pending-but-unserved request is simply gone (no message, no error, no status bit) — the correct behaviour, because a reset CSR domain has no pending software intent left to honour. Proven for one clock (formal/preproc_sync, task tereqrst) and measured across two unrelated clocks (scripts/cli_syncreqrst_test.sh).

    +
    • +
  • +

    It may cost one extra synchronization message if the reset lands between the generator serving a request and the launch side observing the acknowledgement — always safe to emit, and a reset re-anchors the decoder anyway.

    +
    • +
+
+
+

Every other domain resets in the ordinary way: state in the reset domain is gone, and the trace stream re-anchors on the first qualifying retirement afterward.

+
+
+
+

25.2. Instruction ingress (tip_if)

+
+

One beat per retirement opportunity, single-retirement by default (CT_EN_BLOCK_TIP = 0). The rules integrations get wrong most often (doc/integration.adoc, "Instruction ingress"):

+
+
+
    +
  • +

    iretire=1 marks a retired instruction; iaddr/ilastsize must be valid on that beat.

    +
    • +
  • +

    A synchronously faulting instruction (ecall/ebreak/illegal) does not retire (iretire=0, itype=EXCEPTION_TRAP) and its PC never appears in the decoded stream — the 1:1 retirement rule. Interrupts use itype=INTERRUPT with iretire=0; the pre-empted instruction is re-executed after mret and appears then.

    +
    • +
  • +

    itype must be valid whenever it is non-OTHER, even with iretire=0 (trap markers ride non-retiring beats).

    +
    • +
  • +

    Sideband levels (debug_mode, power_down) must rise after the last pre-window retire and fall before the first post-window retire.

    +
    • +
+
+
+

Block ingress (CT_EN_BLOCK_TIP = 1) is the escape hatch for a superscalar hart that cannot serialize its commit stream: iretire becomes the halfword count retired by the beat (width CT_IRETIRE_WIDTH, elaboration-checked to 2..8 — the lower bound because a 1-bit block bus cannot report even one 32-bit instruction, the upper because a beat that alone reaches the ICNT pre-drain threshold wedges the indirect-branch history hold), iaddr becomes the block’s first instruction, ilastsize the last instruction’s size, and itype how the block terminated. Only the last instruction of a block may be a control-flow event. A core whose block generator has no bound of its own (CVA6’s ITI accumulates until the next control-flow instruction) must have its adapter split longer linear runs into several itype=OTHER blocks — free on the wire, since an OTHER block raises no message and only accumulates the count. The switch adds no message type and no wire field (no CAPS bit): a block beat produces exactly the messages a serialised beat sequence would, measured byte-identical in the reset configuration (scripts/cli_blocktip_test.sh). Two consequences an integrator still has to reason about even though the stream stays well-formed either way: InstSyncMode = 6 counts retirement beats, not instructions, so periodic sync lands after a different amount of program at a block ingress; and an armed instruction filter sees block starts only, so per-instruction address filtering is not expressible on a block ingress — a property of the port, not a filter shortfall. Use the single-retirement ingress where per-instruction filtering matters.

+
+
+

tip_if is deliberately the only ingress contract: everything core-specific lives in an adapter outside the encoder. Three adapter families exist today (AMD MicroBlaze™ V TRACE bus, the CVA6 instruction-trace interface fed from RVFI probes, and the Rocket TraceCoreInterface) — their port mapping and itype semantics are the trace-sources-and-adapters chapter’s subject, not this one. Writing a fourth adapter means answering the same three questions for the new core — which beat is a retirement, how a trap is signalled, whether the address is the instruction’s or the next one’s — against a measured truth table before it reaches RTL.

+
+
+
+

25.3. Control interface and programming contract

+
+

CSR access is Wishbone (wb_if); an AXI-Lite bridge (ct_axil_to_wb) is available at integration level. Feature configuration is Enable-locked: trTeInstFeatures and the sync-mode fields are writable only while trTeControl.Enable=0 — writes issued after arming are silently void. The required order is Active → configuration → Enable + InstTracing. A short, deliberately non-locked exception list (session handles, status-clear bits, the message-class enables a decoder recognises by TCODE, the timestamp unit’s own run control, and the two ACT stall thresholds) stays writable while the trace runs; the authoritative list is the swwel block header in rdl/ct_cs_cpuif.rdl, machine-checked by make lint. The configuration chapter documents the one historical gap in this lock (closed 2026-08-16) and the concrete failure mode of getting the ordering wrong — read it before writing a board driver from scratch.

+
+
+

trTeControl.Active gates the encoder’s clock enables; keep it set for the whole session, including shutdown polling (see below). The decoder invoked against a capture must be told which features were programmed (e.g. -bp iff InstEnBranchPrediction was set) — or, since trTeControl.SendConfig, it can read that from the stream itself; see the decoding chapter.

+
+
+
+

25.4. Trace egress and protocol selection

+
+

Trace bytes leave on ATB (atb_if) in the framing of the back end the encoder was built with: Nexus MDO/MSEO chunks for N-Trace, reference-raw te_inst packets for E-Trace. Which protocol an encoder speaks is a synthesis-time decision, not a runtime one. ct_encoder takes two parameters, EN_NTRACE and EN_ETRACE (default from the build profile, CT_EN_NTRACE/CT_EN_ETRACE in rtl/pkg/ct_pkg.sv); exactly one must be set per instance, both-0 and both-1 abort elaboration. Only the selected back end is instantiated, so an unused protocol costs nothing, and a multi-encoder SoC can mix protocols across instances out of the same netlist sources — see the configuration chapter for the pitfall this creates (every instance needs an explicit parameter once more than one protocol is in the netlist). Software discovers the built-in protocol read-only: trTeProtocolSel.Protocol (0 = N-Trace, 1 = E-Trace) and trTeImpl.ProtocolMajor (1 = N-Trace 1.x, 2 = E-Trace 2.x); there is no write path — an earlier runtime-selectable dual build was removed in 2026-08 because it cost a full second back end in area and was never used in a product.

+
+
+

atb_te_raw (0 = Nexus, 1 = te_inst) advertises the framing to a downstream funnel or sink. The funnel shipped in this repository (ct_L1_funnel, see the funnel chapter) merges N-Trace channels only — it derives packet boundaries from the Nexus MSEO bits, which an E-Trace channel does not carry. Feeding an E-Trace instance into a mixed SoC therefore needs its own ATB sink until the raw-framing funnel extension lands.

+
+
+

Backpressure via atready is legal at any time; sustained backpressure raises FIFO-overrun episodes, which are announced loss — an ERROR message plus a recovery sync re-anchor the decoder, never a silent drop (verdict-tested across backpressure duty/random/burst profiles). A live consumer that wants a bounded re-anchor distance inside a ring-buffer window programs the trace-quota cadence; the recipe with measured board numbers is in the configuration chapter.

+
+
+
+

25.5. Pause, stop, flush — the shutdown contract and bring-up order

+
+

These semantics are contract-tested (gate 11_pause_edge, campaign verdicts V7/V8):

+
+
+
    +
  • +

    Pause (InstTracing 0→…​→1 with Enable held): the encoder closes the stream with a trace-off correlation (TCODE 33), suppresses everything positionless, and re-anchors with a TRACE_ENABLE sync. Pauses may be issued asynchronously at any time.

    +
    • +
  • +

    Flush (afvalid or the sink’s flush control) drains all queued trace. To reach Empty=1 afterward, close the stream while the core still retires: with InstTracing=1 and a stopped core, exactly one control-flow event is permanently in flight (its successor address can never be observed), and Empty=0 is the correct report in that state, not a bug.

    +
    • +
  • +

    trTeControl.Empty is a conservative, CDC-safe status: it rises only after the entire chain (accumulators, formatter, packer, CDC FIFOs, ATB queue) has been observably quiet, and falls immediately on any visible substance.

    +
    • +
+
+
+

The proven order, both for bring-up and for shutdown, is:

+
+
+
    +
  1. +

    Hold the domains in reset as needed; bring up clocks per the table above.

    +
    2. +
  2. +

    trTeControl.Active = 1, kept set for the whole session.

    +
    3. +
  3. +

    Program configuration (trTeInstFeatures, sync mode/max, SendConfig, filters, …) while Enable = 0 — see the programming contract above and the configuration chapter’s pitfalls before deviating from RDL reset values.

    +
    4. +
  4. +

    Enable = 1, then InstTracing = 1 (and DataTracing = 1 if used).

    +
    5. +
  5. +

    Run.

    +
    6. +
  6. +

    To shut down cleanly: flush → InstTracing = 0 while the core still retires → stop the core → poll trTeControl.Empty.

    +
    7. +
+
+
+
+

25.6. Build switches, runtime fields, and structural parameters

+
+

The full switch-by-switch reference — every CT_EN_* compile switch against its runtime CSR field, reset value, CAPS bit, per-profile default and measured LUT cost — is generated from rtl/pkg/ct_pkg.sv, rdl/ct_cs_cpuif.rdl and the CAPS map (consistency machine-checked by scripts/check_feature_flags.py, make check-flags) into the register model chapter; it is not reproduced here; the reset footprint/timing figures per profile live in the footprint-profiles chapter. Two structural parameters that are decisions an integrator makes once, at elaboration, and cannot change afterward:

+
+
+
    +
  • +

    CT_XLEN — the attached hart’s architectural address width, 32 (default) or 64. Not a runtime mode: it sizes the TIP address ports, the Nexus address fields, the address comparators, the jump-target-cache index fold and the eTIP payload in one place, and is advertised on the wire (CAPS bit 23, ADDR64) because a decoder cannot infer it from variable-length address fields with leading zeros stripped. Constraint: CT_EN_ETRACE with CT_XLEN = 64 is rejected at elaboration (the te_inst address fields are sized for 31 bits; 64-bit E-Trace is a separate step).

    +
    • +
  • +

    CT_CONTEXT_WIDTH — width of the TIP context bus (tip._context), 2 by default or as wide as the attached hart’s context identifier (16 for RISC-V satp.ASID under Sv39/Sv48, 9 under Sv32). Unlike CT_XLEN this is not advertised on the wire and needs no CAPS bit: the Ownership message carries it in a 44-bit variable-length field that is self-delimiting on the wire. Legal range 1..44, elaboration-checked — a wider bus would otherwise be truncated silently by the composer’s cast and the stream would name the wrong process.

    +
    • +
+
+
+
+

25.7. Versioning caveat for core-specific adapters

+
+

Adapters from non-standardized core trace buses (for example the AMD MicroBlaze™ V TRACE bus) are pinned to a specific core/tool version by construction — the bus itself is documented as not backward-compatible. Keep the adapter outside the encoder core and re-characterize it per core version; that characterization gate lives with the SoC integration project, not with the encoder (doc/integration.adoc, "Versioning caveat for core-specific adapters").

+
+
+
+
+
+

26. Configuration Recipes and Pitfalls

+
+
+

This chapter collects the configuration mistakes that are known to have actually happened, with the exact register values involved, and the recipes that turn a documented contract (see the integration guide and the register model chapters) into a working configuration. Every entry below is sourced to a commit, a test, or an RDL field — none is a hypothetical "integrators might get this wrong".

+
+
+

26.1. Baseline programming order

+
+

Feature configuration is Enable-locked: all trTeInstFeatures fields and the sync-mode fields are writable only while trTeControl.Enable=0 (the protocol back end is not among them — it is a synthesis parameter, not a runtime write, see the integration guide). Writes issued after arming are silently void. The required order is:

+
+
+
+
Active -> configuration -> Enable + InstTracing
+
+
+
+

Not everything is locked, and the exceptions are deliberate: the session handles (Active, Enable, InstTracing, DataTracing, InstSyncReq), the status-clear bits (including the RW1C overflow flags and the FIFO-histogram controls), the message-class enables a decoder recognises by TCODE (SendConfig, Context, InstSeqSyncEnable, InstTrigEnable), the timestamp unit’s own run control (trTsControl), and the two ACT stall thresholds trPerfCntControl.IFetchThreshold / DataWrThreshold stay writable while the trace runs. The authoritative list, with a reason per group, is the header of the swwel block in rdl/ct_cs_cpuif.rdl; make lint (check-swwel-census) fails if a field leaves that list without either a lock or an entry (doc/integration.adoc, "Control interface and programming contract").

+
+
+ + + + + +
+
Note
+		 +
+

This lock had a gap until 2026-08-16. An external register-access
+audit (finding U10 F-1) found that the eight
+trTeInstFeatures.InstEn* compression-suite bits were not on the
+swwel list, so they could be flipped mid-session even though the rest
+of the register already behaved as Enable-locked. They are locked now.
+Software written against an older build that relied on programming them
+after Enable was relying on a write that is documented-void today and
+must move those writes ahead of the arming step
+(doc/integration.adoc, same section).

+
+
+
+
+
+

26.2. Pitfalls

+
+

26.2.1. Vendor Config message silently suppressed by a stale control word

+
+

This is the pitfall to check first if a decoder hangs or loses sync partway through an otherwise-working capture.

+
+
+

trTeControl.SendConfig[8:7] controls whether the encoder emits the Vendor Config message (TCODE 58) that lets a decoder auto-configure from the stream (self-describing trace — see the decoding chapter and the self-identification chapter). The field resets to 1 (CFG_ONCE, rdl/ct_cs_cpuif.rdl:218) — but a hand-built control word that predates the field, or one copied from an older working example, can carry 0 (CFG_NONE) without anyone noticing, because the symptom is conditional on a second, unrelated setting.

+
+
+

Concretely (c-trace commit 7d91c2f8e0c8458d96af4d6d1d7a787164008374, examples/kv260/cva6_linux/board/cva6_linux_boot_trace.sh): a board driver used the constant trTeControl = 0x01060067, which has SendConfig[8:7] = 0. With InstSyncMax = 0 (a sync every 16 instructions) this went unnoticed for weeks — a sync that frequent never let the branch-history buffer overflow, so the decoder never needed the CAPS map the Config message would have carried. Once InstSyncMax moved to its RDL reset value 6 (period 1024, see the next pitfall), the first Repeated-History overflow message (RCODE = 2) reached a decoder that had never seen a Config message and therefore did not know the stream’s compression format — it walked the listing into _start_hang for 20 million PCs (observed on the KV260 reference board, 2026-08-17 23:38). The fix was trTeControl = 0x016600E7 (SendConfig = 1 / CFG_ONCE, InstSyncMax = 6, both at their RDL reset values).

+
+ +++++ + + + + + + + + + + + + + + + + + + + +
Control wordSendConfig[8:7]Symptom

0x01060067

0 (CFG_NONE)

Symptomless with a tight sync cadence; decoder hang (20 M PCs into _start_hang) once the branch-history buffer actually overflows between syncs.

0x016600E7

1 (CFG_ONCE, RDL reset)

Config message sent on every trace-on edge; decoder auto-configures correctly.

+
+

Recipe: never hand-assemble trTeControl from an old constant. Start from the RDL reset value and only clear the fields a specific test deliberately needs off (--sendconfig 0 in the driver above reproduces the old, broken behaviour on purpose, for regression testing only). If a capture must be decoded without a Config message (e.g. SendConfig = CFG_NONE for a stream that is meant to stay strict N-Trace 1.0, see the standards-baseline chapter), pass the equivalent flags to the decoder explicitly instead of relying on auto-configuration.

+
+
+
+

26.2.2. InstSyncMax reset changed from 0 to 6 (2026-08-12)

+
+

trTeControl.InstSyncMax[23:20] sets the periodic-sync period to 2(InstSyncMax+4) units (unit selected by InstSyncMode). The RDL reset value changed from 0 (period 16) to 6 (period 1024) on 2026-08-12. InstSyncMode itself still resets to 0 (no periodic cadence at all), so a build that never enables the cadence is bit-for-bit unaffected — what changed is the period a design gets the moment it does enable a cadence without also writing InstSyncMax.

+
+
+

Measured over 100 010 retires with only the period varied (doc/release-notes.adoc, "Changed reset value", gate tests/instruction/37_sync_cadence): the old reset (period 16) cost 97 844 trace bytes, the new reset (period 1024) costs 41 072, against 40 060 with the cadence effectively off — a factor 2.44 versus a 2.5 % overhead. Against a finite sink (40 MB/s, same workload) the old reset announced 790 overflows and lost 5 064 events; the new reset is byte-identical to the same run against an infinite sink.

+
+
+

Recipe: if a configuration relies on the periodic-sync period matching what the previous reset value gave (16 units), write InstSyncMax explicitly — do not rely on the reset. The minimum period remains available as an explicit stress configuration, it is simply no longer the default. Anyone who already programs InstSyncMax explicitly sees no change from this reset move at all.

+
+
+
+

26.2.3. Data-address compression mode invisible on a data-only stream

+
+

trTeDataControl.DataAddrCompress = 1 XOR-compresses data-trace addresses against the previous data-trace message’s address (see the trace-format chapter). A decoder learns which mode is active from the Vendor Config message — but the Config message rides on instruction tracing (SendConfig fires on the instruction trace-on edge). A stream with InstTracing = 0 (data trace only, no program trace) therefore carries no Config message at all, and a decoder attaching to such a stream mid-stream cannot auto-detect the compression mode from the stream itself (doc/trace-format.adoc, "Extensions beyond strict N-Trace 1.0", "Data-only caveat").

+
+
+

Recipe: for a data-only capture, either keep a synchronizing program-trace stream running alongside it so the Config message is still emitted, or provide the compression mode to the decoder out-of-band (a command-line flag, a sideband channel) instead of relying on auto-configuration.

+
+
+
+

26.2.4. Trace-quota window counter does not re-arm the way a naive model expects

+
+

With the trace-quota cadence (CT_EN_QUOTA_SYNC,
+trTeControl.InstSyncMode = 1 or 4), two behaviours are easy to get
+wrong when reasoning about worst-case re-anchor distance
+(doc/release-notes.adoc, "Known limitations",
+"Trace-quota window semantics"):

+
+
+
    +
  • +

    The quota counter rearms when the sync is emitted, not when it is requested — the sync message’s own bytes count into the new window, and no second request is raised while one is already pending (no sync avalanche at small quotas).

    +
    • +
  • +

    After a FIFO-overrun recovery the counter is not re-based: the first post-recovery quota sync can arrive earlier than one full quota (a harmless extra re-anchor), but never later than the programmed bound.

    +
    • +
+
+
+

With CT_EN_QUOTA_SYNC = 0 compiled out, modes 1 and 4 stay writable on InstSyncMode but are inert — no WARL clamp, exactly the pre-feature behaviour, so a build that compiles the switch out does not need its integration software to avoid programming the mode.

+
+
+
+

26.2.5. Setting both or neither protocol parameter aborts elaboration

+
+

ct_encoder takes two per-instance parameters, EN_NTRACE and EN_ETRACE, defaulting to the build profile (CT_EN_NTRACE / CT_EN_ETRACE in rtl/pkg/ct_pkg.sv). Exactly one must be set per instance — both-0 and both-1 abort elaboration with a $fatal (doc/integration.adoc, "Protocol choice — a synthesis parameter, per encoder instance"). This only becomes a live pitfall in a multi-encoder SoC that mixes protocols: because the choice is per instance, every instance needs an explicit EN_NTRACE/EN_ETRACE — relying on the package default is only safe when every instance in the netlist wants the same protocol. scripts/cli_etrace_test.sh mixed (tests/instruction/24_protocol_param) is the gate for exactly this case: two differently parameterised encoders in one netlist, each checked against its own atb_te_raw framing advertisement.

+
+
+
+

26.2.6. Waveform debug of encoder internals crashes Vivado™ XSIM

+
+

Not a register-configuration mistake, but a tooling trap worth listing next to the others because it costs the same kind of debugging session: Vivado XSIM 2026.x crashes with waveform instrumentation enabled on this code base; -debug off is required (doc/release-notes.adoc, "Known limitations"). Use Verilator (with coverage, for make coverage) or $display/counter instrumentation instead of a live waveform when debugging encoder internals in simulation.

+
+
+
+
+

26.3. Recipe: bounding the re-anchor distance for a live/ring consumer

+
+

A live consumer that cuts a window of W bytes out of a ring buffer needs at least one sync message inside that window to anchor the decode. With the trace-quota cadence (trTeControl.InstSyncMode = 4, counting raw ATB bytes — whole output beats including alignment padding and flush idle beats), the maximum sync-to-sync distance becomes a programmed number instead of a workload property (doc/integration.adoc, "Live / ring operation — bounded re-anchor distance"):

+
+
+
    +
  1. +

    Program InstSyncMode = 4.

    +
    2. +
  2. +

    Choose InstSyncMax so that 2^(InstSyncMax+4) ⇐ W / 2 — the factor 2 absorbs in-flight/CDC overshoot plus the sync message itself.

    +
    3. +
  3. +

    The RDL reset value 6 already gives an 8-KiB quota (a 16-KiB window), which is why only the mode has to be written for that window size; a 16-KiB dashboard window uses InstSyncMax = 9 (8-KiB quota) instead.

    +
    4. +
+
+
+

Measured (simulation, gate 29_sync_quota_bytes, 64-B quota InstSyncMax = 2, mixed compressible/incompressible workload): 12 syncs in 1100 raw ATB bytes, maximum re-anchor distance 96 B (the 64-B quota plus 32 B of in-flight/CDC overshoot); the analytic never-exceed ceiling for the overshoot is +324 B (scripts/check_sync_window.py).

+
+
+

Measured (board, KV260 ring-capture path, InstSyncMode = 4, InstSyncMax = 9 → 8192-B quota, 1-MiB URAM ring filled 3.08 times over, 16 631 920 PCs decoded from 131 071 messages): sync-to-sync distance was a constant 8192 B over 127 gaps — the programmed quota exactly. 40 randomly cut 16-KiB windows were 40 / 40 anchorable, with a maximum distance from the window start to its first sync of 8111 B — 81 B under the programmed quota and 405 B under the never-exceed bound. That headroom is not a proven reserve (the workload behind this capture is highly repetitive, which is why the gaps come out constant); the guarantee is the bound, not the observed constancy. The cadence cost 0.061 % of the stream (640 sync bytes in 1 048 571 raw bytes) on this capture. Discriminance check on the same capture path at InstSyncMode = 0: 0 / 40 windows anchorable (doc/integration.adoc, same section; raw data in the internal measurement archive, external to this delivery and not independently verifiable from it).

+
+
+

The message-count cadence (InstSyncMode = 1) works the same way with on-wire messages as the counted unit instead of bytes. While neither cadence mode is selected, the underlying counters hold at zero and add no trace bytes.

+
+
+
+
+
+

27. Decoding the Trace Stream

+
+
+

CTTE ships a second, independent implementation of the wire format it emits — a decoder — because a decode-and-compare loop is what turns a trace byte stream into evidence (see the verification-strategy chapter for the full argument). This chapter is the integrator-facing counterpart: the three places a trace stream gets decoded, what a decoder needs from the stream to configure itself, and the two export formats a decode produces.

+
+
+

27.1. Three decoding paths

+
+

27.1.1. HDL-level decoding (in simulation)

+
+

tests/lib/ct_nexus_decoder.sv (CEDARtools.TraceEncoder Nexus Decoder (ATB → nexus_message_t)) is an RTL-side Nexus message parser instantiated directly inside testbenches. It is not the primary verification oracle — that role belongs to the PC-stream and CTXP comparison against cpu_model described below and detailed in the verification-strategy chapter — but a second, cross-checking implementation at the RTL/testbench boundary: tests/lib/test/ct_nexus_decoder_tb.sv replays a captured ATB binary stream directly into ct_nexus_decoder and compares the decoded message sequence and key fields against a checked-in CTTD -dump text transcript of the same capture. Because it runs inside the simulator, this path catches message-framing defects without invoking an external binary.

+
+
+
+

27.1.2. Offline decoding — CTTD, the reference decoder

+
+

The reference decoder for every decode verdict in this repository and in its examples is CTTD (CEDARtools.TraceDecoder) — a second, independent implementation of the RISC-V N-Trace / Nexus wire format, not a CTTE component. It is derived from the RISC-V Nexus Trace TG reference decoder NexRv (ISC-licensed) and extended by Accemic with E-Trace decoding (-decoe), Data Acquisition decoding, multi-target decode (-target, for a funnelled multi-core stream) and CTXP export (doc/verification.adoc, "Components"; earlier informal names for this tool in source identifiers and older documentation include NexRv and NexRv for C-Trace — where those appear in scripts or environment variable names (NEXRV) they mean this same binary).

+
+
+

Since 2026-08-17 the decoder is no longer committed to this repository. It is fetched by version and platform:

+
+
+
+
1
+2
+
py scripts/fetch_cttd.py            # this host
+py scripts/fetch_cttd.py --all      # all three platforms (a board deploy needs linux-arm64)
+
+
+
+
+

The pin — version plus a sha256 per platform — lives in scripts/cttd.pin (at the time of writing: v2.3.0-cttd3); a checksum mismatch is a hard error, because every decode verdict in this repository is only worth what the decoder binary is (bin/README.md). The pin’s base_url names the CTTD GitHub release the assets are downloaded from. Bumping the pin is deliberate, in its own commit, with the behavioural reason recorded — never a side effect of an unrelated change.

+
+
+

CLI surface used by this repository’s own gates (CT_NEXRV_OPTS in scripts/ct_env.sh): -deco (decode a Nexus ATB capture), -decoe (decode an E-Trace te_inst capture), -dump (print one line per decoded message/packet, the format the HDL-level replay test above compares against), -enco (re-encode, used by cross-checking tools), -pcinfo <file> (program-structure input, see below), -pcout <file> (write the decoded PC stream), -full, -bp (branch prediction / jump-target-cache aware decode, needed iff those features are compiled in), -none, -csstrict (strict reading of the return-address mirror — the suite’s default policy; a test that legitimately switches context sets NEXRV_CS_LENIENT=1 for the lenient reading instead), and -target <id> for pulling one source’s stream back out of a funnelled multi-core capture by its Nexus SRC field. The decoder’s own flags must match the programmed encoder features — e.g. -bp iff InstEnBranchPrediction was set (see the configuration chapter); getting this wrong is a decode-time error, not the auto-hang class of defect the "SendConfig suppressed" pitfall describes.

+
+
+

scripts/decode_and_check.sh wraps CTTD for this repository’s test suite: it runs the decoder on a captured .atb.bin and compares against the cpu_model-generated expected files, selected by flag — --pc (PC stream), --ctxp (CTXP records), --data (loads/stores, address and size only, no CTXP), --sync N (at least N sync messages present), --disabled (a trace-off correlation message must be present), --overflow (an Error/QueueOverrun message must be present), --soft (report a divergence without failing the gate).

+
+
+
+

27.1.3. Online / live decoding

+
+

No live/streaming decoder ships in this repository. What the encoder’s wire format is built to support is a bounded re-anchor distance for a consumer that decodes from a moving window instead of a complete capture — the trace-quota cadence recipe in the configuration chapter is exactly that mechanism, with measured numbers from a board ring-buffer capture. Accemic’s live-processing product line, CEDARtools, decodes a trace stream in FPGA hardware as it arrives; the top-level README.md names it explicitly as one of the targets this design aims for compatibility with ("Targeted for live processing…​ for improved compatibility with technologies like CEDARtools"). CEDARtools itself is a separate product (see the CTTE-in-context chapter) and outside this repository’s scope — this manual documents the wire contract CEDARtools decodes, not the CEDARtools decoder.

+
+
+
+
+

27.2. Auto-configuration from the stream

+
+

A decoder does not need an out-of-band configuration file to know which optional features a given capture uses: with trTeControl.SendConfig enabled (the RDL reset is CFG_ONCE — one Config message per trace-on edge), the encoder emits a Vendor Config message (TCODE 58) carrying its compiled-in capability map (CAPS), the currently active runtime configuration (ENAB), and structural parameters (source-ID width, sync mode/period, timestamp configuration, return-stack/branch-predictor/ jump-target-cache sizes). CTTD reads this and configures itself — a flag-less decode of a stream that carries a Config message equals the explicitly-flagged decode. The full field layout is in the self-identification chapter; the pitfall of a control word that accidentally suppresses this message is documented in the configuration chapter ("Vendor Config message silently suppressed").

+
+
+

One field in the capability map is not a feature switch: CAPS bit 23 (ADDR64) tells the decoder whether this netlist carries 64-bit addresses (CT_XLEN = 64) — information a decoder cannot otherwise infer, because Nexus address fields are variable-length with leading zeros stripped, so a 40-bit and a 64-bit address whose top bits happen to be zero are byte-for-byte identical on the wire.

+
+
+
+

27.3. The CTXP export format

+
+

Besides the plain PC stream, CTTD reconstructs a second, richer view of a decoded capture: CTXP (CTTE eXPort records) — https://github.com/accemic/CTXP-format. CTXP records cover control flow (SYNC, BRANCH_*, CALL, RETURN), memory accesses (MEMREAD_n / MEMWRITE_n, carrying the data value, unlike the address/ size-only --data check) and instrumentation (DAQ_*, the ACT-CAP/ACT-ST output described in the hardware-instrumentation chapters). cpu_model emits the matching expected-CTXP files during simulation, and decode_and_check.sh --ctxp compares record-for-record (doc/verification.adoc, "The loop" / "Components").

+
+
+

CTTD writes the CTXP text export when the environment variable CTXP_TEXT_TRACEFILE names an output file, alongside -deco/-decoe. CTXP records additionally carry the absolute time CTTD reconstructed for them, which the --tsmono check in decode_and_check.sh verifies is monotone.

+
+
+

On the E-Trace side, tools/etrace/etrace_ctxp_ref.py is a second, independent CTXP producer — a Python reference model that reconstructs control-flow records directly from a te_inst raw stream plus an objdump listing, without going through CTTD at all. The E-Trace CTXP gate (scripts/cli_etrace_ctxp_test.sh, regression class EC) checks CTTD’s CTXP output against this independent model (EC3), against a dump_te.py interrupt count from the raw te_inst stream (EC4, tools/etrace/dump_te.py — the E-Trace sibling of a Nexus -dump), and against the simulation’s own expected files — three independent cross-checks of the same decode, not one tool trusted three times.

+
+
+
+

27.4. Program-structure input: PCINFO

+
+

A decode that wants to classify control-flow events (direct vs. indirect jump, call vs. return) rather than just list PC values needs a static description of the program under trace. -pcinfo <file> takes a CSV-like per-address classification, one line per instruction address: address, a two-letter class plus instruction size in bytes, and — for direct/relative control flow — the resolved target address. Example, from a generated run file (prog.pcinfo of an examples/kv260/mbv/board/ run; run directories stay local to the measurement host and are not part of the published tree):

+
+
+
+
1
+2
+
0x10,BD4,0x20
+0x1C,JD4,0x10
+
+
+
+
+

— a 4-byte direct branch at 0x10 targeting 0x20, and a 4-byte direct jump at 0x1C targeting 0x10.

+
+ ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
#CodeDescriptionRISC-V itype this maps from

1

JD

Jump, direct

INFERRABLE_TAIL_CALL and other direct jumps

2

JI

Jump, indirect

UNINFERABLE_JUMP

3

BD

Branch, direct (always direct on RISC-V)

TAKEN_BRANCH, NON_TAKEN_BRANCH

4

CD

Call, direct

direct jal

5

CI

Call, indirect

indirect jalr

6

R

Return (always indirect)

jalr to the link register

7

L

Linear

everything else (OTHER)

+
+

This repository’s own PCINFO producer is scripts/objdump_to_oracle.py, which reads objdump -d -M no-aliases,numeric output — the no-aliases,numeric form is required, because the aliased form (jalr a5, ret, j) hides the destination register and misclassifies an indirect call as an indirect jump. Companion tools in the same family: scripts/nm_to_json.py (symbol table) and scripts/bin_to_memh.py (binary-to-memory-image conversion for simulation); on the E-Trace side, tools/etrace/objdump2listing.py and tools/etrace/pcinfo2listing.py convert between the objdump-derived listing format and a .pcinfo/ .nexrv.info file.

+
+
+
+
+
+

28. Demonstrators and Reference Designs

+
+
+

Everything under examples/ in the CTTE repository shows the encoder doing real work: driven by a real RISC-V core, captured by a real sink, decoded by the real reference decoder (CTTD, see the decoding chapter). This chapter catalogs the demonstrators, what each one gates, and — for the ones that have run on hardware — the verdict with its exact numbers and the commit that produced them. Sources: examples/README.md (commit 586cad97fa, 2026-08-17) cross-checked against the board-gate scripts and logs it summarizes, and the board runs of 2026-08-21, recorded in the internal measurement archive (external to this delivery and not independently verifiable from it).

+
+
+
+ + + + + + + + + + +
+
+
+ mbv +
+ MicroBlaze(TM) V, RV32 +
+ 26 772 of 26 772 PCs (fixture) +
+
+
+ + + mbv... + + + + + + + + + + + +
+
+
+ tgc5b2_axis_wp +
+ TGC5B + watchpoints +
+ 851 of 851 (fixture) +
+
+
+ + + tgc5b2_axis_wp... + + + + + + + + + + + +
+
+
+ duo +
+ two cores through the funnel +
+ core0 PASS, board-gated +
+
+
+ + + duo... + + + + + + + + + + + +
+
+
+ trio +
+ three cores, mixed protocols +
+ 1 353 645 instructions, board-gated +
+
+
+ + + trio... + + + + + + + + + + + +
+
+
+ cva6_linux +
+ CVA6, OpenSBI + Linux boot +
+ 4 619 090 instructions / 0 errors +
+
+
+ + + cva6_linux... + + + + + + + + + + + +
+
+
+ cva6_linux64 +
+ CVA6 RV64, OpenSBI + Linux boot +
+ 4 246 697 instructions, board-gated +
+
+
+ + + cva6_linux64... + + + + + + + + + + + +
+
+
+ cva6_2 +
+ two CVA6 cores, AMP pair +
+ both guests to login, board-gated +
+
+
+ + + cva6_2... + + + + + + + + + + + +
+
+
+ rocket_linux +
+ Rocket RV64, Linux boot +
+ 5 414 841 instructions, board-gated +
+
+
+ + + rocket_linux... + + + + + + + + + + + +
+
+
+ rocket2 +
+ two Rocket harts, SMP Linux +
+ 7 770 406 instructions, board-gated +
+
+
+ + + rocket2... + + + + + + + + + + + +
+
+
+ tgc5b2_rvcfi +
+ two TGC5B, runtime verification +
+ board-verified 2026-08-26 +
+
+
+ + + tgc5b2_rvcfi... + + + + + + + + + + + +
+
+
+ KV260 board +
+ xck26-sfvc784-2LV-c +
+
+
+ + + KV260 board... + + + + + + + + + + + + +
+
+
+ Trace sink +
+ ring buffer / TE port +
+
+
+ + + Trace sink... + + + + + + + + + + + +
+
+
+ CTTD reference decoder +
+ (offline verdict) +
+
+
+ + + CTTD reference decoder... + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+
+
+ ATB trace +
+
+
+ + + ATB trace + + + + + + + + + + + + +
+
+
+ captured bytes +
+
+
+ + + captured bytes + + + + + + + + + + Text is not SVG - cannot display + + + + +
+
Figure 14. The ten KV260 demonstrators
+
+
+

Two of the ten, mbv and tgc5b2_axis_wp, carry (fixture) in their verdict line: their figures are byte-identical fixture reproductions from the predecessor project rather than a fresh capture from this tree — see the provenance note above. The tenth, tgc5b2_rvcfi, gained its first board verdicts on 2026-08-26 (see its catalog row below); it is gated by its own twin-table board gate rather than by the shared decode gate of the other nine.

+
+
+

The other nine share one board, one sink and one offline decoder.

+
+
+

The registers these flows drive — the control window every KV260 example exposes to the processing system, and the address spaces of the TGC5B example SoC — are in Chapter 35, generated from the same SystemRDL the example RTL is built from.

+
+
+ + + + + +
+
Important
+		 +
+

Provenance of the board verdicts. Nine KV260 examples are described
+below as board-gated. Seven of them (duo, cva6_linux, cva6_linux64,
+rocket_linux, rocket2, cva6_2, trio) were run and verified from
+this repository — duo and cva6_linux on 2026-08-18, the other five plus
+a re-run of duo on 2026-08-21 — with the run logs committed under
+examples/kv260/<name>/board/ or the run driven by the board recipes under
+examples/dashboard/boot/. The other two (mbv,
+tgc5b2_axis_wp) carry verdicts that originate from the predecessor
+project (an internal archive, not part of this repository) and
+were reproduced byte-identically against the historical fixtures when their
+Bash board-gate scripts were ported into this repository — the porting
+commits said so explicitly (translated: "NOT YET run on the board";
+"ALL still NOT run on the board (H3)").
+The numbers are real board results, but their most recent confirmation
+from this tree is a fixture reproduction, not a fresh capture; the local
+run artifacts that would show a fresh capture (examples/kv260/<name>/board/run/) are
+gitignored and are not part of the versioned repository. This distinction
+is carried into each subsection below rather than glossed over.

+
+
+

A second distinction runs alongside it and carries the same weight: a verdict
+measured against a simulation oracle — what the program is defined to do —
+is not the same as a verdict measured against a recorded reference, which
+holds what the hardware did on an earlier run. Both kinds appear below and are
+named as such, per core.

+
+
+
+
+

28.1. Entry levels

+
+

Three ways to see CTTE work, by rising effort (examples/README.md):

+
+ ++++ + + + + + + + + + + + + + + + + + + + + +
LevelWhat it needs

Dashboard demo mode

No hardware, no FPGA tools, stdlib-only Python. py examples/dashboard/server.py --demo, then open http://localhost:8099 — replays committed captures from real runs.

Simulation

make sim-examples runs every simulable integration (needs abc plus a simulator; program artifacts are committed, so no RISC-V toolchain is required).

KV260 board flows

Build a bitstream, deploy, watch live trace, under examples/kv260/. Without Vivado: every demo ships its packaged, ready-to-load app in the repository under examples/kv260/<demo>/fpga/prebuilt/ (bundle provenance and sha256 recorded in scripts/demo.pin; verify a set with sha256sum -c MANIFEST.sha256).

+
+
+

28.2. Catalog overview

+ +++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
ExampleCore(s)Status (examples/README.md)

kv260/common/tgc5b/

MINRES TGC5B (RV32)

In tree — not an example but the shared library eight examples build on: the vendored core, the AXI-Lite-to-Wishbone bridge, SoC RAM/CLINT/INTC with their SystemRDL, and the hello_trace program. Its own SoC bench is make sim-tgc5b-soc.

dashboard/

any (consumes captures)

In tree — browser dashboard; demo mode replays committed captures without hardware.

kv260/mbv/

AMD MicroBlaze™ V (RV32)

In tree, board-gated 2026-08-17 (provenance note above) — 11 bare-metal programs, TRACE-bus ingress adapter.

kv260/cva6_linux/

CVA6 (RV32, config cv32a6_ima_sv32_fpga)

In tree; boots on the board 2026-08-17/18 — OpenSBI + Linux kernel.

kv260/cva6_linux64/

CVA6 (RV64, core cv64a6_imac_sv39_ctrace)

In tree, board-gated 2026-08-21 — boots to buildroot login: (11 004 bytes of guest console, 0 drops); a one-shot capture from core start decodes 4 246 697 instructions.

kv260/cva6_2/

CVA6 (AMP pair)

In tree, board-gated 2026-08-21 — AMP pair, both guests boot to buildroot login:: 544 507 540 and 542 494 739 retired instructions, both PCs in the kernel idle loop, 22 389 bytes of guest console, 0 drops, both window guards at 0.

kv260/rocket_linux/, kv260/rocket2/

Rocket (RV64, 2-hart SMP)

In tree, board-gated 2026-08-21 — rocket_linux boots to buildroot login: and 5 414 841 instructions decode against the pinned pcinfo; rocket2 reports M5_TWOHART_HW PASS with both harts retiring (+25 087 923 / +34 975 513 in one second), reaches the login prompt, and 7 770 406 instructions decode from its DDR sink. Board recipes: examples/dashboard/boot/rocket_linux64_run.sh and rocket2_linux_run.sh.

kv260/duo/

AMD MicroBlaze™ V + MINRES TGC5B

In tree; board-gated 2026-08-18 (fresh capture, this tree) — multi-core funnel, first-ever duo board run.

kv260/trio/

AMD MicroBlaze™ V + MINRES TGC5B + CVA6

In tree — per-instance protocol mix (N-Trace next to E-Trace raw in one CTMX container). Run the E-Trace branch on its own: a mixed stream does not decode (see below). Board-gated 2026-08-21 — DUO_BOARD PASS over the same gate as duo (--app trio_ctrace_kv260 --pl-mhz 68), 1 353 645 instructions, core 0 against the simulation oracle; the CVA6 branch stays stopped in that run.

kv260/tgc5b2_axis_wp/

2x MINRES TGC5B

In tree, board-gated 2026-08-17 (provenance note above) — watchpoint/DAQ testbed.

kv260/tgc5b2_rvcfi/

2x MINRES TGC5B

Board-verified 2026-08-26 — runtime-verification testbed: shared UltraRAM memory, per-core consoles, a doorbell ACT-CAP TIP adapter that reinterprets a store to a fixed address as the CSR beat the encoder expects (see Chapter 20), and one DDR record ring per core. Its own board gate reports BOARD_VERDICTS_OK over a twelve-leg twin table (both record transports: MM-FIFO and DDR ring); a full-tilt run of ~1.14 million records per core finished with ring drops 0/0, where the FIFO path under the same load loses records by design and says so. The verdict tables are the closing status chapter of its TUTORIAL_runtime_verification.md; its register maps are printed in Section 35.6.

+
+
+

28.3. KV260 board-gated examples

+
+

28.3.1. MicroBlaze™ V (mbv)

+
+

A KV260 (Kria™ K26 SOM, xck26-sfvc784-2LV-c) demonstrator that traces a bare AMD MicroBlaze™ V RISC-V core. The Zynq UltraScale+ PS runs Linux and drives the whole SoC through a single AXI4-Lite aperture (0xA000_0000); the PL holds the MicroBlaze™ V core, the rtl/adapters/amd_microblaze_v/ TRACE-bus-to-tip_if adapter, one CTTE encoder instance and a 1 MiB URAM capture ring readable from Linux (examples/kv260/mbv/README.md). Migrated from the predecessor project at commit 9cddf14c (2026-08-17).

+
+
+

Verdict (examples/README.md, "board-gated 2026-08-17"; program
+oracle from the predecessor project, reproduced by
+examples/kv260/mbv/board/mbv_board_gate.sh, commit c0c2476d33):
+26 772 / 26 772 PCs prefix-identical against the simulation oracle
+(check_pcout_vs_retired.py --ref-prefix-ok), Vivado 2026.1 build,
+WNS +2.094 ns. As stated in the provenance note above, this figure was
+established on the predecessor project’s board run and reproduced
+byte-identically as a fixture when the gate script was ported here; the
+Bash port itself had not been executed against live hardware from this
+repository as of the commit that introduced it.

+
+
+
+

28.3.2. Dual TGC5B watchpoint/DAQ testbed (tgc5b2_axis_wp)

+
+

Two independent MINRES TGC5B RISC-V cores on one KV260, each with its own CTTE encoder instance and its own ct_axis_wp_shim that turns the encoder’s 96-bit AXIS watchpoint-hit stream into 32-bit records for a Linux host to drain over /dev/mem. In parallel, both encoders' Nexus (N-Trace) ATB output is merged by ct_L1_funnel into the same three-sink subsystem (URAM ring + DDR4 + PIB) the duo/trio examples use, so a program-flow capture is available alongside the watchpoint records for cross-checking (examples/kv260/tgc5b2_axis_wp/README.md). Migrated from the predecessor project at commit 9cddf14c (2026-08-17).

+
+
+

Verdict (examples/README.md, "board-gated 2026-08-17";
+examples/kv260/tgc5b2_axis_wp/board/wp_board_gate.sh, commit
+d0cdd64fc7): bitstream built here, Vivado 2026.1, WNS +1.575 ns;
+851 / 851 watchpoint records per core on the KV260, cross-core merge
+monotone (checksa phase reproduced against fixtures, plus a
+1702/0 cross-core merge check). The software pipeline gate is independent
+of the board and runs on this workstation:
+examples/kv260/tgc5b2_axis_wp/sw/check_consistency.py prints
+E0_ALL_PASS over the full 1023-entry watchpoint set
+(examples/kv260/tgc5b2_axis_wp/README.md). The same provenance caveat as
+mbv applies to the 851/851 figure: reproduced from the predecessor
+project’s fixtures, not yet a fresh capture from this repository’s own
+gate script.

+
+
+
+

28.3.3. MicroBlaze™ V + TGC5B, funnelled (duo)

+
+

Two independent RISC-V cores traced at once: an AMD MicroBlaze™ V (same branch as mbv) and a MINRES TGC5B (from the shared TGC5B base), each with its own CTTE encoder instance. A ct_L1_funnel (N_STREAMS=2, MDO_WIDTH=6) merges both encoders' ATB (Nexus) streams into one packet-atomic stream; the decoder tells the two sources apart by the Nexus SRC field (examples/kv260/duo/README.md). Migrated from the predecessor project at commit 9cddf14c (2026-08-17).

+
+
+

Verdict — fresh capture from this repository
+(examples/kv260/duo/board/duo_board_gate.sh, commit f77005f22c,
+2026-08-18; the run directory
+examples/kv260/duo/board/board_run_duo_ctrace_kv260/ — including a
+board.err transcript of the live SSH/board session — stays local to the
+measurement host: examples/kv260/duo/board/.gitignore excludes run
+directories, so these artefacts are not part of the published tree):

+
+
+
    +
  • +

    core0 (MicroBlaze™ V): PASS, 31 240 / 31 240 PCs — the simulation oracle is completely contained as a prefix of the decoded sequence (check0.log). A second core-0 verdict exists from the re-run of 2026-08-21 and reads 26 772 / 629 371; the two are not in conflict and the denominators say why. Both gates compare an oracle prefix against a capture, and the pair is (oracle length / captured length): the 2026-08-18 run compared a 31 240-PC oracle against a capture of the same length, while the re-run compared the 26 772-PC MicroBlaze™ V oracle — the same oracle length quoted for the mbv example — against a 629 371-PC capture. Neither figure is a coverage ratio, and 31 240 / 31 240 in particular does not mean "the whole capture was checked".

    +
    • +
  • +

    core1 (TGC5B): PASS against the recorded reference. That reference is a reproduction result, not an oracle result: this repository holds no TGC5B simulation reference, so the file records what the hardware did on an earlier run. Since 2026-08-21 the gate defaults to refs/core1_hello_trace.recorded_20260821.pcs; the 2026-08-19 recording is kept beside it and no longer reproduces. Three board runs of 2026-08-21 — duo at 75 MHz, duo at 68 MHz and trio at 68 MHz — diverge from the older file at the same index 855 with identical PCs while being identical to each other over all 720 238 decoded core-1 PCs, which rules out interrupt timing as the cause; the older file’s own context shows 0x20 three times after 0x1ec, a stopped core rather than a running program. Which of the two recordings is correct is open — neither has been held against what hello_trace is defined to do (examples/kv260/duo/board/refs/README.md).

    +
    • +
  • +

    Re-run of 2026-08-21, at duo’s own 75 MHz — a different clock from the one the reference was recorded at: `DUO_BOARD PASS, core 0 against the real oracle (26 772 of 629 371) and core 1 against the new reference (100 000 of 748 081).

    +
    • +
  • +

    Combined decode (both cores through the same TE port): Decoded OK, 899 799 instructions (commit message f77005f22c); the run directory’s deco.log (local-only, see above) reports 0 error messages and a very close 898 924-instruction decode from the same capture, consistent within one re-run.

    +
    • +
  • +

    This is the first duo board run over the TE port from this repository. It was re-run on 2026-08-21 at 75 MHz and at 68 MHz; both runs decode identical PC sequences on both cores, so the PL clock does not change the instruction stream.

    +
    • +
+
+
+
+

28.3.4. CVA6 Linux (cva6_linux)

+
+

A single RV32IMA CVA6 core (config cv32a6_ima_sv32_fpga, no C extension) booting Linux, traced with CTTE. The Zynq UltraScale+ PS drives the SoC through a single AXI4-Lite aperture (0xA000_0000); the PL holds the CVA6 core, an atomics/address-demux crossbar, a minimal CLINT + 8250 peripheral, the rtl/adapters/cva6/ cva6_trace_wrap/cva6_iti_to_ctte_tip chain, one CTTE encoder instance and three trace sinks (on-chip capture ring, linear DDR sink, optional parallel PIB port, Section 12.2) (examples/kv260/cva6_linux/README.md). Migrated from the predecessor project at commit 9cddf14c (2026-08-17).

+
+
+

Verdict — fresh capture from this repository
+(commit 2664bb5c99afdcb2b00df5977a7e6db336896433, scripts/demo.pin
+entry cva6_linux_ctrace_kv260, 2026-08-18): bitstream 4dec7b54
+board-gated, OpenSBI and Linux boot captured and decoded: 4 619 090
+instructions, 0 errors, over the TE port.

+
+
+

This run only succeeded after a configuration defect was found and fixed the same night: the board driver’s trTeControl constant suppressed the Vendor Config message (TCODE 58), which left the decoder without the CAPS map it needed once the periodic-sync history buffer overflowed for the first time. See the "SendConfig suppressed" pitfall in the configuration recipes chapter (commit 7d91c2f8e0) — the fix (--sendconfig 1, the RDL reset) is what this verdict is measured with.

+
+
+
+
+

28.4. The shared TGC5B base (kv260/common/tgc5b)

+
+

This is the lowest entry step in the catalog, and the only one that needs no board at all. It is also no longer an example: since 2026-08-21 the directory holds the building blocks eight KV260 examples share, and the example it grew out of is gone (examples/README.md). What it still carries, and what makes it the entry point, is a complete SoC bench of its own.

+
+
+

The contents are a MINRES TGC5B (RV32I) core wired to ct_encoder with just enough SoC around it — program/data RAM, a timer, an interrupt controller — to run a small program and check the encoded trace against the reference decoder. Three nested modules, all under examples/kv260/common/tgc5b/ (README.md there):

+
+
+
    +
  • +

    ct_soc_synth_wrap — the bare SoC: TGC5B core, RAM, CLINT + INTC, the encoder fed from the core’s H2E trace port through ct_tip_adapter.

    +
    • +
  • +

    ct_soc_top — the control port: one AXI4-Lite slave for control/status registers, program load, the encoder CSRs and two capture BRAMs (16 KiB ATB, 4 KiB AXIS/DAQ).

    +
    • +
  • +

    ct_soc_kv260_top — the bitstream top, Zynq PS reaching the SoC over M_AXI_HPM0_FPD, based at 0xA000_0000.

    +
    • +
+
+
+

The bench runs fully in simulation with make sim-tgc5b-soc (Verilator via abc), which is the cheapest way to see the encoder produce a decodable stream — no board, no Vivado. The same SoC also runs on KV260 hardware, driven entirely from Linux with devmem and no custom driver.

+
+
+

Beyond the bench, the directory supplies the parts the other examples reuse: the vendored core and its licence sidecar under cpu/, the AXI-Lite-to-Wishbone bridge, the SoC RAM, CLINT and interrupt controller together with the SystemRDL that describes them (Section 35.4), the AXI-Stream observation buffer examples/kv260/common/tgc5b/rtl/ct_soc_axis_buf.sv, and the hello_trace program that several board gates decode against. A change here is therefore a change to eight examples at once, which is the reason it is documented as a library and not as a demonstrator.

+
+
+
+

28.5. More KV260 examples, board-gated 2026-08-21

+
+

Four further examples were migrated with their bitstream flow in place and were run on the board from this repository on 2026-08-21. They are grouped here rather than above because they were gated in one night, and partly through the board recipes under examples/dashboard/boot/ instead of a per-example examples/kv260/<name>/board/ gate script. Measurements and raw data live in the internal measurement archive, external to this delivery and not independently verifiable from it.

+
+
+

28.5.1. CVA6 RV64 Linux (cva6_linux64)

+
+

An RV64 CVA6 (core cv64a6_imac_sv39_ctrace, sv39 paging) booting Linux — not a second RV32 top.

+
+
+

Verdict — fresh capture from this repository (KV260 reference board, PL clock
+68 MHz, app cva6_linux64_ctrace_kv260, recipe
+examples/dashboard/boot/cva6_linux64_run.sh): the 17 703 992-byte payload
+is written into the guest window and reads back byte-identically, the guest
+reaches buildroot login: with 11 004 bytes of guest console and 0
+drops, the live trace stream adds 1 124 208 bytes in 2 s (LIVE_OK), and a
+one-shot capture from core start decodes 4 246 697 instructions against a
+freshly built pcinfo. The decode stops at 0x64ba007a — an address the
+listing deliberately does not cover, since user space is excluded from it —
+not at a decode error.

+
+
+
+

28.5.2. Rocket RV64, single and dual hart (rocket_linux, rocket2)

+
+

Two Rocket tops from the same Buildroot br2_external sources: one hart booting Linux, and the two-hart AMP variant behind the multi-hart funnel (ct_L1_funnel, CTTD -target).

+
+
+

Verdict — fresh captures from this repository (KV260 reference board, PL clock
+75 MHz, recipes examples/dashboard/boot/rocket_linux64_run.sh and
+rocket2_linux_run.sh):

+
+
+
    +
  • +

    rocket_linux (app rocket_x64_ctrace_kv260): 34 678 856-byte payload written and read back byte-identically, buildroot login: reached with 15 331 bytes of guest console and 0 drops, RETIRES 973 127 483 with WIN_ERR_CNT 0, and 5 414 841 instructions decoded against dashboard/demo/rocket64.pcinfo — the decode stops at the listing boundary 0x8020_0000, not at an error.

    +
    • +
  • +

    rocket2 (app rocket2_ctrace_kv260): same payload, byte-identical read-back, boot arbitration clean (_boot_lottery/coldboot_done 0/0 after loading), M5_TWOHART_HW PASS with hart 0 retiring +25 087 923 and hart 1 +34 975 513 instructions within one second, both PCs virtual and therefore with paging active, DDR sink 27 452 136 bytes at 0 drops and WIN_ERR_CNT 0 with the funnel in round-robin (0x11),
    +buildroot login: reached with 15 556 bytes of console and 0 drops,
    +and 7 770 406 instructions decoded from the first 4 MiB of the DDR sink
    +against dashboard/demo/rocket2.pcinfo.

    +
    • +
+
+
+

Both payloads are 34.7 MB, more than twice the 16 MiB limit described under the loader rule in Section 28.7; without that fix neither board leg was available.

+
+
+ + + + + +
+
Note
+		 +Both Rocket examples run at 75 MHz, unlike cva6_linux64, trio and both cva6_2 configurations, which run at 68 MHz. The label is not a preference in either case but the timing reserve: 75 MHz costs 0.729 ns against the 71.114 MHz constraint, and rocket_linux has +2.114 ns of slack, rocket2 +3.578 ns — whereas cva6_linux64 has +0.603 ns, trio +0.215 ns, which is less than the step costs. Both Rocket device trees declare clock-frequency = 75000000, so while the runner labelled them 68 the guest computed roughly 10 % fast: nothing crashed, but every delay, timeout and in-guest timestamp was wrong by that factor. The PL clock does not touch the decoded trace at all — measured, not assumed: both Rocket captures decode to exactly the same instruction counts against the pinned pcinfo at either clock, and a duo run at 75 MHz and one at 68 MHz produce identical PC sequences over all 720 238 decoded core-1 PCs. What the clock changes is wall-clock time inside the guest. +
+
+
+
+

28.5.3. CVA6 AMP pair (cva6_2)

+
+

The only AMP demonstrator in the tree: two CVA6 cores on one KV260, each booting its own RV64 Linux into a private 32 MiB window, both traced through one funnel.

+
+
+

Verdict — fresh capture from this repository (KV260 reference board, 2026-08-21
+07:22, examples/kv260/cva6_2/board/cva6_2_run.sh on a power-cycled board):
+both guests boot to buildroot login: — 544 507 540 and 542 494 739
+retired instructions, both PCs in the kernel idle loop, both boot lotteries
+won, 22 389 bytes of guest console, 0 drops, both window guards at 0.
+Measurements and raw data live in the internal measurement archive, external
+to this delivery and not independently verifiable from it.

+
+
+ + + + + +
+
Caution
+		 +That verdict is a single successful run, and the requirement list below is necessary but demonstrably not sufficient. Two later runs with the same register configuration did not reach the prompt — core 1 stopped at 15 and at 5 338 retires. A stopping point that moves looks like a race, not like a width; the honest reading of this example today is that the conditions below are all needed and something beyond them is still unresolved. A single won race is not a solution. +
+
+
+

Five requirements had to be met before that verdict, none of them visible from the build output and each one sufficient on its own to prevent the boot. Four concern the guest image; the fifth is not in the image at all, but in the PS (see Section 28.7).

+
+ +++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
#RequirementWithout it

1

FW_PAYLOAD_FDT_OFFSET=0x01F00000 when OpenSBI is built

OpenSBI with PLATFORM=generic defaults the offset to FW_JUMP_FDT_OFFSET = 0x2200000 (34 MiB), which lies 2 MiB past the end of a 32 MiB window. The guest never finds its devicetree, and the hart is parked in sbi_hart_hang without emitting a single console character — which makes the failure look like a dead core rather than a misplaced pointer. The working value sits above the payload and 1 MiB below the end of the window.

2

A kernel without loadable modules, and the driver classes that switch pulls in turned off as well

23 of 29 MiB of the rootfs were kernel modules — 340 symbols that arch/riscv/configs/defconfig builds as =m and that nothing on this SoC ever loads, carried into the image because the rootfs is an initramfs inside it. CONFIG_MODULES=n alone makes the image larger, because Kconfig promotes =m drivers to =y wherever their default says so; the driver classes (PCI, DRM, FB, sound, USB, MMC, SCSI, ATA, NVMe, network and WLAN cards, media, virtio) have to go with it.

3

CONFIG_FLATMEM instead of SPARSEMEM

SPARSEMEM_EXTREME sizes its section table from MAX_PHYSMEM_BITS, not from the RAM actually present: a 16 MiB table for a 32 MiB machine. The result is the panic memblocks_present: Failed to allocate 16777216 bytes in sparse_init.

4

A second kernel cut: network stack, io_uring, journaling file systems, ftrace and kprobes off, CC_OPTIMIZE_FOR_SIZE on

A 17.7 MiB kernel next to a 6.4 MiB initramfs leaves nothing to run in 32 MiB: the guest reaches the init phase and dies after about 10 s with System is deadlocked on memory. After the cut the kernel is 15.61 MB instead of 24.19 MB.

5

The PS port of each core configured — saxigp4 (AFIFM4) as well as saxigp3 (AFIFM3)

Core 1 cannot write at all and stands at RETIRES = 14 on OpenSBI’s first amoswap.w, while looking perfectly alive because its read path is unaffected. The rule and the one-variable proof are in Section 28.7.

+
+

Sizes worth quoting: Image 15 606 820 B, rootfs.cpio 6 438 912 B, fw_payload.bin 17 703 992 B = 16.88 MiB per core against a 32 MiB window.

+
+
+
+

28.5.4. Three cores with mixed protocols (trio)

+
+

Three cores — MicroBlaze™ V, TGC5B and CVA6 — behind one funnel, adding the per-instance protocol mix: N-Trace next to E-Trace raw framing in one CTMX container, with a demultiplex tool vendored in the example.

+
+
+

Verdict — fresh capture from this repository (KV260 reference board, PL clock
+68 MHz): the control map for MicroBlaze™ V and TGC5B matches duo, so the
+proven duo_board_gate.sh was pointed at the trio app unchanged
+(--app-dir …​/trio_ctrace_kv260 --app trio_ctrace_kv260 --pl-mhz 68).
+Result: DUO_BOARD PASS — core 0 against the real simulation oracle
+(26 772 PCs complete as a prefix of 624 064), core 1 against the recorded
+reference discussed under duo above, 1 353 645 instructions decoded.
+The CVA6 branch stays stopped in that run, for the reason in the box below.

+
+
+ + + + + +
+
Caution
+		 +
+

Run the E-Trace branch of trio on its own. A mixed stream is not
+decodable, and this is a property of the sinks, not a configuration
+mistake. The frame length of each beat lives in the ATB signal ATBYTES
+(4 bytes for N-Trace, 1 byte for E-Trace), and no sink keeps it per beat: the
+URAM ring does evaluate the signal, but only as a running sum in its byte
+counter (examples/kv260/common/ct_soc_trace_ring.sv:97), while the DDR sink
+and the PIB never receive it at all (ct_soc_ddr_sink.sv:64-65,
+ct_soc_pib.sv:64-65). Every E-Trace byte therefore lands in the ring as
+nn FF FF FF, and a decode run aborts at the framing with
+MSEO='10' is not allowed, for all targets in the container, not only
+the third. Measured on the board. The 0xFF padding itself is not what
+aborts the decode — 0xFF carries MSEO='11' and is discarded as IDLE; the
+abort comes from the payload byte in the lowest lane.

+
+
+

How much of the container is padding depends on the mix. A pure E-Trace
+stream is 75.00 % padding (measured on
+evidence/board_20260819/trio_cva6.bin), the mixed stream of all three cores
+44.73 % (trio3.bin), a pure N-Trace stream 18.75 % (ddr_ok.bin). Reading
+the 75 % figure as the mixed case underestimates the payload.

+
+
+

The sum that is kept is still worth reading. Because the ring’s byte
+counter sums ATBYTES while its beat counter does not, TRACE_BYTES against
+TRACE_BEATS already shows whether E-Trace beats are in the container
+(bytes == beats instead of bytes == 4 * beats) — but not which ones.

+
+
+

It cannot be repaired after the fact: an N-Trace beat with idle padding is
+byte-for-byte indistinguishable from an E-Trace byte with padding. Running
+the E-Trace branch alone puts a pure E-Trace stream in the ring, which
+decodes cleanly. What a later rework would cost is recorded as item B-01 of the internal
+backlog, outside this delivery.

+
+
+
+
+
+
+

28.6. Dashboard demo mode

+
+

examples/dashboard/ is a browser dashboard that consumes captures from any of the examples above; its demo mode (py examples/dashboard/server.py --demo) replays committed captures with no hardware and no FPGA tools attached, which is why it is listed as the lowest-effort entry level. It also participates in the feature matrix of examples/README.md — program trace, sync/quota, watchpoints, DAQ/AXIS, filters and overflow/resync recovery are all exercised through captures it ships with.

+
+
+

28.6.1. Protocol interlock

+
+

Since commit be3f1c675b2 the dashboard refuses to run N-Trace and E-Trace cores at the same time, and it does so before the attempt rather than failing afterwards. Expect the lock; it is not a defect:

+
+
+
    +
  • +

    The server rejects starting a core while a core of the other protocol is running, and likewise rejects the collective start (CONTROL bit 0 releases all cores at once). The rejection names ATBYTES as the reason and states the way around it.

    +
    • +
  • +

    In the interface, the run button of a blocked core is disabled before the click and carries the reason in its tooltip.

    +
    • +
  • +

    The mapping is data-driven: every core carries a protocol field (ntrace / etrace) in scenarios.json. The code does not compare names — which back end an encoder was built with is a synthesis parameter, and the register reporting it (trTeProtocolSel) is read-only.

    +
    • +
+
+
+

The reason behind the lock is the one described for trio above: the sinks do not store the per-beat frame length, so a mixed stream cannot be demultiplexed afterwards.

+
+
+
+
+

28.7. Operating the KV260 flows

+
+

Five rules that no script enforces and that cost time when missed.

+
+
+

Stop the dashboard service before reprogramming the PL. It holds
+/dev/mem mappings into the PL aperture; changing the PL underneath them
+hangs the AXI interconnect on the next access — every IP dead, the board no
+longer answers ssh, and only the power switch recovers it. Reproduced three
+times in a row on 2026-08-21, one attempt each, until the service was stopped
+first; the immediately following attempt loaded cleanly. The order is: stop
+the service, xmutil unloadapp, set the PL clock, xmutil loadapp. The clock
+belongs between unload and load: a frequency change under a running design
+is a clock glitch. Since 2026-08-21 deploy_kv260_app.sh stops the service
+itself before touching the PL, and deliberately does not start it again — a
+different design sits in the PL after a deploy than the one the dashboard was
+serving.

+
+
+

After a guest run, prep and start do not return the core to its initial
+state — only a fresh loadapp, which is a real PL reset, does. Whoever
+skips it measures states instead of changes.

+
+
+

Configure the PS port width of every port the design uses — including the
+second one. psu_init does not run for a DFX app, so the AFIFM ports keep
+their 128-bit reset value until a board recipe sets them. Every recipe in
+this repository configured two ports, because every other design has one
+core and therefore one guest window. cva6_2 gives each core a private PS
+port: core 0 on saxigp3 (AFIFM3), core 1 on saxigp4 (AFIFM4,
+0xFD3A_0000). With AFIFM4 at its reset value, core 1 cannot write at all —
+no store reaches DDR, and the window guard reports nothing because the
+accesses never get that far — while its read path is unaffected, so the core
+looks perfectly alive. The first operation that waits for its answer,
+OpenSBI’s boot lottery amoswap.w, then hangs forever and the core stands at
+RETIRES = 14. One-variable discrimination, reproduced in both directions on
+a power-cycled board: AFIFM4 at its reset value gives one guest and
+RETIRES1 = 14; AFIFM4 at 64 bit lets both guests boot to
+buildroot login:.

+
+
+

And write those registers read-modify-write. FABRIC_WIDTH occupies bits
+[1:0] of RDCTRL/WRCTRL, whose reset value is 0x3B0: several bits above
+[1:0] are marked reserved, yet are RW and set out of reset (UG1087). Writing
+the whole register with the width code clears them. Correct is
+new = (old & ~0x3) | width, that is 0x3B1 for 64 bit and 0x3B2 for
+32 bit. All five board recipes use a read-modify-write helper for this.

+
+
+

A board restart empties /tmp — tools and payloads placed there are gone
+afterwards, and the next step fails silently on the missing script.

+
+
+

Reach the guest window with mmap only, never with read()/write(), and
+keep the accesses 32 bit wide. For no-map reserved regions the /dev/mem
+write path answers "Bad address"; and a glibc memcpy — which is what every
+mmap slice assignment compiles to — issues NEON stores that abort with
+SIGBUS on a Device-nGnRnE mapping, measured at exactly 16 MiB. A loader that
+did this halved payloads above 16 MiB silently, and the guest still printed
+a fully plausible kernel log, because OpenSBI and the head of the kernel lie
+within the first 16 MiB and only the tail with the initramfs was missing.
+A word loop over ctypes writes the same payload completely, verified by
+byte-identical read-back.

+
+
+
+

28.8. Tool-version note for the KV260 flows

+
+

Two Vivado generations are in play on purpose, not by drift (examples/README.md, "Vivado versions, honestly"):

+
+
+
    +
  • +

    Core simulation and the gate battery (make sim, make sim-examples) pin Vivado 2022.1 (xsim, via .abc.config at the repository root) — every core verdict in ci/ is calibrated against this version.

    +
    • +
  • +

    The kv260/ bitstream flows are verified with Vivado 2026.1 (C:\Xilinx\2026.1\Vivado on the reference workstation); every KV260 board gate in this chapter was built with it.

    +
    • +
+
+
+

The two generations are not interchangeable, and the split is deliberate: a version bump on either side is always a measured change, never a side effect. Anyone reproducing a resource or timing figure from this manual must use the version the figure was taken with — the profile table in Chapter 24 names it per row.

+
+
+
+
+
+

29. Verification Strategy

+
+
+
+
cpu_model
(scripted core)
cpu_model...
ct_encoder
(DUT)
ct_encoder...
.atb.bin
.atb.bin
CTTD
(ref decoder)
CTTD...
decoded:
PCs · CTXP
decoded:...
expected:
PCs · data · CTXP
expected:...
compare
compare
PASS / FAIL
PASS / FAIL
drives TIP
drives TIP
trace
bytes
trace...
reconstruct
reconstruct
records what it ran
records what it ranText is not SVG - cannot display +
+
Figure 15. The verification round trip — the scripted core drives the encoder, the reference decoder reconstructs, and the two are compared
+
+
+

29.1. The oracle principle

+
+

CTTE’s test harness is built around a single idea: a scripted CPU model is both the stimulus and the answer key. cpu_model (tests/lib/cpu_model.sv) is a task-based scripted core — run, branch_taken, call, ret, load, store, csr_write, interrupt, … — that drives the encoder’s TIP interface exactly as a real hart would, and simultaneously logs a sideband event stream of what it just did. No binary image and no instruction-set simulator are needed; the tasks themselves are the program. The shared ct_env harness (tests/lib/ct_env.sv) wires the model to the DUT and to the trace sinks.

+
+
+

The encoder turns the TIP stream into an N-Trace or E-Trace byte stream on the ATB. An independent reference decoder, CTTD (CEDARtools.TraceDecoder) — a second, independent implementation of the wire format, not a CTTE component — turns the bytes back into a trace. scripts/decode_and_check.sh runs CTTD against the captured .atb.bin and diffs the result against the cpu_model-logged expected files. If the encoder mangles the trace anywhere in the pipeline, the reconstruction will not match the log, and the check fails. CTTD reconstructs two views from the same bytes: the PC stream (instruction trace) and the CTXP export — control-flow, memory-access and instrumentation records with data values — and cpu_model emits matching expected files for both.

+
+
+

CTTD is derived from the RISC-V Nexus Trace TG reference decoder NexRv (ISC-licensed) and extended by Accemic (E-Trace -decoe, DAQ, multi-target -target, CTXP export). Since 2026-08-17 it is no longer committed to the encoder tree: scripts/cttd.pin names the release and the per-platform sha256, and scripts/fetch_cttd.py downloads it from the CTTD repository that the pin names in its base_url (assets on the dist branch) into the gitignored bin/, with a checksum mismatch treated as a hard error.

+
+
+

decode_and_check.sh supports the check flags --pc (PC stream), --ctxp (memory accesses with data values plus DAQ instrumentation), --data (loads/stores, address and size only), --sync N (at least N sync messages), --disabled (trace-off correlation present), --overflow (an Error/QueueOverrun message must be present) and --soft (report divergence without failing the gate). It also fixes one decoder policy for the whole regression suite: decoding runs with -csstrict, the strict reading of the implicit-return address mirror. A scripted cpu_model never switches task context, so a mirror mismatch there is a genuine defect and must be fatal; a test that legitimately switches context (real-core simulation legs, see Section 29.9) sets NEXRV_CS_LENIENT=1 to get the lenient reading instead.

+
+
+
+

29.2. What makes a check a gate

+
+

A passing check proves nothing by itself; what makes it evidence is that it would have failed for the defect it claims to catch. A gate that cannot turn red for its own defect class is a green light with no lamp behind it. Every verification mechanism in CTTE’s suite therefore carries one of four falsifiability shapes:

+
+
+
+
Historical counter-proof
+
+

the check is re-run against a git worktree of the pre-fix commit and must fail there. Used for defect classes that really occurred — the class-8 and class-9 formal targets are red at a named BMC step on their pre-fix trees (see Section 29.8).

+
+
Mutation counter-proof
+
+

where no historical defect commit exists, the check is run against a deliberately broken copy of the design — a wrong end-of-message code, a suppressed EOM, a context cast narrowed back to its old width, a filter made ineffective, one instruction shifted by two bytes in a reference listing. run_red.sh for formal targets; MUTATE=1 or an explicit -ExpectFail leg for the script gates.

+
+
Vacuity leg
+
+

an implication whose antecedent never occurs is green for free and proves nothing. Assertions of that shape need a scenario that demonstrably exercises the antecedent — invariant I10 (Section 29.7) has one.

+
+
Reachability
+
+

a check nobody runs is not a check. This class has been found three times in this project’s own history and is recorded rather than quietly fixed: a bound checker whose counter was too narrow to represent the violation it guards (Section 29.7); assertion failures that XSIM wrote only into a log the CLI scripts silenced (now scanned by scripts/cli_status_test.sh); and CTTD’s own five test runners, which were wired into no CI pipeline at all until 2026-08 (Section 29.12).

+
+
+
+
+

The question to ask of any gate in this chapter is therefore not "does it pass" but "what was done to make it fail".

+
+
+
+

29.3. Components

+ ++++ + + + + + + + + + + + + + + + + + + + + + + + + +
ComponentRole

cpu_model (tests/lib/cpu_model.sv)

Task-based scripted core; both the stimulus and the reference for every test in the suite. See the oracle principle above.

CTTD (scripts/fetch_cttd.py → bin/cttd-<platform>)

Reference decoder for the N-Trace wire format; a second, independent implementation, pinned by hash (see Section 29.4).

CTTD’s own regression runners

Five runners shipped by the decoder repository (run_etrace_ctxp, run_callstack, run_ctxswitch, run_reserved_tcode, run_addr64), collected behind that repository’s own runner script — not a file of the encoder tree, whose test entry points are the make sim* targets and tests/README.md. CI stage 1 runs them when a decoder source tree is available (NEXRV_SRC); a plain clone of the encoder repository reports SKIP for this step — the decoder source is Accemic-internal.

decode_and_check.sh

Runs CTTD on the captured ATB dump and compares against the cpu_model-logged expected files; see the flag list above.

+
+
+

29.4. The reference decoder is a gate input, not a given

+
+

Every PASS in this suite is a statement about two independent implementations: the encoder wrote the bytes and the decoder read them back. That makes the decoder binary a measuring instrument, which has to be verified before its readings are trusted. A re-pin of CTTD is therefore treated like a wire-format change: it is accepted only with evidence recorded in the scripts/cttd.pin commit and the CTTD repository’s own changelog, never in an unrelated commit. The evidence a re-pin must carry is the defect it removes (reproduced on the old binary with the same input, not argued from source reading), byte neutrality on everything that already passed (old and new binary run over the frozen corpora, comparing the full log and exit code, not just the PC list), and its measured price (a decoder change that removes an abort also removes whatever that abort used to catch).

+
+
+

Two re-pins in 2026-08 illustrate the discipline:

+
+
+
    +
  • +

    64-bit addresses. The prior decoder could not decode a 64-bit address at all — on an Sv39 kernel window it truncated to the low 32 bits and exited 9. The replacement derives its output width from CAPS bit 23 (ADDR64) in the configuration message rather than a CLI switch, and was shown byte-identical to the binary it replaced across 525 of 525 32-bit artefacts. Its immediate successor then fixed a follow-on defect (a process-global width flag bleeding across funnel sources): guard run_addr64 went from PASS=16/FAIL=6 to PASS=22/FAIL=0, with 440 of 440 artefacts unchanged at 32-bit.

    +
    • +
  • +

    Context switches are not decoder errors. The implicit-return address mirror predicts a ret target; under a preemptive kernel, a task switch makes the prediction wrong while the stream is right (the target is carried explicitly). The old pin treated that as fatal, so no multitasking kernel was decodable past its first context switch. The new pin reports a visible re-anchor and keeps decoding — on the same recorded board stream, decode moved from 34,537 instructions plus an abort to 818,663 instructions with zero error messages. The price was measured, not assumed: a one-byte mutation sweep over 40 cases is caught 25 times by the new binary versus 27 by the old one (the two losses are UADDR flips at returns the strict mirror caught by accident); the -csstrict default (above) restores the old detection strength for the scripted suite while leaving real-kernel streams decodable.

    +
    • +
+
+
+ + + + + +
+
Caution
+		 +the general rule behind this section applies to every tool in a verification chain: a gate that can only fail together with its own tool judges nothing. This is why the 64-bit emission gate (instruction/35_addr64, Chapter 30) reads its verdict off the raw ATB bytes rather than asking the decoder, and why the decoder itself is cross-checked against independent artefacts (oracles, disassembly listings, its own fixtures) rather than solely against the encoder it is meant to be checking. +
+
+
+
+

29.5. Test scenarios and round-trip gates

+
+

Scenarios live under tests/; make sim runs the full suite and prints a per-category PASS/FAIL summary, make sim-<name> runs one. The full catalog, by directory and gate, is the test catalog chapter; this section states the checking principle each category shares.

+
+ +++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
CategoryLocationRound-trip principle

Instruction trace

tests/instruction/ (39 numbered scenarios)

CTTD --pc reconstruction of the PC stream against the cpu_model log; strict return-address mirror (-csstrict).

Data trace

tests/data/ (6 scenarios)

--ctxp/--data reconstruction of memory accesses (address, size, and where applicable value) against the logged access stream.

Hardware-supported instrumentation (HSI)

tests/hsi/ (1 scenario, all ACT-CAP commands)

AXIS beat self-check plus CTXP DAQ record reconstruction.

Overflow / robustness

tests/overflow/ (15 scenarios)

Full overrun lifecycle (inject or natural overflow, resync, soft-reset recovery); --overflow is a hard gate. See Section 29.6.

Combined

tests/combined/ (1 scenario)

Instruction + data + ACT-CAP sync exercised together, to catch cross-feature interaction the per-feature legs miss in isolation.

+
+

Known-failing regression gates can be listed in SIM_XFAIL in the Makefile: they run and report XFAIL without failing make sim, and a surprise pass shows as XPASS — a signal to promote the test once the underlying fix lands.

+
+
+

The compression features additionally carry byte-identity legs (cli_{bp,ir,jtc,rh,rb}_test.sh): the same stimulus run with the feature OFF and ON from one build. The OFF prefix must equal the reference byte-for-byte; the ON stream must decode to the same PC stream at a strictly smaller byte count. These legs pin the wire format itself — any incidental byte change from an unrelated fix turns them red.

+
+
+
+

29.6. Robustness gates (state across discontinuities)

+
+

Every cross-message compression state (JTC mirror, branch predictor, implicit-return stack, ICNT/HIST accounting) has to re-converge at every stream discontinuity: a FIFO-overrun recovery, a trace pause, a session stop. Each defect class first found on real hardware (KV260 robustness campaigns) carries a standing regression gate with a documented red counter-proof; the fifteen tests/overflow/ scenarios plus three tests/instruction/ gates that guard this state family are cataloged individually in Chapter 30. Two properties of the family are worth stating here because they explain why this many scenarios exist for what looks like one contract: several defects were found only by combining two features that were each clean in isolation (e.g. branch prediction alone was green, periodic sync alone was green, the combination was not — overflow/06_suite_isync), and several were found only by forcing an anchor onto a specific retire kind — a control-flow retire, a not-taken branch, a trap marker — because the injector’s inject_hold logic covered some retire kinds and not others.

+
+
+

Honesty note (2026-08-07): the 2026-07 E-Trace verification claim "mid-trace periodic resync solved" was too broad. The P10 seed-driven soak campaign found three pre-existing defects the original directed leg (instruction/23_etrace_resync) never crossed: a resync anchoring on a predicted-return retire, a target report whose address is also linearly reachable, and an overflow anchor landing on a branch. These are closed by the resyncir gate (instruction/34_etrace_resync_ir) and an overflow-anchor deferral in ct_L2_te_inst_gen.sv. One class remains open by wire-format necessity — see Chapter 33.

+
+
+
+

29.7. Standing in-RTL invariants (SVA)

+
+

The most expensive lessons of the hardware campaigns are encoded as concurrent assertions inside the RTL itself (simulation-only, pragma translate_off), so they run in every simulation of every consumer and fire at the first sim rather than on a board:

+
+ ++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
IDInvariant

I1 / I2

No ordinary control-flow eTIP while a pause re-anchor is outstanding, or while instruction tracing is paused.

I3

The implicit-return stack is empty when the trace-off correlation is emitted.

I4

A next_iaddr capture fires only when a control-flow event owes one (pairing conservation).

I5

A gap re-anchor sync on a call/return retire leaves the return stack untouched (side-effect-free anchors).

I6

A correlation message implies a cleared JTC mirror and predictor count.

I7

A FIFO-overrun recovery sync carries ICNT=0 (pure re-anchor).

I8

trTeControl.Empty implies an empty ATB output queue per backend tail.

I9

Device ID precedes the config message precedes the first synchronizing message, on the wire, when both CT_EN_DEVICE_ID and CT_EN_CONFIG_MSG are enabled.

I10

A watchpoint slot never coexists with a DAQ slot in one beat — the exclusion that lets CT_EN_WATCHPOINT_MSG share the DAQ slot instead of widening the eTIP slot count.

I11

No ordinary control-flow eTIP inside a filter-suppressed gap (CT_EN_FILTER_SYNC; vacuous while no filter is programmed, i.e. in every unfiltered run).

I12

Every emitted instruction count fits the N-Trace I-CNT field width (8 bit, or 16 with InstEnWideIcnt) — the only invariant in this set that guards conformance rather than internal consistency: an over-cap value costs one extra wire byte, decodes correctly, and keeps every other gate green while the stream has left the standard.

+
+

Because XSIM writes assertion failures only into the per-leg log and the CLI scripts silence the simulator’s own output, scripts/cli_status_test.sh scans those logs and fails the gate on any Error:/Fatal: line — an assertion nobody reads is not a gate (the reachability shape above). A bound check is only as good as its counter’s ability to represent a violation: msg_id_next (guarded by a_p4_slot_bound, feeding I10’s slot-sharing argument) used to be sized for eight allocation sites when nine could be simultaneously enabled, which would have wrapped silently past the bound it exists to catch. The width now follows ct_pkg::ETIP_SLOT_SITES, computed from the source rather than hand-set, and formal/composer_slots/run.sh counts the real allocation sites before every proof run so a newly added arm fails the gate rather than the field.

+
+
+
+

29.8. Formal property gates (SymbiYosys)

+
+

The three encoder defect classes found in the 2026-08 board campaigns (trap anchor, resume-anchor race, flush clobber) shared one shape: local cycle collisions in a tiny state space, phase-dependent and found dynamically only by lucky draws — exactly what formal methods find in seconds. The emission core therefore carries property gates on the license-free open-source route (sv2v + Yosys/SymbiYosys, smtbmc):

+
+ +++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
TargetWhat is provedResult

ovf_injector (parallel and SEQ_INJECT variants)

Element conservation, episode debt, inject_done/inject_hold semantics — full functional correspondence against an independent mirror model.

Unbounded (k-induction) + cover

ct_L23_preproc_sync

No periodic sync while a trace-enable re-anchor is outstanding (class-9 fix 335393b6); one-shot arming/drop semantics; sync anchors only on qualified retires; the trace-output quota protocol including the real CDC pairs; the explicit sync-request pacing protocol (ct_sync_req_pacer) with no lost and no double request.

Mixed unbounded / bounded + cover (see caveat below)

ct_L2_msg_gen (abstracted eTIP payload)

A consume beat never coincides with a flush-marker emission (class-8 fix 8f8e85aa); backpressure holds TraceMsg bit-stable; the latched flush debt is never lost.

BMC depth 50 + cover

MDO/MSEO output stage

Reserved dual-pin code never emitted; the IEEE-ISTO-5001-2012 Table 5-1 encoding table; message conservation (one end-of-message chunk per accepted message); CDC-seam non-overrun; beat alignment.

BMC depth 40 + cover + bounded liveness (depth 120)

ct_L23_preproc_composer_etip eTIP slot bound

msg_id_next ⇐ ETIP_PAR_MSG at the allocation site, over a fully free environment, for both SPLIT_DATA_ACCESS settings.

Unbounded (k-induction)

+
+

Every regression property carries a two-sided red counter-proof: it passes on the fixed RTL and fails on a git worktree of the pre-fix commit. ct_L23_preproc_sync’s CDC-closing properties are proved at equal clocks (this environment’s single-clock assumption) — what is proved is the pacing protocol and the toggle synchronizers, not the general behaviour of a toggle synchronizer between two independent clocks, which remains a CDC-methodology argument rather than a formal one. All targets are proved at `ct_pkg::CT_XLEN = 32 with hand-retyped address ports; only nexus_formatter additionally runs as nexus_formatter_xlen64 against a width-flipped source copy. Until 2026-08 every formal gate had only ever run at 32 bit — an audit finding, not a plan.

+
+
+

One documented pitfall for one-directional properties (formal/README.md, condition A-2): a property whose model appears only on the conclusion side of an implication gets weaker, never stronger, as the model’s own arming widens, and a DUT that stops arming altogether satisfies it vacuously. Measured on ct_L23_preproc_sync: removing the TCI trigger action from the RTL entirely still reported "successful proof by k-induction" for that property. The completeness obligation on the other side (a bounded next-cycle requirement) is what actually catches a DUT that stopped arming, and it does go red on the same mutation.

+
+
+
+

29.9. Hardware-in-the-loop and SoC integration

+
+

Everything above runs against a scripted cpu_model, which cannot produce a real hart’s retirement timing, a real memory system’s backpressure, or a real operating system’s behaviour. Three ingress adapters exist outside the encoder core — AMD MicroBlaze™ V’s TRACE bus, the CVA6/cv64a6 instruction-trace interface fed from its RVFI probes, and the Rocket TraceCoreInterface — and each is characterized before it is trusted: a truth table per event class, measured against the core’s own retire stream, is the entry gate for a new adapter.

+
+
+

Robustness campaign (MicroBlaze V, KV260). A directed 95-run matrix over overflow regimes (including ATB backpressure profiles), feature sets, workload mixes, sync modes, trace-window/stop/flush edges, IRQ, BTM, one-factor bisection legs and a determinism pair, judged against an RV32 reference model on eight verdict axes (decode integrity, loss accounting, post-recovery losslessness, counter consistency, liveness, determinism, window semantics, flush completeness). Result as of 2026-08-01 (campaign rob_allgreen): 95 PASS / 0 FAIL / 0 invalid. A full-SoC XSIM twin of the same workload (real MicroBlaze V plus adapter at the board’s 1:1 clock profile, 343,629 retires, 24 natural overflow recoveries) decodes transitions-exact as the simulation-side positive control. A seed-driven soak campaign on top of this directed matrix is what found the three 2026-08 encoder defect classes now held by the formal gates above, plus the four pre-existing E-Trace classes named in the honesty note (Section 29.6).

+
+
+

64-bit harts, cv64a6 and Rocket (2026-08-08). ct_pkg::CT_XLEN = 64 is established beyond a testbench: both cores were brought up in the KV260 PL beside the encoder and boot Linux (Buildroot + OpenSBI) to a login prompt. Simulation leg (cv64a6): the full chain core → RVFI → ITI → shim → encoder → ATB → CTTD → scoreboard reconstructs 10,167 of 10,167 instructions, delta 0, in the low address window and again with Sv39 kernel addresses. Board leg: a recorded window of the running kernel decodes to 34,453 instructions (32,413 with addresses >= 2^32), zero error messages, verified by an independent flow check that walks the decoded PC sequence against the disassembly rather than trusting the decoder — PASS, with five deviations all landing on the same address, OpenSBI’s M-mode trap vector (the physical target of a virtually-addressed kernel). With the current decoder pin the same stream decodes 818,663 instructions uncompressed and 883,577 with the compression suite armed, both zero-error and PASS on the independent flow check. Two open items at time of writing: parallel retirement is not exercised (both harts run a single commit port), and an E-Trace instance with CT_XLEN = 64 is rejected at elaboration rather than truncating silently — see Chapter 33.

+
+
+

Tracing one process, end to end (trTeComp[].PInput = 1, context filter). Verified as a chain rather than a register: two programs with different ASIDs run on the cv64a6 model. Unfiltered, both appear (204 and 168 instructions in their ranges) and Ownership messages carry both ASIDs. Filtered to process A: 204 of 204 for A, 0 of 168 for B, only A’s ASID on the wire — and the substance of the feature is that the filter suppresses at the source, not that it marks: two counter-proofs confirm this is not vacuous (an ineffective filter returns the full 437-PC stream; compiling out the filter anchoring produces zero decodable instructions, the pre-fix behaviour the anchoring exists to prevent). This leg is simulation with real core RTL; filtering real Linux processes on a board, where the ASID is written by the kernel rather than the test, is a follow-on package and not claimed here.

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29.10. Timing and resource verification

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Out-of-context synthesis timing is gated at two budgets per build profile: 13.333 ns / 75 MHz (the KV260 reference design’s constrained clock — the pass criterion, "all user specified timing constraints are met" with zero failing endpoints) and 5.0 ns / 200 MHz (reported headroom, not required). scripts/p10_timing_matrix.sh drives all five profiles and files every report under verification/evidence/P10/<profile>/. CAUTION: the constrained clock is not automatically the clock the board delivers — loading an application overlay that names only a firmware file can leave the PS clock register at its boot default (measured 2026-08-08: 100 MHz instead of the constrained 75 MHz), which is a property of the loading mechanism, not of the encoder, but has to be set explicitly by an integration. The current per-profile figures, tool version and artefact paths belong to the footprint-profiles chapter (D6), not here, to avoid a second, drifting copy of the same numbers.

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29.11. Reference-stream families and supersession

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Byte-identity gates compare emitted streams against a pinned family of reference md5 hashes (the REF_FINAL family), minted by scripts/r2_final_mint.sh. A family is re-minted only when the byte delta against the previous family is provably explained: the delta must be localized to a specific message-dump difference, a build with the causing feature compiled back out must reproduce the previous family md5-exactly, and the superseded hashes stay in the mint log as documentation rather than being discarded. Wire-neutral RTL work therefore never touches the family; a deliberate wire evolution (for example, a CAPS-map extension for a new config-message bit) produces exactly one documented supersession, with the byte-neutrality cross-check as the proof. A family is selected by matching the build’s own CAPS word, not inherited positionally — scripts/ref_family.py select computes the word a build’s CT_EN_* switches produce and picks the archived family with that word (newest mint stamp wins among same-word candidates); a build whose CAPS word matches no archived family is a hard error rather than a silent mismatch.

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29.12. CI stages

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Since 2026-08-21 the public continuous integration runs as GitHub Actions on hosted runners, in two workflows. .github/workflows/ci.yml carries five jobs — Lint + static guards (make lint: the drift guards plus Verible over the RTL and tests), Publication guards (make check-publication: the six checks that decide whether the tree is fit to be published), Dashboard self-tests, REUSE / SPDX compliance, and Simulation (Verilator) (make sim and make sim-examples, with the decode verdict when the pinned decoder is reachable). .github/workflows/formal.yml runs the SymbiYosys property gates through scripts/run_formal.sh on a licence-free toolchain: a fast subset per pull request, the full set nightly (RED=1 additionally runs the red counter-proofs against the pre-fix worktrees). Stage nomenclature and the lab-runner stage of earlier revisions are gone with the ci/ directory they lived in.

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What a hosted runner cannot do is stated in the repository rather than left to the reader (CONTRIBUTING.md): the gate battery scripts/run_gates.sh — 51 gates named in scripts/gates.list — needs Vivado™ XSIM, hardware verdicts need a real KV260 board, and the decode verdict needs the pinned CTTD reference decoder. make sim is the simulator-agnostic subset that CI does run.

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Caution
+		 +The 51 gates of that battery and the 62 system-level testbenches of Chapter 30 count different things and must not be added or compared. The testbench count is the number of scenario directories under tests/; the gate count is the number of runs the battery drives, several of which exercise one scenario in more than one configuration, and some of which are not scenario runs at all. +
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Stage 1 carries eight host guards, six of them drift guards over the register map, the profiles and the harness. The other two guard the evidence itself, because the same two findings recurred in every package audit of this campaign: scripts/check_doc_evidence.py requires every documentation table cell quoting LUTs, flip-flops or block RAM to name an existing .rpt file under verification/evidence/ and matches the cell value against that report (twice, a cost table pointed into gitignored bld/, which the next run silently overwrote with a different configuration); scripts/check_evidence_stamp.py requires every verdict under verification/evidence/ to carry a # HEAD stamp naming a commit in the branch’s history, or an explicit # superseded-by pointer — five logs were once stamped with a rebased-away commit and nothing had shown it.

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A gate reports SKIP when an input it needs is not present in the repository and TOOL when the toolchain or build tree could not be established; neither reads as a property failure.

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30. Test Catalog

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This chapter catalogs every high-level testbench under tests/ as of this writing: 39 instruction-trace scenarios, 6 data-trace scenarios, 1 hardware-supported-instrumentation scenario, 15 overflow/robustness scenarios and 1 combined end-to-end scenario — 62 system-level testbenches in total, plus the shared verification infrastructure under tests/lib/ (cpu_model, ct_env, decoder wrappers) that every one of them uses. This supersedes any "Tests 06-20" framing: the suite has grown well past that range, and several of the newest scenarios (Sections Section 30.4, Section 30.6) exist specifically to close gaps the 06-20 generation did not cover.

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Every scenario follows the pattern in Chapter 29: a cpu_model-scripted stimulus is both driven into the encoder and logged as the oracle; a CLI wrapper script (scripts/cli_<name>_test.sh, or scripts/decode_and_check.sh directly for the plainer scenarios) builds the testbench, runs it, decodes the captured ATB stream with CTTD and diffs the result against the oracle. Per-module unit testbenches (rtl/<module>/test/) are out of scope for this chapter; per tests/README.md they are not part of the system/integration suite cataloged here.

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30.1. Basic control-flow and exception semantics

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TestStimulusVerification principle and gate

instruction/01_basic

Linear execution, taken/not-taken conditional branches, a call/return pair.

Smoke gate for the instruction-trace path. make sim-basic; CTTD --pc round-trip plus the trace-off correlation message (TCODE 33).

instruction/02_interrupts

Single interrupt with mret, exception with mret, nested interrupts, back-to-back interrupts, exception followed by an interrupt.

make sim-interrupts; PC round-trip across every interrupt/exception shape named in tests/README.md.

instruction/03_stress

A scheduler-style dispatch loop that builds and overflows branch HIST, mirroring a pattern observed on real customer workloads that made the stream undecodable.

Regression gate for a fixed encoder bug: on a HIST overflow the encoder must not zero its instruction-count accumulator, because inferable/linear instructions do not all carry a HIST bit. make sim-stress; PC round-trip.

instruction/04_periodic_sync

Periodic sync firing while the encoder’s HIST register still holds pending branch-direction bits.

Regression gate for cf_sync_hist_flush_hold (rtl/ct_L2_msg_gen.sv): a periodic ProgTraceSync (TCODE 9, no HIST field) must be preceded by a HIST pre-flush ResourceFull, or the decoder desyncs from FADDR. make sim-periodic-sync; PC round-trip.

instruction/05_exceptions

Illegal-instruction trap where the faulting instruction never retires (iretire=0), a co-reported exception for contrast, and the same never-retired trap right after a taken branch.

make sim-exceptions; PC round-trip, exercising the EXCEPTION_TRAP branch the 02_interrupts group (iretire=1) does not reach.

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30.2. Compression suite

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TestStimulusVerification principle and gate

instruction/06_implicit_return

A long loop of call/return pairs (plus branches and nested calls) with periodic instruction sync, so a large number of predicted returns are folded.

With InstEnImplicitReturn set, a predicted return is folded like an inferable branch; the decoder recovers the target from its own call stack. Byte-identity leg scripts/cli_ir_test.sh: OFF prefix equals reference, ON decodes to the same PCs at a strictly smaller byte count.

instruction/07_repeated_history

A tight all-taken counting loop (uniform HIST patterns) plus segments designed to miss the exact-match detector.

With InstEnRepeatedHistory set, an exact repeat of a full HIST pattern is counted instead of re-sent (ResourceFull RCODE=2). Byte-identity leg scripts/cli_rh_test.sh.

instruction/08_repeat_branch

A tight uninferable-jump dispatch loop producing byte-identical IndirectBranchHist messages lap after lap, ending on a coda that forces the drain path.

With InstEnRepeatBranch set, an IBH identical to the last emitted one is suppressed and counted, closed by RepeatBranch (TCODE 30). Byte-identity leg scripts/cli_rb_test.sh.

instruction/09_jtc

An indirect dispatch cycle over three far-apart code blocks — the case where a differential UADDR is expensive and a cache-index hit wins.

With InstEnJumpTargetCache set, a cache-hit plain IBH goes out as VendorJTC (TCODE 57, 6-bit index) instead of a differential address; first lap misses (installs), later laps hit. Byte-identity leg scripts/cli_jtc_test.sh.

instruction/10_branch_predict

A trained counting loop (best case for the predictor) plus a cold-start/mispredict segment.

With InstEnBranchPrediction set, encoder and decoder run bit-identical 2^9x2-bit predictors; only a mispredict emits VendorBP (TCODE 56). Byte-identity leg scripts/cli_bp_test.sh.

instruction/13_ibhs

A short periodic-sync window so syncs repeatedly fire with pending HIST bits.

With CT_EN_IBHS set, IndirectBranchHistorySync (TCODE 29) carries the pending history directly instead of a pre-flush pair. scripts/cli_ibhs_test.sh; both OFF and ON legs PC-lossless.

instruction/14_repeat_instr

A single-instruction spin loop (60 iterations) inside a short periodic-sync window, so syncs repeatedly land on the loop branch.

With InstEnRepeatInstr set (TCODE 31/32, reserved in ratified N-Trace 1.0, hence reset 0), spin-loop iterations after the first are counted rather than resent. scripts/cli_rpti_test.sh.

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30.3. Robustness, status and register features

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TestStimulusVerification principle and gate

instruction/11_robustness

One rich control-flow workload run under four CSR configurations from the same binary: compression off, HIST-family stack, BP-family stack, and a deliberate misprogramming (+ROBUST_ALL, all six compression bits) that must be byte-identical to the BP-family leg because BP hardware-excludes RH/RB.

scripts/cli_robust_test.sh; every leg PC-lossless, plus a negative gate (a BP stream decoded without -bp must fail hard).

instruction/12_debug_power_events

Debug entry with pending branch history, debug exit, an EVTI pulse while tracing.

Regression gate for CT_EN_DEBUG_EVENTS/CT_EN_POWER_EVENTS/CT_EN_EVTI: Correlation EVCODE 0 on debug entry (residual ICNT + pending HIST), SYNC=3 (not 5) on the very first post-debug retire, SYNC=0 upgrade on an EVTI pulse. scripts/cli_dbg_test.sh.

instruction/15_trig_seq_own

One workload, four CSR legs: reset defaults, +InstTrigEnable, +InstSeqSyncEnable, +Context.

Trigger-Sync (SYNC=6), Seq-Sync (SYNC=4, a documented Accemic extension — N-Trace binds SYNC=4 to BTM) and Ownership (TCODE 2) against one identical PC reference per leg. scripts/cli_tso_test.sh. Also the gate for the TIP context-width build knob (ct_pkg::CT_CONTEXT_WIDTH), rebuilt in a detached worktree per width and checked for the predicted PROCESS value (scripts/cli_ctxwidth_test.sh); red counter-proof narrows the composer’s context cast back to [1:0].

instruction/16_config_msg

One branch-rich workload, five CSR legs: SendConfig=CFG_NONE/CFG_ONCE/CFG_ON_SYNC, plus a BP leg decoded via CTTD autoconfig and its negative control.

Vendor config message (TCODE 58): none/exactly-one-as-message-0/one-per-sync placement; and "flagless decode == flagged decode" via ENAB.5 autoconfig. scripts/cli_cfg_test.sh, 12/12 gates.

instruction/17_btm

One branch-rich workload, two CSR legs: HTM (InstMode=6, reset default) and BTM (InstMode=3).

Proves both N-Trace 1.0 instruction-trace modes (Table 8, "3 or 6 settable") against the same cpu_model reference. scripts/cli_btm_test.sh.

instruction/18_fifo_histogram

Dense periodic syncs, Ownership and config messages under a serialized 1-slot/cycle drain to pressure the eTIP CVS FIFO, then a quiescent read of the 16 histogram bins.

CT_FIFO_HIST_BINS diagnostic CSRs (trTeTipFifoHist0..7): at least one nonzero bin, HistClear zeroes all bins, a second run re-arms. scripts/cli_fifohist_test.sh; stream PC-losslessness checked as usual.

instruction/19_feature_matrix

A sequence of short configuration phases over a linear workload: comparator P-function sweep, input mux (CONTEXT/TVAL/DADDR), S-function sweep plus MODE1 latch, filter chain, performance-counter thresholds, DF range memory, timestamp prescale and core source, SRC field, external sync sources, and (phase 10) ACT-ST watchpoint hits.

The comparator/filter/perfcnt/timestamp/sync configuration CSRs are Enable-locked, so every phase configures inside an off-tracing window with drain idles at the transitions. scripts/cli_featurematrix_test.sh. This is the test that closed the largest coverage-gap classes in ct_L23_preproc_comp_filters and act_proc/act_st (see Chapter 31).

instruction/31_status_msgs

One workload, seven CSR legs covering Device ID (TCODE 1) and Watchpoint (TCODE 15) status messages, including a WARL negative control (illegal SendDeviceId encoding).

Both message types are PC-neutral (no ICNT, no address reference). Contract DO-1: Device ID, when sent, is message #0 — before the config message and before the first synchronizing message. scripts/cli_status_test.sh.

instruction/32_trig_regs

One workload, six CSR legs covering the TCI trigger configuration registers (trTeTrigExtInControl at 0x050/0x054/0x058), including the historical InstTrigEnable path for contrast.

CTTE owns exactly one external trigger input; every other TCI trigger field reads back the read-only 0 the spec prescribes for a trigger that does not exist. scripts/cli_trigregs_test.sh.

instruction/33_te_sync_req

One workload per scenario: no request, one write, two back-to-back writes, three back-to-back writes, a request during an active byte quota, a request during an overflow storm, a request colliding with an ACT-CAP CF_SYNC on the same retire.

trTeControl.InstSyncReq (bit 27): one write → one SYNC=14 message, queue depth of one in flight plus one remembered (two writes → two messages, three → still two), SyncReqSource=4 read back, no message when nothing was requested. scripts/cli_tesyncreq_test.sh.

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30.4. Sync cadence, ICNT and wide-field edge cases

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TestStimulusVerification principle and gate

instruction/20_icnt_overflow

One long straight-line block (longer than the 255-halfword narrow ICNT cap), three CSR legs: default HTM, +BTMLEG (BTM), and the wide-ICNT variant.

Closes coverage-worklist item T1 (no other test exercised the ResourceFull(ICNT_OVERFLOW) drain family before this test existed). scripts/cli_i20_test.sh.

instruction/29_sync_quota_bytes

Alternating compressibility: a long compressible linear run, then a jump-dense incompressible run, against InstSyncMode=TRACE_BYTES.

The trace-output byte quota bounds re-anchor distance by emitted bytes (2^(Max+4)), independent of workload compressibility — unlike an instruction-count sync, whose byte distance varies with how compressible the code is. scripts/cli_syncquota_test.sh.

instruction/30_sync_quota_msgs

The message quota (InstSyncMode=TRACE_MSG, every 16 messages) exercised together with an ACT-CAP CF_SYNC command and an ATB sync-request pulse, per collision design D8.

Message quota counts on-wire EOM boundaries; the collision legs prove the quota does not double up with the other two explicit sync sources. scripts/cli_syncquota_test.sh.

instruction/35_addr64

Deliberately plain control flow; what matters is the base PC (0x0000_1000 at CT_XLEN=32 vs. 0xFFFF_FFC0_0000_1000 — above 2^32, with a plausible-looking low half — at CT_XLEN=64).

The verdict is read off the raw ATB bytes (scripts/check_addr64_emission.py reconstructs PC_FADDR from the MDO nibbles), never from a decoder — per Section 29.2, a gate that can only fail together with its own tool judges nothing, and the reference decoder had no 64-bit support when this gate was written. scripts/cli_addr64_test.sh.

instruction/36_block_tip

One instruction sequence written once, driven two ways in the same block build: one instruction per TIP beat (+SERIAL), or blocks of 1-4 instructions per beat terminated by every retire kind.

CT_EN_BLOCK_TIP (R1.3): packaging changes, reconstructed control flow does not. Both legs log a per-instruction oracle and must decode to it exactly; anti-vacuity witness measured at tip_if (76 halfwords in 14 beats vs. 38 beats, largest beat 8 halfwords). Four red counter-proofs (MUT=M1..M4). scripts/cli_blocktip_test.sh; byte-neutrality of the default (off) build via scripts/r13_off_neutrality.sh (31 of 31 reference artefacts identical).

instruction/38_core_xlen

Three legs: a DECLARED_XLEN matching the netlist’s ct_pkg::CT_XLEN (accept), a mismatch, and an undeclared (0) value.

Elaboration guards genCoreXlenMismatch/genCoreXlenUndeclared (see Chapter 5) must reject the latter two. scripts/cli_corexlen_test.sh.

instruction/37_sync_cadence

A 100,010-retire, 15 %-control-flow-density scenario against a finite-bandwidth sink (one accepted ATB beat per 10 cycles = 40 MB/s — an always-ready sink cannot pose this question at all). The positive leg deliberately does not program InstSyncMax (flies the reset value); the counter-proof leg forces +SYNCMAX=0 (minimum period).

Reset-value regression gate (P0-02): zero Error messages and a strictly lossless decode (100,008 of 100,008 PCs) at the shipped reset, versus 790 Error messages and 5,064 dropped events at the old reset (InstSyncMax=0) under the same finite sink. The cadence is read back off the wire (config-message P1[12] bits [10:7]) and cross-checked against both the RDL declaration and the generated RTL reset — a three-way agreement no source read alone could establish. scripts/cli_synccadence_test.sh.

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30.5. Multi-source separation

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One scenario stands apart from the groups above because it is the only unit-level testbench that runs two encoders at once.

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TestStimulusVerification principle and gate

instruction/39_dual_src

Two encoder instances with different trTeInstFeatures.SrcID at SrcBits = 2 — the width every multi-core demonstrator uses — pushing into one ct_L1_funnel from a single fork. The two sources deliberately run different programs at disjoint address ranges (base 0x0000_7000 and 0x2000_0000).

Separation is shown, not asserted. Seven legs: the merged stream is well formed (0 error messages); both SRC values appear and each source’s config message carries its own {SrcID, SrcBits}; the funnel actually interleaved (a floor on source changes between consecutive messages); each half of the merged stream decodes to the reference PC sequence of its own source; decoding one source against the other source’s PCInfo must fail (falsifiability); merge-then-split is byte-lossless against what each encoder produced alone; and the multi-target command line the board gates use (-target 0 … -target 1 …) yields both sequences. scripts/cli_dualsrc_test.sh.

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Why the disjoint programs matter is worth stating, because it is the reason the scenario exists at all: in a capture where both sources run the same image at the same addresses, a decoder that evaluates SRC perfectly and one that ignores it produce identical output, so such a capture can neither confirm nor refute separation. Before this scenario the only evidence for source separation was a whole-SoC demonstrator, where a failure has a dozen possible causes.

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30.6. E-Trace and protocol-parameter legs

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All of the following are driven by one shared runner, scripts/cli_etrace_test.sh <leg>, unless noted otherwise.

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TestStimulusVerification principle and gate

instruction/21_etrace_ir (leg ir)

Nested calls with stack-predicted returns, a branch pair and an uninferable jump, ending with a clean trace-off (Enable=0 → correlation beat), unlike the 06_implicit_return donor scenario.

CT_EN_ETRACE implicit-return mode: OFF and ON from one build, both PC-lossless, ON strictly smaller.

instruction/22_etrace_f1n_trap

An async interrupt with icnt==0 directly after branch #31 of a full Format-1 branch map, and the same a few linear instructions later; all branches not-taken for a trivially checkable PC path.

Regression guard for the "trap right after a full 31-bit branch map" corner, where the decoder’s position after a Format-1-without-address packet is the 31st branch, not the last address-packet target.

instruction/23_etrace_resync

Linear stretches, branches, a call/return pair and an uninferable jump, with a small periodic-sync window firing several times mid-trace.

Composer periodic syncs must re-anchor via deferred Format 3.0 packets rather than being dropped; the cli leg requires >= 2 mid-trace F3.0 anchors. See the honesty note in Section 29.6 — this leg’s original 2026-07 claim was narrower than three defects the P10 soak campaign later found; those are closed by 34_etrace_resync_ir below.

instruction/24_protocol_param (leg mixed)

Two ct_encoder instances elaborated side by side from the same sources, one N-Trace, one E-Trace, each with its own Wishbone CSR port.

Proves the P9 per-instance protocol parameter: each instance reports its own atb_te_raw framing and trTeProtocolSel.Protocol/trTeImpl.ProtocolMajor discovery, and a write to the discovery register has no effect (read-only).

instruction/25_etrace_jtc (leg jtc)

A fixed dispatcher round executed three times; round 1 installs five jump targets, rounds 2-3 hit the 64-entry cache.

InstEnJumpTargetCache on the E-Trace back end: OFF/ON from one build, both lossless, ON smaller, >= 2 Format-0.1 packets.

instruction/26_etrace_bp (leg bp)

An 80-iteration self-loop with a highly predictable taken branch.

InstEnBranchPrediction on the E-Trace back end: first map fill goes out as Format 1 (initial mispredicts), the second fill switches to COUNT mode (no packet), the loop exit closes as Format 0.0. OFF/ON both lossless, ON smaller, >= 1 F0.0 packet.

instruction/27_etrace_df (leg df)

Branches interleaved with loads/stores of all four sizes, aligned and unaligned, with values exercising the data_len sign strip.

te_data packets (msg_type 3) checked byte-exact via etrace_data_check.py, with the interleaved PC trace staying lossless.

instruction/28_etrace_daq (leg daq)

The deterministic DAQ commands (DIRECT_DATA, DATA, DADDR, DATA_DADDR, PC_CURR) via ACT-CAP, routed to the Nexus sink.

Byte-exact vendor packet content (idtag + three 64-bit elements) via etrace_data_check.py --daq; interleaved PC trace stays lossless.

instruction/34_etrace_resync_ir (leg resyncir)

A braid of far-call/return and call-to-next-address/double-return shapes under a tight periodic sync window, implicit return off and on, both with >= 3 mid-trace F3.0 anchors.

Regression guard for the P10 soak findings S-1/S-2 (pre-existing E-Trace defects, since closed): a periodic sync anchoring on a predicted-return retire must stay folded, and a target report whose address is also linearly reachable must carry the updiscon flag. Red counter-proof: on the pre-fix tree the implicit-return-OFF half already fails (prefix mismatch, 332/336).

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One class remains open by wire-format necessity rather than by test coverage: with irdepth field width 0, an implicit-return-folded loop crossing a positional binding point cannot express its visit count (measured 6/33 red among implicit-return-armed runs of a free-axis calibration, seed 20260806). The implicit-return bit is masked from the E-Trace soak campaign until an irdepth field exists; see Chapter 33.

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30.7. Data trace

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TestStimulusVerification principle and gate

data/01_basic

Loads and stores at every supported size (byte/halfword/word/doubleword) interleaved with short linear runs, data trace only (instruction trace off).

make sim-data-basic; the encoder must emit DataRead/DataWrite messages independent of the instruction-trace path.

data/02_split_load

The SPLIT_DATA_ACCESS=1 elaboration leg: stores emit their DF at dretire, loads capture the filter hit at dretire and emit at lresp; an overwritten pending load is deliberately never traced.

scripts/decode_and_check.sh --pc --data split_load_tb; the --data oracle encodes the split-load pending-slot contract explicitly (the TB marks the overwritten access untraced).

data/03_addr_compress

WARL probes of the unimplemented DIFF/XOR_DIFF modes (must legalize to FULL), block accesses (small XOR deltas), scatter accesses (large deltas, byte granularity), and a DataTracing=0 window with accesses inside (negative gate).

CT_EN_DF_ADDR_COMPRESS with trTeDataAddrCompress=XOR — the only implemented mode (E-P3-2). scripts/cli_dfcompress_test.sh.

data/04_data_sync

A combined instruction+data stream: a clean baseline, an ATB stall plus a jump-indirect storm with interleaved data accesses that trips a QueueOverrun, then release and drain.

Re-anchor contract T2: every synchronizing CF message and every emitted ERROR re-arms the DF re-anchor (first post-event data message must carry a full address, TCODE 13/14). scripts/cli_dfcompress_test.sh.

data/05_df_workload

The same access sequence driven twice: FULL-mode (uncompressed) and XOR-compressed addressing.

P3 DF-bandwidth workload; scripts/cli_dfworkload_test.sh.

data/06_df_drop

One stimulus, two legs differing only in trTeDataControl.DataDropEna: without it, a stalled-ATB burst overflows the eTIP queue and drops instruction trace with it; with it, the drop watermark sheds data-trace messages first and instruction trace stays lossless.

Status-bit contract (G12, RW1C, checked in-sim since it is not wire-observable): InstStallOrOverflow / DataDrop set correctly per leg. scripts/cli_dfdrop_test.sh.

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30.8. Hardware-supported instrumentation

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TestStimulusVerification principle and gate

hsi/01_csr_cap

Every ACT-CAP command issued as a functional NOP CSR write (RISC-V CSR 0x0B10): all DAQ_* commands routed to both the AXIS and Nexus sinks, plus ACT_CAP_ST_CF_SYNC routed to the Nexus sink only.

make sim-hsi-csr-cap; AXIS beat self-check (TID = command) plus CTXP DAQ record reconstruction on the Nexus side. The AXIS-only variant (element-2 compiled out) is the scripts/cli_axists_test.sh leg of the same testbench.

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30.9. Overflow and robustness (cross-cutting)

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Every scenario in this group was written from a defect first observed on real hardware (KV260 soak/robustness campaigns), and each carries a documented red counter-proof — see Section 29.6 for why this many scenarios exist for what is structurally one contract (state re-convergence across a stream discontinuity).

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+ +++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
TestStimulusVerification principle and gate

overflow/01_overrun_recovery

Instruction and data tracing both on; clean baseline, then an ATB stall plus dense CF storm that saturates the composer’s CDC FIFOs, then release and recovery.

Full overrun lifecycle — inject, resync, soft-reset recovery. make sim-overrun-recovery; official gates: --overflow (3 ERROR`s), `--disabled correlations, decode to stream end, data 7/7, byte-neutral REF.

overflow/02_natural_overflow

Two 700-jump storm bursts of back-to-back uninferable jumps (disjoint fresh targets) separated by a calm phase, at the MicroBlaze™ V KV260 equal-clock regime (no forced injector).

Reproducer for a natural (non-injected) overflow regime the injector-forced tests never enter. scripts/cli_natovf_test.sh.

overflow/03_jtc_overflow

A ring of repeating jump targets (not all-fresh) with JTC enabled, so cache hits occur whose install may lie inside a drop window.

Regression guard: after a FIFO_OVERRUN recovery, the encoder must not reference a JTC entry the decoder never saw installed. scripts/cli_jtcovf_test.sh.

overflow/04_ir_overflow

Calls and returns inside a natural-overflow discard window, structured like 03_jtc_overflow.

Regression guard: the encoder’s implicit-return stack must be cleared at the FIFO_OVERRUN recovery anchor (ret_sp clear in ct_L23_preproc_composer_etip), or a stale frame desyncs the decoder’s own call stack. scripts/cli_irovf_test.sh.

overflow/05_bp_hwsync

A dense branch-heavy jalr ring with branch prediction and half-word periodic sync, no storm and no stall; iteration length coprime to the sync period so every phase offset is hit.

Isolates a sync-boundary attribution defect (a branch retiring in the same beat as a periodic-sync emission) without any overflow in the picture. scripts/cli_bphws_test.sh.

overflow/06_suite_isync

A trained counting loop plus an indirect jalr ring, full compression suite plus periodic sync, no overflow.

Reproducer for a defect the single-factor legs (BP alone, BP + IRQ, 05_bp_hwsync) do not reach — it takes the full suite combination. scripts/cli_suiteisync_test.sh.

overflow/07_board_replay

The exact instruction sequence of a hardware run (auto-generated oracle via scripts/gen_replay.py) replayed with the exact hardware configuration.

Bisects the encoder core against the adapter path: if the replay reproduces a hardware-observed defect, it is in the core (fixable in sim); if it stays clean, the defect is adapter-specific. scripts/cli_boardreplay_test.sh.

overflow/08_bp_syncbranch

A four-instruction loop under a 16-instruction sync period (a multiple of the loop length), all four phase alignments run, branch prediction on.

Forces the collision fingerprint identified from a hardware-vs-replay message diff (a sync-carried branch, IBHS with HIST=2) that the 07_board_replay phase alignment never happened to hit. scripts/cli_bpsyncbr_test.sh.

overflow/09_bp_ovfanchor

Periodic sync off, overflow active, branch prediction on — the recovery-anchor variant of the same state family.

Regression guard: a FIFO_OVERRUN anchor must not land on a not-taken-branch retire without being held, since that retire is not itself a control-flow change but still owns an outcome bit. scripts/cli_bpovfanchor_test.sh.

overflow/10_replay_ovf

A 30,000-instruction oracle prefix (from scripts/gen_replay.py) with real predictor training (one branch taken 14,376 times), natural overflows forced by ATB throttling.

Adds real branch-outcome history to the 09_bp_ovfanchor class — exactly the ingredient behind the hardware-observed VendorBP BCNT misattribution after FIFO_OVERRUN anchors. scripts/cli_replayovf_test.sh.

overflow/11_pause_edge

InstTracing toggled off and on asynchronously, phase-swept, in the middle of a CF-dense retire stream.

Regression guard for a defect with no overflow involved: a live-sampled trace-active qualifier could lose or misplace up to max_delay instructions at the pause edges. scripts/cli_pausedge_test.sh.

overflow/12_trap_anchor

An indirect call ring (ATB-throttled, hundreds of natural recoveries) where every fourth iteration traps synchronously (no-retire ecall, handler, mret).

Third case of the recovery-anchor assumption, after CF and not-taken-branch: an anchor must not land on a trapping instruction that never retires. scripts/cli_trapanchor_test.sh.

overflow/13_jtc_stopdrain

JTC-only configuration, a call ring with a constant return target, dense periodic sync, ATB throttle (backpressure plus natural overflows), InstTracing lowered on a running core.

Regression guard for message-ordering-under-backpressure at the stop drain: a VendorJTC message must not overtake a later sync in the stream. scripts/cli_jtcstopdrain_test.sh.

overflow/14_ovf_window

Cross-term stress: trace-window edges combined with FIFO overflow, branch prediction / JTC and dense periodic sync.

Guards two hardware-found ICNT-accounting defects at emission-cycle collisions between the overflow injector and the drain chains. scripts/cli_ovfwindow_test.sh.

overflow/15_flush_clobber

ATB flush pulses in the middle of a dense JTC stream under backpressure.

Regression guard for a message-granular silent loss: a trailing if (FlushRequest) send_flush_msg() could overwrite a just-composed message when a flush service cycle collided with a consume_etip beat. scripts/cli_flushclobber_test.sh.

+
+
+

30.10. Combined end-to-end

+ +++++ + + + + + + + + + + + + + + +
TestStimulusVerification principle and gate

combined/01_all

Linear code, a taken branch, a call/return pair, varied-size loads and stores interleaved with the code, and one ACT_CAP_ST_CF_SYNC issued mid-stream via the ACT-CAP CSR.

Instruction, data and ACT-CAP paths run together to catch cross-feature interactions the per-feature tests miss in isolation. Three checks on one capture, all from the single decode driver: scripts/decode_and_check.sh (PC stream), the same script with --data (DataRead/DataWrite) and with --sync 3 (at least three synchronization messages). NOTE: with both instruction and data tracing on, data-trace messages flush ahead of buffered instruction messages, so record order is not program order — this scenario checks --data, not --ctxp (see Chapter 29).

+
+
+
+
+

31. Coverage Evidence

+
+
+

The line-coverage evidence for CTTE is a single measured figure: 93.42 % measured (4,972 of 5,322 product-RTL lines) and 100.00 % effective (4,972 of 4,972) line coverage, Verilator 5.040, full-profile build with both the N-Trace and the E-Trace back end compiled in, measured 2026-07-25 (Round 5, the first round to measure both protocols together) and recorded in an internal measurement report outside the published tree (Section 31.7). Three qualifications belong to that sentence as much as the number does, and all three are stated in full further down this chapter rather than left implicit: the recording location is outside this repository’s version control (Section 31.7); the figure predates a later RTL change that removed measured lines (Section 31.8); and the effective half can no longer be recomputed from the published tree at all, because the tools that computed it were removed on 2026-08-24 (Section 31.5).

+
+
+

31.1. Measured vs. effective, and what closes the gap between them

+
+

"Measured" is the raw Verilator line-coverage rate over rtl/ (excluding test infrastructure under rtl/external/’s simulation-only tasks, which are covered separately). It is a union metric: `scripts/coverage_report.sh merges every testbench’s coverage_*.dat with verilator_coverage --write-info, and a line counts as covered if any test in the suite hit it — it is not an average of per-test rates (individual testbench rates run 44-50 %, which is expected and not a suite-quality figure in itself).

+
+
+

"Effective" is measured coverage with every line that carries an ACCEPTED waiver excluded from the denominator. The waiver mechanism (a triage tool and its waiver ledger; neither has ever been part of the published tree, and the tool was removed on 2026-08-24 — see Section 31.5 and Section 31.7) auto-classifies two trivial shapes on its own — $stop/$fatal/$error guard paths whose correctness criterion is non-firing, and empty default: arms of an otherwise-exhaustive case — and seeds every other uncovered line as a candidate that a human must disposition with a file/line anchor, a rationale and a source citation. A line reaches "effective 100 %" only when every one of its uncovered siblings is either one of the two auto-trivial shapes or has an ACCEPTED waiver; there is no third way to make a line stop counting.

+
+
+
+

31.2. The waiver ledger

+
+

The waiver ledger held 68 entries at Round 5 (2026-07-25):

+
+ ++++ + + + + + + + + + + + + + + + + + + + + +
StatusCount

ACCEPTED

57

REJECTED

8

PROPOSED

3

+
+

A REJECTED entry is not a residual gap: all eight are auto-rule duplicate findings on lines a different, ACCEPTED waiver already covers (e.g. AUTO-0017/AUTO-0018 on rtl/external/stream/sink_if.sv/source_if.sv, superseded by the ACCEPTED W-0004/W-0005) or a structural-arm finding retired because a later edit moved the line (AUTO-0031). They are kept in the store as an audit trail of what the auto-rule found, not because they exclude anything themselves.

+
+
+

A PROPOSED entry is the opposite: a completely uncovered function or task, auto-flagged as "unused convenience OR missing test — review required" and not yet dispositioned. Three remain PROPOSED in the Round-5 store — AUTO-0014 (send_icnt_overflow_msg, rtl/ct_L2_msg_gen.sv), AUTO-0027 (unpack_act_st_cmd, rtl/preproc/ct_L23_preproc_act_st.sv) and AUTO-0029 (set_match_next, rtl/preproc/ct_L23_preproc_comp_filters.sv) — and are not folded into either the "effective 100 %" figure or the internal gap worklist’s "0 real residual gaps" statement; see the BEFUND at the end of this chapter for why that statement and the open PROPOSED entries do not currently agree.

+
+
+

By waiver type (all 68 entries of the Round-5 ledger):

+
+ ++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
TypeCount

STRUCTURAL_ARM

14

UNUSED_CODE

12

DEFENSIVE_UNREACHABLE

11

CARRYOVER_P3

7

ELAB_DEAD

4

CARRYOVER_P2

4

UNUSED_CONVENIENCE_OR_GUARD

3

CONFIG_DEAD

3

DIAGNOSTIC

3

NEVER_FIRE_GUARD

2

TEST_INFRA, GENERATED_CODE, TOOL_ATTRIBUTION, UNREACHABLE_INTEGRATION, UNREACHABLE_SIM

1 each

+
+

Representative dispositions: rtl/external/wishbone/wb_package.sv (W-0001, TEST_INFRA) is Wishbone simulation tooling, not product RTL; rtl/external/common/counter.sv (W-0002, ELAB_DEAD) carries generic-IP MODE arms this design never instantiates; the sink_if/source_if/cvsink_if have_available functions (DEFENSIVE_UNREACHABLE) are error detectors whose non-firing is the correctness criterion — a hit would itself be a test failure; ct_cs_cpuif.sv, the PeakRDL register-block generate, carries uncovered read/write-decode arms for rarely-touched CSRs, dispositioned as "generator correctness, not hand-written logic" with the CSR-contract-relevant fields covered separately by the hsi/csr_cap WARL tests.

+
+
+
+

31.3. Gap-closure history

+ ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
RoundDateScopemeasured / effective

1-2

2026-07-21 (morning)

OFF-legs only, then + ON-leg pass (scripts/coverage_on_legs.sh)

79.65 % / — then 84.67 % / — 

3-4

2026-07-21

+ Tests 19/20, split-load leg, 6 new ON-legs, one RTL bugfix (below)

93.17 % / 99.34 % (26 residual lines, 5 clusters)

5

2026-07-25

+ E-Trace and DUAL profiles measured together, four new coverage phases, one RTL bugfix (below)

93.42 % / 100.00 % (0 residual lines against the store as it stood that day)

+
+

Round 3-4’s largest single cause was methodological, not a test deficiency: the OFF-only union under-measured ct_L2_msg_gen (52.25 % → 77.50 % once ON-legs ran), ct_L2_nexus_formatter (70.10 % → 98.97 %) and ct_L23_preproc_composer_etip (93.50 % → 95.07 %), because the feature testbenches existed and ran, but only their OFF leg was part of the merged .dat set. scripts/coverage_on_legs.sh is now a fixed part of every coverage run for exactly this reason.

+
+
+

Round 5 closed 103 fresh residual-gap lines from that round’s first pass: 57 through new test stimulus (four plusarg-gated coverage phases on existing E-Trace testbenches — +BPX, +JTCX, +ANCHORJUMP, +TH0, plus natural_ovf_tb run under the E-profile) and 46 through waivers (21 new: 11 diagnostic-instrumentation lines gated behind +TE_BEAT_DUMP/+TE_PKT_DUMP plusargs, W-0122-W-0124, and a BpCount saturation arm at 2^32-1 correct predictions, W-0125, UNREACHABLE_SIM; 25 carryover dispositions of the Round-4 clusters below).

+
+
+
+

31.4. Residual carryover clusters from Round 3-4, dispositioned in Round 5

+ +++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Cluster (Round-4 residual)LinesRound-5 disposition

bit_slicer_impl field-combination edge arms

15

W-0126-W-0129, CARRYOVER_P2: reachable only by dedicated field-list unit stimulus; the N-Trace system legs do not reach the edge lists.

composer_axis sink-routing else arms

5

W-0130-W-0134, CARRYOVER_P3: full sink-routing matrix; the Nexus-sink side is covered via the hsi/DAQ legs.

comp_filters MatchMode-INPUT edge arms

2

W-0135, CARRYOVER_P3, with a findings trail: comparator mechanics proven identical via the P-function formal target; the hierarchical interface probe needed to reach this arm directly crashes Verilator 5.040 (XSIM-wave clarification pending).

act_proc ACT_CAP_TE_DATA_TRACING arm

3

W-0136, CARRYOVER_P3: watchpoint stimulus exists (Test 19, phase 10) and reaches a hit, but not this specific arm; the structurally identical INSTR_TRACING twin is covered.

ct_cs_cpuif_wb single line

1

Covered by the Round-5 runs without a waiver.

+
+
+

31.5. Measurement mechanics

+
+

Reproduction (c-trace repo root):

+
+
+
+
1
+2
+3
+4
+
bash scripts/coverage_suite.sh          # OFF-legs, resumable, 900 s per-task timeout
+bash scripts/coverage_on_legs.sh        # feature ON-legs over the built Verilator executables
+bash scripts/coverage_etrace.sh         # E and (pre-P9) DUAL profiles, see the currency note below
+bash scripts/coverage_report.sh         # union merge -> bld/coverage/merged.info
+
+
+
+
+ + + + + +
+
Important
+		 +That sequence reproduces the measured rate only. The three tools that produced the per-module gap report, the HTML report and above all the waiver triage — scripts/coverage_gap_report.py, scripts/coverage_html_report.py and scripts/sv_cov_triage.py — were removed from the repository on 2026-08-24 (5ed46b6abb6, "Remove unused tools"). The removal was deliberate, and the repository says so in the same commit: the waiver ledger, the per-gap dispositions and the triage tooling that maintains them are not part of the published tree, so the effective rate cannot be recomputed from this repository. The 93.42 % measured half stays reproducible with the four scripts above; the 100.00 % effective half is a recorded measurement of 2026-07-25 and, with the tools in the tree today, is not. +
+
+
+

Measurement caveats recorded alongside the Round-5 figures and carried forward here because they qualify the headline number:

+
+
+
    +
  • +

    Two tools, two exclusion definitions. the triage tool computes effective coverage over auto-rules plus ACCEPTED waivers (350 excluded lines) and reports 100.00 %; the separately generated gcovr-style HTML report of that round excludes only the ACCEPTED waivers themselves (348 lines) and reports 99.96 % — a 2-line difference made up of auto-classified trivial lines that carry no store entry. Both numbers are correct for their own definition.

    +
    • +
  • +

    Profile-dependent generated file. rtl/pkg/ct_cs_cpuif.sv (the RDL register-block generate) has a different line count per build profile, which makes the gcovr tool print a line-count mismatch warning. This is annotation noise, not a biased measurement: the file’s rate is identical (1,884/2,038 = 92.44 %) in the default-only merge and in the combined merge — the profile variant adds no lines to the union.

    +
    • +
  • +

    Four suite tasks contribute no .dat. Three Verilator-discrepancy testbenches (funnel, formatter, formatter_err — 100 % green under XSIM, the reference gate; the Verilator failures are simulator-scheduling artefacts — TSTAMP/UADDR values arriving as 0, or a handshake timeout — not product defects) and ct_nexus_decoder_tb, which cannot build at all: tests/lib/ct_nexus_decoder.abc references ../../nexus/mseo2_decoder.sv, a path that exists in neither the vendored tree nor the upstream pin (verified 2026-07-21 by sparse-cloning the encoder repository — then still published under its retired name accemic/C-Trace, today accemic/TraceEncoder — at 3a74ea59: no nexus/ directory, no mseo2* file). None of the four are product RTL under test — the DUT modules of the three discrepancy testbenches are covered through the system testbenches instead, and the decoder testbench is verification infrastructure (tests/lib).

    +
    • +
+
+
+
+

31.6. RTL defects the coverage campaign found

+
+

Coverage-driven stimulus surfaced two RTL defects that no directed test had reached, both fixed with byte-neutrality evidence before the round closed:

+
+
+
    +
  • +

    Round 3-4: the wrapper mapping block ct_cs_cpuif_wb.sv did not map PInput/SInput — the CONTEXT/TVAL/DADDR comparator inputs were silently inert regardless of configuration. Two-line fix; byte-neutral (cli_ir_test.sh OVERALL PASS, md5-prefix gates green).

    +
    • +
  • +

    Round 5: the +ANCHORJUMP coverage phase tripped the pre-existing icnt-convention assertion. Root cause: when a FIFO-overrun recovery or trace-enable anchor lands on a control-flow instruction, that instruction’s half-words count into the following segment by composer convention (exclusive anchor), but NextAddr was set to the jump target instead of target minus anchor width — desynchronizing retirement tracking by one instruction width. Fixed in ct_L2_te_inst_gen.sv, commit 3e066b22; the full function matrix plus the N-Trace regression suite were re-run afterward.

    +
    • +
+
+
+
+

31.7. Provenance

+
+ + + + + +
+
Note
+		 +The coverage figures in this chapter are quoted with date, tool version and measurement scope, but the underlying report, gap worklist and waiver ledger are not currently version-controlled: docs/ is excluded by that repository’s .gitignore. There is no commit hash to cite for the 93.42 % / 100.00 % figures, and this chapter cannot be independently reproduced against a tagged state of the source repository until that is corrected. Once docs/COVERAGE_verilator.md, docs/COVERAGE_gaps_worklist.md and docs/coverage_waivers.json are brought under version control, this note is to be replaced by the commit hash of the versioned report; no other wording in this chapter needs to change. +
+
+
+
+

31.8. Currency

+
+

The 2026-07-25 figures were measured on the RTL as it stood before a later synthesis-parameter change (P9, 2026-08-04) removed the dual-protocol build of ct_encoder — roughly 135 lines, plus the associated etrace_dual_tb testbench and the DUAL coverage profile in scripts/coverage_etrace.sh. Both the numerator and the denominator of the headline figure move with that change, so the 93.42 % / 100.00 % pair is not line-for-line comparable to a measurement on the current tree, and doc/verification.adoc and doc/release-notes.adoc both say so explicitly: the coverage rate "has not been re-measured since P9 changed numerator and denominator." No later measurement exists in the repository at the time of writing. A fresh run of the reproduction sequence above is required before this figure can be cited as current rather than as last measured.

+
+
+
+
+
+

32. Implementation Status Matrix

+
+
+

This chapter gives a review-friendly, feature-by-feature view of what is implemented in the CTTE RTL, checked against the tree as of this writing. Unless stated otherwise: the RTL in rtl/ is authoritative; register semantics are authoritative per the SystemRDL sources and the generated PeakRDL outputs (rtl/pkg/ct_cs_cpuif*.sv); verification evidence refers to the test catalog (Chapter 30) and the coverage measurement (Chapter 31).

+
+
+

32.1. Legend

+
+
+
Implemented
+
+

Feature exists in RTL, is verified (a directed test with a CTTD round trip and/or a byte-identity gate) and covered by the line-coverage union.

+
+
Partial
+
+

Feature exists but is known incomplete, constrained, or not fully verified.

+
+
Not implemented
+
+

Feature is explicitly not present in this repository snapshot (an open item).

+
+
n/a (by design)
+
+

Capability deliberately not offered — no implementation gap. Example: Program Trace Correction (TCODE 10) is not adopted by ratified N-Trace 1.0 (Table 9 keeps it Reserved), so it is not tracked as a CTTE gap.

+
+
+
+
+
+

32.2. Status Matrix

+ ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Feature / TopicStatusEvidence (RTL / RDL)Evidence (Verification)

Trace Encoder Control/Status register block (TCI mapping)

Implemented

PeakRDL outputs rtl/pkg/ct_cs_cpuif*.sv; profile-dependent register omission via the RDL preprocessor (scripts/gen_rdl_profile.py) — registers of compiled-out units are omitted entirely (no address decode / readback), never merely masked.

hsi/01_csr_cap WARL tests; full-profile regenerate byte-identical.

Instruction trace — Branch History Trace (ITR_BRANCH_HIST, InstMode 6)

Implemented

ct_L2_msg_gen.sv (history accumulation, IBH/IBHS, sync forms).

Instruction-trace system suite; CTTD PC-lossless round trips; REF_FINAL md5 family (Chapter 29).

Instruction trace — Branch Trace Messaging (ITR_BRANCH, InstMode 3, TCODE 3/4)

Implemented

CT_EN_BTM (full=1, slim=0, synthesizable-away); ct_L2_msg_gen.sv ITR_BRANCH arm; WARL accepts InstMode 3 and 6.

instruction/17_btm (scripts/cli_btm_test.sh): HTM and BTM legs both PC-lossless against the same cpu_model reference.

ICNT overflow drains (RCODE=0) — all silent-CF accumulation paths

Implemented

ct_L2_msg_gen.sv: indirect-/BTM-/BP-drain holds and the inline guards of the silent arms; send_icnt_overflow_msg.

instruction/20_icnt_overflow (scripts/cli_i20_test.sh): whole drain family covered; decode with ResourceFull ICNT adjustments PC-lossless.

Timestamps (system + core source, prescaler)

Implemented

ct_L23_preproc_ts.sv; trTsControl — enum values TR_TS_SYSTEM='h2, TR_TS_CORE='h3 (0/1 reserved).

Timestamps are on implicitly in every scenario; prescale stages 1-3 and the core-source arm covered (instruction/19_feature_matrix phase 7); TSTAMP decoded by CTTD.

Periodic synchronization (cycles / instructions / halfwords / ATB / trace-quota bytes and messages) + explicit sync requests

Implemented

ct_L23_preproc_sync.sv + egress quota counters (CT_EN_QUOTA_SYNC, CAPS bit 18); trTeSyncStatus.SyncReqSource (none/CSR/ATB/quota/TE-register); vendor SYNC 14. Reset value of trTeControl.InstSyncMax changed 0 → 6 (period 16 → 1024 units) on 2026-08-12.

instruction/04_periodic_sync, 12, 15, 19; trace-quota bytes/messages (instruction/29_sync_quota_bytes, 30_sync_quota_msgs, scripts/cli_syncquota_test.sh); reset-value regression instruction/37_sync_cadence (scripts/cli_synccadence_test.sh) — zero Error messages / lossless at the shipped reset vs. 790 `Error`s / 5,064 dropped events at the pre-2026-08-12 reset, under an identical finite-bandwidth sink.

Self-identification — NEXUS_MSG_VENDOR_CONFIG (TCODE 58, SendConfig)

Implemented

Config message carries CAPS/ENAB/P0-P3 sampled at emission from cs_proc; structure constants in ct_pkg (SSOT); CT_EN_CONFIG_MSG (slim default 0).

instruction/16_config_msg (scripts/cli_cfg_test.sh), 12/12 gates; flag-less CTTD decode equals flagged decode, negative control diverges.

Ownership messages (TCODE 2)

Implemented

ctype/priv-change/after-sync emission; PROCESS LSB-first; on-wire CONTEXT width = TIP_CONTEXT_WIDTH (integration parameter, now ct_pkg::CT_CONTEXT_WIDTH, default 2).

instruction/15_trig_seq_own (scripts/cli_tso_test.sh), exact PROCESS values for FORMAT 0/2.

Debug / Power / EVTI events (SYNC 3/9/0, correlation EVCODE 0/1)

Implemented

Generic event ports (tip.debug_mode/tip.evti/tip.power_down).

instruction/12_debug_power_events (scripts/cli_dbg_test.sh), 6/6 gates.

IBHS (TCODE 29) — syncs carry pending HIST

Implemented

CT_EN_IBHS; 1:1 replacement of the pre-flush.

instruction/13_ibhs (scripts/cli_ibhs_test.sh): payload -17 %/messages -45 %, PC-lossless both legs.

RepeatInstruction (TCODE 31/32)

Implemented

CT_EN_REPEAT_INSTR; spin-loop compression.

instruction/14_repeat_instr (scripts/cli_rpti_test.sh): payload -67 %, PC-lossless.

Implicit Return compression

Implemented

CT_EN_IMPLICIT_RETURN + trTeInstFeatures.InstEnImplicitReturn; composer return-stack prediction, the decoder recovers targets from its own stack.

instruction/06_implicit_return (scripts/cli_ir_test.sh): PC-lossless OFF==ON at a strictly smaller byte count on the dedicated stimulus.

Repeated-History compression (RCODE 2) incl. 28/27-bit partial-match conversion

Implemented

CT_EN_REPEATED_HISTORY; hist_partial_match_shift (s=1/s=2 trimmed-match conversion).

instruction/07_repeated_history (scripts/cli_rh_test.sh, with WideICNT); coverage phase exercises the partial-match conversion arms.

RepeatBranch (TCODE 30) — identical-IBH suppression (jump and return repeats)

Implemented

CT_EN_REPEAT_BRANCH; separate arms in the plain-IBH group and in the RETURN arm.

instruction/08_repeat_branch (scripts/cli_rb_test.sh); coverage phase exercises the return-repeat arm.

Jump Target Cache (vendor TCODE 57)

Implemented

CT_EN_JTC; XOR-fold index (widened to the full address at CT_XLEN=64, see below); learn-on-miss on plain IBH and on unpredicted returns.

instruction/09_jtc (scripts/cli_jtc_test.sh, 595 x TCODE 57); coverage phase exercises return-target hits.

Branch Prediction (vendor TCODE 56)

Implemented

CT_EN_BP; bit-identical 2^9x2-bit predictor on both sides; TCODE 56 only on mispredict.

instruction/10_branch_predict (scripts/cli_bp_test.sh); BP legs also exercised in instruction/11, 16, 20.

Wide ICNT (16-bit cap)

Implemented

CT_EN_WIDE_ICNT + trTeInstFeatures.InstEnWideIcnt (narrow default: 8-bit cap = 255 halfwords).

instruction/07_repeated_history leg; per-cap drain behavior in instruction/20_icnt_overflow.

Comparator-based trace filters (instruction/data qualification)

Implemented

ct_L23_preproc_comp_filters*.sv; P/S functions EQ..ALWAYS; inputs IADDR/CONTEXT/TVAL/DADDR; latch mode is MODE3 ('h3).

instruction/19_feature_matrix (function/input/mode sweeps, filter chain, ecause/interrupt predicates, scripts/cli_featurematrix_test.sh); instruction/11_robustness CSR matrix.

ACT-CAP (CSR-based control access protocol) + ACT-ST (Smart Trigger)

Implemented

ct_L23_preproc_act_cap/act_st/act_proc.sv. Watchpoint memory is the backing store of a perfect binary search tree (vector_binary_search_2clk); capacity grew from 4 levels/15 slots to 10 levels/1,023 slots (M0_DIM=10, M0_N=1,023) on 2026-08-13 (C0b). The direct flat-address write window at 0x4100 was removed in the same change (1,023 entries would collide with the df component at 0x5000); loading and readback now go exclusively through trWpIndex (0x400C, auto-increment), trWpDataLow/trWpDataHigh (0x4010/0x4014, commit-on-High), trWpReadLow/trWpReadHigh (0x4018/0x401C) and trWpCap (0x4020, capacity discovery). Load registers are Enable-locked. Software must still fill all trWpCap.Entries slots in sorted order (partial fill leaves the tree root empty).

instruction/19_feature_matrix phase 10 (indirect-table load/readback, full-table load, wrap behavior, Enable-lock, soft-reset-to-0 — see the testbench’s own "the INDIRECT path (C0b — the direct 0x4100 window is gone)" comment); watchpoint-hit → SINK_TE INSTR_TRACING/DATA_TRACING verified via the same phase; ACT-CAP direct CSR commands incl. DAQ range-error and unknown-command arms.

Performance counters (thresholds + ranges) and DAQ

Implemented

ct_L23_preproc_perfcnt.sv (threshold FSM; the IDLE state itself saturates into TH_ITH_OVERFLOW during long instruction-less stretches); DAQ via ACT commands.

instruction/19_feature_matrix phase 5 (threshold FSM incl. saturation and iretire exit); hsi/01_csr_cap.

Split Load tracing (SPLIT_DATA_ACCESS elaboration parameter, default 0)

Implemented

ct_L23_preproc_df.sv (PendingLoadHit), ct_L23_preproc_composer_etip.sv (STORE at dretire, LOAD at lresp), trTeDataControl.DataSplitLoad.

data/02_split_load (SPLIT=1 elaboration leg; store/load/lresp and pending-overwrite paths, scripts/decode_and_check.sh --pc --data).

Data address compression (XOR)

Implemented

CT_EN_DF_ADDR_COMPRESS (rtl/pkg/ct_pkg.sv:164, =1); trTeDataAddrCompress selects XOR mode (E-P3-2: the only implemented mode — DIFF/XOR_DIFF are WARL-legalized back to FULL). TCODE 13/14 re-anchor on every synchronizing CF message and every emitted ERROR.

data/03_addr_compress, data/04_data_sync, data/05_df_workload (scripts/cli_dfcompress_test.sh, scripts/cli_dfworkload_test.sh).

Overflow / overrun handling (ERR / resync)

Implemented

ovf_injector (serialize and parallel paths). A substantial defect family was found and fixed across the 2026-07/2026-08 hardware campaigns — not a fixed count, see Chapter 30 for the full, currently 15-scenario tests/overflow/ catalog (natural overflow, JTC/implicit-return state across recovery, sync-boundary attribution, board-sequence replay, pause edges, trap-window anchors, stop-drain ordering, flush clobber).

tests/overflow/01_overrun_recovery through 15_flush_clobber (Chapter 30); official gates on 01: --overflow (3 ERROR`s), `--disabled correlations, decode to stream end, data 7/7; byte-neutral REF.

eTIP serialization (CT_ETIP_SERIALIZE) and Compact Packer (CT_COMPACT_PACKER)

Implemented

Serialize is the full-profile default and is byte-identical; the compact packer replaces formatter, slicer and MSEO controller in the control-flow-only path. Resource figures for both are in Chapter 24, which carries the tool version, commit and report path per row.

Serialize proof 15/15 byte-identical; compact-pair tests 12/12 verdicts / 14/14 message-identical.

FIFO fill-level histogram (diagnostics)

Implemented

CT_FIFO_HIST_BINS (default 16); DSP48 counters; serial readout CSR pair (map independent of BINS); no CDC (trace-quiescent read contract).

instruction/18_fifo_histogram (scripts/cli_fifohist_test.sh) incl. BINS=8 smoke; slim profile exactly neutral via register omission.

SRC field (multi-source)

Implemented

trTeControl.InhibitSrc (bootstrap rule) + trTeInstFeatures.SrcBits/SrcID; the formatter keeps the field array dense.

instruction/19_feature_matrix phase 8 (field emitted with SrcBits=4); since 2026-08-19 also instruction/39_dual_src (scripts/cli_dualsrc_test.sh), which runs two encoders with different SrcID at SrcBits=2 into one funnel and takes the merged stream apart again with the decoder’s -src/-srcfilter and -target paths — including the falsifiability leg, in which decoding one source against the other’s PCInfo must fail (Section 30.5). The decode-verification follow-up carried here from the predecessor status is thereby closed.

Multiple retirements per TIP block

Implemented, off by default

CT_EN_BLOCK_TIP (default 0) turns iretire from a strobe into the halfword count of the retiring block, iaddr naming the first instruction and ilastsize the size of the last. At the default the encoder behaves exactly as before.

instruction/36_block_tip (scripts/cli_blocktip_test.sh): one instruction sequence driven both as blocks and serially, both must decode to the identical per-instruction oracle; four red counter-proofs (MUT=M1..M4); byte-neutrality of the default build, 31 of 31 reference artefacts (scripts/r13_off_neutrality.sh). Exercising it on real hardware still needs a core configured for two commit ports — both RV64 hardware harts brought up to date (Section 29.9) run a single commit port, so this remains a simulation-only claim.

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32.3. Features added in the 1.0.0 cycle

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The features below were added on the way to release 1.0.0 (2026-08-28) and are documented in that release’s notes (doc/release-notes.adoc). They are cataloged here for completeness rather than folded into the table above, because none of them existed at the point the inherited rows were written — those rows come from a status document that was retired on 2026-08-18 and is named in Chapter 36 for anyone tracing their provenance.

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Feature / TopicStatusEvidence (RTL / RDL)Evidence (Verification)

Protocol as a synthesis parameter (N-Trace / E-Trace back-end selection)

Implemented

EN_NTRACE/EN_ETRACE instance parameters of ct_encoder (2026-08-04, P9); the historical runtime-selected dual build (both back ends plus an eTIP demux and ATB mux) is removed. trTeProtocolSel.Protocol/trTeImpl.ProtocolMajor are read-only, hardware-driven discovery.

instruction/24_protocol_param (scripts/cli_etrace_test.sh mixed): two ct_encoder instances elaborated side by side, one N-Trace, one E-Trace, each correctly self-reporting.

64-bit addresses as a build knob (ct_pkg::CT_XLEN, default 32)

Implemented (32-bit builds unaffected; E-Trace at 64-bit is n/a by design)

One width definition replaces five package-local constants; sizes TIP address, Nexus F-ADDR/U-ADDR, comparators, JTC index fold, ACT-ST/DF-range keys and the eTIP payload. Announced on the wire as CAPS bit 23 (ADDR64). genEtrace64 elaboration guard rejects a 64-bit E-Trace instance (te_inst address fields are sized CT_ETRACE_ADDR_BITS=31 and would truncate silently).

instruction/35_addr64 (scripts/cli_addr64_test.sh, raw-byte verdict, not decoder-dependent, Section 29.2); RV64 hardware bring-up of cv64a6 and Rocket, both booting Linux with zero decoder error messages (Section 29.9).

Trace one process, not one address range (per-process filter, CT_EN_FILTER_SYNC)

Implemented

trTeComp[].PInput=1 (context) turns the existing comparator bank into a per-process filter; region-exit correlation (TCODE 33, EVCODE "Program Trace Disabled") and region-entry SYNC=5 close the hole where a filtered-out anchor retire previously produced no re-anchor and left the stream undecodable. No new message type, no CAPS bit.

verification.adoc "Tracing one process, end to end" (cv64a6 simulation, two ASIDs): unfiltered both processes decode (204 + 168 instructions, both ASIDs on the wire); filtered to A: 204/204 for A, 0/168 for B; two counter-proofs (ineffective filter returns the full 437-PC stream; compiled-out filter anchoring decodes zero instructions). Real-Linux-process filtering on a board is a follow-on package, not claimed here.

Explicit sync request over the TE register (trTeControl.InstSyncReq, bit 27)

Implemented

CT_EN_INST_SYNC_REQ; the TCI-standard request path (existed and auto-cleared before, but had no consumer). On the wire: SYNC=14, same code as the ACT-CAP CF_SYNC command and the ATB sync-request input. SyncReqSource grew to 3 bits (new source value 4).

instruction/33_te_sync_req (scripts/cli_tesyncreq_test.sh): one write → one message; queue depth one-in-flight-plus-one-remembered (two writes → two messages, three → still two); byte-neutral in both builds, 31 of 31 streams md5-identical ON and OFF.

TCI trigger configuration registers

Implemented

trTeTrigExtInControl (0x054, CT_EN_TRIG_REGS): 0 none / 2 trace-on / 3 trace-off / 4 trace-notify (TCI Table 20), additive to the historical InstTrigEnable → SYNC=6 path. trTeTrigDbgControl (0x050) and trTeTrigExtOutControl (0x058) read 0 — the TCI-prescribed answer for a trigger sideband and a trigger output port CTTE does not have.

instruction/32_trig_regs (scripts/cli_trigregs_test.sh).

Data-trace drop policy (trTeDataControl.DataDropEna)

Implemented

CT_EN_DF_DROP (CAPS bit 22): sheds data-trace messages at 3/4 eTIP-queue fill to keep instruction trace intact; one Error/ECODE=0x02 marker per drop episode, deliberately without the generic overflow’s SYNC=7 re-anchor. InstStallOrOverflow/DataStallOrOverflow/DataDrop implemented as sticky RW1C (overflow half only — the stall half has no hart-side back channel and stays unimplemented).

data/06_df_drop (scripts/cli_dfdrop_test.sh): one stimulus, drop-disabled vs. drop-enabled legs contrasted directly.

Device ID (TCODE 1) and Watchpoint (TCODE 15) status messages

Implemented

SendDeviceId (WARL, DID_NONE/DID_ONCE), trWpMask.WEM; both message types are PC-neutral (no ICNT, no address reference). Device ID, when sent, precedes the config message and the first synchronizing message on the wire (contract DO-1, also SVA invariant I9, Section 29.7).

instruction/31_status_msgs (scripts/cli_status_test.sh): seven CSR legs including a WARL negative control.

Standing in-RTL invariants (SVA, I1-I12)

Implemented

Twelve concurrent assertions (simulation-only, pragma translate_off) encoding the board campaigns' contract lessons directly in the RTL; run in every simulation of every consumer.

See Section 29.7 for the full list and the falsifiability argument for each.

trTeControl.Empty driven end to end

Implemented

Was structurally tied inactive before 2026-08; now a conservative empty chain per backend tail (2-FF synchronizer plus a quiet filter into the ATB domain), covering the preprocessor’s CDC FIFOs and whatever the generator still holds.

SVA invariant I8; exercised by the pause-edge and stop-drain overflow scenarios (Chapter 30).

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33. Known Limitations and Deviations

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This chapter merges the predecessor status document’s limitations list with the current, more detailed "Known limitations" section of doc/release-notes.adoc, and removes what has since been resolved. Where a limitation is a deliberate design contract rather than a gap, it is stated as a contract, not apologized for.

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33.1. Limitations that constrain integration (by design)

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+

These are read-before-filing-a-bug items: each is deliberate behavior with a stated reason, not an open defect.

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TopicContract

Empty with a stopped core

With InstTracing=1 and the core halted, exactly one control-flow event is permanently in flight (its successor address can never be observed) — Empty=0 is the correct report. Close the stream (InstTracing=0) while the core still retires, then stop.

Byte-level run-to-run determinism under overflow

FIFO-overrun drop positions depend on real CDC/ATB phase relations; two identical runs produce equivalent but not byte-identical streams. The verified property is decode equivalence. Byte identity holds in drop-free regimes with timestamps off.

Trace-off correlation under overflow

The correlation is an ordinary message: if a pause edge falls into a drop episode it is lost and announced (ERROR plus recovery sync); the resume re-anchor still recovers the decoder.

Post-pause position ambiguity

After a pause, the first decoded segment may be positionally ambiguous against a full-execution reference when the code is homogeneous (the pause length is unknowable from the stream alone). Content stays fully checkable; tooling should pair by anchor and verify transitions rather than forcing positional alignment.

Trace-quota window semantics

The quota counter rearms when the sync is emitted — the sync message’s own bytes count into the new window, and no second request is raised while one is pending (no sync avalanche at small quotas). After a FIFO-overrun recovery the counter is not re-based: the first post-recovery quota sync can arrive earlier than one full quota (a harmless extra re-anchor, never a late one). With CT_EN_QUOTA_SYNC=0, InstSyncMode 1/4 stay writable but inert (no WARL clamp — exactly the pre-feature behaviour).

Non-standard core trace buses

Core-side adapters (e.g. the AMD MicroBlaze™ V TRACE bus) are pinned to the characterized core/tool version; the bus is documented as not backward-compatible across core or tool-version changes.

XSIM waveform debug of encoder internals

Vivado™ XSIM 2026.x crashes with wave instrumentation on this code base (-debug off required); use Verilator (with coverage, Chapter 31) or $display/counter instrumentation instead.

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33.2. Spec-compatibility corners

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  • +

    CDF is emitted as 1 in both instruction-trace modes; N-Trace requires 0 in branch mode. For the Program Trace Correlation message (TCODE 33), N-Trace 1.0 Table 24 binds the CDF field to the mode: 1 in history mode (HTM), 0 in branch mode (BTM). The encoder emits the constant 2’b01 in both. In HTM this is correct; in BTM it is a deviation from the ratified specification. The practical consequence is confined to decoders that dispatch on CDF to decide whether a HIST field follows: the encoder always emits the field, encoded as 0x1 when the history is empty, so a decoder that reads it unconditionally — including the reference decoder — reconstructs correctly either way. A decoder written strictly to Table 24 and run against a BTM stream will not. Field detail in Chapter 14. Disclosed rather than corrected: the fix is a one-line mode dependency in the formatter, but it changes the on-wire bytes of every stream containing this message and therefore invalidates the byte-identity reference set, which is a versioned change rather than an editorial one.

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  • +

    Two vendor-extension enables are writable where N-Trace requires them hard-wired to zero. N-Trace 1.0 Table 8 states that trTeInstEnBranchPrediction and trTeInstEnJumpTargetCache "must be hard coded as 0" — the specification reserves the bits but forbids an implementation from making them settable, because the features behind them are not part of N-Trace. CTTE implements both features as declared vendor extensions and therefore makes both bits writable. A configuration tool that assumes the bits read back as zero will be surprised; a decoder is not affected, because it learns the active feature set from the configuration message (Chapter 18) rather than from the register. The full deviation list with the specification clauses is in Chapter 4.

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  • +

    ICNT 8-bit cap not enforced for control-flow-free runs longer than 255 halfwords. The composer-side ResourceFull(RCODE=0) drain item is computed combinationally but the beat never commits without an accompanying event, so for a purely linear run longer than the cap the item never reaches ct_L2_msg_gen. Correctness is unaffected — the variable-length ICNT field carries the true count regardless, and decode stays PC-lossless (measured 950/950 in instruction/20_icnt_overflow phase 0, a 300-halfword linear run) — but the 8-bit spec-compatibility cap itself is not enforced for such runs. Tracked as waiver W-0118 (ACCEPTED, type UNREACHABLE_INTEGRATION) rather than a functional defect.

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  • +

    E-Trace implicit-return visit count at a zero-width irdepth field. With irdepth field width 0, an implicit-return-folded loop that crosses a positional binding point (a trap/off flush, a window or resync anchor) cannot express its visit count on the wire. Measured 6 of 33 red among implicit-return-armed runs of a free-axis calibration (seed 20260806). The implicit-return bit is masked out of the E-Trace soak campaign until an irdepth field exists (Chapter 30, E-Trace section); every other compression bit is drawn normally.

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  • +

    Comparator, ACT-ST and DF-range bounds are CSR-programmable in the low 4 GiB only, at CT_XLEN=64. The compared address itself is full width; the CSR side of these three subsystems stays a 32-bit word pair.

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33.3. Deliberately not implemented / follow-on packages

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  • +

    64-bit E-Trace. ct_pkg::CT_XLEN=64 together with EN_ETRACE=1 is rejected at elaboration (genEtrace64 guard, Chapter 5): the te_inst address fields are sized CT_ETRACE_ADDR_BITS=31 and would truncate silently rather than fail loudly. n/a by design until a wider E-Trace address field exists.

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  • +

    Parallel retirement on RV64 cores is not exercised. Both RV64 harts brought up to date (cv64a6, Rocket) run a single commit port; the multi-retire path (CT_EN_BLOCK_TIP) remains verified only in simulation with a scripted multi-instruction-per-beat stimulus (Chapter 32), not on real multi-retire hardware.

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  • +

    Filtering real Linux processes on a board. The per-process filter chain (CT_EN_FILTER_SYNC) is verified end to end in simulation with real core RTL and a scripted ASID; filtering where the ASID is written by a running kernel on a board is a follow-on package and not claimed here.

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  • +

    count_fields (mseo formatter), referenced by the predecessor RM, no longer exists in the RTL tree — see the BEFUND note at the end of this chapter.

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33.4. Caller-less helper code (retirement candidates)

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Two functions in ct_L23_preproc_comp_filters.sv remain without a caller in the current tree: set_match_now (line ~414, W-0119, ACCEPTED/UNUSED_CODE — only set_match_next is invoked, at line ~502) and set_match_next itself (AUTO-0029, still PROPOSED — not yet dispositioned as either a genuine test gap or a further retirement candidate; see the coverage-ledger caveat in Chapter 31). Both are candidates for removal rather than functional defects.

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33.5. Vendor extensions — no standard-conformance claim

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  • +

    Vendor TCODEs 56 (BranchPredict), 57 (JumpTargetCache) and 58 (Config) occupy the N-Trace vendor TCODE range; no standard-conformance claim is made for them.

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  • +

    SYNC=4 (sequential instruction counter) is bound to BTM by N-Trace; its use with HTM is a documented Accemic extension (runtime reset 0).

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  • +

    Sync reasons 12/13 were replaced by the single vendor SYNC=14, with SyncReqSource diagnosing the actual origin (CSR, ATB, quota, or the TE register, Chapter 32); the standard-reserved codes 12/13 are not emitted.

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34. Development Support

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This chapter describes the internal SystemVerilog testbench patterns, the simulation verification infrastructure, and the recommended development workflow for CEDARtools.TraceEncoder (CTTE). It complements the Verification chapters (Part F), which describe test strategy and coverage; this chapter describes the tooling those tests are built from.

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34.1. Repository layout and build flow

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The build driver is abc (abc-flow): Vivado™-based, text-defined projects. Tool versions are pinned in .abc.config. Every umbrella command routes through the Makefile:

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TargetWhat it does

make help

List available targets.

make sim

Run all testbenches; print a PASS/FAIL summary.

make sim-<name>

Run one testbench (e.g. sim-basic).

make sim-examples

Run every simulable example under examples/.

make lint

The host guards, then verible-verilog-lint over rtl/ and tests/.

make clean

Remove the (gitignored) bld/ directory.

make rdl

Regenerate the PeakRDL-derived SystemVerilog from rdl/*.rdl.

make rdl-html

Render the browsable HTML register reference into bld/rdl-html/.

make bld-bootstrap

Generate the xsim projects the cli_* gates clone.

make bld-refresh

The same, but regenerate them even if they exist.

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RTL is organized under rtl/: top-level encoder modules directly in rtl/ (ct_encoder.sv, ct_L1_funnel.sv, ct_L2_nexus_formatter.sv, ct_L2_mseo_mdo_formatter.sv, …​), rtl/pkg/ for type and parameter packages, rtl/preproc/ and rtl/mseo_mdo/ for the respective sub-pipelines, and rtl/external/ for vendored infrastructure shared across sibling Accemic repositories (AMBA interfaces, Wishbone, stream primitives, the tt test package). Each subsystem carries its own test/ subdirectory for the unit testbenches that exercise it (rtl/preproc/test/, rtl/mseo_mdo/test/, rtl/test/); the top-level tests/ directory is reserved for high-level / system / integration tests that span multiple modules (tests/instruction/, tests/data/, tests/hsi/, tests/overflow/, tests/combined/, and shared infrastructure in tests/lib/).

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34.1.1. Starting from a fresh clone or worktree

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bld/ is gitignored, and every cli_*_test.sh gate drives xvlog/xelab/xsim by hand over an xsim project that abc generates below it. The gates bootstrap the project they need (ct_need_prj in scripts/ct_env.sh), so a fresh worktree runs them without a separate warm-up step; the first gate to need a given project pays roughly a minute for it.

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Three outcomes are reported distinctly:

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Exit / lineMeaning

77 → SKIP

The gate needs an input this repository does not ship (a captured hardware run, a decoder build with -decoe). Not a pass, not a failure.

78 → TOOL

The toolchain or the build tree could not be established (no Vivado, no abc, no working Python, a bootstrap that did not produce a project). Never a statement about the encoder.

anything else → FAIL

The gate ran and its check failed.

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A byte-neutrality run whose legs did not all complete reports BYTE NEUTRALITY: INCONCLUSIVE rather than DRIFT — an incomplete manifest cannot claim byte identity either way.

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34.1.2. Simulation backend

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.abc.config pins sim_backend=verilator — the Vivado-free default that make sim and the coverage runs use. The cli_* gate battery needs an xsim project, so those scripts request the Vivado backend explicitly (abc --sim-backend vivado -sim …​) rather than depending on the repository-wide setting.

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34.1.3. Toolchain discovery

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Scripts under scripts/ and ci/ source scripts/ct_env.sh, which resolves the toolchain without machine-specific paths: CT_VIVADO_BIN / CT_VIVADO_ANY, CT_ABC_BIN, CT_ABC_TIMEOUT (seconds a bootstrap abc -sim may take; default 900), CT_PRJ_REFRESH, CT_PYTHON_BIN (resolved via ct_need_python, because a fresh Windows shell’s bare python/python3 are often Microsoft Store stubs), NEXRV, VERILATOR_ROOT, and the replay-only CT_REPLAY_PCINFO / NEXRV_DECOE (without these the two hardware-replay gates skip with exit 77 rather than failing).

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34.2. Register (RDL) flow

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SystemRDL is the source of truth for the register map (rdl/). The committed PeakRDL-derived SystemVerilog under rtl/pkg/ (and the Wishbone helper under tests/lib/) is generated from it and must never be hand-edited:

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  1. +

    Edit rdl/ct_cs_cpuif.rdl.

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  2. +

    Run make rdl to regenerate rtl/pkg/ct_cs_cpuif.sv, rtl/pkg/ct_cs_cpuif_pkg.sv, rtl/pkg/ct_cs_cpuif_wb_pkg.sv, rtl/pkg/ct_cs_cpuif_types_pkg.sv, and tests/lib/ct_cs_cpuif_wb_helper.sv. The Wishbone<→CPUIF adapter rtl/pkg/ct_cs_cpuif_wb.sv is hand-written and not regenerated.

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  3. +

    Commit the RDL change and the regenerated SystemVerilog in the same commit — CI fails a PR whose generated SV is stale.

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    Run make rdl-html to render the browsable register reference into bld/rdl-html/ (the bare encoder map, and the example SoC’s KV260 app map with absolute devmem addresses).

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make rdl provisions a pinned, local toolchain (peakrdl==1.5.0, peakrdl-regblock==1.3.1, peakrdl-html==2.12.2, systemrdl-compiler==1.32.2, per rdl/requirements.txt) into a gitignored .venv-rdl*/; a linked git worktree resolves the main checkout’s venv via git rev-parse --git-common-dir (scripts/gen_rdl_profile.py). If no pinned venv is found, the flow refuses to fall back to a peakrdl found on PATH — an unpinned install has silently produced a regblock without the addrmap localparams in the past, which fails simulation hours later with an error that does not point at the real cause.

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34.3. Testbench architecture

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Two related, queue-based patterns are in use, depending on scope.

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34.3.1. Per-module: directed queue-based scoreboarding

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Per-module unit testbenches under rtl/<subsystem>/test/ use a lightweight, directed, queue-based scoreboarding pattern. The pattern recurs across many testbenches, e.g. rtl/preproc/test/ct_L23_preproc_tb.sv and rtl/preproc/test/ct_L23_preproc_comp_filters_tb.sv.

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Queue-based scoreboarding provides:

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    deterministic, directed tests (no hidden randomness);

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    decoupling of stimulus generation from checking;

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    clear "what was expected" bookkeeping even with variable pipeline latency.

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Core components, as implemented in
+rtl/preproc/test/ct_L23_preproc_comp_filters_tb.sv:

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+
+
    +
  1. +

    Test item struct — test data as a packed struct plus metadata (description, test ID, expected flags).

    +
    2. +
  2. +

    Input queue — stimulus is generated once and pushed into input_queue[$].

    +
    3. +
  3. +

    Expected queue(s) — expected results are pushed into one or more expected_queue[$]; a multi-sink DUT (e.g. one that drives both a control-flow and a data-flow filter) uses separate queues per sink.

    +
    4. +
  4. +

    Feeding task — pops from the input queue and drives the DUT.

    +
    5. +
  5. +

    Checking task(s) — wait for valid DUT outputs, pop the matching expected item, and compare, e.g.:

    +
    +
    +
    1
+2
+3
+4
+5
+6
+
    if (cf_filter.hit_valid) begin
+    exp = expected_queue.pop_front();
+    void'(tt_assert(cf_filter.hit == exp.cf_hit,
+        $sformatf("%0.2f: Line %0d / Test %0d (%s) mismatch",
+                  $realtime, `__LINE__, exp.test_id, exp.desc)));
+end
+
    +
    +
    +
    6. +
  6. +

    Parallel execution — feeding and checking commonly run concurrently via fork …​ join plus a FeedingDone && CheckingDone wait.

    +
    7. +
+
+
+

Pitfalls: guard every queue pop with a size() > 0 check; if the DUT can emit multiple outputs per cycle, the checker must pop the matching number of expected items; a testbench that never calls tt_assert(…​) anywhere gets flagged by tt_evaluate() as having checked nothing (a silent pass is not allowed to look like a real one).

+
+
+
+

34.3.2. System level: scripted CPU model with an oracle event stream

+
+

High-level / system tests under tests/ (tests/instruction/, tests/data/, tests/hsi/, tests/overflow/, tests/combined/) are driven by a different, complementary mechanism: a scripted RISC-V CPU model, tests/lib/cpu_model.sv, that mimics a core via a task-based API (enter / run / branch_taken / branch_not_taken / jump_to / uninferable_jump / call / ret / interrupt / load / store / csr_write / …​). Each task both drives the encoder-facing TIP signals with the correct itype/iaddr/daddr/…​ and logs a high-level event into a sideband event_q that the scoreboard cross-checks against the encoder’s decoded output. No binary program or separate stimulus file is needed — the test’s task calls are the program; there is no binary-trace player in this suite.

+
+
+

A test instantiates the shared tests/lib/ct_env.sv, which wires cpu_model, the DUT, and the trace sinks together, drives the scenario through the cpu_model task API, then writes the expected.* reference files that scripts/decode_and_check.sh diffs against the CTTD decode (see Section 34.6). Test directories are named NN_<scenario>/ with a numeric prefix so tests sort simple to sophisticated; each has a <scenario>_tb.sv + <scenario>_tb.abc pair.

+
+
+
+

34.3.3. tt assertions (rtl/external/testtools/tt.sv)

+
+

The tt package (rtl/external/testtools/tt.sv) is the shared simulation-only assertion helper used by both testbench styles above (it is not synthesizable — string operations are used throughout). Import with import tt::*;.

+
+
+
    +
  • +

    tt_assert(cond, msg) increments the assertion counters; on failure it stores the message in an internal error queue and calls $error(msg) (optionally $stop if stop-on-error is enabled). Typical use:

    +
    +
    +
    1
+2
+
    void'(tt_assert(dut_out == expected,
+    $sformatf("%0.2f: Line %0d / Test %0d: ...", $realtime, `__LINE__, test_id)));
+
    +
    +
    +
    • +
  • +

    tt_evaluate(), called at the end of simulation, prints a concise summary: the list of testcases with pass/fail status, the number of checked assertions, and any captured error messages. A testbench always terminates with tt_evaluate(); $finish();.

    +
    • +
+
+
+
+
+

34.4. Simulation helper modules

+
+

Reusable, simulation-only infrastructure modules, as they exist in the repository today:

+
+ +++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
ModuleLocationPurpose

TIP dumper (tip_dump)

tests/lib/tip_dump.sv

Dumps the TIP signal stream to a file after flush, in RAW, PCINFO (address,type,<dest>), or PLAIN (per-address branch-kind counts) mode.

AXIS dump, DAQ-specific (ct_axis_dump)

tests/lib/ct_axis_dump.sv

Simulation-only dump of CTTE’s DAQ AXI-Stream transactions. Writes both a text dump and a fixed-record-size binary raw dump (<CT_DATE_TIME>_<realtime>_ct_axis.{txt,raw}); unconditional — the instance presence is the gate.

AXIS dump, generic (axis_dump)

rtl/external/amba/test/axis_dump.sv

Lower-level, RAW-only AXI-Stream dumper shared across Accemic AMBA testbenches (not CTTE-DAQ-specific).

AXIS decoder (ct_axis_decoder)

tests/lib/ct_axis_decoder.sv

Converts one AXIS beat into a structured record (ct_axis_decoder_pkg::ct_axis_msg_t) so a testbench can assert on fields without manually slicing tdata/tid/tstrb.

ATB dump (atb_dump)

rtl/external/amba/test/atb_dump.sv

Writes accepted ATB beats (atvalid && atready) to a binary file; prints the final path and byte count at end of simulation even if no flush occurred.

ATB sink model (atb_sink_model)

rtl/external/amba/test/atb_sink_model.sv

Minimal ATB consumer with deterministic stalls: releases atready after STARTUP_STALL_CYCLES, then injects stall windows of 0..MAX_STALL_CYCLES drawn from an LFSR (reproducible under Verilator and across a simulation resume, unlike $random).

ATB stall injector (atb_stall_injector)

rtl/external/amba/test/atb_stall_injector.sv

ATB pass-through that injects Aurora-like bursty backpressure between an ATB master and slave, to emulate SerDes-link flow control. Sizing rule: average sink rate >= average master rate, and STALL_PERIOD several times larger than STALL_LENGTH_MAX (enforced by an elaboration check).

Overflow injector (ovf_injector)

rtl/external/stream/ovf_injector.sv

Counted-vector stream overflow marker injector: forwards input to output while there is room; on downstream full (or a driven force_inject) it discards concurrent input, counts the discards, and once room exists emits one or two configured marker elements. A SEQ_INJECT parameter forces the two markers into separate cycles when the downstream sink is single-element-per-beat wide — combining them into one beat silently truncates and loses a marker (found 2026-07-20 via the serialized eTIP path).

+
+
+

34.5. Long-running simulations: watchdog policy

+
+

Two independent timeout mechanisms exist today, at different levels:

+
+
+
    +
  • +

    Per-testbench, simulation-time watchdogs. Several testbenches arm their own $fatal-based watchdog that fires after a fixed amount of simulated time or a fixed cycle count if the DUT never reaches the expected state — e.g. rtl/preproc/test/ct_L23_preproc_sync_tb.sv:181-186 (WATCHDOG_TIMEOUT_NS, sized to roughly two orders of magnitude above the longest legitimate wait in that test) and rtl/mseo_mdo/test/ct_L2_mseo_mdo_formatter_tb.sv:288-291 (MAX_SIM_CYCLES). This is a simulation-content watchdog: it protects against the DUT hanging or a testbench waiting on an event that never comes, independent of wall-clock runtime.

    +
    • +
  • +

    Bootstrap / compile timeout. CT_ABC_TIMEOUT (default 900 s, see Section 34.1.1) bounds how long a bld/-project bootstrap abc -sim may take at the tool level.

    +
    • +
+
+
+
+

34.6. Recommended workflow

+
+
    +
  1. +

    Implement or change RTL, and regenerate every register model the change touches in the same commit: make rdl for rdl/ct_cs_cpuif.rdl, make rdl-soc for examples/kv260/common/tgc5b/rdl/ct_soc.rdl, and make rdl-kv260 for the demonstrator maps under examples/kv260/. Skipping the last one leaves the KV260 address map behind, which the drift gate of the documentation build then reports rather than the build that caused it.

    +
    2. +
  2. +

    Update or extend the corresponding testbench(es) if behavior changed.

    +
    3. +
  3. +

    Run the relevant testbench(es): make sim-<name> for a single system scenario under tests/, make sim for the full suite, make sim-examples for the worked integrations. The unit testbenches of a subsystem are not sim-* targets — they live beside their RTL in rtl/<subsystem>/test/ and are driven from there.

    +
    4. +
  4. +

    For an end-to-end / system test, use scripts/decode_and_check.sh to check the CTTD decode of the captured ATB stream against the test’s expected.* reference. The script decodes once and can then run any combination of: --pc (exact PC-stream match, or --soft for a warn-only prefix check), --data (data-access sequence), --ctxp (value-aware CTXP export match), --tsmono (timestamp monotonicity), --sync N / --hist N (minimum synchronization / branch-history message counts), --disabled (trace-off correlation message present), and --overflow (a Nexus Error / QueueOverrun message was actually emitted). With no flag, --pc is assumed.

    +
    5. +
  5. +

    Ensure the testbench ends with tt_evaluate(); $finish();.

    +
    6. +
  6. +

    Run make lint (Verible; opt-in ruleset, .rules.verible_lint) before submitting.

    +
    7. +
  7. +

    Every new file carries an SPDX header; contribution and CLA rules are covered in Chapter 37.

    +
    8. +
+
+
+
+
+
+

35. Demonstrator Register Maps

+
+
+

The demonstrator chapter Chapter 28 describes what each example design does; this appendix states which registers drive them. It exists because the reference manual is meant to be the single source for every SystemRDL register description that CEDARtools.TraceEncoder ships, and the example designs bring their own — the control window a host uses to start a core and drain a trace buffer is not part of the encoder map in Chapter 16, and reading a bare offset out of a prose sentence is not the same as reading a register with its access type and its reset value.

+
+
+

The tables here are generated from the same SystemRDL sources the example RTL is built from, by the same generator and under the same drift gate as the encoder tables. What is written by hand is the prose: which map applies to which design, how far each one matches the hardware as built, and where a value comes from that the table cannot state.

+
+
+

35.1. Scope: which SystemRDL source appears where

+
+

Eleven SystemRDL files live in the encoder repository, outside its build tree (the per-profile copies under bld/ are build output, not sources). They serve three different purposes, and this manual treats them accordingly:

+
+ +++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
SystemRDL sourcePrintedWhy

rdl/ct_cs_cpuif.rdl (with rdl/ct_profile.inc.rdl)

Section 16.7

The encoder control and status registers: the product interface, and the map every integration programs.

examples/kv260/common/rdl/ct_kv260_ctrl.rdl (with ct_kv260_ctrl/ct_kv260_common.rdl and ct_kv260_ctrl/ct_kv260_sinks.rdl)

Section 35.3

The control window every KV260 example exposes to the Zynq UltraScale+ processing system: core run control, capture counters, and the three trace sinks.

examples/kv260/common/tgc5b/rdl/ct_soc.rdl (with ct_soc/ct_ps_ctrl.rdl)

Section 35.4

The address spaces of the TGC5B example SoC, and the registers of its processing-system control port.

examples/kv260/common/tgc5b/rdl/ct_soc/ct_clint.rdl, …​/ct_intc.rdl

referenced, not reprinted — Section 35.7

Two minimal interrupt peripherals of the example SoC. Seven registers whose names follow an established convention and whose behaviour the example needs but the encoder does not; a transcription here would suggest they are part of the trace subsystem.

examples/kv260/tgc5b2_axis_wp/rdl/ct_tgc5b2_kv260.rdl

Section 35.5

The address map of the delivered two-core device as the processing system sees it: both cores, both encoder instances, the core control block, the merged trace ring and the two stream FIFOs the watchpoint records are drained from. This is the map a reader holding the KV260 bundle is looking for, which is why it is printed rather than referenced.

examples/kv260/tgc5b2_rvcfi/rdl/ct_tgc5b2_rvcfi_kv260.rdl

Section 35.6

The address maps of the runtime-verification testbed, including the banks this manual could not print before that SystemRDL existed: the read-only observation bank, the per-core console, the two DDR record rings and the core-side map with the ACT-CAP doorbell.

+
+

Two limits of this appendix are worth stating before the tables rather than after them.

+
+
+

These maps are examples, not product interfaces. The interface-stability rule that governs the encoder map — additive change preferred, a breaking change justified in writing — does not extend to the example designs. An example is free to move a register when its design changes, and several have; Section 35.3 says how far.

+
+
+

A register map is not a driver. The sequence in which these registers are written, and the traps that sequence holds, are in Section 28.7. This appendix answers what a register is, not when to write it.

+
+
+
+

35.2. Reading the generated tables

+
+

Each table is produced by scripts/gen_ctte_regs.py in this documentation repository, one fragment per SystemRDL top:

+
+
+
+
1
+2
+3
+
python3 scripts/gen_ctte_regs.py --list    # the sources and their fragments
+python3 scripts/gen_ctte_regs.py           # regenerate all of them
+make check-generated                       # the gate the documentation build runs
+
+
+
+
+

Four conventions apply to every table below. They are the encoder map’s conventions as well, and not by agreement: the same generator writes both, so a column means the same thing here as it does in Chapter 16.

+
+
+
    +
  • +

    Offsets. Each table states what its offset column is relative to. The distinction matters in this appendix more than in the encoder chapter, because the TGC5B map is printed in four views of one design — the same register appears at a physical address in one and at an aperture-relative offset in the next.

    +
    • +
  • +

    Access. RW and RO are the software access the SystemRDL declares. A parenthesised qualifier is the property that changes what a write or a read does: hw-written marks a status field the hardware drives, self-clearing a write-one pulse that never reads back as set.

    +
    • +
  • +

    Reset. The value the SystemRDL declares. Where a top instantiates the block with a different elaboration parameter, the table shows the declared default and the description says so — sinks.ddr_base is the case that matters.

    +
    • +
  • +

    Provenance. Each generated fragment carries, in its header comment, the SHA-256 of every SystemRDL file that fed it. A reader holding a printed manual and a checkout can therefore establish whether the two describe the same hardware, which is the whole purpose of generating these tables instead of typing them.

    +
    • +
+
+
+
+

35.3. The unified KV260 control window

+
+

Every KV260 example places a control window at the base of its own AXI4-Lite aperture, and the processing system reaches that aperture at 0xA000_0000. The window is how a Linux host on the Zynq UltraScale+ processing system starts and stops the traced core, re-arms the capture path, reads how much trace has accumulated, and configures the three trace sinks — all with devmem, without a custom driver.

+
+
+

The SystemRDL below is the target layout for that window, and the distinction is not academic. The first 0x38 bytes are intended to be identical across all nine example tops. Measured against the tops as built, five of the nine diverge somewhere in that range, and the divergent tops were deliberately not retrofitted when the layout was fixed (examples/kv260/common/rdl/README.md, section "As-built drift", carries the per-top measurement). A reader working on one specific design therefore verifies the offsets against that design’s own module header; a reader writing new host code against the shared layout uses the table below.

+
+
+

Three properties of this window come from its history and are invisible in the table:

+
+
+

The two halves have different standing. Offsets 0x00--0x14 (common) document registers that each top still implements in its own AXI4-Lite front-end — there is no shared module behind CONTROL and STATUS. Offsets 0x18--0x38 (sinks) are transcribed one to one from examples/kv260/common/ct_trace_sinks.sv, a single shared module that three tops instantiate verbatim. The sink half describes hardware that exists once; the common half describes an agreement between several implementations of the same thing.

+
+
+

Only three bits are universal. An inventory across the nine as-built tops found CONTROL.core_run, CONTROL.trace_clear and STATUS bit 0 identical in position and meaning everywhere. Every other bit differs by design — per-core run bits, console clear, window-guard clear, interrupt-generator enable — and is therefore modelled as one undifferentiated passthrough field (top_ctrl, top_status) rather than as named bits. Naming a bit that means something else on the next top would misdocument the hardware, which is worse than leaving the field open.

+
+
+

One offset is deliberately absent. Local 0x1C of the sink block, absolute 0x34, carries no register in the shared map: the sink module reserves it for the instantiating top, where it is a funnel control register today. A gap in the offset column is that reservation, not an omission.

+
+
+

The unified CTRL window of the KV260 example designs, as the SystemRDL describes it. Offsets are relative to the base of the window; every example top places that base at the start of its own AXI4-Lite aperture. Register and field descriptions in the tables below are reproduced verbatim from that SystemRDL, which is Accemic’s own text; the column heading names it as the source.

+
+
+

35.3.1. Component overview

+ +++++ + + + + + + + + + + + + + + + + + + + +
BaseComponentRegisters

0

common

6

0x18

sinks

8

+
+
+

35.3.2. Component common (base 0)

+
+

KV260 example SoC - common CTRL registers (CONTROL..TRACE_BUFSZ)

+
+ +++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
OffsetRegisterFields

0x000

common.control

3

0x004

common.status

2

0x008

common.trace_beats

1

0x00C

common.trace_bytes

1

0x010

common.axis_beats

1

0x014

common.trace_bufsz

1

+
+
common.control — offset 0x000
+
+

Board-level control, written over devmem to drive the SoC. Bits 2..31 are top-specific — see top_ctrl and the owning top’s own module header (e.g. b2 is trace_flush on mbv/duo/trio/tgc5b2_axis_wp but con_clear on the cva6_linux/cva6_linux64/rocket_linux/rocket2/cva6_2 family; README.md 'CONTROL b2' finding).

+
+
+
+common.control bit layout +
+
+ +++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsFieldAccessResetDescription (SystemRDL of the example)

31:2

top_ctrl

RW

0

Top-specific control bits (b2..b31): trace_flush, con_clear, win_err_clear, obs_clear, irq_gen_en, per-core run bits (core0_run/core1_run/ cva6_run/cva6_run2), etc. — see the owning top’s header. NOT wired to any hardware behaviour by this shared regblock; a future per-top instantiation drives its own subset of these bits itself.

1

trace_clear

RW

0

Level: while set, re-arm the trace capture path (ring, and where present AXIS/sink counters). Universal across every observed top.

0

core_run

RW

0

0 = hold the core(s) in reset, 1 = run. On multi-core tops this is the COLLECTIVE bit (b0 OR each top’s own per-core run bit in top_ctrl); on single-core tops it is the only run bit there is.

+
+
+
common.status — offset 0x004
+
+

Board-level status (read-only). Bits 1..31 are top-specific — see top_status and the owning top’s own module header (e.g. b1 is axis_overflow on mbv/duo/trio but uram_stopped on the cva6_linux/cva6_linux64/rocket_linux/rocket2/cva6_2 family; README.md 'STATUS b1' finding).

+
+
+
+common.status bit layout +
+
+ +++++++ + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsFieldAccessResetDescription (SystemRDL of the example)

31:1

top_status

RO (hw-written)

0

Top-specific status bits (b1..b31): axis_overflow, uram_stopped, win_err_sticky(+_was_write), core_ndreset/core_rst_hold, per-core running mirrors, observation-channel stickies, last-seen privilege level, timer_irq/sw_irq, etc. — see the owning top’s header.

0

trace_wrapped

RO (hw-written)

0

1: the trace ring/capture buffer has wrapped or overflowed at least once since the last trace_clear (naming differs — trace_wrapped on most tops, trace_overflow on duo/trio/tgc5b2_axis_wp — the condition is the same: capture continues, nothing stalls, the oldest beats are gone). Universal across every observed top.

+
+
+
common.trace_beats — offset 0x008
+
+
+common.trace_beats bit layout +
+
+ +++++++ + + + + + + + + + + + + + + + + + + +
BitsFieldAccessResetDescription (SystemRDL of the example)

31:0

value

RO (hw-written)

0

ATB beats captured since the last trace_clear (monotonic, does NOT stop at the ring capacity — read TRACE_BUFSZ for the capacity). Ring write position = TRACE_BEATS % (TRACE_BUFSZ/4). Identical offset and meaning on every observed top.

+
+
+
common.trace_bytes — offset 0x00C
+
+
+common.trace_bytes bit layout +
+
+ +++++++ + + + + + + + + + + + + + + + + + + +
BitsFieldAccessResetDescription (SystemRDL of the example)

31:0

value

RO (hw-written)

0

ATB bytes captured since the last trace_clear (monotonic). Poll delta = live trace bandwidth. Identical offset and meaning on every observed top.

+
+
+
common.axis_beats — offset 0x010
+
+
+common.axis_beats bit layout +
+
+ +++++++ + + + + + + + + + + + + + + + + + + +
BitsFieldAccessResetDescription (SystemRDL of the example)

31:0

value

RO (hw-written)

0

AXIS instrumentation beats captured (read-only). Populated only on tops with an AXIS capture path (mbv, duo, trio, per README.md); reads 0 on every other top, consistent with the 'outside the window reads 0' convention ct_trace_sinks.sv already establishes for its own CTRL indices. This is the canonical slot for AXIS_BEATS in the unified layout — see README.md for the per-top offset this displaces (AXIS_BEATS was already at this offset on mbv/duo/trio; TRACE_BUFSZ moves off of it on the tops that used to park it here, see @0x14 below).

+
+
+
common.trace_bufsz — offset 0x014
+
+
+common.trace_bufsz bit layout +
+
+ +++++++ + + + + + + + + + + + + + + + + + + +
BitsFieldAccessResetDescription (SystemRDL of the example)

31:0

value

RO (hw-written)

0

Trace ring capacity in bytes (read-only; TRACE_DEPTH * 4). Identical MEANING on every observed top; this is the canonical offset (0x10 TRACE_BUFSZ on six of the nine tops already; AXIS_BEATS moves off of 0x10 on the other three — see README.md).

+
+
+
+

35.3.3. Component sinks (base 0x18)

+
+

KV260 example SoC - shared three-sink subsystem CTRL window

+
+ +++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
OffsetRegisterFields

0x018

sinks.sink_ctrl

9

0x01C

sinks.ddr_base

1

0x020

sinks.ddr_size

1

0x024

sinks.ddr_wptr

1

0x028

sinks.sink_stat

5

0x02C

sinks.ddr_drops

1

0x030

sinks.pib_drops

1

0x038

sinks.ddr_beats

1

+
+
sinks.sink_ctrl — offset 0x018
+
+

Trace sink enable/config. Stored bits use write mask 0xFFFF_FFDD (everything except the two write-1 pulses); EN_DDR=0 additionally masks b0/b2, EN_PIB=0 masks b4/b6/b[10:8]/b[13:12] (ct_trace_sinks.sv SINK_WR_MASK).

+
+
+
+sinks.sink_ctrl bit layout +
+
+ +++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsFieldAccessResetDescription (SystemRDL of the example)

13:12

pib_pattern

RW

0

PIB calibration pattern (reference trPibCalibPattern). Values: 0 = STANDARD; 1 = MOVING_ONE; 2 = MOVING_ZERO.

10:8

pib_div

RW

0

PIB port clock divider: pib_clk = clk / 2^(div+1); 0 is clamped to 1 in the PIB module.

6

pib_calib

RW

0

1: PIB emits the calibration pattern instead of trace (reference trPibCalibrate); the trace input is not consumed while set.

5

pib_clear

RW

0

Write-1 pulse (captured one cycle after the write, NOT stored — always reads back 0): reset the PIB drop counter. The hardware does not enforce pib_en=0 first (ct_trace_sinks.sv:125,142-146).

4

pib_en

RW

0

1: PIB parallel trace port enabled (pib_clk runs, beats serialized).

3

uram_oneshot

RW

0

URAM ring mode: 0 = circular (default, keeps the most recent capacity), 1 = one shot (stop when full, SINK_STAT.uram_stopped sets).

2

ddr_circ

RW

0

DDR capture mode: 0 = one shot (stop when full), 1 = circular (wrap modulo DDR_SIZE, write offset = DDR_WPTR % DDR_SIZE).

1

ddr_clear

RW

0

Write-1 pulse (captured one cycle after the write, NOT stored in this register — always reads back 0): reset DDR_WPTR/full/wrapped/err/drops and SINK_STAT.ddr_cfg_rej. The hardware does not enforce ddr_en=0 first.

0

ddr_en

RW

0

1: DDR4 sink enabled (writes beats to PS DDR at DDR_BASE).

+
+
+
sinks.ddr_base — offset 0x01C
+
+
+sinks.ddr_base bit layout +
+
+ +++++++ + + + + + + + + + + + + + + + + + + +
BitsFieldAccessResetDescription (SystemRDL of the example)

31:0

value

RO (hw-written)

0x50000000

DDR4 sink base address in PS DDR (byte address, 32-byte aligned — low 5 bits are masked). U9-1 (2026-08-16): hardware-enforced WARL with an EMPTY set of legal software values — the register is hard-wired to the DDR_BASE_RST elaboration parameter for the life of the bitstream, EVERY write is discarded (not just while armed, as the earlier U6 interlock did), and every discarded write latches SINK_STAT.ddr_cfg_rej. To relocate the window: change DDR_BASE_RST, rebuild the bitstream, move the reserved-memory node with it (correspondence rule, ct_trace_sinks.sv header). Reset value shown is the DDR_BASE_RST default (0x5000_0000, address plan v4); tops may instantiate ct_trace_sinks with a different DDR_BASE_RST/DDR_SIZE_RST — read the register, the elaboration parameter is not visible over devmem.

+
+
+
sinks.ddr_size — offset 0x020
+
+
+sinks.ddr_size bit layout +
+
+ +++++++ + + + + + + + + + + + + + + + + + + +
BitsFieldAccessResetDescription (SystemRDL of the example)

31:0

value

RO (hw-written)

0x10000000

DDR4 sink buffer size in bytes (4-byte aligned — low 2 bits are masked). Same U9-1 hardware-enforced WARL as DDR_BASE: fixed to DDR_SIZE_RST for the life of the bitstream, every write discarded and latched in SINK_STAT.ddr_cfg_rej.

+
+
+
sinks.ddr_wptr — offset 0x024
+
+
+sinks.ddr_wptr bit layout +
+
+ +++++++ + + + + + + + + + + + + + + + + + + +
BitsFieldAccessResetDescription (SystemRDL of the example)

31:0

value

RO (hw-written)

0

DDR4 sink write pointer: TOTAL bytes written since the last ddr_clear (monotonic, read-only). One shot: host reads [DDR_BASE, DDR_BASE+min(WPTR,SIZE)). Circular: write offset = WPTR % SIZE (same contract as the URAM ring).

+
+
+
sinks.sink_stat — offset 0x028
+
+

Trace sink status flags (read-only; the DDR bits clear on ddr_clear).

+
+
+
+sinks.sink_stat bit layout +
+
+ +++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsFieldAccessResetDescription (SystemRDL of the example)

4

ddr_cfg_rej

RO (hw-written)

0

1: a DDR_BASE/DDR_SIZE write was REFUSED (U9-1: EVERY write is refused, armed or not; sticky until ddr_clear).

3

uram_stopped

RO (hw-written)

0

1: URAM one-shot capture stopped (buffer full, first capacity kept).

2

ddr_wrapped

RO (hw-written)

0

1: circular DDR buffer wrapped at least once (oldest bytes overwritten).

1

ddr_axi_err

RO (hw-written)

0

1: an AXI write returned BRESP != OKAY (sticky, clears on ddr_clear).

0

ddr_full

RO (hw-written)

0

1: DDR buffer full in one-shot mode; further beats drop.

+
+
+
sinks.ddr_drops — offset 0x02C
+
+
+sinks.ddr_drops bit layout +
+
+ +++++++ + + + + + + + + + + + + + + + + + + +
BitsFieldAccessResetDescription (SystemRDL of the example)

31:0

value

RO (hw-written)

0

DDR4 sink dropped beats (FIFO overflow or buffer full; saturating; read-only; clears on ddr_clear).

+
+
+
sinks.pib_drops — offset 0x030
+
+
+sinks.pib_drops bit layout +
+
+ +++++++ + + + + + + + + + + + + + + + + + + +
BitsFieldAccessResetDescription (SystemRDL of the example)

31:0

value

RO (hw-written)

0

PIB sink dropped beats (FIFO overflow when the port rate is below the trace rate; saturating; read-only; clears on pib_clear).

+
+
+
sinks.ddr_beats — offset 0x038
+
+
+sinks.ddr_beats bit layout +
+
+ +++++++ + + + + + + + + + + + + + + + + + + +
BitsFieldAccessResetDescription (SystemRDL of the example)

31:0

value

RO (hw-written)

0

Beats offered to the DDR sink while ddr_en (accepted = this value - DDR_DROPS; cleared by ddr_clear; read-only) — the cheap proof that beats reach the sink at all. T2 addition: this counter sat at CTRL 0x30 on the pre-T2 tgc5b2 C0B_DDR build; since the shared three-sink subsystem it is here, 0x38 absolute, and 0x30 is PIB_DROPS.

+
+

The two DDR registers deserve one sentence the table cannot carry. sinks.ddr_base and sinks.ddr_size read as writable in the register model and are not: the hardware discards every write and latches sinks.sink_stat.ddr_cfg_rej when it does. Both are fixed for the life of the bitstream to the elaboration parameters the top instantiated the sink module with, so the reset values in the table are the defaults of that module and not necessarily what a given board reports. Relocating the DDR window means changing the parameter, rebuilding the bitstream and moving the reserved-memory node with it. Software reads the registers; it cannot negotiate with them.

+
+
+
+
+
+

35.4. The TGC5B example SoC

+
+

The TGC5B example SoC is the design that runs both in simulation and on the board, and its register map shows something the encoder chapter cannot show: the encoder is one addressable component inside a larger address space, and where that space puts it is the integrator’s choice. The same encoder map appears twice in the tables below — at 0x2000_0000 on the CPU data bus and at 0x0001_0000 in the processing-system control port — and both are the map of Section 16.7, which is why it is not reprinted here.

+
+
+

Three facts about these views are structural, and each one has cost debugging time somewhere:

+
+
+
    +
  • +

    The memory windows are wider than the memories behind them. The control port selects a region from the top address bits of the aperture, so each window spans 1 MiB while holding 64 KiB, 16 KiB or 4 KiB. A read past the last entry aliases back to entry 0 instead of failing. A host that walks a window to its end therefore sees the buffer repeat, not the end of the data.

    +
    • +
  • +

    The program RAM window is gated by the run bit. The load window is accessible only while ctrl.control.core_run is 0. Loading a program into a running core does not fail loudly; it does not arrive.

    +
    • +
  • +

    Only one of the four maps becomes RTL. Only the peripheral block is generated from this SystemRDL. The control port, the data-bus decode and the physical placement are hand-written modules, described here so that the map is complete rather than because a generator consumes them. Keeping the two in step is a manual obligation stated in the SystemRDL itself.

    +
    • +
+
+
+

The address spaces of the TGC5B example SoC, and the registers of its PS control port. The encoder registers reachable in these spaces are the map of the register-model chapter and are not reprinted here. Register and field descriptions in the tables below are reproduced verbatim from that SystemRDL, which is Accemic’s own text; the column heading names it as the source.

+
+
+

35.4.1. KV260 application view (physical addresses)

+
+

Physical-address view on the KV260: the Zynq PS FPD window places the ct_soc_top control port at 0xA000_0000 (M_AXI_HPM0_FPD).

+
+
+

The offsets in this table are physical addresses: what devmem takes on the board.

+
+ +++++++ + + + + + + + + + + + + + + + + + + +
OffsetComponentKindSizeContent

0xA0000000

soc

address map

3076 KiB

TGC5B example SoC - PS control port

+
+
+

35.4.2. PS control port (aperture-relative)

+
+

The AXI4-Lite control port ct_soc_top presents to the Zynq PS. Offsets are relative to the port aperture (the RTL decodes the low 22 address bits); see ct_soc_kv260_top for the absolute devmem addresses on the KV260.

+
+
+

Offsets are relative to the base of the control-port aperture.

+
+ +++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
OffsetComponentKindSizeContent

0

ctrl

register file

20 B

ct_soc_top control / status

0x10000

encoder

address map

24696 B

CEDARtools.TraceEncoder Control / Status Registers

0x100000

ram

memory

64 KiB

Program RAM load window (ct_soc_ram): 16384 words = 64 KiB (MEM_WORDS). Accessible only while core_run = 0. 16384 entries of 32 bit.

0x200000

trace

memory

16 KiB

Captured ATB read-back (ct_soc_trace_buf): 4096 words = 16 KiB (TRACE_DEPTH), one word per ATB beat. Read TRACE_BEATS words and keep the first TRACE_BYTES bytes. 4096 entries of 32 bit.

0x300000

axis

memory

4 KiB

Captured AXIS instrumentation read-back (ct_soc_axis_buf): 256 DAQ beats of four words = 1024 words = 4 KiB (AXIS_DEPTH). Read AXIS_BEATS * 4 words. 1024 entries of 32 bit.

+
+
+

35.4.3. Registers of ctrl (base 0)

+
+

ct_soc_top control / status

+
+
+
ctrl.control — offset 0x000
+
+

Control register, written over devmem to drive the SoC.

+
+
+
+ctrl.control bit layout +
+
+ +++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsFieldAccessResetDescription (SystemRDL of the example)

2

trace_flush

RW

0

Request an encoder trace flush.

1

trace_clear

RW

0

Level: while set, re-arm BOTH capture buffers (ATB and AXIS).

0

core_run

RW

0

0 = hold core in reset, 1 = run.

+
+
+
ctrl.status — offset 0x004
+
+

Status register. An overflow bit latches when its buffer is full and a further beat arrives — the capture is then truncated, not complete. Cleared by trace_clear.

+
+
+
+ctrl.status bit layout +
+
+ +++++++ + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsFieldAccessResetDescription (SystemRDL of the example)

1

axis_overflow

RO (hw-written)

0

AXIS capture buffer full (>256 beats).

0

trace_overflow

RO (hw-written)

0

ATB capture buffer full (>4096 beats).

+
+
+
ctrl.trace_beats — offset 0x008
+
+
+ctrl.trace_beats bit layout +
+
+ +++++++ + + + + + + + + + + + + + + + + + + +
BitsFieldAccessResetDescription (SystemRDL of the example)

31:0

value

RO (hw-written)

0

ATB beats captured (one 32-bit word per beat), saturating at the buffer depth of 4096 words = 16 KiB.

+
+
+
ctrl.trace_bytes — offset 0x00C
+
+
+ctrl.trace_bytes bit layout +
+
+ +++++++ + + + + + + + + + + + + + + + + + + +
BitsFieldAccessResetDescription (SystemRDL of the example)

31:0

value

RO (hw-written)

0

Valid ATB bytes captured, saturating at 16384 (4 * 4096). Read TRACE_BEATS words from the TRACE window and keep the first TRACE_BYTES bytes — only the last beat can be partial.

+
+
+
ctrl.axis_beats — offset 0x010
+
+
+ctrl.axis_beats bit layout +
+
+ +++++++ + + + + + + + + + + + + + + + + + + +
BitsFieldAccessResetDescription (SystemRDL of the example)

31:0

value

RO (hw-written)

0

AXIS instrumentation beats captured, saturating at the buffer depth of 256 beats = 4 KiB. One 128-bit record — four 32-bit words at AXIS+0x0..0xC — per beat: tdata elem0..2, then {tlast, tid[7:0], tkeep[11:0]}; tid[5:0] is the ACT-CAP/ACT-ST command.

+
+
+
+

35.4.4. CPU data bus (dBus)

+
+

Address map the CPU’s AXI4-Lite dBus sees, decoded by ct_soc_synth_wrap.

+
+
+

Offsets are addresses on the CPU data bus.

+
+ +++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
OffsetComponentKindSizeContent

0

ram

memory

64 KiB

Program + data RAM (ct_soc_ram): 16384 words = 64 KiB (MEM_WORDS). 16384 entries of 32 bit.

0x10000000

clint

register file

20 B

Core-local interruptor (timer + software interrupt)

0x10001000

intc

register file

8 B

Minimal external interrupt controller

0x20000000

encoder

address map

24696 B

CEDARtools.TraceEncoder Control / Status Registers

+
+
+

35.4.5. Generated peripheral block

+
+

CLINT + INTC register block (AXI4-Lite), based at PERIPH (0x1000_0000).

+
+
+

Offsets are relative to the base of the generated block.

+
+ +++++++ + + + + + + + + + + + + + + + + + + + + + + + + + +
OffsetComponentKindSizeContent

0

clint

register file

20 B

Core-local interruptor (timer + software interrupt)

0x1000

intc

register file

8 B

Minimal external interrupt controller

+
+
+
+

35.5. The delivered two-core device (tgc5b2_axis_wp)

+
+

This is the only map in this appendix that describes a whole device rather than a building block: two MINRES TGC5B cores with one encoder instance each, the control block that starts and holds them, the merged trace ring the funnel writes, and the two AXI-Stream FIFOs the watchpoint and instrumentation records are drained from. A reader holding the loadable KV260 application has this map in front of them at the physical addresses devmem takes.

+
+
+

Three things are worth knowing before the tables:

+
+
+
    +
  • +

    The encoder map appears twice. Both instances are the map of Section 16.7, at 0x0001_0000 and 0x0002_0000 inside the control-port aperture. It is not reprinted here.

    +
    • +
  • +

    Only the encoder registers are generated into RTL. The control block, the watchpoint-shim status block and the address router are hand-written modules. The SystemRDL describes them so that the map is complete in one place, and says so itself; keeping the two in step is a manual obligation, the same one Section 35.4 states.

    +
    • +
  • +

    The memories are memories, not registers. The two core RAMs and the trace ring are declared external, and their entry counts mirror the RTL parameters rather than being read back from hardware.

    +
    • +
+
+
+

The address map of the delivered tgc5b2_axis_wp KV260 design: two TGC5B cores, their two encoder instances, the core control block, the merged trace-sink window and the two AXI-Stream FIFOs the watchpoint and instrumentation records are drained from. The encoder registers instantiated twice in these spaces are the map of the register-model chapter and are not reprinted here. Register and field descriptions in the tables below are reproduced verbatim from that SystemRDL, which is Accemic’s own text; the column heading names it as the source.

+
+
+

35.5.1. KV260 device view (physical addresses)

+
+

Absolute addresses on the board. The Zynq PS reaches all of this through M_AXI_HPM0_FPD → width converter → AXI4-Lite → a 1:4 router. pl_clk0 must be driven to 75 MHz before use.

+
+
+

The offsets in this table are physical addresses: what devmem takes on the board.

+
+ +++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
OffsetComponentKindSizeContent

0xA0000000

soc

address map

3 MiB

tgc5b2_axis_wp SoC — PS control-port view (aperture-relative)

0xA0400000

wpctrl

register file

44 B

AXIS watchpoint shim status

0xA0410000

fifo0

register file

52 B

AXI4-Stream FIFO (PG080), RX path

0xA0420000

fifo1

register file

52 B

AXI4-Stream FIFO (PG080), RX path

+
+
+

35.5.2. Registers of wpctrl (base 0xA0400000)

+
+

AXIS watchpoint shim status

+
+
+
wpctrl.magic — offset 0xA0400000
+
+
+wpctrl.magic bit layout +
+
+ +++++++ + + + + + + + + + + + + + + + + + + +
BitsFieldAccessResetDescription (SystemRDL of the example)

31:0

value

RO (hw-written)

0x41575031

Magic identifier, reads 0x41575031 ("AWP1"). This is the proof that the PL is loaded and answering on the AXI bus — read it before any other access to the design.

+
+
+
wpctrl.shim0_drop — offset 0xA0400004
+
+
+wpctrl.shim0_drop bit layout +
+
+ +++++++ + + + + + + + + + + + + + + + + + + +
BitsFieldAccessResetDescription (SystemRDL of the example)

31:0

value

RO (hw-written)

0

Core 0 shim: records dropped because its FIFO was full (saturating).

+
+
+
wpctrl.shim0_fill — offset 0xA0400008
+
+
+wpctrl.shim0_fill bit layout +
+
+ +++++++ + + + + + + + + + + + + + + + + + + +
BitsFieldAccessResetDescription (SystemRDL of the example)

31:0

value

RO (hw-written)

0

Core 0 shim: current FIFO fill level in records.

+
+
+
wpctrl.shim0_ovf — offset 0xA040000C
+
+
+wpctrl.shim0_ovf bit layout +
+
+ +++++++ + + + + + + + + + + + + + + + + + + +
BitsFieldAccessResetDescription (SystemRDL of the example)

0

overflow

RO (hw-written)

0

Core 0 shim: sticky overflow flag (latches on the first drop).

+
+
+
wpctrl.shim1_drop — offset 0xA0400010
+
+
+wpctrl.shim1_drop bit layout +
+
+ +++++++ + + + + + + + + + + + + + + + + + + +
BitsFieldAccessResetDescription (SystemRDL of the example)

31:0

value

RO (hw-written)

0

Core 1 shim: records dropped because its FIFO was full (saturating).

+
+
+
wpctrl.shim1_fill — offset 0xA0400014
+
+
+wpctrl.shim1_fill bit layout +
+
+ +++++++ + + + + + + + + + + + + + + + + + + +
BitsFieldAccessResetDescription (SystemRDL of the example)

31:0

value

RO (hw-written)

0

Core 1 shim: current FIFO fill level in records.

+
+
+
wpctrl.shim1_ovf — offset 0xA0400018
+
+
+wpctrl.shim1_ovf bit layout +
+
+ +++++++ + + + + + + + + + + + + + + + + + + +
BitsFieldAccessResetDescription (SystemRDL of the example)

0

overflow

RO (hw-written)

0

Core 1 shim: sticky overflow flag (latches on the first drop).

+
+
+
wpctrl.ftime_lo — offset 0xA040001C
+
+
+wpctrl.ftime_lo bit layout +
+
+ +++++++ + + + + + + + + + + + + + + + + + + +
BitsFieldAccessResetDescription (SystemRDL of the example)

31:0

value

RO (hw-written)

0

Low half of the free-running 64-bit fabric counter — the SHARED time base both encoders stamp their records with. READ ORDER MATTERS: reading FTIME_LO atomically snapshots the high half into FTIME_HI. Read LO first, then HI, or the two halves can straddle a carry.

+
+
+
wpctrl.ftime_hi — offset 0xA0400020
+
+
+wpctrl.ftime_hi bit layout +
+
+ +++++++ + + + + + + + + + + + + + + + + + + +
BitsFieldAccessResetDescription (SystemRDL of the example)

31:0

value

RO (hw-written)

0

High half of the fabric counter, as snapshotted by the last FTIME_LO read.

+
+
+
wpctrl.rx_fifo_words — offset 0xA0400024
+
+
+wpctrl.rx_fifo_words bit layout +
+
+ +++++++ + + + + + + + + + + + + + + + + + + +
BitsFieldAccessResetDescription (SystemRDL of the example)

31:0

value

RO (hw-written)

0x1000

Build parameter mirror: RX FIFO depth in 32-bit words per axi_fifo_mm_s (4096 = 1024 records).

+
+
+
wpctrl.shim_records — offset 0xA0400028
+
+
+wpctrl.shim_records bit layout +
+
+ +++++++ + + + + + + + + + + + + + + + + + + +
BitsFieldAccessResetDescription (SystemRDL of the example)

31:0

value

RO (hw-written)

0x100

Build parameter mirror: internal record depth per ct_axis_wp_shim.

+
+
+
+

35.5.3. PS control port (aperture-relative)

+
+

The 22-bit window the AXI4-Lite router forwards to the SoC.

+
+
+

Offsets are relative to the base of the 22-bit control-port aperture the router forwards to the SoC.

+
+ +++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
OffsetComponentKindSizeContent

0

ctrl

register file

60 B

tgc5b2_axis_soc_top control / status

0x10000

enc0

address map

24696 B

CEDARtools.TraceEncoder Control / Status Registers

0x20000

enc1

address map

24696 B

CEDARtools.TraceEncoder Control / Status Registers

0x80000

ram1

memory

64 KiB

TGC5B core 1 program/data RAM, 64 KiB (MEM_WORDS). Write only while core 1 is held — see CONTROL. 16384 entries of 32 bit.

0x100000

ram0

memory

64 KiB

TGC5B core 0 program/data RAM, 64 KiB (MEM_WORDS). Write only while core 0 is held — see CONTROL. 16384 entries of 32 bit.

0x200000

trace

memory

1 MiB

Merged ATB ring (TRACE_DEPTH = 1 MiB). Both encoders' N-Trace output after ct_L1_funnel; the SRC field attributes each message back to its source encoder. Read TRACE_BEATS words and keep the first TRACE_BYTES bytes. 262144 entries of 32 bit.

+
+
+

35.5.4. Registers of ctrl (base 0)

+
+

tgc5b2_axis_soc_top control / status

+
+
+
ctrl.control — offset 0x000
+
+

Control register, written over devmem to drive the SoC. The two cores have nothing to do with each other — there is no SMP here. Effective run state of core i is core_run OR core_i_run. LOADER CONTRACT, PER CORE: only write RAM_i while core_i_run (and core_run) are 0. An access to a RUNNING core’s RAM never gets ready and hangs the transaction.

+
+
+
+ctrl.control bit layout +
+
+ +++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsFieldAccessResetDescription (SystemRDL of the example)

9

core1_run

RW

0

Run core 1 individually.

8

core0_run

RW

0

Run core 0 individually.

2

trace_flush

RW

0

Request a global funnel flush.

1

trace_clear

RW

0

Level: while set, re-arm the ATB ring.

0

core_run

RW

0

Collective bit: run BOTH cores.

+
+
+
ctrl.status — offset 0x004
+
+

Status register. Cleared by trace_clear.

+
+
+
+ctrl.status bit layout +
+
+ +++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsFieldAccessResetDescription (SystemRDL of the example)

9

core1_running

RO (hw-written)

0

Core 1 running (effective state).

8

core0_running

RO (hw-written)

0

Core 0 running (effective state).

0

trace_overflow

RO (hw-written)

0

ATB ring wrapped — capture truncated.

+
+
+
ctrl.trace_beats — offset 0x008
+
+
+ctrl.trace_beats bit layout +
+
+ +++++++ + + + + + + + + + + + + + + + + + + +
BitsFieldAccessResetDescription (SystemRDL of the example)

31:0

value

RO (hw-written)

0

Merged ATB beats captured into the ring (one 32-bit word per beat).

+
+
+
ctrl.trace_bytes — offset 0x00C
+
+
+ctrl.trace_bytes bit layout +
+
+ +++++++ + + + + + + + + + + + + + + + + + + +
BitsFieldAccessResetDescription (SystemRDL of the example)

31:0

value

RO (hw-written)

0

Valid ATB bytes captured. Only the last beat can be partial.

+
+
+
ctrl.trace_bufsz — offset 0x010
+
+
+ctrl.trace_bufsz bit layout +
+
+ +++++++ + + + + + + + + + + + + + + + + + + +
BitsFieldAccessResetDescription (SystemRDL of the example)

31:0

value

RO (hw-written)

0

Ring capacity in bytes (TRACE_DEPTH * 4 = 1 MiB).

+
+
+
ctrl.sink_ctrl — offset 0x018
+
+

Sink control. The DDR4 sink and the PIB parallel port are additive observers on the funnel output; the URAM ring always runs.

+
+
+
+ctrl.sink_ctrl bit layout +
+
+ +++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsFieldAccessResetDescription (SystemRDL of the example)

13:12

pib_pattern

RW

0

PIB calibration pattern select.

10:8

pib_div

RW

0

PIB clock divider.

6

pib_calib

RW

0

Emit the PIB calibration pattern.

5

pib_clear

RW

0

Pulse: clear PIB counters.

4

pib_en

RW

0

Enable the PIB parallel trace port.

3

uram_oneshot

RW

0

URAM ring one-shot (stop on full).

2

ddr_circ

RW

0

Circular mode (wrap instead of stop).

1

ddr_clear

RW

0

Pulse: clear DDR counters/flags.

0

ddr_en

RW

0

Arm the DDR4 sink.

+
+
+
ctrl.ddr_base — offset 0x01C
+
+
+ctrl.ddr_base bit layout +
+
+ +++++++ + + + + + + + + + + + + + + + + + + +
BitsFieldAccessResetDescription (SystemRDL of the example)

31:0

value

RW

0x50000000

DDR4 sink window base. Writable only while ddr_en = 0; a write while the sink is armed is rejected and reported in SINK_STAT.ddr_cfg_rej. Reset is the reserved-memory window that the boot device tree must carve out (no-map).

+
+
+
ctrl.ddr_size — offset 0x020
+
+
+ctrl.ddr_size bit layout +
+
+ +++++++ + + + + + + + + + + + + + + + + + + +
BitsFieldAccessResetDescription (SystemRDL of the example)

31:0

value

RW

0x10000000

DDR4 sink window size in bytes (reset 256 MiB). Same write-while-disarmed rule as DDR_BASE.

+
+
+
ctrl.ddr_wptr — offset 0x024
+
+
+ctrl.ddr_wptr bit layout +
+
+ +++++++ + + + + + + + + + + + + + + + + + + +
BitsFieldAccessResetDescription (SystemRDL of the example)

31:0

value

RO (hw-written)

0

Bytes written to DDR in TOTAL (monotonic, not modulo the window).

+
+
+
ctrl.sink_stat — offset 0x028
+
+

Sink status.

+
+
+
+ctrl.sink_stat bit layout +
+
+ +++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsFieldAccessResetDescription (SystemRDL of the example)

4

ddr_cfg_rej

RO (hw-written)

0

A window write was rejected because the sink was armed.

3

uram_stopped

RO (hw-written)

0

URAM ring stopped (one-shot).

2

ddr_wrapped

RO (hw-written)

0

DDR window wrapped (circular mode).

1

ddr_axi_err

RO (hw-written)

0

DDR AXI error response seen.

0

ddr_full

RO (hw-written)

0

DDR window full.

+
+
+
ctrl.ddr_drops — offset 0x02C
+
+
+ctrl.ddr_drops bit layout +
+
+ +++++++ + + + + + + + + + + + + + + + + + + +
BitsFieldAccessResetDescription (SystemRDL of the example)

31:0

value

RO (hw-written)

0

Beats dropped by the DDR sink (saturating).

+
+
+
ctrl.pib_drops — offset 0x030
+
+
+ctrl.pib_drops bit layout +
+
+ +++++++ + + + + + + + + + + + + + + + + + + +
BitsFieldAccessResetDescription (SystemRDL of the example)

31:0

value

RO (hw-written)

0

Beats dropped by the PIB port (saturating).

+
+
+
ctrl.ddr_beats — offset 0x038
+
+
+ctrl.ddr_beats bit layout +
+
+ +++++++ + + + + + + + + + + + + + + + + + + +
BitsFieldAccessResetDescription (SystemRDL of the example)

31:0

value

RO (hw-written)

0

ATB beats OFFERED to the sink since ddr_en — the proof that beats reach the sink at all. Cleared via ddr_clear.

+
+
+
+
+

35.6. The runtime-verification testbed (tgc5b2_rvcfi)

+
+

The runtime-verification testbed is the second whole-device map in this appendix: two TGC5B cores with one encoder instance each, the shared memory both programs race over, and the banks that exist for runtime verification specifically — a read-only observation bank, a per-core console, and one DDR record ring per core. Until 2026-08-27 this appendix could not print any of it: the banks existed only in the RTL, and an earlier revision of this manual said so rather than transcribing them by hand. The example now carries its own SystemRDL source, written as-built against the RTL and under the same drift gate as every other table here, so the previous deliberate absence is closed the only way this appendix closes gaps — by generating.

+
+
+

Four things are worth knowing before the tables:

+
+
+
    +
  • +

    Nothing in this SystemRDL generates RTL. The control window, the banks and the router are hand-written modules; only the two encoder CSR windows are generated, and they are the map of Section 16.7, at 0x01_0000 and 0x02_0000 in the SoC aperture. The SystemRDL exists so the map is readable in one place, and it names the RTL, host-tool and tutorial locations it must be kept in step with.

    +
    • +
  • +

    The observation bank is read-only by design, and the design says why. Offset 0x40 differs from CONTROL in a single address bit; a write alias there would start both cores by accident, so writes into the bank are discarded in hardware.

    +
    • +
  • +

    The ring base and size are WARL. A write that is misaligned, out of the reserved DDR window, or arrives while the ring is enabled is rejected and latches ring_stat.cfg_rej — on this board family an unchecked AXI write outside the reservation does not error, it wedges the interconnect until the power switch, which is why the check is in hardware rather than in the driver.

    +
    • +
  • +

    The core-side map is the one map the processing system cannot reach. The ACT-CAP doorbell in particular is a core-side address; Chapter 20 describes the command word it carries.

    +
    • +
+
+
+

The address maps of the tgc5b2_rvcfi runtime-verification demonstrator: two TGC5B cores with one encoder each, the shared memory they race over, the RV/CFI observation, console and DDR-record-ring banks, and the core-side map with the ACT-CAP doorbell. The two ring banks (ring0 @ 0x80, ring1 @ 0xA0) are instances of the same register file; the bit-level table is printed once for ring0. Register and field descriptions in the tables below are reproduced verbatim from that SystemRDL, which is Accemic’s own text; the column heading names it as the source.

+
+
+

35.6.1. KV260 device view (physical addresses)

+
+

The SoC behind the 1:4 AXI4-Lite router, plus the shim status block and the two PG080 FIFOs the records are drained from in FIFO mode. Router select bits: address [17:16] within the 4 MiB region above the SoC.

+
+
+

The offsets in this table are physical addresses: what devmem takes on the board.

+
+ +++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
OffsetComponentKindSizeContent

0xA0000000

soc

address map

3 MiB

RV/CFI demo SoC (22-bit AXI4-Lite aperture)

0xA0400000

wpctrl

register file

28 B

WPCTRL — watchpoint shim status

0xA0410000

fifo0

memory

64 KiB

Core 0’s record FIFO in FIFO mode. Idle when that core’s ring_ctrl.route_ddr is set. 16384 entries of 32 bit.

0xA0420000

fifo1

memory

64 KiB

axi_fifo_mm_s 1 (PG080 lite register set) 16384 entries of 32 bit.

+
+
+

35.6.2. Registers of wpctrl (base 0xA0400000)

+
+

Per-shim record accounting. The drop counters are CUMULATIVE since bitstream load and have no clear register on purpose (a counter that can be cleared can be cleared by accident): a run is judged by the DELTA over its own window.

+
+
+
wpctrl.shim0_drops — offset 0xA0400004
+
+
+wpctrl.shim0_drops bit layout +
+
+ +++++++ + + + + + + + + + + + + + + + + + + +
BitsFieldAccessResetDescription (SystemRDL of the example)

31:0

value

RO (hw-written)

0

Shim 0: records dropped because its FIFO was full.

+
+
+
wpctrl.shim0_fill — offset 0xA0400008
+
+
+wpctrl.shim0_fill bit layout +
+
+ +++++++ + + + + + + + + + + + + + + + + + + +
BitsFieldAccessResetDescription (SystemRDL of the example)

31:0

value

RO (hw-written)

0

Shim 0: current FIFO occupancy (watch it approach the depth).

+
+
+
wpctrl.shim0_overflow — offset 0xA040000C
+
+
+wpctrl.shim0_overflow bit layout +
+
+ +++++++ + + + + + + + + + + + + + + + + + + +
BitsFieldAccessResetDescription (SystemRDL of the example)

31:0

value

RO (hw-written)

0

Shim 0: sticky 'it overflowed at least once'.

+
+
+
wpctrl.shim1_drops — offset 0xA0400010
+
+
+wpctrl.shim1_drops bit layout +
+
+ +++++++ + + + + + + + + + + + + + + + + + + +
BitsFieldAccessResetDescription (SystemRDL of the example)

31:0

value

RO (hw-written)

0

Shim 1: records dropped because its FIFO was full.

+
+
+
wpctrl.shim1_fill — offset 0xA0400014
+
+
+wpctrl.shim1_fill bit layout +
+
+ +++++++ + + + + + + + + + + + + + + + + + + +
BitsFieldAccessResetDescription (SystemRDL of the example)

31:0

value

RO (hw-written)

0

Shim 1: current FIFO occupancy.

+
+
+
wpctrl.shim1_overflow — offset 0xA0400018
+
+
+wpctrl.shim1_overflow bit layout +
+
+ +++++++ + + + + + + + + + + + + + + + + + + +
BitsFieldAccessResetDescription (SystemRDL of the example)

31:0

value

RO (hw-written)

0

Shim 1: sticky overflow flag.

+
+
+
+

35.6.3. PS control port (aperture-relative)

+
+

Two TGC5B cores with one CTTE encoder each, a shared memory, the merged ATB ring, and the RV/CFI banks. Hand-written decode in rtl/tgc5b2_rvcfi_soc_top.sv; only the ENC windows are generated.

+
+
+

Offsets are relative to the base of the 22-bit control-port aperture the router forwards to the SoC.

+
+ +++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
OffsetComponentKindSizeContent

0

ctrl

register file

20 B

tgc5b2_rvcfi_soc_top control / status

0x40

obs

register file

32 B

RV/CFI observation bank

0x60

console

register file

28 B

Per-core console

0x80

ring0

register file

28 B

DDR record ring (one instance per core)

0xA0

ring1

register file

28 B

DDR record ring (one instance per core)

0x10000

enc0

address map

24696 B

CEDARtools.TraceEncoder Control / Status Registers

0x20000

enc1

address map

24696 B

CEDARtools.TraceEncoder Control / Status Registers

0x40000

shared

memory

256 KiB

The memory both programs race over. UltraRAM: no bitstream initialization, and NO byte-write enables — a partial strobe is refused (SLVERR at the block), so every write is a whole word. One 32-bit word per address, deliberately: two words per URAM row would collide exactly on Peterson’s flag pair. Reachable from the PS ONLY while both cores are held. 65536 entries of 32 bit.

0x80000

ram1

memory

64 KiB

Load only while core1_run = 0 (loader contract). 16384 entries of 32 bit.

0x100000

ram0

memory

64 KiB

Load only while core0_run = 0 (loader contract). 16384 entries of 32 bit.

0x200000

trace

memory

1 MiB

Both encoders' ATB streams after the funnel. Read-only; a write is ignored. mementries mirrors TRACE_DEPTH. 262144 entries of 32 bit.

+
+
+

35.6.4. Registers of ctrl (base 0)

+
+

tgc5b2_rvcfi_soc_top control / status

+
+
+
ctrl.control — offset 0x000
+
+

Control register, written over devmem. The two cores have nothing to do with each other — own RAM, own CLINT, own encoder, no SMP. Effective run state of core i is core_run OR core_i_run. LOADER CONTRACT, PER CORE: only write RAM_i while core_i_run (and core_run) are 0. An access to a RUNNING core’s RAM never gets ready and hangs the transaction. SHARED-MEMORY CONTRACT: the PS window onto SHARED is muxed away while EITHER core runs. Publish the control area and open the barrier BEFORE the release; a write afterwards never gets ready.

+
+
+
+ctrl.control bit layout +
+
+ +++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsFieldAccessResetDescription (SystemRDL of the example)

9

core1_run

RW

0

Run core 1 individually.

8

core0_run

RW

0

Run core 0 individually.

2

trace_flush

RW

0

Request a global funnel flush.

1

trace_clear

RW

0

Level: while set, re-arm the ATB ring.

0

core_run

RW

0

Collective bit: run BOTH cores.

+
+
+
ctrl.status — offset 0x004
+
+

Status register. Cleared by trace_clear.

+
+
+
+ctrl.status bit layout +
+
+ +++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsFieldAccessResetDescription (SystemRDL of the example)

9

core1_running

RO (hw-written)

0

Core 1 running (effective state).

8

core0_running

RO (hw-written)

0

Core 0 running (effective state).

0

trace_overflow

RO (hw-written)

0

ATB ring wrapped — capture truncated.

+
+
+
ctrl.trace_beats — offset 0x008
+
+
+ctrl.trace_beats bit layout +
+
+ +++++++ + + + + + + + + + + + + + + + + + + +
BitsFieldAccessResetDescription (SystemRDL of the example)

31:0

value

RO (hw-written)

0

Merged ATB beats captured into the ring (one 32-bit word per beat).

+
+
+
ctrl.trace_bytes — offset 0x00C
+
+
+ctrl.trace_bytes bit layout +
+
+ +++++++ + + + + + + + + + + + + + + + + + + +
BitsFieldAccessResetDescription (SystemRDL of the example)

31:0

value

RO (hw-written)

0

Valid ATB bytes captured. Only the last beat can be partial.

+
+
+
ctrl.trace_bufsz — offset 0x010
+
+
+ctrl.trace_bufsz bit layout +
+
+ +++++++ + + + + + + + + + + + + + + + + + + +
BitsFieldAccessResetDescription (SystemRDL of the example)

31:0

value

RO (hw-written)

0

ATB ring capacity in bytes (TRACE_DEPTH * 4).

+
+
+
+

35.6.5. Registers of obs (base 0x40)

+
+

RV/CFI observation bank

+
+
+
obs.db0_hits — offset 0x040
+
+
+obs.db0_hits bit layout +
+
+ +++++++ + + + + + + + + + + + + + + + + + + +
BitsFieldAccessResetDescription (SystemRDL of the example)

31:0

value

RO (hw-written)

0

Doorbell stores accepted, core 0 (saturating).

+
+
+
obs.db0_last — offset 0x044
+
+
+obs.db0_last bit layout +
+
+ +++++++ + + + + + + + + + + + + + + + + + + +
BitsFieldAccessResetDescription (SystemRDL of the example)

31:0

value

RO (hw-written)

0

Last ACT-CAP command word written by core 0.

+
+
+
obs.db1_hits — offset 0x048
+
+
+obs.db1_hits bit layout +
+
+ +++++++ + + + + + + + + + + + + + + + + + + +
BitsFieldAccessResetDescription (SystemRDL of the example)

31:0

value

RO (hw-written)

0

Doorbell stores accepted, core 1 (saturating).

+
+
+
obs.db1_last — offset 0x04C
+
+
+obs.db1_last bit layout +
+
+ +++++++ + + + + + + + + + + + + + + + + + + +
BitsFieldAccessResetDescription (SystemRDL of the example)

31:0

value

RO (hw-written)

0

Last ACT-CAP command word written by core 1.

+
+
+
obs.actcap0 — offset 0x050
+
+
+obs.actcap0 bit layout +
+
+ +++++++ + + + + + + + + + + + + + + + + + + +
BitsFieldAccessResetDescription (SystemRDL of the example)

31:0

value

RO (hw-written)

0

TIP beats CONVERTED into ACT-CAP by the adapter, core 0.

+
+
+
obs.actcap1 — offset 0x054
+
+
+obs.actcap1 bit layout +
+
+ +++++++ + + + + + + + + + + + + + + + + + + +
BitsFieldAccessResetDescription (SystemRDL of the example)

31:0

value

RO (hw-written)

0

TIP beats CONVERTED into ACT-CAP by the adapter, core 1.

+
+
+
obs.shared_sz — offset 0x058
+
+
+obs.shared_sz bit layout +
+
+ +++++++ + + + + + + + + + + + + + + + + + + +
BitsFieldAccessResetDescription (SystemRDL of the example)

31:0

value

RO (hw-written)

0

Shared memory size in bytes (SHARED_KIB * 1024).

+
+
+
obs.magic — offset 0x05C
+
+
+obs.magic bit layout +
+
+ +++++++ + + + + + + + + + + + + + + + + + + +
BitsFieldAccessResetDescription (SystemRDL of the example)

31:0

value

RO (hw-written)

0x52564349

0x5256_4349 ("RVCI"). The probe that says THIS design is in the PL — an app listed by xmutil is not evidence.

+
+
+
+

35.6.6. Registers of console (base 0x60)

+
+

Per-core console

+
+
+
console.con0_stat — offset 0x060
+
+

Core 0 console status.

+
+
+
+console.con0_stat bit layout +
+
+ +++++++ + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsFieldAccessResetDescription (SystemRDL of the example)

31:16

tx_cnt

RO (hw-written)

0

Bytes waiting in the core’s TX FIFO.

15:0

rx_free

RO (hw-written)

0

Free space in the core’s RX FIFO.

+
+
+
console.con0_pop — offset 0x064
+
+

Core 0 TX pop. READING THIS REGISTER POPS one character.

+
+
+
+console.con0_pop bit layout +
+
+ +++++++ + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsFieldAccessResetDescription (SystemRDL of the example)

31

valid

RO (hw-written)

0

1: data valid — 0: FIFO was empty.

7:0

data

RO (hw-written)

0

The popped character.

+
+
+
console.con0_push_drops — offset 0x068
+
+
+console.con0_push_drops bit layout +
+
+ +++++++ + + + + + + + + + + + + + + + + + + +
BitsFieldAccessResetDescription (SystemRDL of the example)

31:0

value

RW

0

Core 0: WRITE pushes one character into the core’s RX FIFO; READ returns the RX overflow counter (pushes dropped because the FIFO was full — counted, never silent).

+
+
+
console.con1_stat — offset 0x070
+
+

Core 1 console status.

+
+
+
+console.con1_stat bit layout +
+
+ +++++++ + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsFieldAccessResetDescription (SystemRDL of the example)

31:16

tx_cnt

RO (hw-written)

0

Bytes waiting in the core’s TX FIFO.

15:0

rx_free

RO (hw-written)

0

Free space in the core’s RX FIFO.

+
+
+
console.con1_pop — offset 0x074
+
+

Core 1 TX pop. READING THIS REGISTER POPS one character.

+
+
+
+console.con1_pop bit layout +
+
+ +++++++ + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsFieldAccessResetDescription (SystemRDL of the example)

31

valid

RO (hw-written)

0

1: data valid — 0: FIFO was empty.

7:0

data

RO (hw-written)

0

The popped character.

+
+
+
console.con1_push_drops — offset 0x078
+
+
+console.con1_push_drops bit layout +
+
+ +++++++ + + + + + + + + + + + + + + + + + + +
BitsFieldAccessResetDescription (SystemRDL of the example)

31:0

value

RW

0

Core 1: WRITE pushes into RX; READ returns the RX overflow count.

+
+
+
+

35.6.7. Registers of ring0 (base 0x80)

+
+

DDR record ring (one instance per core)

+
+
+
ring0.ring_ctrl — offset 0x080
+
+

Ring control. Switch the route only with the cores stopped and a clear pulse issued — a mid-record switch tears one record across the two consumers.

+
+
+
+ring0.ring_ctrl bit layout +
+
+ +++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsFieldAccessResetDescription (SystemRDL of the example)

3

route_ddr

RW

0

1: records go to the ring — 0: to the MM-FIFO (default, pre-N3 behaviour).

2

circ

RW

1

1: circular (wrap) — 0: one shot.

1

clear

RW

0

Write-1 pulse: clear wptr/stat/beats. Use while en = 0.

0

en

RW

0

Enable the sink.

+
+
+
ring0.ring_base — offset 0x084
+
+
+ring0.ring_base bit layout +
+
+ +++++++ + + + + + + + + + + + + + + + + + + +
BitsFieldAccessResetDescription (SystemRDL of the example)

31:0

value

RW

0x50000000

Ring base address. WARL: 32-byte aligned and inside [0x5000_0000, 0x6000_0000); writes while en = 1 are rejected and set cfg_rej. Reset: 0x5000_0000 (core 0) / 0x5800_0000 (core 1) — the two halves of the 256-MiB reserved window.

+
+
+
ring0.ring_size — offset 0x088
+
+
+ring0.ring_size bit layout +
+
+ +++++++ + + + + + + + + + + + + + + + + + + +
BitsFieldAccessResetDescription (SystemRDL of the example)

31:0

value

RW

0x8000000

Ring size in bytes. WARL: multiple of 32, non-zero, and base + size within the window (an exact fit at the window end is legal); writes while en = 1 are rejected. Reset: 128 MiB.

+
+
+
ring0.ring_wptr — offset 0x08C
+
+
+ring0.ring_wptr bit layout +
+
+ +++++++ + + + + + + + + + + + + + + + + + + +
BitsFieldAccessResetDescription (SystemRDL of the example)

31:0

value

RO (hw-written)

0

TOTAL bytes written, monotonic — NOT an offset. The write offset is wptr % size; when wrapped, the oldest record starts there and the host re-orders [off..size) +\+ [0..off).

+
+
+
ring0.ring_stat — offset 0x090
+
+

Ring status.

+
+
+
+ring0.ring_stat bit layout +
+
+ +++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
BitsFieldAccessResetDescription (SystemRDL of the example)

3

cfg_rej

RO (hw-written)

0

Sticky: a base/size write was rejected (illegal value, or arrived while enabled). Cleared by the clear pulse.

2

wrapped

RO (hw-written)

0

Circular mode: wrapped at least once.

1

axi_err

RO (hw-written)

0

Sticky: a write response was not OKAY.

0

full

RO (hw-written)

0

One-shot mode only: buffer full.

+
+
+
ring0.ring_drops — offset 0x094
+
+
+ring0.ring_drops bit layout +
+
+ +++++++ + + + + + + + + + + + + + + + + + + +
BitsFieldAccessResetDescription (SystemRDL of the example)

31:0

value

RO (hw-written)

0

Records the sink itself had to drop (its FIFO was full), saturating. At record rates this must stay 0 — the bench and rvmon both treat any nonzero value as a failed run.

+
+
+
ring0.ring_beats — offset 0x098
+
+
+ring0.ring_beats bit layout +
+
+ +++++++ + + + + + + + + + + + + + + + + + + +
BitsFieldAccessResetDescription (SystemRDL of the example)

31:0

value

RO (hw-written)

0

Words offered to the sink while enabled: the proof that the feed reaches it at all. wptr = 4 * beats in a healthy run. Cleared by the clear pulse.

+
+
+
+

35.6.8. Core-side map (not reachable from the PS)

+
+

Core-side map (identical for both cores)

+
+
+

Offsets are addresses on the RISC-V cores' own bus; the map is identical for both cores.

+
+ +++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
OffsetComponentKindSizeContent

0

ram

memory

64 KiB

Own program/data RAM 16384 entries of 32 bit.

0x10000000

periph

memory

64 KiB

Own CLINT / INTC 16384 entries of 32 bit.

0x20000000

encoder

address map

24696 B

CEDARtools.TraceEncoder Control / Status Registers

0x30000000

shared

memory

256 KiB

Shared memory — the SAME view from both cores 65536 entries of 32 bit.

0x40000000

actcap_doorbell

register

4 B

ACT-CAP doorbell

+
+
+
+

35.7. The interrupt peripherals of the example SoC

+
+

The example SoC instantiates two small peripherals that the trace subsystem does not use and a booting core does: a core-local interruptor providing a machine timer and a software interrupt, and a minimal external interrupt controller with a single software-triggerable source. Their register names — msip, mtimecmp, mtime — are the names the RISC-V privileged architecture uses for those facilities, and reusing them is what makes the example’s startup code look like ordinary RISC-V startup code.

+
+
+

Neither block is a conformant implementation of the corresponding standard peripheral, and neither claims to be. The SystemRDL calls each one a deliberately minimal teaching peripheral: five registers where a full core-local interruptor has per-hart arrays, two registers where a platform-level interrupt controller has priority, threshold and claim/complete machinery. Their register tables are therefore not printed in this manual. Two reasons, in this order: a reader who needs them is working in the example’s own source tree, where examples/kv260/common/tgc5b/rdl/ct_soc/ct_clint.rdl and ct_intc.rdl are twenty-odd lines each and authoritative; and a table in a CEDARtools manual, printed in the same form as the encoder registers, would suggest a conformance claim that the blocks do not make.

+
+
+

The address at which each block sits is printed — it is part of the address space, and Section 35.4 shows it in both the data-bus view and the generated peripheral block.

+
+
+ + + + + +
+
Note
+		 +For the machine-mode timer and software-interrupt facilities these two blocks stand in for, the normative document is the RISC-V privileged architecture specification (riscv/riscv-isa-manual). It is named here for orientation only. It is not one of the specifications CTTE is verified against — those four, and the conformance statement for each, are in Chapter 36 and Chapter 4. +
+
+
+
+
+
+

36. References

+
+
+

This chapter lists the normative specifications, source repositories, tools, and related Accemic documents behind CEDARtools.TraceEncoder (CTTE). Where a predecessor reference could not be re-verified against a live source, it is marked accordingly instead of being carried over silently.

+
+
+

36.1. Standards and specifications

+
+

CTTE targets four public specifications. The authoritative in-repo
+statement of which parts of each are implemented, and which deviations
+exist, is
+doc/trace-format.adoc
+(conformance section) in the public repository; this reference list only
+points to the source documents themselves.

+
+ ++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
SpecificationPublic source

The Nexus 5001 Forum™ Standard for a Global Embedded Processor Debug Interface, IEEE-ISTO 5001-2012, v3.0.1

riscv-nexus-trace — cited under the :nexus-spec: attribute in doc/architecture.adoc, doc/trace-format.adoc and doc/enhanced-features.adoc.

RISC-V N-Trace (Nexus-based Trace) Specification, Version 1.0 (ratified 2024-11-21), RISC-V International

riscv-non-isa/riscv-nexus-trace (working repository of the RISC-V Nexus Trace Task Group; also hosts the Trace Control Interface and Trace Connectors specifications). CTTE’s own citation for the N-Trace text points to riscv-non-isa/riscv-trace-spec (doc/trace-format.adoc, its specification-link attributes) — both repositories currently serve N-Trace content; consult the upstream Task Group for the current split.

RISC-V Trace Control Interface Specification, Version 1.0 (ratified 2024-11-21), RISC-V International

docs.riscv.org (cited in doc/architecture.adoc)

Efficient Trace for RISC-V, Version 2.0 (ratified 2022-05-05), RISC-V International — the E-Trace te_inst packet format CTTE’s E-Trace profile emits (ct_L2_te_inst_gen, see doc/integration.adoc, "Trace egress")

riscv-non-isa/riscv-trace-spec

NexRv Tool (Nexus trace for RISC-V) description

see Section 36.5 (accemic/CTTD, which absorbed the earlier NexRv fork)

+
+
+

36.2. Core and trace-source adapters

+
+

Sources for the cores CTTE’s ingress side is verified against, and for the RTL that adapts each core’s native trace/retire interface to CTTE’s TIP (tip_if, rtl/pkg/tip_pkg.sv):

+
+ ++++ + + + + + + + + + + + + + + + + + + + + + + + + +
Core / interfaceWhere the adapter lives

MicroBlaze™ V TRACE bus

rtl/adapters/amd_microblaze_v/ (RTL); semantics and signal mapping in doc/adapters/microblaze_v_adapter_mapping.adoc, microblaze_v_trace_ports.adoc, microblaze_v_trace_semantics.adoc, microblaze_v_supported_configurations.adoc, and the itype decode vectors in itype_decoder_vectors.csv.

CVA6 Instruction Trace Interface (ITI)

rtl/adapters/cva6/ (RTL: cva6_iti_to_ctte_tip.sv, cva6_riscv_itype_refine.sv); semantics in doc/adapters/cva6_iti_semantics.adoc. The upstream CVA6 ITI itself was added in OpenHW Group’s cva6 repository, commit f314dcb1 ("Instruction Trace Interface", PR #2927; verified reachable 2026-08-18).

Rocket Trace Core Interface (TCI)

rtl/adapters/rocket/ (RTL: rocket_tci_to_ctte_tip.sv); semantics in doc/adapters/rocket_tci_semantics.adoc.

MINRES TGC5B (TGC5B_AXI4L_H2E), example-SoC core only

Vendored verbatim at examples/kv260/common/tgc5b/cpu/TGC5B_AXI4L_H2E.sv; provenance and dual license (CERN-OHL-S-2.0 OR LicenseRef-MINRES-Commercial) in examples/kv260/common/tgc5b/cpu/README.md. Not part of the CTTE IP itself — see Chapter 37.

+
+ + + + + +
+
Note
+		 +The predecessor document listed a partner-channel TRISTAN Trace IP repository (git.minres.com/TRISTAN/TraceIP) for MINRES integration collateral. That host requires partner/internal credentials and was not re-verified here; it is not a public reference. +
+
+
+
+

36.3. Tools

+ +++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
ToolVersion (as pinned)Purpose / source

abc-flow

pinned per .abc.config

Text-defined, Vivado-based build driver for every make target. Public repository: accemic/abc-flow (verified 2026-08-18).

Verilator

resolved via VERILATOR_ROOT (see doc/development.adoc)

Default simulation backend (make sim, coverage runs). Project: veripool.org/verilator. Guided by the CHIPS Alliance and Linux Foundation.

Xilinx® Vivado™

pinned in .abc.config

Alternate simulation backend for the cli_* gate battery (abc --sim-backend vivado -sim …​); required for the xsim-based byte-neutrality and gate scripts (doc/development.adoc).

Verible (verible-verilog-lint)

n/a (opt-in ruleset, .rules.verible_lint)

Static lint for rtl/ and tests/, invoked by make lint. Project: chipsalliance/verible (CHIPS Alliance).

PeakRDL toolchain (peakrdl, peakrdl-regblock, peakrdl-html, systemrdl-compiler)

1.5.0 / 1.3.1 / 2.12.2 / 1.32.2

Register (RDL) flow: make rdl / make rdl-html; versions pinned in rdl/requirements.txt. Project: peakrdl.readthedocs.io.

CTTD reference decoder (bin/cttd-<platform>)

pinned by version and per-platform sha256 in scripts/cttd.pin

Offline oracle decoder used by scripts/decode_and_check.sh. Fetched by scripts/fetch_cttd.py, never committed; descended from the IAR Systems NexRv tool. See Section 29.4.

+
+
+

36.4. Related Accemic documents

+
+
    +
  • +

    The public documentation set in the TraceEncoder repository (doc/architecture.adoc, doc/development.adoc, doc/enhanced-features.adoc, doc/integration.adoc, doc/release-notes.adoc, doc/trace-format.adoc, doc/verification.adoc, doc/adapters/*.adoc) is this Reference Manual’s primary technical source for RTL-facing content; where this RM condenses or reorganizes that material, the public chapter is the fuller treatment.

    +
    • +
  • +

    doc/release-notes.adoc — version history and the profile-level resource/timing figures cited in the Footprint profiles chapter.

    +
    • +
  • +

    This Reference Manual’s own predecessor, rm-ctrace.adoc (revisions 1.0 to 1.3), which this edition supersedes. It was removed from the doc repository when this edition replaced it and remains available in the repository history; an internal migration plan records what changed and why.

    +
    • +
  • +

    CEDARtools.TraceDecoder (CTTD) — the reference decoder, public under accemic/CTTD since 2026-08-27 with sealed binary releases (current v2.3.0-cttd3: three platform binaries plus SHA256SUMS); CTTE pins it by tag and checksum in scripts/cttd.pin.

    +
    • +
+
+
+
+

36.5. Public repositories

+ +++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
RepositoryPublic URLNotes

CEDARtools.TraceEncoder

accemic/TraceEncoder

The GitHub address is the repository’s public home and the one its own README links. The earlier short name C-Trace is retired from prose and survives only in identifiers and in names fixed outside the repository (Chapter 1); addresses built from it are not guaranteed to resolve and should not be relied on.

CEDARtools.TraceDecoder (CTTD)

accemic/CTTD

The reference decoder (previous section), derived from the IAR Systems NexRv tool; its earlier repository names (most recently NexRv-for-TraceEncoder) redirect to the current one (verified 2026-08-28). Every decode verdict in this manual is CTTD’s; see Section 29.4.

CTXP format specification

accemic/CTXP-format

"Format Specification for Unified Processor Trace." Renamed from its C-Trace-era name; the encoder repository’s verification chapter cites the current name directly. Not the same repository as CTTD (previous row).

Trace-FS (TRISTAN demonstrator)

Fraunhofer-IPMS-DCC/Trace-FS

Functional-safety (ISO 26262 / IEC 61508) tracing demonstrator on a KR260 lockstep RISC-V subsystem (Fraunhofer IPMS EMSA5), with a TSN trace link. The encoder integrated in the repository as published is an earlier C-Trace release, predating CTTE release 1.0.0 — its README already uses the CEDARtools.TraceEncoder name, but nothing in this manual’s verification evidence covers that integration (checked 2026-08-27).

Trace-Link

Fraunhofer-IPMS-DCC/Trace-Link

IP core packaging ATB trace data into IPv4/UDP Ethernet frames over AXI4-Stream, used by the Trace-FS demonstrator.

abc-flow

accemic/abc-flow

Build driver, see Section 36.3 above.

+
+

All URLs in this section were confirmed reachable on 2026-08-28. Several carry a rename history (old names still resolve via GitHub’s redirect); where this document’s own predecessor cited the pre-rename name, that is called out above rather than silently updated.

+
+
+
+

36.6. TRISTAN acknowledgment

+
+

Parts of CTTE were developed as part of the TRISTAN project, a European Union research initiative. The full acknowledgment text and funding reference are given in README.md of the public repository: TRISTAN, project no. 101095947, is supported by the Chips Joint Undertaking (CHIPS-JU) and its member states; see https://tristan-project.eu/ for details.

+
+
+
+

36.7. Related ecosystem references

+
+

Prior art and adjacent open trace implementations referenced during CTTE’s development (all links verified reachable 2026-08-18):

+
+
+ +
+
+
+
+
+ +
+
+

This chapter states two separate things that must not be conflated: the license of this documentation, and the license of the CEDARtools.TraceEncoder (CTTE) IP it describes. It also states the trademark rules that apply when writing about CTTE, RISC-V, and the cores and tools it interoperates with.

+
+
+

37.1. This document’s license

+
+

Copyright © 2026 Accemic Technologies GmbH. This document (and CTTE’s documentation generally) is licensed under the Creative Commons Attribution 4.0 International License (CC BY 4.0). Under this license the work may be shared and adapted for any purpose, including commercial, provided appropriate credit is given, a link to the license is provided, and any changes are indicated. Full legal text: https://creativecommons.org/licenses/by/4.0/legalcode.en (plaintext: https://creativecommons.org/licenses/by/4.0/legalcode.txt), SPDX identifier CC-BY-4.0.

+
+
+ + + + + +
+
Note
+		 +The IP-core license of the CTTE encoder itself is separate from
+this documentation license and is described in
+IP license model below. +
+
+
+

37.1.1. References used, and attribution for excerpts

+
+

This document, and CTTE’s public documentation generally, cites and/or draws on the following technical specifications; excerpts, paraphrases, or derived explanations from these sources are credited accordingly (title, author, source, license):

+
+
+
    +
  • +

    RISC-V N-Trace (Nexus-based Trace) Specification, Version 1.0 (ratified 2024-11-21), RISC-V International; CC BY 4.0 per the document’s own copyright and license section. Source: see the References chapter.

    +
    • +
  • +

    RISC-V Trace Control Interface Specification, Version 1.0 (ratified 2024-11-21), RISC-V International; CC BY 4.0, same terms.

    +
    • +
  • +

    Efficient Trace for RISC-V, Version 2.0 (ratified 2022-05-05), RISC-V International; CC BY 4.0 per the source repository’s LICENSE file.

    +
    • +
  • +

    The Nexus 5001 Forum™ Standard for a Global Embedded Processor Debug Interface, IEEE-ISTO 5001-2012 v3.0.1, IEEE Industry Standards and Technology Organization (IEEE-ISTO) / Nexus 5001 Forum. Not CC BY 4.0 — this document carries its own copyright terms, which are reproduced in Section 37.1.2 below as those terms require.

    +
    • +
+
+
+

Where this document quotes, paraphrases, or adapts figures or tables from the three RISC-V International specifications above, that content is marked and attributed, and modifications are identified, consistent with CC BY 4.0’s attribution and "indicate changes" requirements. Material from the Nexus standard is covered by Section 37.1.2 instead. Citing or excerpting these specifications does not imply endorsement by RISC-V International, the IEEE-ISTO, or any contributor to the cited specifications, and no affiliation is claimed beyond citation and attribution.

+
+
+

A copy of the CC BY 4.0 license (or its URL) accompanies any redistributed or adapted version of this work, with attribution retained and changes identified.

+
+
+
+

37.1.2. Notice required by the Nexus 5001 Forum™ standard

+
+

This manual explains and assists in the implementation of the Nexus standard and quotes field descriptions from it. The standard permits exactly that, on the condition that its copyright notice, the paragraph below and the document title are carried on every such work. They are therefore reproduced here verbatim:

+
+
+
+
+

Copyright © 2012 IEEE-ISTO. All rights reserved.

+
+
+

This document may be copied and furnished to others, and derivative works that comment on, or otherwise explain it or assist in its implementation may be prepared, copied, published and distributed, in whole or in part, without restriction of any kind, provided that the above copyright notice, this paragraph and the title of the Document as referenced below are included on all such copies and derivative works. However, this document itself may not be modified in any way, such as by removing the copyright notice or references to the IEEE-ISTO and the Nexus 5001 Forum™.

+
+
+

Title: The Nexus 5001 Forum™ Standard for a Global Embedded Processor Debug Interface, Version 3.0

+
+
+
+— IEEE-ISTO 5001-2012 v3.0.1
+Copyright notice +
+
+
+

The IEEE-ISTO and the Nexus 5001 Forum™ disclaim all warranties, express or implied, for the standard itself; that disclaimer is theirs and is not repeated on Accemic’s behalf. The standard may be updated, replaced or made obsolete at any time; this manual describes CTTE against the version named above.

+
+
+

This document is provided "as-is" without warranties of any kind; CC BY 4.0 does not imply endorsement or constitute legal advice. All product names, logos, and brands mentioned remain the property of their respective owners; see Trademarks and naming below for the specific rules that apply to this repository.

+
+
+

For attribution corrections, permissions beyond CC BY 4.0, or questions about included third-party material, contact info@accemic.com.

+
+
+
+
+

37.2. IP license model

+
+

CTTE is licensed per artifact type: which license applies to a given file is declared by that file’s own SPDX-License-Identifier header, or — for files that cannot carry a header — by REUSE.toml. The repository states that it is REUSE-compliant, so the machine-readable headers are the authoritative statement; this chapter is the human-readable summary (LICENSE.md). The full text of every license used ships in LICENSES/.

+
+ +++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
ArtifactWhat it coversLicense

Hardware IP

RTL (.sv), register description (.rdl), timing/placement constraints (.xdc), and the SystemVerilog/.abc verification testbenches

CERN-OHL-S-2.0 OR LicenseRef-Accemic-Commercial (dual)

Software

Build, tooling and CI — shell/Python scripts, Makefile, GitHub workflows, config and metadata

ISC

Documentation

Markdown, AsciiDoc, and documentation images

CC-BY-4.0

Third-party IP

MINRES TGC5B core, vendored for the example SoC (examples/kv260/common/tgc5b/cpu/)

CERN-OHL-S-2.0 OR LicenseRef-MINRES-Commercial (dual — licensed by MINRES, not Accemic)

Fetched, not vendored

the CTTD reference decoder under bin/ (gitignored; descended from the IAR Systems NexRv tool)

ISC upstream; CTTD itself is a separate Accemic product under its own terms and is not conveyed with this repository

+
+

37.2.1. Hardware IP — dual license

+
+

The hardware design and its testbenches are dual-licensed. Either:

+
+
+
    +
  1. +

    CERN Open Hardware License Version 2 — Strongly Reciprocal (CERN-OHL-S-2.0) — the default open-source license. It ensures modifications and derivative works remain open when distributed. Full text: LICENSES/CERN-OHL-S-2.0.txt; SPDX record: https://spdx.org/licenses/CERN-OHL-S-2.0.html.

    +
    2. +
  2. +

    Accemic Commercial License — for organizations that require integration without the copyleft obligations of CERN-OHL-S-2.0. Text: LICENSES/LicenseRef-Accemic-Commercial.txt. Inquiries: sales@accemic.com.

    +
    3. +
+
+
+

The SPDX expression on these files is
+SPDX-License-Identifier: CERN-OHL-S-2.0 OR LicenseRef-Accemic-Commercial.

+
+
+
+

37.2.2. Third-party IP — the MINRES TGC5B core

+
+

examples/kv260/common/tgc5b/cpu/TGC5B_AXI4L_H2E.sv is not Accemic’s work: it is the MINRES TGC5B RISC-V core (Copyright 2020-2022 MINRES Technologies GmbH), vendored so the integration example builds and simulates against a real core. MINRES has permitted its publication under the same dual-license structure this repository uses for its own hardware IP: SPDX-License-Identifier: CERN-OHL-S-2.0 OR LicenseRef-MINRES-Commercial — but MINRES, not Accemic, is the licensor of both arms (LICENSES/LicenseRef-MINRES-Commercial.txt). Accemic conveys the file verbatim under CERN-OHL-S-2.0 and holds no right to sublicense it: the file is byte-identical to MINRES' delivery, and its SPDX metadata lives in a REUSE .license sidecar so the upstream notices stay intact. A commercial license for the core comes from MINRES only; an Accemic commercial license for the encoder conveys no rights to the core, and vice versa. The permission covers this specific delivered netlist (core configuration TGC5B_AXI4L_H2E) only, not other TGC5B configurations or versions. The encoder IP itself does not depend on the core — nothing under rtl/, rdl/, or tests/ references it.

+
+
+

What this means when shipping a product:

+
+ ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
You want to shipEncoderTGC5B coreLicense(s) needed

An open-source design

CERN-OHL-S-2.0

CERN-OHL-S-2.0

none — both open arms apply

A closed-source design with your own core

Accemic commercial

not used

Accemic only

A closed-source design containing the TGC5B

Accemic commercial

MINRES commercial

both, negotiated separately

Evaluation, simulation, internal development

either

either

none

+
+

The third row follows from CERN-OHL-S-2.0 itself: including Covered Source in a larger work makes the larger work modified Covered Source (§3.2), and conveying a Product built from it requires providing the Complete Source (§4). Keeping the TGC5B in a product therefore keeps the product under CERN-OHL-S-2.0 regardless of the encoder’s license. The second row is the usual case — the example SoC is a worked integration, not part of the IP deliverable, and integrators bring their own core.

+
+
+
+

37.2.3. Software — ISC

+
+

Build scripts, tooling, CI, and configuration are licensed under the permissive ISC license. Full text: LICENSES/ISC.txt.

+
+
+
+

37.2.4. Documentation — CC BY 4.0

+
+

Public documentation (Markdown, AsciiDoc) and documentation images are licensed under CC-BY-4.0 — shareable and adaptable with attribution. Full text: LICENSES/CC-BY-4.0.txt. This is the IP repository’s documentation license; this internal Reference Manual carries its own, separately stated, CC BY 4.0 header above.

+
+
+
+

37.2.5. The reference decoder is fetched, not vendored

+
+

No decoder binary is part of this repository. Earlier revisions of this manual described a committed bin/NexRv built from an Accemic fork of the IAR Systems NexRv tool (ISC); that fork is superseded by CTTD (CEDARtools.TraceDecoder) and the binaries left the tree on 2026-08-17. bin/ is gitignored and holds whatever scripts/fetch_cttd.py places there against the pin in scripts/cttd.pin (Section 29.4). CTTD is a separate Accemic product under its own licence terms, not a component of the CTTE delivery, and REUSE.toml therefore carries no entry for it. The NexRv lineage remains relevant as provenance — CTTD descends from the RISC-V Nexus Trace Task Group reference code, copyright IAR Systems AB and Accemic Technologies GmbH, ISC-licensed — but nothing in this repository conveys it.

+
+
+
+

37.2.6. Commercial licensing

+
+

Organizations that cannot comply with the copyleft obligations of CERN-OHL-S-2.0 for the hardware IP may obtain a commercial license from Accemic Technologies GmbH. Inquiries: sales@accemic.com. That license covers the CTTE IP — everything in rtl/, rdl/, tests/, and the Accemic-authored parts of examples/. It does not cover the vendored MINRES TGC5B core, which carries its own dual license from MINRES (see above).

+
+
+
+

37.2.7. Evaluation

+
+

Per LICENSE.md, evaluation, simulation, and internal development use of the hardware IP requires no license beyond choosing either the open (CERN-OHL-S-2.0) or the commercial arm — there is no additional gate for internal-only assessment stated in the current license documents.

+
+
+
+
+

37.3. Contributions and the Contributor License Agreement (CLA)

+
+

To preserve the dual-license option for the hardware IP, contributions require acceptance of a Contributor License Agreement (CLA) assigning the necessary rights to Accemic Technologies GmbH, while the contributor retains copyright over their own work. Contact info@accemic.com to arrange the CLA before a contribution can be merged (CONTRIBUTING.md).

+
+
+

The CLA is not a standalone document in this repository; it is arranged by contacting Accemic directly. CONTRIBUTING.md’s quick checklist for a pull request also requires: a branch named `<handle>/<short-description> off main; every new file carrying its SPDX header; make lint and make sim passing; regenerated RDL output committed alongside any rdl/ct_cs_cpuif.rdl change; commit messages that explain why; and CI green (lint, make sim and make sim-examples under Verilator, REUSE) plus at least one maintainer review before merge.

+
+
+

Contributors who do not sign the CLA are not thereby excluded from using the project: the hardware IP’s open arm, CERN-OHL-S-2.0, applies regardless of CLA status to anyone using, modifying, or redistributing it on that license’s terms (strong copyleft applies to redistributed modifications either way). What the CLA specifically enables is upstream inclusion under the maintainers' dual-license offering.

+
+
+
+

37.4. Mechanisms described by earlier revisions

+
+

Revisions up to 1.3 of this manual described five licensing mechanisms that no longer exist: a CLA-gated feature switch (LICENSED_FEATURES) that would have enabled part of the functionality only for signatories, a "community branch" for contributions without a signed CLA, a separate Evaluation License Agreement, a name- and logo-use restriction tied to CLA status, and a dedicated attribution obligation for third-party implementations of ACT-CAP and ACT-ST.

+
+
+

All five belong to an earlier plan under which the encoder would have been published as two repository states — an open one and a commercial one with additional functionality. That plan was dropped in favour of releasing the full encoder and differentiating through the dual license instead. With one repository and one feature set, a mechanism that gates functionality by license status has nothing left to gate, and the constructs built around it became unnecessary along with it.

+
+
+

They are named here rather than silently removed, because a reader who knows the earlier manual will look for them. The terms that apply are the ones in Section 37.2: the same code for everyone, under whichever arm of the dual license the user chooses.

+
+
+
+

37.5. ACT-CAP / ACT-ST attribution

+
+

The Accemic CEDARtools CSR Access Protocol (ACT-CAP) and CEDARtools Smart Trigger (ACT-ST) mechanisms are implemented in the hardware IP (rtl/) and are covered by the same dual license as the rest of the hardware IP — see Section 37.2. No additional attribution obligation beyond that license is currently sourced for third-party implementations of these mechanisms.

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37.6. Trademarks and naming

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CEDARtools is a registered trademark of Accemic Technologies GmbH. Its use in this project’s name (CEDARtools.TraceEncoder) and documentation identifies the project’s origin; it does not grant any trademark rights beyond what the licenses above state.

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CTTE implements and references several open specifications and interoperates with third-party tools. Third-party marks appear only descriptively, to identify those specifications, interfaces, and tools (nominative use). Their use does not imply any affiliation with, sponsorship by, or endorsement by the trademark owners.

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37.6.1. Attribution

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    CEDARtools and Accemic are trademarks of Accemic Technologies GmbH.

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    RISC-V, RISC-V International, and the RISC-V logos are trademarks of RISC-V International.

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    MicroBlaze™, Vivado™, Xilinx™, and Kria™ are trademarks of Advanced Micro Devices, Inc.

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    Arm®, AMBA®, AXI®, ATB®, and CoreSight™ are trademarks or registered trademarks of Arm Limited (or its affiliates).

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    Nexus and IEEE-ISTO 5001 are marks of the IEEE Industry Standards and Technology Organization (IEEE-ISTO) / Nexus 5001 Forum.

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    IAR and IAR Systems are trademarks of IAR Systems AB.

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    All other product names, logos, and brands are the property of their respective owners and are used for identification only; such use does not imply affiliation, sponsorship, or endorsement.

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37.6.2. Use of the RISC-V mark

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Accemic Technologies GmbH is not a member of RISC-V International. The mark therefore appears only in its descriptive sense — naming the architecture and the specifications this encoder targets, as in "trace encoder for RISC-V cores" or "implements the RISC-V N-Trace specification."

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This repository, and this Reference Manual, must not:

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    use the RISC-V logo;

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    use "RISC-V" as part of the product, module, or domain name — the product is CEDARtools.TraceEncoder, and RISC-V only describes what it targets;

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    claim membership, partnership, certification, approval, or endorsement;

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    claim conformance or compatibility certified by any official RISC-V programme. Deviations from the specifications are listed openly (see the Standards baseline and Conformance chapters, Part A), and the vendor TCODEs 56/57/58 are Accemic extensions that imply no claim of standard conformance.

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"RISC-V" is written in block letters with a hyphen; the only admissible spellings are RISC-V and RISC-V International.

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37.7. Summary of obligations

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ScenarioLicense neededKey obligations

Use, modify, or redistribute the hardware IP under the open arm

CERN-OHL-S-2.0

Strong copyleft on redistributed modifications; provide Complete Source when conveying a Product built from it (§4).

Contribute changes intended for upstream inclusion

CLA (in addition to using either license arm)

Grants Accemic the rights needed to keep offering the dual-license model; contact info@accemic.com. Contributions without a CLA remain usable under CERN-OHL-S-2.0 on that license’s own terms, but are not merged upstream.

Integrate the encoder in a closed-source product with your own core

Accemic Commercial License

No copyleft disclosure obligation; contact sales@accemic.com.

Integrate the encoder together with the vendored MINRES TGC5B core in a closed-source product

Accemic Commercial License and a MINRES Commercial License, negotiated separately

Neither commercial license alone covers the other party’s IP.

Evaluate, simulate, or develop internally without redistribution

either license arm

No additional license needed beyond choosing CERN-OHL-S-2.0 or the commercial arm.

Use, adapt, or redistribute this documentation

CC-BY-4.0

Attribution, link to the license, indicate changes.

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+ + + \ No newline at end of file diff --git a/doc/rm-ctte.pdf b/doc/rm-ctte.pdf new file mode 100644 index 0000000..d50dc16 Binary files /dev/null and b/doc/rm-ctte.pdf differ diff --git a/doc/trace-format.adoc b/doc/trace-format.adoc index 5fdb0e5..f358298 100644 --- a/doc/trace-format.adoc +++ b/doc/trace-format.adoc @@ -5,15 +5,19 @@ :toc: macro :toclevels: 3 :nexus-spec: https://github.com/riscv-non-isa/riscv-nexus-trace/blob/main/docs/nexus-standard/IEEE-ISTO-5001-2012-v3.0.1-Nexus-Standard.pdf +:ntrace-spec: https://docs.riscv.org/reference/nexus-trace/index.html +:etrace-spec: https://docs.riscv.org/reference/e-trace/v2.0/index.html -CEDARtools.TraceEncoder emits trace messages following the -https://github.com/riscv-non-isa/riscv-trace-spec[RISC-V N-Trace +CEDARtools.TraceEncoder (CTTE) emits trace messages following the +{ntrace-spec}[RISC-V N-Trace specification], which is a RISC-V interpretation of the {nexus-spec}[**IEEE-ISTO 5001-2012 (Nexus)** standard]. This page summarizes the message types the encoder produces and the synchronization / resource / error sub-codes it uses. The authoritative definitions live in -link:../rtl/pkg/nexus_vendor_riscv_pkg.sv[`rtl/pkg/nexus_vendor_riscv_pkg.sv`]. +link:../rtl/pkg/nexus_vendor_riscv_pkg.sv[`rtl/pkg/nexus_vendor_riscv_pkg.sv`]; +which of them are compiled in is decided by the build switches in +link:../rtl/pkg/ct_pkg.sv[`rtl/pkg/ct_pkg.sv`]. toc::[] @@ -31,107 +35,180 @@ RISC-V N-Trace fixes the interpretation of the address and instruction-count fields for RISC-V, and defines the program-trace, data-trace and synchronization messages that a compliant encoder emits. -NOTE: This page covers the *encoded* MDO/MSEO trace stream. CEDARtools.TraceEncoder also -provides a separate 96-bit *AXI-Stream* output (`axis_if.master`) that -carries ACT-CAP / DAQ instrumentation independently of the Nexus stream — -intended for on-chip consumers (e.g. a runtime verification) that process -instrumentation data inside the fabric rather than off-chip. See +NOTE: This page covers the *encoded* MDO/MSEO trace stream of the +N-Trace backend. CTTE also builds with an alternative +{etrace-spec}[**E-Trace 2.0**] +(`te_inst`) backend — a different wire format, not covered here. Which +of the two an encoder speaks is a *synthesis parameter* of that encoder +instance (`EN_NTRACE` / `EN_ETRACE`), reported read-only in +`trTeProtocolSel`; see link:integration.adoc[Integration]. Independently +of either backend, a +96-bit *AXI-Stream* output (`axis_if.master`) carries ACT-CAP / DAQ +instrumentation for on-chip consumers that process instrumentation data +inside the fabric rather than off-chip; see link:enhanced-features.adoc#axis-output[Enhanced features → Output: AXIS export and the ATB funnel]. -[#where-traceencoder-sits] -=== Where CEDARtools.TraceEncoder sits — at a glance +[#where-ctte-sits] +=== Where CTTE sits — at a glance -image::images/specs-overlap.drawio.png[CEDARtools.TraceEncoder relative to the Nexus and N-Trace specifications,width=400] +image::images/specs-overlap.drawio.png[CTTE relative to the Nexus and N-Trace specifications,width=400] -CEDARtools.TraceEncoder targets the *RISC-V N-Trace specification* v1.0 (ratified +CTTE targets the *RISC-V N-Trace specification* v1.0 (ratified 2024-11-21), a profile of *IEEE-ISTO 5001-2012 (Nexus)* v3.0.1, and aims -for *strict* interoperability with a stock N-Trace decoder. The matrix -shows how each message and capability is treated by the base Nexus -standard, the N-Trace profile, and the CEDARtools.TraceEncoder implementation; the -<> section details only the gaps and deviations. - -[%autowidth, cols="3,^1,^1,2", options="header"] +for *strict* interoperability with a stock N-Trace decoder. It implements +the **complete N-Trace 1.0 program-trace message set in both instruction +trace modes** — history (HTM, `InstMode` = 6) and branch (BTM, +`InstMode` = 3), which satisfies N-Trace Table 8 ("3 OR 6 settable") — +plus the optional bandwidth optimizations of N-Trace chapter 9 and a +small set of Accemic vendor extensions in the Nexus vendor TCODE range. + +The matrix shows how each message and capability is treated by the base +Nexus standard, the N-Trace profile, and the CTTE implementation; the +three right-hand columns name the compile switch, the runtime control +and the CAPS bit that govern it in CTTE. The <> section +details the remaining gaps and the opt-in extensions. + +[cols="3,^1,^1,2,2,2,^1", options="header"] |=== -| Capability / message (TCODE) | Nexus | N-Trace | CEDARtools.TraceEncoder - -4+s| Program / instruction trace -| Program Trace Synchronization (9) | ✔ | ✔ (req.) | ✔ -| Indirect Branch History (28) — HTM | ✔ | ✔ (HTM) | ✔ -| Direct / Indirect Branch w/ Sync (11/12) | ✔ | ✔ | ✔ -| Resource Full (27) — ICNT/HIST overflow | ✔ | ✔ | ✔ -| Direct Branch (3) / Indirect Branch (4) — BTM | ✔ | ✔ (BTM) | ○ intentionally omitted (BTM — bandwidth-inefficient) -| Program Trace Correlation (33) | ✔ | ✔ | ◐ CDF deviation in HTM -| Program Trace Correction (10) | ✔ | optional | ○ - -4+s| Program-trace optimizations (bandwidth) -| Implicit return — infer returns from a call/return stack (≤ 32 deep; `InstImplicitReturnMode`) | — | optional (ch. 9) | ○ -| Sequential jump — infer `LUI`/`AUIPC`-loaded jump targets (`InstEnSequentialJump`) | — | optional (ch. 9) | ○ -| Repeated history — Resource Full RCODE=2 + `HREPEAT` repeat count (`InstEnRepeatedHistory`) | — | optional (ch. 9) | ○ -| Virtual-address MSB elision — skip identical address MSBs (`InstExtendAddrMSB`) | — | optional (ch. 9) | ○ -| Repeat Branch (30) | ✔ | optional | ○ -| Repeat Instruction / w/ Sync (31/32) | ✔ | optional | ○ - -4+s| Context / system -| Ownership / Context (2) | ✔ | ✔ | ○ (planned) -| Device ID (1) | ✔ | optional | ○ -| Debug Status (0) | ✔ | optional | ○ - -4+s| Data trace (outside the N-Trace program-trace profile) -| Data Trace Read / Write (5/6) | ✔ | — | ✔ -| Data Acquisition (7) — DAQ | ✔ (vendor) | — | ✔ - -4+s| Errors / control -| Error (8) + ECODE (variable-length) | ✔ | ✔ | ✔ -| Vendor Config (56) | vendor | — | ○ (planned) - -4+s| Encoding / modes -| MDO/MSEO framing | ✔ | ✔ | ✔ -| Address XOR + LSB-shift compression | ✔ | ✔ | ✔ -| Timestamps | ✔ | ✔ (absolute on sync, delta else) | ✔ (absolute on sync, delta else) -| Message Source (SRC) field | ✔ | ✔ | ✔ -| Vendor SYNC reasons 12/13 | Reserved | Reserved | ◐ deviation (see below) +| Capability / message (TCODE) | Nexus | N-Trace | CTTE | Build switch | Runtime control | CAPS + +7+s| Program / instruction trace +| Program Trace Synchronization (9) | ✔ | ✔ (req.) | ✔ | `CT_EN_QUOTA_SYNC` (trace-output quota cadence modes 1/4 only — the message itself and the other cadence modes are always present) | `trTeControl.InstSyncMode` / `InstSyncMax` | 18 +| Indirect Branch History (28) — HTM | ✔ | ✔ (HTM) | ✔ | — | `trTeControl.InstMode` = 6 | — +| Indirect Branch History w/ Sync (29) | ✔ | ✔ | ✔ | `CT_EN_IBHS` | `trTeInstFeatures.InstEnIbhs` | 8 +| Direct / Indirect Branch w/ Sync (11/12) | ✔ | ✔ | ✔ | — | — | — +| Resource Full (27) — ICNT/HIST overflow | ✔ | ✔ | ✔ | — | — | — +| Direct Branch (3) / Indirect Branch (4) — BTM | ✔ | ✔ (BTM) | ✔ | `CT_EN_BTM` | `trTeControl.InstMode` = 3 (WARL) | — +| Program Trace Correlation (33) | ✔ | ✔ | ✔ | — | — | — + +7+s| Program-trace optimizations (bandwidth) +| Implicit return — infer returns from a call/return stack (16 slots) | — | optional (ch. 9) | ✔ | `CT_EN_IMPLICIT_RETURN` | `trTeInstFeatures.InstEnImplicitReturn` | 0 +| Sequential jump — inferable `LUI`/`AUIPC`-loaded jump targets | — | optional (ch. 9) | ✔ | `CT_SIJUMP` (elaboration attribute) | — (ingress convention) | 6 +| Repeated history — Resource Full RCODE=2 + repeat count | — | optional (ch. 9) | ✔ | `CT_EN_REPEATED_HISTORY` | `trTeInstFeatures.InstEnRepeatedHistory` | 1 +| Repeat Branch (30) | ✔ | optional | ✔ | `CT_EN_REPEAT_BRANCH` | `trTeInstFeatures.InstEnRepeatBranch` | 3 +| Repeat Instruction / w/ Sync (31/32) | ✔ | reserved | ✔ (opt-in — see <>) | `CT_EN_REPEAT_INSTR` | `trTeInstFeatures.InstEnRepeatInstr` | 9 +| Wide instruction count — 16-bit internal ICNT cap | — | — | ✔ [CTTE] | `CT_EN_WIDE_ICNT` | `trTeInstFeatures.InstEnWideIcnt` | 2 +| Jump-target cache (57) | vendor | — | ✔ [CTTE] (64 entries) | `CT_EN_JTC` | `trTeInstFeatures.InstEnJumpTargetCache` | 4 +| Branch prediction (56) | vendor | — | ✔ [CTTE] (512 entries) | `CT_EN_BP` | `trTeInstFeatures.InstEnBranchPrediction` | 5 +| Virtual-address MSB elision (`InstExtendAddrMSB`) | — | optional (ch. 9) | ○ (measured: zero benefit at 32-bit addresses — LZS is already byte-minimal; planned with RV64/X2) | — | — | — + +7+s| Context / system +| Ownership / Context (2) | ✔ | ✔ | ✔ | `CT_EN_OWNERSHIP` | `trTeControl.Context` | 7 +| Device ID (1) | ✔ | — | ✔ (opt-in — see <>) | `CT_EN_DEVICE_ID` + `CT_DEVICE_ID` (elaboration value) | `trTeControl.SendDeviceId` = `DID_ONCE` | 19 +| Debug Status (0) | ✔ | — | ○ (no core contract for the 16 status bits — see <>) | — | — | — +| Watchpoint (15) | ✔ | — | ✔ (opt-in — see <>) | `CT_EN_WATCHPOINT_MSG` (requires `CT_EN_ACT`) | `trWpMask.WEM` + ACT-ST command `ACT_CAP_ST_WATCHPOINT` | 20 + +7+s| Data trace (outside the N-Trace program-trace profile) +| Data Trace Read / Write (5/6) | ✔ | — | ✔ (addresses XOR-compressed when `DataAddrCompress` = 1) | `CT_EN_DATA_TRACE` | `trTeDataControl.DataTracing` | 16 +| Data Trace Read / Write w/ Sync (13/14) | ✔ | — | ✔ (opt-in — see <>) | `CT_EN_DF_ADDR_COMPRESS` | `trTeDataControl.DataAddrCompress` = 1 (XOR; modes 2/3 WARL-legalize to 0) | 21 +| Data Acquisition (7) — DAQ | ✔ (vendor) | — | ✔ | `CT_EN_DAQ` | — (ACT-CAP/ACT-ST command-driven) | 17 +| Data-trace drop policy — shed data trace before the queue runs full | ✔ (TCI `DataDropEna`) | — | ✔ (opt-in — see <>) | `CT_EN_DF_DROP` (requires `CT_EN_DATA_TRACE`) | `trTeDataControl.DataDropEna`; status `DataDrop` (RW1C) | 22 +| Data-trace stall policy (`DataStallEna`) | ✔ (TCI) | — | ○ (no back channel to the hart — see <>) | — | — | — +| Data-trace field elision (`DataNoValue` / `DataNoAddr`) | ✔ (TCI) | — | ○ (deferred: opt-in format variants, decoder-visible — see <>) | — | — | — + +7+s| Errors / control +| Error (8) + ECODE (variable-length) | ✔ | ✔ | ✔ | — | — | — +| Vendor Config (58) | vendor | — | ✔ [CTTE] | `CT_EN_CONFIG_MSG` | `trTeControl.SendConfig` | — + +7+s| Encoding / modes +| MDO/MSEO framing | ✔ | ✔ | ✔ | — | — | — +| Address XOR + LSB-shift compression | ✔ | ✔ | ✔ | — | — | — +| 64-bit addresses (RV64) — the whole address path, comparators and JTC fold included | ✔ | ✔ | ✔ (build-time width; the wire fields are variable-length either way) | `CT_XLEN` = 64 (default 32) | — (a synthesis parameter, not a runtime mode) | 23 +| Timestamps | ✔ | ✔ (absolute on sync, delta else) | ✔ (absolute on sync, delta else) | `CT_EN_TIMESTAMP` | `trTsControl.Enable` | 15 +| Message Source (SRC) field | ✔ | ✔ | ✔ | — | `trTeControl.InhibitSrc` + `trTeInstFeatures.SrcID` / `SrcBits` | — +| Synchronization reasons | ✔ | ✔ | ✔ (standard codes; one vendor code 14 — see <>) | `CT_EN_DEBUG_EVENTS` / `CT_EN_POWER_EVENTS` / `CT_EN_EVTI` / `CT_EN_TRIG_SYNC` / `CT_EN_SEQ_SYNC` (one switch per switchable reason — see <>) | `trTeControl.InstTrigEnable` / `trTeControl.InstSeqSyncEnable` (SYNC 6/4 only; the remaining reasons have no runtime knob) | 10–14 + +7+s| Beyond N-Trace and E-Trace — CTTE-only capabilities +| ACT-CAP / ACT-ST hardware instrumentation — DAQ payload up to 192 bit, 1023 watchpoint slots | — | — | ✔ [CTTE] | `CT_EN_ACT` / `CT_EN_DAQ` | indirect watchpoint table (`trWpIndex`/`trWpData*`, capacity `trWpCap`) + CPU CSR `0x0B10` (`trActCapStCmd`) | 17 +| AXIS export — 96-bit instrumentation stream for in-fabric consumers | — | — | ✔ [CTTE] | `CT_EN_AXIS_TS` (timestamp element 2 on `DAQ_PC_CURR` beats; the sink itself has no switch) | — (per-command sink routing; the timestamp element follows `trTsControl`) | — +| Performance-counter block — per-region counters and thresholds | — | — | ✔ [CTTE] | `CT_EN_ACT` | `pc.trPerfCntControl` + range registers | — +| Address / range / context filters and comparators | — | — | ✔ [CTTE] | `CT_EN_FILTERS`; anchoring `CT_EN_FILTER_SYNC` | `trTeInstFilters` / `trTeDataFilters`, `trTeFilter[]`, `trTeComp[]` (`trTeComp[].PInput` = 1 selects the TIP context bus, i.e. filtering by process) | — footnote:[A filter gap is announced with the *existing* pause vocabulary — TCODE 33 `EVCODE=Program Trace Disabled` on region exit, `SYNC=5` on region entry — so no decoder change is needed; see link:enhanced-features.adoc#filter-anchoring[Enhanced features → What a filtered stream looks like on the wire].] +| eTIP FIFO fill-level histogram (diagnostics) | — | — | ✔ [CTTE] | `CT_EN_FIFO_HIST` | `trTeTipFifoHistCtrl` / `trTeTipFifoHistData` | — +| Protocol choice — N-Trace *or* E-Trace, per encoder instance | — | — | ✔ [CTTE]footnote:[Synthesis parameter, not a runtime switch: `ct_encoder` takes `EN_NTRACE`/`EN_ETRACE` (defaults from the two `CT_EN_*` switches), exactly one per instance, so a multi-encoder SoC can mix protocols in one netlist. `trTeProtocolSel.Protocol` and `trTeImpl.ProtocolMajor` are read-only discovery driven by that parameter. The committed full profile builds N-Trace-only (`CT_EN_ETRACE`=0). The former dual build with a runtime select was removed in 2026-08.] | `CT_EN_NTRACE` + `CT_EN_ETRACE` | `trTeProtocolSel.Protocol` (RO) | — +| ATB funnel — packet-aware multi-source merge | — | — | ✔ [CTTE]footnote:[Verified end to end since 2026-08-19 by `tests/instruction/39_dual_src` (gate `scripts/cli_dualsrc_test.sh`, CI stage 2): two encoder instances with `SrcBits`=2 and `SrcID` 0/1 run **different programs at disjoint addresses** and send at the same time; the merged stream is split again by source and each half decodes line for line onto its own reference, while cross-decoding fails and the filtered result is byte-identical to a single-encoder run. The disjoint addresses are the point: two sources running the *same* image differ in one bit per message, and a test that cannot fail confirms nothing.] | — (separate module `ct_L1_funnel`) | — | — +| Overflow / overrun recovery — announced loss + re-anchor | — | — | ✔ [CTTE] | — | — | — +| Explicit synchronization request (SYNC 14) | — | — | ✔ [CTTE] | `CT_EN_INST_SYNC_REQ` (TE-register path) · `CT_EN_SYNC_STATUS` (diagnostic CSR) | `trTeControl.InstSyncReq` (TCI, write-1) — also requestable via ACT-CAP `CF_SYNC` and the ATB input; source read back in `trTeSyncStatus.SyncReqSource` (RO) | — +| Overflow status bit (`InstStallOrOverflow`) | ✔ (TCI) | ✔ (req.) | ✔ (overflow half; the stall half has no back channel — see <>) | — (always present) | `trTeControl.InstStallOrOverflow` (RW1C) | — +| External trigger configuration — TCI trigger registers `0x050`/`0x054`/`0x058` | ✔ (TCI 6.2) | ✔ (delegated to TCI) | ✔ (input #0 = `tip.trigger`; #1..7, the trigger outputs and the debug-trigger register are fixed at 0 per TCI Tables 19–21) | `CT_EN_TRIG_REGS` | `trTeTrigExtInControl.ExtInAction0` (WARL 0/2/3/4) | — +| Timestamp unit — prescale, type, runtime width | — | — | ✔ [CTTE] | `CT_EN_TIMESTAMP`, `CT_TS_WIDTH` | `trTsControl.Type` / `Prescale` / `Width` | 15 +| `Empty` / flush shutdown contract | — | — | ✔ [CTTE] | — | `trTeControl.Empty` (RO) | — +| Profile scaling with register omission | — | — | ✔ [CTTE] | — (per-feature `CT_EN_*`) | — | — +| Self-description — CAPS/ENAB via Vendor Config (58) | — | — | ✔ [CTTE] | `CT_EN_CONFIG_MSG` | `trTeControl.SendConfig` | — |=== [.small] -✔ defined & implemented conformantly • ◐ partial, unverified, or deviating -(see notes) • ○ defined by the spec but not implemented in CEDARtools.TraceEncoder • — -not defined / not applicable in that spec. +✔ defined & implemented conformantly • ○ defined by the spec but not +implemented in CTTE • — not defined / not applicable in that spec. + +*Build switch* = compile-time switch in `ct_pkg.sv` (— = no switch: +always present, or — in the ○ rows — feature not implemented); +*Runtime control* = CSR field per `rdl/ct_cs_cpuif.rdl` (— = +no runtime knob); *CAPS* = bit position in the TCODE-58 CAPS/ENAB +capability map (<>; — = not advertised). +`CT_EN_CONFIG_MSG` has no CAPS bit by design — it is the feature that +transmits the map. The full `CT_EN_*` ↔ RDL ↔ CAPS reference, including +per-profile defaults and measured LUT costs, lives in +link:integration.adoc#feature-flags[Integration → Feature flags]; +matrix ↔ RTL ↔ RDL consistency is machine-checked by +`scripts/check_feature_flags.py` (`make check-flags`). NOTE: The mode names *HTM* and *BTM* are RISC-V N-Trace's; the underlying methods are pure Nexus. {nexus-spec}[Nexus] §3.3.2 (Branch Trace Messaging) defines two kinds of branch message — *traditional* (per-branch, = N-Trace BTM) and *history* (the HIST field + Indirect Branch History messages, TCODE -28/29, = N-Trace HTM) — so both are defined in Nexus too. CEDARtools.TraceEncoder -implements only the history method (HTM); the traditional per-branch -method (BTM) is intentionally omitted because it is bandwidth-inefficient. +28/29, = N-Trace HTM). CTTE implements both and selects between them at +run time through the WARL `trTeControl.InstMode`. HTM is the default and +the bandwidth-lean choice; BTM exists for decoders and workflows that +require per-branch messaging. The compression suite listed above is +HTM-only and is inert in BTM mode by construction. + +[#build-profiles] +=== Build profiles — what a given netlist actually contains + +Every capability marked ✔ above is present in the *full* build profile. +Each one has its own compile switch in `ct_pkg.sv` (`CT_EN_BTM`, +`CT_EN_OWNERSHIP`, `CT_EN_JTC`, …), so slim profiles can omit it +entirely — the logic, its model storage and its CSR bits const away +together. Two consequences worth knowing before reading a stream: + +* An omitted feature reads back as 0 / read-only in its CSR, which is the + spec-conformant way to advertise an absent option. +* The *Vendor Config* message (TCODE 58, <>) carries the + compiled-in capability map (`CAPS`) and the currently enabled subset + (`ENAB`), so a decoder can discover both without out-of-band knowledge. == Message types -TCODEs are defined by `nexus_tcode_e`. The categories CEDARtools.TraceEncoder works with: +TCODEs are defined by `nexus_tcode_e`. The categories CTTE works with: [cols="1,2,3", options="header"] |=== | TCODE | Message | Notes -| 3, 4 | Program Trace Direct / Indirect Branch | Control-flow program trace. +| 2 | Ownership / Context | Processor context: `PROCESS` payload (privilege + `scontext`/`hcontext`), on context events, privilege changes and after every synchronizing message. +| 3, 4 | Program Trace Direct / Indirect Branch | Control-flow program trace in BTM mode (`InstMode` = 3): one message per taken direct / per indirect branch. | 9 | Program Trace Synchronization | Periodic / trace-enable sync; carries SYNC + ICNT + FADDR (+ timestamp). | 11, 12 | Program Trace Direct / Indirect Branch Sync| Branch message combined with a sync point. | 27 | Program Trace Resource Full | ICNT / HIST overflow (see <>). -| 28, 29 | Indirect Branch History (+ Sync) | History-mode indirect branch. -| 33 | Program Trace Correlation | Emitted on trace-off (EVCODE = Program Trace Disabled) with residual ICNT and pending HIST. -| 5, 6 | Data Trace Write / Read | Data-flow trace: DSZ, ELSZ, address, data value (+ timestamp). -| 13, 14 | Data Trace Write / Read Sync | Data trace combined with a sync point. +| 28, 29 | Indirect Branch History (+ Sync) | History-mode indirect branch. The Sync variant carries the pending history instead of pre-flushing it as a separate Resource Full. +| 30 | Program Trace Repeat Branch | Repeat count for identical consecutive Indirect Branch History messages. +| 31, 32 | Program Trace Repeat Instruction (+ Sync) | Single-instruction spin-loop compression: iterations after the first are counted into R-CNT instead of one HIST bit each. +| 33 | Program Trace Correlation | Emitted on trace-off, debug entry and low-power entry with residual ICNT and pending HIST (see <>). +| 5, 6 | Data Trace Write / Read | Data-flow trace: DSZ, ELSZ, address, data value (+ timestamp). The address is XOR-compressed against the previous data-trace message's address when `trTeDataControl.DataAddrCompress` = 1 (reset 0 = full addresses). +| 13, 14 | Data Trace Write / Read with Sync | Synchronizing data-trace variant carrying the full, uncompressed address (+ absolute timestamp). Emitted, with `DataAddrCompress` = 1, for the first data-trace message after a re-anchor event (see <>). | 7 | Data Acquisition | Vendor instrumentation (DAQ); IDTAG + up to 192-bit payload. | 8 | Error | Message loss; ETYPE + ECODE (see <>). -| 56 | Vendor Config | Encoder configuration for the decoder. +| 56 | Vendor Branch Predict | [CTTE] Count of correctly predicted direct branches instead of HIST bits; the branch after the counted run mispredicted. +| 57 | Vendor Jump Target Cache | [CTTE] Indirect Branch History with a jump-target-cache index in place of UADDR. +| 58 | Vendor Config | [CTTE] Encoder configuration for the decoder (see <>). |=== The concrete field layout per message is built by `get_msg_format()` in the package. The actively-tabulated formats are Program Trace Sync (9), -Data Trace Write/Read (5/6), Program Trace Correlation (33) and Data -Acquisition (7); the remaining program-trace messages are composed by the -formatter from the same field primitives. +Data Trace Write/Read (5/6) and their sync variants (13/14), Program +Trace Correlation (33), Data Acquisition (7) and Vendor Config (58); the +remaining program-trace messages are composed by the formatter from the +same field primitives. === Key field widths @@ -141,10 +218,11 @@ formatter from the same field primitives. | `NEXUS_MSG_ADDRESS_WIDTH` | 32 | Address (FADDR / UADDR) width. | `NEXUS_MSG_PC_ADDR_SHIFT` | 1 | PC addresses are right-shifted by 1 before encoding. -| `NEXUS_MSG_I_CNT_WIDTH` | 8 | Instruction-count field width. +| `NEXUS_MSG_I_CNT_WIDTH` | 8 | Instruction-count cap in the default configuration. +| `NEXUS_MSG_I_CNT_WIDTH_WIDE` | 16 | Internal ICNT cap with `InstEnWideIcnt` (the on-wire field stays variable-length either way). | `NEXUS_MSG_HIST_WIDTH` | 30 | Branch-history field width. -| `NEXUS_MSG_DATA_WIDTH` | 192 | Data / DAQ payload width (>64 bit for vendor DAQ). -| `NEXUS_MSG_TSTAMP_WIDTH` | 64 | Timestamp width. +| `NEXUS_MSG_DATA_WIDTH` | 192 | Data / DAQ payload width (>64 bit for vendor DAQ; narrows to 64 / 32 in profiles without DAQ / data trace). +| `NEXUS_MSG_TSTAMP_WIDTH` | 64 | Timestamp width (build knob `CT_TS_WIDTH`). | `NEXUS_MDO_WIDTH` | 6 | MDO bits per chunk (6/14/30 supported). | `NEXUS_MAX_FIELDS` | 10 | Maximum fields per message. |=== @@ -155,39 +233,148 @@ reference address (`GetUaddr`) and right-shifted by `NEXUS_MSG_PC_ADDR_SHIFT`. [#sync-reasons] == Synchronization reasons -The SYNC field of a sync message uses `nexus_sync_reason_e`. CEDARtools.TraceEncoder -implements: +The SYNC field of a sync message uses `nexus_sync_reason_e`. CTTE emits: [cols="1,2,3", options="header"] |=== | Value | Reason | Use -| 2 | `PERIODIC` | Periodic synchronization (implemented). -| 5 | `TRACE_ENABLE` | Emitted when tracing is enabled (implemented). -| 7 | `FIFO_OVERRUN` | Restart marker after a queue overrun. -| 12 | `REQ_CSR` | [CEDARtools.TraceEncoder] sync requested via CSR. -| 13 | `REQ_ATB` | [CEDARtools.TraceEncoder] sync requested via APB. -| 14 | `TRACE_QUOTA` | [CEDARtools.TraceEncoder] sync due to a trace quota limit (# messages / # bytes). +| 0 | `EVTI` | External trigger marker on a `tip.evti` pulse while tracing (`CT_EN_EVTI`, optional in the spec). +| 1 | `EXIT_FROM_SYS_RST` | One-shot re-anchor on the first retired instruction after reset. Subsumes every other pending one-shot. +| 2 | `PERIODIC` | Periodic synchronization. +| 3 | `EXIT_FROM_DEBUG` | First synchronizing message after leaving debug mode (`CT_EN_DEBUG_EVENTS`; N-Trace Required). +| 4 | `SEQ_INSTR_COUNTER` | Full sync instead of the RCODE-0 pre-drain on I-CNT overflow, while `trTeControl.InstSeqSyncEnable` is set (`CT_EN_SEQ_SYNC`, reset 0 — see <>). +| 5 | `TRACE_ENABLE` | First qualifying retire after the encoder was enabled mid-stream. +| 6 | `WATCHPOINT` | Watchpoint / trigger marker (Trace Event) while `trTeControl.InstTrigEnable` is set (`CT_EN_TRIG_SYNC`). +| 7 | `FIFO_OVERRUN` | Restart marker after a queue overrun. +| 9 | `EXIT_FROM_POWERDOWN` | First retire after power-down exit (`CT_EN_POWER_EVENTS`, optional). +| 14 | `REQ` | [CTTE, Vendor-Defined range] Explicit sync request — from a write of 1 to `trTeControl.InstSyncReq` (`CT_EN_INST_SYNC_REQ`), from an ACT-CAP `CF_SYNC` command or from the ATB sync-request input. |=== -Values 0, 1, 3, 4, 6, 8–11 are defined by the standard (external -trigger, reset/debug/powerdown exit, I-CNT overflow, watchpoint, -contention) and reserved here for completeness. +Values 8 and 10–13 are Reserved by the standard and are not emitted. + +NOTE: Code 14 is the *single* vendor sync reason. The request source is +irrelevant to a decoder — every sync is a full re-anchor — so it is not +encoded on the wire but recorded for diagnosis in the read-only CSR +field `te.trTeSyncStatus.SyncReqSource` (0 = none, 1 = ACT-CAP `CF_SYNC` +from the traced hart, 2 = ATB input, 3 = trace quota, 4 = a write to +`trTeControl.InstSyncReq` over the control bus). A quota-triggered sync +arrives on the wire as `PERIODIC` (2) — the quota modes are periodic +cadences, not explicit requests — while `SyncReqSource` reports 3 for +diagnosis. Values 1 and 4 are kept apart on purpose: the requester is a +different actor (the hart's own instruction stream versus the external +control/debug bus), which is exactly what the register is read for. + +Requesting a synchronization message through the TE register is the +TCI-standard path (`trTeControl.InstSyncReq`, bit 27, write-1, +self-clearing — it always reads back 0). It is not tied to a cadence: +the field works in every `InstSyncMode`, including mode 0 (off). A +request written while instruction tracing is paused is *deferred* — it +is served after the resume anchor (`TRACE_ENABLE`, 5), not dropped. +Requests arriving from two sources on the same retire are satisfied by +that one message. + +The contract is one message per request, with a request depth of one in +flight plus one remembered. A write that lands while a request is still +outstanding is *not* swallowed: it is launched as its own request once +the outstanding one has been served, and produces its own +synchronization message. Only a write that arrives when a request is +already waiting to be launched collapses into it — it asks for exactly +what is about to be asked anyway. Measured on +`scripts/cli_tesyncreq_test.sh` (legs `req`, `req2`, `req3`): one write +yields one `SYNC = 14`, two writes back to back yield two, three writes +back to back still yield two. + +[NOTE] +==== +The contract is about the *encoder*, not about the link. Once the +request has been served it is an ordinary synchronization message, and +under an eTIP overflow it can be dropped like any other message — the +loss is announced by the overflow `Error` message and the recovery +anchor re-synchronizes the decoder. `SyncReqSource` still shows that +the request was raised, which is what the overflow leg of the system +test checks; it deliberately does not claim that the `SYNC = 14` +reached the wire. +==== + +The *periodic* sync cadence is selected by `trTeControl.InstSyncMode` +together with `InstSyncMax`. Implemented modes are 0 (off), 1 (trace +messages), 2 (hart clock cycles), 3 (instruction half-words), 4 (trace +bytes), 5 (wallclock cycles), 6 (instructions) and the CTTE-specific 7 +(ATB sync requests). + +The two fields reset to *`InstSyncMode` = 0* (no periodic cadence at +all) and *`InstSyncMax` = 6*, i.e. a period of 2^(6+4)^ = 1024 units in +whichever unit the mode selects. That split is deliberate: the *unit* +depends on the sink and only the integrator knows it, while the +*period* is the same number in every unit and can be pre-set. So +enabling the cadence is a single write of `InstSyncMode`, and it lands +on a period that costs 2.5 % of the trace stream (measured over 100 010 +retires, gate `tests/instruction/37_sync_cadence`) instead of on the +tightest period the hardware has. `InstSyncMax` = 0 (every 16 units) +remains available as an explicit stress configuration; on the same +workload it costs a factor 2.4 in bytes and loses trace against a +finite sink. Mode 3 counts the half-words of *retired +instructions* — a compressed instruction is one half-word, an +uncompressed one two, and a block ingress contributes the whole block — +so it bounds the re-anchor distance in *binary size*, whereas mode 6 +bounds it in instruction count. + +The two trace-*quota* modes 1 and 4 +(`CT_EN_QUOTA_SYNC`, CAPS bit 18) measure the trace *output* itself, +with a threshold of 2^(`InstSyncMax`+4)^ units. Counting-point +semantics: mode 4 counts bytes as accepted on ATB — whole beats, +including alignment padding and flush idle beats, i.e. exactly what a +downstream ring buffer stores — and mode 1 counts on-wire messages at +their end-of-message boundary (flush pseudo-slots that carry no message +do not count). The counter runs in whichever egress path the build uses +(MSEO/MDO formatter, compact packer or E-Trace packetizer), raises a +held request at the threshold and rearms when the sync is emitted; the +sync message's own bytes count into the *new* window, and no second +request is raised while one is pending. Compiled out +(`CT_EN_QUOTA_SYNC = 0`) both modes stay writable but inert. For the +ring-buffer window recipe built on mode 4 — including the measured +re-anchor distance — see +link:integration.adoc#quota-sync-live[Integration → Live / ring +operation]. [#resource-codes] == Resource codes -The Resource Full message (TCODE 27) uses `nexus_rcode_e`: +The Resource Full message (TCODE 27) uses `nexus_rcode_e`. On the wire +only three values occur: [cols="1,2,3", options="header"] |=== | Value | RCODE | Meaning -| 0 | `ICNT_OVERFLOW` | Instruction count exceeded the 8-bit field. -| 1 | `HIST_OVERFLOW` | Branch history filled the HIST field. -| 2 | `HIST_OVERFLOW_REPEATED`| History overflow with pending bits. +| 0 | `ICNT_OVERFLOW` | Instruction count exceeded the ICNT cap. +| 1 | `HIST_OVERFLOW` | Branch history filled the HIST field. +| 2 | `HIST_OVERFLOW_REPEATED` | History overflow with a repeat count (`InstEnRepeatedHistory`). |=== +Values 3–5 (`TRACE_DISABLED`, `CORR_DEBUG_ENTRY`, `CORR_LOW_POWER`) are +CTTE-internal markers on the composer → `msg_gen` path that request a +Program Trace Correlation message with the matching EVCODE. They are +consumed inside `msg_gen` and never leave it. + +[#evcodes] +== Correlation event codes + +The Program Trace Correlation message (TCODE 33) carries an EVCODE: + +[cols="1,2,3", options="header"] +|=== +| Value | EVCODE | Emitted on + +| 0 | Entry into Debug Mode | Debug-mode entry (`CT_EN_DEBUG_EVENTS`; N-Trace Required — not substituted by code 4). +| 1 | Entry into Low-power Mode | Power-down entry (`CT_EN_POWER_EVENTS`, optional). +| 4 | Program Trace Disabled | Trace-off, flushing the residual ICNT and pending HIST. +|=== + +In HTM the CDF field is always 1 and the HIST field is always present +(empty if no history is pending), per N-Trace 1.0 Table 24. + [#error-codes] == Error codes @@ -212,69 +399,311 @@ indicating which message classes were lost: The ECODE is transmitted as a variable-length field, so unused high bits cost no bytes. +CTTE only sets the bits for message classes the build can actually +produce: `0x04` (control flow) unconditionally, `0x02` with +`CT_EN_DATA_TRACE`, `0x20` with `CT_EN_DAQ`/`CT_EN_ACT`, `0x08` with +`CT_EN_OWNERSHIP` and `0x01` with `CT_EN_WATCHPOINT_MSG`. `0x10` +(Status) is never set — CTTE emits no Debug Status message. `ETYPE` = 1 +(HIGH_PRIO contention) is structurally unreachable: there is no priority +preemption between message classes. + +The data-trace **drop policy** (`trTeDataControl.DataDropEna`, +<>) uses the same message with a *single* ECODE bit, +`0x02`, and — unlike the generic overflow path — **without** a following +`SYNC = 7` re-anchor: only data-trace messages were shed, the +instruction trace is intact and must not be forced to re-anchor. One +such marker is emitted per drop *episode*. + +NOTE: A lost **Device ID** message has no ECODE bit — the Nexus ECODE +map defines none for TCODE 1. That is not a gap in CTTE: the Device ID +is emitted on the trace-on edge, and an overflow episode there is +announced by the ERROR message plus the `SYNC = 7` re-anchor like any +other loss. Software that needs the identity reliably re-arms the trace +(the message is re-emitted on the next trace-start edge). + +NOTE: Until P4 the Watchpoint bit `0x01` was gated by `CT_EN_TRIG_SYNC`, +which claimed a message class that did not exist (the trigger feature +only upgrades a CF message to `SYNC = 6`). It now follows +`CT_EN_WATCHPOINT_MSG`. P7 completed the same clean-up for `0x02` +(Data Trace) and `0x20` (DAQ), which were unconditional and therefore +claimed losses a control-flow-only profile can never produce. The full +profile has all of these features on, so its ECODE value is unchanged +(`0x2F`); profiles without the watchpoint message now report `0x2E`, and +a CF-only profile reports `0x04` instead of `0x26`. + +[#config-message] +== Vendor Config message (TCODE 58) + +The Vendor Config message makes the stream *self-describing*: it tells +the decoder which features this netlist contains and which of them are +currently switched on, so no out-of-band configuration file is needed. +Emission is controlled by `trTeControl.SendConfig`: `CFG_NONE` (0), +`CFG_ONCE` (1) or `CFG_ON_SYNC` (2, additionally after every periodic +sync). The full profile resets to `CFG_ONCE`. `CFG_ONCE` fires on +**every** trace-on edge (rising edge of effective instruction tracing), +not once per session — after an instruction-tracing pause the config is +sent again. Same trigger as `SendDeviceId = DID_ONCE`; both are visible +twice in the `didtwice` leg of `tests/instruction/31_status_msgs`. + +Payload version 1 — one fixed field followed by six variable-length +fields (leading zeros suppressed, as everywhere in Nexus): + +[cols="1,1,4", options="header"] +|=== +| Field | Max bits | Content + +| `CFGVER` | 4 (fixed) | Config-message format version (`CT_CFGMSG_VER` = 1). +| `CAPS` | 24 | Compiled-in capability map — one bit per feature: 0 IR, 1 RH, 2 WIDE_ICNT, 3 RB, 4 JTC, 5 BP, 6 SIJUMP, 7 OWNERSHIP, 8 IBHS, 9 REPEAT_INSTR, 10 DEBUG_EVENTS, 11 POWER_EVENTS, 12 EVTI, 13 TRIG_SYNC, 14 SEQ_SYNC, 15 TIMESTAMP, 16 DATA_TRACE, 17 DAQ, 18 QUOTA_SYNC, 19 DEVICE_ID, 20 WATCHPOINT_MSG, 21 DF_ADDR_COMPRESS, 22 DF_DROP, 23 ADDR64. +| `ENAB` | 24 | Same bit positions, masked with the *runtime* enables (`trTeInstFeatures`, `trTeControl`, `trTeDataControl`, `trTsControl`; bit 18 = a trace-quota cadence mode is selected in `trTeControl.InstSyncMode`; bit 21 = a non-full `DataAddrCompress` mode is selected; bit 19 = `trTeControl.SendDeviceId` != `DID_NONE`; bit 20 = a non-zero `trWpMask.WEM`; bit 22 = `trTeDataControl.DataDropEna`; bit 23 has no runtime enable and mirrors CAPS). +| `PARAM0` | 16 | `trTeSrcID`, `trTeSrcBits`. +| `PARAM1` | 12 | `trTeInhibitSrc`, `trTeInstSyncMax`, `trTeInstSyncMode`, `trTeInstMode`. +| `PARAM2` | 12 | `trTsWidth`, `trTsPrescale`, `trTsType`, `trTsEnable`. +| `PARAM3` | 13 | Structural sizes: `[12:8]` return-stack depth (16), `[7:4]` log2 branch-predictor entries (512), `[3:0]` jump-target-cache index bits (64 entries). +|=== + +`PARAM3` is built from the same `ct_pkg` constants the implementing +modules consume, so the advertised sizes cannot drift from the built +hardware. The forward-compatibility rule for future versions is +append-only. + +CAPS bit 23 (`ADDR64`) is the one entry that is not a feature: it says +whether this netlist carries 64-bit addresses (`ct_pkg::CT_XLEN` = 64). +The information has to be on the wire because a decoder cannot derive it +from the stream — `F-ADDR` and `U-ADDR` are variable-length with leading +zeros stripped, so a 40-bit address and a 64-bit address whose top bits +happen to be zero are byte-for-byte the same field. A decoder reads the +bit and sizes its own PC state and its jump-target-cache index fold +accordingly (`NexRvDeco.c`). It has no runtime enable — the width is what +the hardware is — so `ENAB` mirrors `CAPS` for it, and `CFGVER` stays 1: +the information is boolean and needs no new payload field. + [#conformance] == Nexus / N-Trace conformance -The matrix in <> gives the status at a glance; this -section details only the gaps and deviations (the ◐ / ○ rows). +The matrix in <> gives the status at a glance; this +section details the opt-in extensions and the remaining gaps. -=== Known deviations +[#extensions] +=== Extensions beyond strict N-Trace 1.0 (opt-in) -[cols="2,2,3,2", options="header"] +CTTE's *reset* configuration produces a stream that is strictly within +N-Trace 1.0 — with the single exception of the config message, see the +note below. The following features leave that envelope when a user +switches them on; each is a deliberate, documented Accemic extension: + +[cols="2,3", options="header"] |=== -| Item | Spec reference | CEDARtools.TraceEncoder behavior | Status - -| Vendor SYNC reasons -| Nexus Table 4-13 (12–13 Reserved, 14–15 Vendor) -| `REQ_CSR` = 12 and `REQ_ATB` = 13 use *Reserved* sync codes for vendor - meaning (`nexus_vendor_riscv_pkg.sv`). -| **Deviation — to fix.** For strict interop these must move to the - Vendor-Defined range (14/15); a stock decoder sees 12/13 as Reserved. - -| Correlation CDF in HTM -| N-Trace Table 24 (HTM: CDF must be 1, HIST always present) -| When no branch history is pending, the encoder emits CDF = 0 and omits - HIST (`ct_L2_nexus_formatter.sv`); it uses the Nexus-base CDF semantics - (CDF signals HIST presence). -| **Deviation — to fix.** For strict interop, always emit CDF = 1 + HIST - in HTM. The bundled NexRv decoder tolerates both forms; a stock decoder - may not. +| Feature | Why it is outside N-Trace 1.0 + +| Branch prediction (TCODE 56) and jump-target cache (TCODE 57), via + `trTeInstFeatures.InstEnBranchPrediction` / `InstEnJumpTargetCache` +| Vendor TCODEs in the Nexus vendor range 56–62. Both sides must run the + bit-identical predictor / cache model; a decoder without it cannot + reconstruct the flow. Reset 0. + +| Repeat Instruction (TCODE 31/32), via `InstEnRepeatInstr` +| IEEE-ISTO 5001-2012 §4.3.14/15 messages, but N-Trace 1.0 Table 9 marks + 31/32 "Reserved for future extensions". Enabling this makes the stream + an Accemic/ISTO extension. Reset 0. + +| Sequential-instruction-counter sync (SYNC = 4) in HTM, via + `trTeControl.InstSeqSyncEnable` +| N-Trace binds SYNC = 4 to BTM. Using it in HTM as a full sync instead + of the RCODE-0 pre-drain is a documented Accemic extension. Reset 0. + +| Vendor Config (TCODE 58), via `trTeControl.SendConfig` +| Vendor TCODE (range 56–62), no N-Trace counterpart. A decoder that + does not know it still frames it correctly through MSEO and can skip + it. **This is the one feature whose full-profile reset is not "off"** + (`CFG_ONCE`) — set `SendConfig = CFG_NONE` for a stream that contains + standard TCODEs only. + +| Wide ICNT (`InstEnWideIcnt`) +| Internal accounting only — the on-wire ICNT field stays variable-length + per Nexus, so an enabled wide cap is *not* a wire-format extension. It + only reduces how often Resource Full (ICNT) messages appear. Reset 0. + +| Data Trace with Sync (TCODE 13/14) + XOR data-address compression, via + `trTeDataControl.DataAddrCompress` = 1 +| Nexus data-trace messages — the N-Trace 1.0 profile excludes data + trace altogether, so both the 13/14 sync variant and the + XOR-compressed DF address sit outside it. Contract: with mode 1 the + 5/6 address is XOR-compressed against the previous data-trace + message's address; the first DF after a re-anchor event (any + synchronizing message, a `DataTracing` 0→1 edge, an ERROR message, + reset) is emitted as the synchronizing 13/14 form carrying the full + address, which re-seeds the decoder's reference. Reset 0 (full + addresses — the legacy stream stays byte-identical). + **Data-only caveat:** a stream with `InstTracing` = 0 carries no + Config message, so a decoder joining such a stream mid-stream cannot + auto-detect the compression mode from the stream itself — keep a + Config message in the stream (`SendConfig`, requires a synchronizing + program-trace stream) or provide the mode to the decoder out-of-band. + +| Device ID (TCODE 1), via `trTeControl.SendDeviceId` = `DID_ONCE` +| Nexus standard message (IEEE-ISTO 5001 §4.3.2), but N-Trace 1.0 + Table 9 does not adopt TCODE 1 — for a strict N-Trace decoder it falls + under "Reserved for future extensions" (which such a decoder must skip + by MSEO framing, so the stream stays parsable). Emitted on **every** + trace-on edge — the rising edge of effective instruction tracing — + *before* the Config message and before the first synchronizing + message, so a decoder learns the device identity first. `DID_ONCE` + therefore means "one message per trace-on edge", *not* "once per + session": after an instruction-tracing pause the message is sent + again. That is the same trigger `SendConfig = CFG_ONCE` uses, and it + is what a decoder attaching during the pause needs. Measured by the + `didtwice` leg of `tests/instruction/31_status_msgs` + (`DIDTWICE two TCODE 1: PASS (2)` next to + `DIDTWICE pause happened (33): PASS (1)`). Payload = the + `CT_DEVICE_ID` elaboration parameter of the encoder instance, laid out + per IEEE-ISTO 5001 Table B-5 (RN | PN | MID). Reset `DID_NONE`. + **Deviation from Table 4-7:** CTTE emits the ID as a *variable-length* + field (leading zeros stripped) instead of "Fixed 32". Reason: a fixed + field would need a special case in both egress paths and in the + decoder's table mechanism, for a message whose value a decoder reads + as an integer anyway. A decoder that expects 32 fixed bits must be + told; the pinned CTTD reads the variable form. + +| Watchpoint (TCODE 15), via `trWpMask.WEM` + the ACT-ST command + `ACT_CAP_ST_WATCHPOINT` +| Nexus standard message (IEEE-ISTO 5001 §4.3.23), also not adopted by + N-Trace 1.0 Table 9. It names *which* watchpoint fired, where the + trigger path (`InstTrigEnable`) only marks *that* something fired + (SYNC = 6). WPHIT = the command's `DirectData[15:0]` AND `WEM`, so the + bit↔slot assignment is a **software convention**: give each + watchpoint-table entry the DirectData bit you want to see and enable + that bit in `WEM`. Reset `WEM` = 0 masks every hit, so the feature is + byte-neutral until software opts in. Requires the ACT blocks + (`CT_EN_ACT`). + **Specification conflict (documented choice):** §4.3.23 prose says the + WPHIT field is "masked by 1", which reads like an inverted mask, while + Table B-26 defines `WEM` as "1 = enabled". CTTE follows **Table B-26** + (a 1 enables reporting). + +| Data-trace drop policy, via `trTeDataControl.DataDropEna` +| The policy itself is standard (TCI / N-Trace `DataDropEna`, "allow + dropping data trace to avoid instruction trace overflows"), but data + trace as such is outside the N-Trace 1.0 program-trace profile, so the + whole feature sits with the other data-trace rows here. + Contract: while armed, the encoder suppresses data-trace messages as + soon as the eTIP queue fill reaches `ct_pkg::CT_DF_DROP_WATERMARK` + (3/4 of the queue depth), keeping the remaining capacity for the + instruction trace. Each drop *episode* is announced by exactly ONE + Error message (TCODE 8) with `ETYPE` = QueueOverrun and `ECODE` = + `0x02`, **without** the `SYNC = 7` re-anchor of the generic overflow + path — the instruction trace was not lost and must not be forced to + re-anchor for a data-trace drop. No new wire format: `ERROR`/`ECODE` + is standard, so every decoder *parses* the marker unchanged. The + *semantics* are not free: a decoder that treats any `Error` as a full + desync discards exactly the instruction trace this marker promises is + intact (measured on `tests/data/06_df_drop`: 269 of 760 PCs with the + pre-P7 NexRv pin, 760 after the fix). A consumer must scope + `ECODE = 0x02` to the data-trace reference; the reference decoder + does. Sticky status: + `trTeDataControl.DataDrop` and `DataStallOrOverflow` (both RW1C). + Unlike the configuration fields, `DataDropEna` is a runtime policy and + may be armed/disarmed while the trace runs. Reset 0. + +| External trigger input actions, via + `trTeTrigExtInControl.ExtInAction0` (`CT_EN_TRIG_REGS`) +| The register is the Trace Control Interface's (TCI 6.2, Table 20), and + N-Trace delegates it there, so using it is conformant — it is listed + here because two of its three implemented actions reach *into* the + encoder's runtime state. Actions: 0 = none (reset), 2 = trace-on, 3 = + trace-off (both gated by `trTeControl.InstTrigEnable`, exactly as the + TCI text prescribes; CTTE has no `trTeDataTrigEnable`, so data tracing + is not affected), 4 = trace-notify = the existing `SYNC = 6` Trace + Event marker. Everything else WARL-legalizes to 0. + **Documented deviation:** CTTE used `InstTrigEnable` as the enable of + the `SYNC = 6` notify marker long before this register existed. That + behaviour is unchanged; action 4 is an *additional* source of the same + one-shot, so a configuration with `InstTrigEnable` = 1 **and** + `Action0` = 4 still produces exactly ONE marker per trigger pulse. + Reset 0 keeps every existing stream byte-identical. |=== -=== Not yet implemented - -The most significant gap: - -* **Ownership / Context message (TCODE 2)** — process/privilege - correlation (`scontext`/`hcontext`, privilege mode). The control bit - (`trTeControl.Context`) and the TIP context fields exist, but the message - is not generated. Needed for OS-aware and multi-hart decode. - -Lower-priority optional messages and modes: +Sync reason 14 (`REQ`) sits in the Nexus Vendor-Defined range (14–15) and +is therefore conformant use of a vendor code, not a deviation. -* **Indirect Branch History with Sync (29)** — functionally covered by a - pre-flush Resource Full (HIST) followed by a plain synchronization - message, rather than the dedicated combined message. -* **Data Trace with Sync (13/14)** and **Program Trace Correction (10)**. -* **Bandwidth optimizations** — none implemented; see the - _Program-trace optimizations_ rows in the capability table above - (implicit return, sequential jump, repeated history, virtual-address MSB - elision, and the Repeat Branch / Repeat Instruction messages). Their - control fields are stubbed but commented out in `rdl/ct_cs_cpuif.rdl`. - -=== Intentionally not implemented +=== Not yet implemented -* **BTM mode** — traditional Branch Trace Messaging (Nexus DirectBranch / - IndirectBranch, TCODE 3/4; N-Trace `ITR_BRANCH`). CEDARtools.TraceEncoder implements - history mode (HTM) only. Per-branch BTM messaging is bandwidth-inefficient - — HTM conveys the same control flow at far lower bandwidth — so BTM is - omitted by design, not pending. The `ITR_BRANCH` encoding is reserved in - `rdl/ct_cs_cpuif.rdl` and must not be programmed; the encoder emits no - control-flow message for it. +Optional messages and modes CTTE does not currently generate: + +* **Debug Status (0)** — optional in Nexus; *not* part of the N-Trace 1.0 + profile (Table 9 does not adopt it). Deliberately **not implemented**, + and the reason is a missing contract, not missing effort: the message + carries a 16-bit status register (IEEE-ISTO 5001 §B.5.8) whose bits + describe the *core's* debug state, and CTTE has no source for them. + All three real ingress adapters tie the debug-related TIP inputs to 0 + (`mbv_to_ctte_tip.sv`, `cva6_iti_to_ctte_tip.sv`, + `rocket_tci_to_ctte_tip.sv`), so only the DBS (debug status) and STP + (stopped) bits could be filled at all — and those two facts CTTE + already states more precisely, and with the flow position attached, as + Correlation `EVCODE` 0/1 plus `SYNC` 3/9. A status field with invented + bit contents would be worse than none. + **Condition for implementing it:** a core that delivers a halt reason + over the TIP (the `tip_if` ingress would gain the field). Sibling + messages Device ID (1) and Watchpoint (15) *are* implemented — see + <>. +* **Data-address compression modes 2 (DIFF) and 3 (dynamic)** + (`trTeDataControl.DataAddrCompress`) — only mode 1 (XOR, with the + TCODE 13/14 re-anchor variant, see <>) is implemented. + DIFF turns negative for descending addresses (stack, backwards + copies) and the wire format carries no sign encoding; the dynamic + mode is not decodable without an extra wire bit. WARL: writes of 2/3 + legalize to 0. +* **Virtual-address MSB elision** (`InstExtendAddrMSB`, N-Trace ch. 9) — + the only bandwidth optimization of chapter 9 still open; the control + field is stubbed and commented out in `rdl/ct_cs_cpuif.rdl`. +* **Debug-trigger and trigger-output registers** (`trTeTrigDbgControl` + `0x050`, `trTeTrigExtOutControl` `0x058`) — both registers exist and + read 0, which is what the Trace Control Interface spec prescribes for + a trigger that does not exist ("If external trigger output #0 does not + exist, then all bits are fixed at 0", TCI Table 21; Table 19 is a + vendor-defined field with nothing behind it here). CTTE has no + debug-module trigger sideband on its ingress port and no trigger + *output* port — adding one would change the encoder's top-level signal + contract and is therefore a separate, approval-bearing scope. The + external trigger *input* side **is** implemented + (`trTeTrigExtInControl` `0x054`, input #0 = the generic `tip.trigger` + port, actions 0/2/3/4; inputs #1..7 fixed at 0 per TCI Table 20). +* **Data-trace hart stall** (`DataStallEna` and the stall half of + `trTeControl.InstStallOrOverflow` / `trTeDataControl.DataStallOrOverflow`) + — **blocked, not deferred**: stalling a hart needs a back channel from + the encoder to the core, and the CTTE ingress port (`rtl/pkg/tip_if.sv`) + is unidirectional by construction — the encoder drives no signal + towards the hart, and none of the three adapters could route one. The + *overflow* half of both status bits is implemented (P7); the drop + policy `DataDropEna` is the implemented alternative to stalling + (see <>). +* **Data-trace field elision** (`trTeDataControl.DataNoValue` / + `DataNoAddr`) — deferred until a concrete request (decision E-P7-1, + 2026-08-04). Both are opt-in **format variants**: a field disappears + from the data-trace message, and because the Nexus field list is + positional a decoder cannot self-detect that — each would need its own + CAPS/ENAB bit *and* a decoder change, and `DataNoAddr` would make the + XOR address reference and the TCODE 13/14 re-anchor (P3) meaningless. + The RDL keeps the stubs commented with that reasoning. + +=== Not applicable by design + +NOTE: **Program Trace Correction (10)** is deliberately absent from the +matrix altogether: it is a Nexus message that ratified N-Trace 1.0 did +*not* adopt (the draft's "Later (maybe not needed)" entry was dropped; +TCODE 10 is Reserved in Table 9). It is not a CTTE capability gap. Per +the spec, decoders ignore Reserved TCODEs for flow reconstruction and +may report them as a warning. === Notes -* **I-CNT field width.** The wire I-CNT field is 8 bits, so long linear +* **I-CNT field width.** The default ICNT cap is 8 bits, so long linear code emits frequent Resource Full (ICNT_OVERFLOW) messages. This is legal (the decoder concatenates) but bandwidth-suboptimal; N-Trace - notes a wider field (≈ 22 bits) is typical. + notes a wider field (≈ 22 bits) is typical. `InstEnWideIcnt` raises the + internal cap to 16 bits and cuts those drains without changing the wire + format. +* **Correlation semantics.** Earlier CTTE revisions emitted CDF = 0 and + omitted HIST in HTM when no branch history was pending, and used the + Reserved sync codes 12/13 for vendor sync requests. Both are fixed: + CDF is always 1 with HIST present (N-Trace Table 24), and vendor sync + requests use the Vendor-Defined code 14. diff --git a/doc/verification.adoc b/doc/verification.adoc index 677649d..1c8f52a 100644 --- a/doc/verification.adoc +++ b/doc/verification.adoc @@ -3,26 +3,77 @@ = Verification — test harness and checking principle +NOTE: The product name is *CEDARtools.TraceEncoder*, abbreviated *CTTE*. +The earlier name *C-Trace* is retired from prose; it survives only in the +`ct_*` identifier prefix (the IP's public API), in board- and +bundle-visible names (`*_ctrace_kv260`, `ctrace_resmem.dtso`, +`ctrace-pl-ddr`, the `mbv_ctrace_soc` block design) and in recorded +captures and evidence files, which are raw data with published checksums. +See the naming note in the README. + A scripted CPU model is **both the stimulus and the answer key**: it drives the encoder's instruction input *and* records what it executed. The encoder turns that into an N-Trace byte stream; an independent -reference decoder (NexRv) turns the bytes back into a trace, which is +reference decoder (CTTD, see below) turns the bytes back into a trace, which is compared to what the model recorded. If the encoder mangles the trace, the reconstruction won't match — and the check fails. == The loop -image::images/verification-loop.drawio.png[Verification loop — cpu_model drives the encoder and records what it ran; NexRv reconstructs the trace from the captured bytes; the decoded and expected streams are compared,width=900] +image::images/verification-loop.drawio.png[Verification loop — cpu_model drives the encoder and records what it ran; CTTD reconstructs the trace from the captured bytes; the decoded and expected streams are compared,width=900] -NexRv reconstructs two views from the bytes: the **PC stream** +CTTD reconstructs two views from the bytes: the **PC stream** (instruction trace) and the -https://github.com/accemic/C-Trace-eXPort-format[**CTXP**] export — -C-Trace eXPort records for +https://github.com/accemic/CTXP-format[**CTXP**] export — +CTTE eXPort records for control flow (`SYNC`, `BRANCH_*`, `CALL`, `RETURN`), memory accesses (`MEMREAD_n` / `MEMWRITE_n`, with the data value) and instrumentation (`DAQ_*`). The `cpu_model` emits the matching expected files, and each is compared. +[#gate-falsifiability] +== What makes a check a gate + +A passing check proves nothing by itself; what makes it evidence is that +it *would have failed*. **A gate that cannot turn red for its own defect +class is not a gate** — it is a green light with no lamp behind it. Every +mechanism in this document therefore carries the counterpart that turns +it red, in one of four shapes: + +Historical counter-proof:: the check is run against a git worktree of the +pre-fix commit and must fail there. Used wherever the defect class really +occurred — the two 2026-08 emission-core classes are red at a named BMC +step on their pre-fix trees, and `RED=1` runs those legs +(<>). + +Mutation counter-proof:: where no historical defect commit exists, the +check is run against a deliberately broken copy: a wrong end-of-message +code, a suppressed EOM, a context cast narrowed back to its old width, a +filter made ineffective, one instruction shifted by two bytes in a +listing. Per formal target this is `run_red.sh`; for the script gates it +is `MUTATE=1` or an explicit `-ExpectFail` leg. + +Vacuity leg:: an implication whose antecedent never occurs is green for +free. Assertions of that shape need a scenario in which the antecedent +demonstrably holds — I10 has one (a run that really raises two DAQ slots), +and without it the invariant would cost nothing and prove nothing. + +Reachability:: a check nobody runs is not a check. Three instances are +recorded in this document rather than quietly fixed, because the class +keeps coming back: a bound checker whose counter was too narrow to +*represent* the violation it guards; assertion failures that xsim writes +only into a log the scripts silence (now scanned, see +<>); and the reference decoder's own five test +runners, which were wired into no pipeline at all (<>). The +sibling SoC project contributed two more of the same shape in the same +month — a disassembly sniff blind to an instruction alias, and an +instruction counter blind to compressed instructions. + +The fourth shape is the one that is easiest to miss in review, because +the check looks present and reports success. The question to ask of any +gate below is therefore not "does it pass" but "what was done to make it +fail". + == Components [cols="1,2", options="header"] @@ -35,24 +86,115 @@ link:../tests/lib/cpu_model.sv[`tests/lib/cpu_model.sv`] is both the stimulus and the reference. The `ct_env` harness wires it to the DUT and the trace sinks. -| `NexRv` + -link:../bin/NexRv[`bin/NexRv`] -| The RISC-V N-Trace reference decoder, independent of CEDARtools.TraceEncoder. Vendored -as a binary. +| CTTD (CEDARtools.TraceDecoder) + +link:../scripts/fetch_cttd.py[`scripts/fetch_cttd.py`] → `bin/cttd-` +| The reference decoder for the RISC-V N-Trace stream — a *second, +independent implementation* of the wire format, not a CTTE component. +Derived from the RISC-V Nexus Trace TG reference decoder NexRv (ISC) and +extended by Accemic (E-Trace `-decoe`, DAQ, multi-target `-target`, CTXP +export). Since 2026-08-17 it is **no longer committed**: `scripts/cttd.pin` +names the release and the sha256 per platform, `fetch_cttd.py` downloads it +from the CTTD GitHub release assets (`base_url` in the pin file) into +the gitignored `bin/`, and a checksum mismatch is a hard error. +Which build is pinned and why is the pin file plus the CTTD changelog; see +<> for why that record is part of the verification argument. + +| CTTD's own regression runners +| The decoder repository ships five runners of its own — `run_etrace_ctxp`, +`run_callstack`, `run_ctxswitch`, `run_reserved_tcode`, `run_addr64` — +collected behind one exit code in its `tests/run_all.sh`. They run +when `NEXRV_SRC` points at a decoder source tree; a plain +clone of *this* repository has none, so the step reports `SKIP` there +(see <>). | `decode_and_check.sh` + link:../scripts/decode_and_check.sh[`scripts/decode_and_check.sh`] -| Runs NexRv on the captured `.atb.bin` and compares against the +| Runs CTTD on the captured `.atb.bin` and compares against the expected files. Check flags: `--pc` (PC stream), `--ctxp` (CTXP records — memory accesses *with data values* and DAQ instrumentation), `--data` (loads/stores, address + size only), `--sync N` (at least N sync -messages), `--hist N` (at least N branch-history messages — guards against -a config that degrades to sync-only), `--disabled` (trace-off correlation -message), `--overflow` (an Error/QueueOverrun message must be present), -`--tsmono` (the reconstructed absolute timestamps are monotonic), `--soft` -(report divergence but do not fail). +messages), `--disabled` (trace-off correlation message), `--overflow` +(an Error/QueueOverrun message must be present), `--soft` (report +divergence but do not fail). + + + +It also fixes one decoder *policy* for the whole regression suite: the +decode runs with `-csstrict`, the strict reading of the return-address +mirror. A scripted `cpu_model` never switches task, so a mirror +mismatch there is a defect and must be fatal. A test that legitimately +switches context sets `NEXRV_CS_LENIENT=1` and gets the lenient +reading instead — see <>. |=== +[#decoder-pin] +== The reference decoder is a gate input, not a given + +Every PASS in this suite is a statement about *two* implementations: the +encoder wrote the bytes and the decoder read them back. That makes the +decoder binary a measuring instrument, and a measuring instrument has to +be verified before its readings are believed. Concretely: **changing the +pin changes every gate in the repository**, so a re-pin is treated like +a wire-format change — it is only accepted with evidence, and the +evidence is recorded with the pin bump (`scripts/cttd.pin` commit message +naming what changed in CTTD and which verdicts here move) and in the CTTD +repository's changelog, not in an unrelated commit message. + +The evidence a re-pin has to carry: + +* **the defect it removes**, reproduced on the *old* binary with the + same input — not argued from source reading; +* **byte neutrality on everything that already passed**: the old and + the new binary are run over the frozen corpora and every output is + compared, including the `-full` log and the exit code, not just the + PC list; +* **its price**, measured. A decoder change that removes an abort also + removes whatever that abort happened to catch. + +Two re-pins in 2026-08 show what that looks like in practice. + +*64-bit addresses (and then: one width per source).* The decoder in the +tree could not decode a 64-bit address at all — on an Sv39 kernel window +it truncated to the low 32 bits, printed `0x00000000` and exited 9. +Every RV64 gate run against it would therefore have been not merely +weaker but meaningless. The replacement derives its output width from +CAPS bit 23 (`ADDR64`) in the configuration message rather than from a +CLI switch, and mirrors the widened jump-target-cache fold of +`rtl/ct_L2_msg_gen.sv`. On 32-bit streams it was shown byte-identical to +the binary it replaced across 525 of 525 artefacts. Its immediate +successor fixed the follow-on defect that the first one had: the width +lived in a process-global flag while the rest of the decode state was +per target, so in a funnel stream one RV64 source switched the printed +width of the RV32 sources as well (guard `run_addr64`: PASS=16 FAIL=6 +before, PASS=22 FAIL=0 after; 440 of 440 artefacts unchanged at 32 bit). + +*A context switch is not a decoder error.* The return-address mirror the +decoder keeps for implicit-return compression predicts where a `ret` +goes. When a preemptive kernel schedules a different task, the +prediction is wrong *and the stream is right* — the target is carried +explicitly. The pinned decoder treated that as fatal, so **any +multitasking kernel was decodable only up to its first context switch**. +The current pin reports a visible re-anchor instead and keeps decoding; +on the same recorded board stream that moves the decode from 34 537 +instructions plus an abort to 818 663 instructions with `Decoded OK` and +zero error messages. + +The price of that change was measured rather than assumed: a one-byte +mutation sweep over 40 cases is detected 25 times by the new binary and +27 times by the old one. The two lost detections are `UADDR` flips at +returns that the strict mirror caught by accident. The counter-measure +is the `-csstrict` default described above — it restores the old +detection strength for the scripted suite and was shown byte-free on all +56 corpora, so the regression path loses nothing while a real kernel +stream can still be decoded. + +CAUTION: the general rule behind this section is worth stating on its +own, because it applies to every tool in a verification chain: *a gate +that can only fail together with its own tool judges nothing.* It is why +the 64-bit emission gate `instruction/35_addr64` reads its verdict off +the raw bytes instead of asking the decoder (see the gate table below), +and why the decoder is cross-checked against independent artefacts — +oracles, listings, its own fixtures — rather than against the encoder +alone. + == Test scenarios Scenarios live under link:../tests/[`tests/`]; `make sim` runs them all @@ -67,7 +209,7 @@ and prints a per-category PASS/FAIL summary, `make sim-` runs one. | `sim-stress` | `tests/instruction/03_stress` | Dense control flow, HIST overflow, inferable calls/returns; branch-HIST sync-seed regression gate. | `sim-periodic-sync` | `tests/instruction/04_periodic_sync`| Periodic sync without HIST loss (pre-flush ResourceFull regression gate). | `sim-exceptions` | `tests/instruction/05_exceptions` | Synchronous exceptions, including the illegal-instruction shape where the faulting instruction never retires (`iretire=0`). -| `sim-data-basic` | `tests/data/01_basic` | Data-trace address, size and data value vs. NexRv CTXP (`--ctxp`). +| `sim-data-basic` | `tests/data/01_basic` | Data-trace address, size and data value vs. CTTD CTXP (`--ctxp`). | `sim-overrun-recovery` | `tests/overflow/01_overrun_recovery`| Full overrun lifecycle: queue-overrun injection, FIFO-overrun resync, soft-reset recovery (`--overflow` is hard). | `sim-hsi-csr-cap` | `tests/hsi/01_csr_cap` | ACT-CAP CSR-driven DAQ; AXIS beat self-check + CTXP DAQ records. | `sim-combined` | `tests/combined/01_all` | Instruction + data + ACT-CAP sync end-to-end. @@ -96,7 +238,626 @@ suite covers, not a per-test average. Plain `make sim` stays uninstrumented It writes into `bld/coverage/`: `merged.info` (lcov, for `genhtml` or the VS Code Coverage Gutters extension), an HTML report under `html/`, and -`coverage-badge.json` — a https://shields.io[shields.io] endpoint document, -ready to be published and pointed at by a badge (the README does not carry a -coverage badge today). The suite still runs to completion if a test FAILs, so -the rate reflects whatever data was produced. +`coverage-badge.json` (a https://shields.io[shields.io] endpoint document) +for the README badge. The suite still runs to completion if a test FAILs, +so the rate reflects whatever data was produced. + +Current suite-wide numbers (Verilator 5.040, full profile incl. E-Trace, +2026-07-25, *pre-P9* — see the note below): **93.42 % measured** line +coverage (4 972 / 5 322 product-RTL lines), **100.00 % effective** — +every uncovered line is either +auto-classified trivial (error detectors, empty `default` arms) or carries +an ACCEPTED waiver with justification and source. The waiver ledger, the +per-gap dispositions and the triage tooling that maintains them are *not* +part of the published tree, so the effective rate cannot be recomputed +from this repository — only the measured one can: `make coverage` +regenerates the report and the measured rate from the sources here. + +NOTE: The 2026-07-25 figures were measured on the pre-P9 RTL and are not +line-for-line comparable to a run on the current tree. P9 removed the +dual-protocol arm of `ct_encoder` (~135 lines) and with it the +`etrace_dual_tb` leg plus the DUAL coverage profile in +`scripts/coverage_etrace.sh` — numerator *and* denominator move. The +rate has not been re-measured since; run `make coverage` + +`scripts/coverage_etrace.sh` + `scripts/coverage_report.sh` before +quoting a current number. + +== Robustness gates (state across discontinuities) + +Every cross-message compression state (JTC mirror, branch predictor, +implicit-return stack, ICNT/HIST accounting) must be re-converged at every +stream discontinuity — FIFO overrun recovery, trace pause, session stop. +Each class that was found on real hardware (KV260 robustness campaigns) +has a standing regression gate with a documented red counter-proof: + +[cols="1,2,3", options="header"] +|=== +| Gate | Script | Contract it guards + +| `overflow/01_overrun_recovery` | `cli_sim.sh overrun_recovery` | Full overrun lifecycle (inject, resync, soft reset). +| `overflow/02_natural_overflow` | `cli_natovf_test.sh` | Natural (non-injected) overflow reaches ERROR + recovery, bounded error count. +| `overflow/03_jtc_overflow` | `cli_jtcovf_test.sh` | JTC valid-mirror cleared on both sides across the recovery anchor (board class B1). +| `overflow/04_ir_overflow` | `cli_irovf_test.sh` | Implicit-return stack emptied at the recovery anchor (board class B3). +| `overflow/05_bp_hwsync` | `cli_bphws_test.sh` | BP × halfword-sync interaction (negative datum for the sync-boundary family). +| `overflow/06_suite_isync` | `cli_suiteisync_test.sh` | Full feature suite × instruction-sync. +| `overflow/07_board_replay` | `cli_boardreplay_test.sh` | Oracle replay of a real board sequence through the encoder core (bisector: core vs. SoC path). +| `overflow/08_bp_syncbranch` | `cli_bpsyncbr_test.sh` | No sync may anchor on a plain direct-branch retire in BP mode (`sync_anchor_ok` deferral); phase-swept forced collision. +| `overflow/09_bp_ovfanchor` | `cli_bpovfanchor_test.sh` | Overflow anchor never collides with a branch retire in the emission cycle (`inject_hold`); transitions-exact decode over hundreds of recoveries. +| `overflow/10_replay_ovf` | `cli_replayovf_test.sh` | Board mix/calls sequence with real predictor training + ATB throttle: transitions-exact across back-to-back recoveries. +| `overflow/11_pause_edge` | `cli_pausedge_test.sh` | Trace-pause contract (async `InstTracing` toggles, phase-swept): no count-carrying message between the trace-off correlation and the re-anchor sync; re-anchor `ICNT=0`; `trTeControl.Empty` reads 1 after stop+flush. +| `instruction/33_te_sync_req` | `cli_tesyncreq_test.sh` | Explicit sync request over the TE register: one request one message, the negative leg (no request, no `SYNC = 14`, `SyncReqSource` unmoved), the queue-depth measurement (two back-to-back writes → two messages, three → still two), the collision with an ACT-CAP `CF_SYNC` on the same retire (one message for both — with the CF_SYNC-only control leg that makes the statement meaningful), a request inside a running trace-byte quota as well as after it, a request inside an overflow storm, and the activity check that the switched-on *and requested* feature changes the byte stream exactly by that one anchor. +| `instruction/35_addr64` | `cli_addr64_test.sh` | Address width on the wire (X2a): the raw ATB bytes carry the FULL instruction address in both builds of `ct_pkg::CT_XLEN`. Leg 32 is the committed tree (base PC `0x0000_1000`); leg 64 builds a detached worktree with `CT_XLEN` = 64 and a base PC of `0xFFFF_FFC0_0000_1000` — above 2^32 and with a plausible-looking low half, so a path that truncates anywhere produces a *valid-looking* stream instead of an obviously broken one. The verdict is read off the byte stream (`scripts/check_addr64_emission.py` reconstructs `PC_FADDR` from the MDO nibbles between the last end-of-field and the end-of-message marker; the testbench inhibits SRC and switches timestamps off so that field is the last one), **not** from a decoder: a gate that can only fail together with its tool judges nothing, and at the time this gate was written the reference decoder could not read 64-bit addresses at all. The gate keeps that property deliberately — it says the bytes carry the address, nothing more. The *round trip* is a separate claim with separate evidence: the decoder pin that reads CAPS bit 23 (<>) and the RV64 board decode (<>). +| `instruction/15_trig_seq_own` (context width) | `cli_ctxwidth_test.sh` | The TIP context bus reaches the wire at the width the build knob names (W2). Rebuilds the ownership testbench in a detached worktree with `ct_pkg::CT_CONTEXT_WIDTH` = _w_ and requires the *predicted* `PROCESS` value in the decoded message dump — `(context << 5) \| (v << 4) \| (prv << 2) \| format`, at _w_ = 16 that is `0x1fffee`. Two built-in counter-proofs: the width-2 value (`0x6e`) must no longer appear (it would be the evidence of a silent narrowing somewhere on the path), and the run must stay PC-lossless against the same `cpu_model` reference the width-2 build is verified against. Red counter-proof `MUTATE=1`: narrowing the composer's context cast back to `[1:0]` — measured `0x1fffee` 0×, `0x6e` 1×, gate red. +| `instruction/34_etrace_resync_ir` | `cli_etrace_test.sh resyncir` | E-Trace mid-stream resynchronization × implicit return (P10 soak family S-1/S-2): a periodic sync anchoring on a predicted RETURN retire must stay folded; discontinuity-target reports whose address is also linearly reachable carry the `updiscon` flag; a fold arriving at the reported address ends the decoder walk. Braid of far-call/return and call-to-next-address/double-return shapes under a tight periodic window, IR off *and* on, both PC-lossless plus ≥3 mid-trace F3.0 anchors. Red counter-proof: on the pre-fix tree the OFF half already fails (`prefix mismatch, 332/336`). + +| `instruction/37_sync_cadence` | `cli_synccadence_test.sh` | The periodic-sync cadence a product comes out of RESET with (P0-02). One scenario -- 100 010 retires, 15 % control-flow density, compact program image -- driven against a sink of FINITE bandwidth (one accepted ATB beat per 10 cycles = 40 MB/s; an always-ready sink cannot answer the question at all, because under it no cadence ever announces an overflow). The positive leg deliberately does NOT write `trTeControl.InstSyncMax`: it flies the reset value, and must produce ZERO `Error` messages (TCODE 8) and a strictly lossless NexRv decode (100 008 of 100 008 PCs), with the cadence read back off the WIRE from the config message (`VendorConfig P1[12]` bits [10:7]) and required to equal both the RDL declaration and the generated RTL reset -- a three-way agreement no source read could establish. The counter-proof varies exactly ONE factor: the same scenario with `+SYNCMAX=0` (the minimum period, 16 units) must still reproduce the stress case, measured 790 Error messages and 5 064 dropped eTIP events. The sink threshold is swept in the same run (lossless from `InstSyncMax` = 2 upwards), and the bandwidth curve behind the chosen reset value is reported against an unthrottled sink: 97 844 bytes at period 16, 41 072 at 1024, 40 060 with the cadence effectively off. +| `instruction/36_block_tip` | `cli_blocktip_test.sh` | Block ingress (R1.3, `ct_pkg::CT_EN_BLOCK_TIP`): reporting several retired instructions in ONE tip beat does not change the reconstructed control flow, only its packaging. ONE scenario is written once and driven TWO ways inside the SAME block build -- one instruction per beat, and blocks of 1..4 instructions with every terminator kind (`OTHER` / taken / not-taken / call / return / indirect jump) plus a loop whose branch jumps back to the start of its own block. Both legs log a PER-INSTRUCTION oracle, so `expected.pcs` is a reference that never saw a block; both must decode to it EXACTLY (`decode_and_check --pc`, strict). The anti-vacuity witness is measured at `tip_if`, not in the bytes -- the halfword distance between two control-flow events does not depend on how the beats were cut, so byte-identical output is the claim and not a symptom; what has to hold is the same halfword total in strictly FEWER beats with at least one beat carrying more than one instruction (measured 76 halfwords in 14 vs 38 beats, largest beat 8 halfwords). Four red counter-proofs (`MUT=M1..M4`): the halfword derivation forced to the single-retirement branch, the control-flow source address forced to the block start, the ProgTraceSync anchor moved to the block's last instruction, and the anchoring block's carry-over reduced to its last instruction -- each fails the block leg while the serial leg stays green. Byte neutrality of the default build: `scripts/r13_off_neutrality.sh` (31 of 31 reference artefacts identical); resource cost: `scripts/r13_ooc_cost.sh`. +|=== + +*Honesty note (2026-08-07):* the 2026-07 E-Trace verification ("mid-trace +periodic resync solved", directed leg `23_etrace_resync`) was too broad a +claim: none of its legs crossed a resync with the implicit-return stack, +with an ambiguous (linearly reachable) target report, or with an overflow +anchor landing on a branch. The P10 seed-driven soak found all three as +**pre-existing** defects of the E-Trace back end (the campaign only widened +the stimulus surface); they are fixed with the `resyncir` gate above and +the overflow-anchor deferral (`OvfPend`, `ct_L2_te_inst_gen.sv`). One class +remains open by wire-format necessity (S-1c): with `irdepth` width 0, an +implicit-return-folded loop crossing a positional binding point (trap/off +flush, window or resync anchor) cannot express the visit count — measured +6/33 red among IR-armed runs of a free-axis calibration (`efix_cal1`, +seed 20260806). The implicit-return bit is therefore masked from the +E-Trace soak draw until an `irdepth` field exists; every other compression bit is drawn. + +The compression features additionally carry **byte-identity legs** +(`cli_{bp,ir,jtc,rh,rb}_test.sh`): feature OFF vs. ON against the same +stimulus — OFF prefix must equal the reference, ON must decode to the +same PC stream at a strictly smaller byte count (lossless fold). These +legs pin the wire format: any by-product byte change in an unrelated fix +turns them red. + +[#in-rtl-invariants] +== Standing in-RTL invariants (SVA) + +The most expensive lessons of the hardware campaigns are encoded as +concurrent assertions inside the RTL (simulation-only, +`pragma translate_off`). They run in *every* simulation of every +consumer, so a regression fires at the first sim instead of on a board: + +[cols="1,4", options="header"] +|=== +| ID | Invariant + +| I1 | No ordinary CF eTIP while the resume gate holds (pause re-anchor pending) — only the sync-anchor beat releases. +| I2 | No ordinary CF eTIP while instruction tracing is paused (aligned qualifier low). +| I3 | The implicit-return stack is empty when the trace-off correlation is emitted. +| I4 | A `next_iaddr` capture fires only when a CF event owes one (pairing conservation). +| I5 | A gap re-anchor sync (TRACE_ENABLE / EXIT_*) on a call/return retire leaves the return stack untouched (side-effect-free anchors). +| I6 | A correlation message implies cleared JTC mirror and predictor count. +| I7 | A FIFO-overrun recovery sync carries `ICNT=0` (pure re-anchor). +| I8 | `trTeControl.Empty` implies an empty ATB output queue (per backend tail). +| I9 | In a beat carrying both, the Device ID slot precedes the config slot (on-wire order "Device ID → config → first synchronizing message", `CT_EN_DEVICE_ID` + `CT_EN_CONFIG_MSG`). +| I10 | A watchpoint slot never coexists with a DAQ slot in one beat — the exclusion that lets `CT_EN_WATCHPOINT_MSG` share the DAQ slot instead of widening `ETIP_PAR_MSG` (`CT_EN_WATCHPOINT_MSG`). +| I11 | No ordinary CF eTIP inside a CF-filter gap — between the region-exit correlation and the re-anchor the decoder has no position, so a plain control-flow message would be one it cannot place. Same contract as I1/I2, one level further in (`CT_EN_FILTER_SYNC`; vacuous while `trTeInstFilters` = 0, i.e. in every unfiltered run). +| I12 | Every emitted instruction count fits the N-Trace I-CNT field — the `ICNT` of an ICNT-bearing message and the `RDATA` of a `ResourceFull` with `RCODE=0`, both against `MAX_NEXUS_ICNT` (8 bit, or 16 with `trTeInstFeatures.InstEnWideIcnt`). A *conformance* invariant, and the only kind of defect no other gate in this tree can see: the field is MSEO-variable-length, so an over-cap value costs one wire byte, decodes correctly and keeps every PC check and every byte-neutrality gate green while the stream has left the standard. +|=== + +NOTE: One contract of the composer is deliberately *not* a concurrent +assertion: the eTIP slot bound (`msg_id_next \<= ETIP_PAR_MSG`, violation += silently dropped messages). `msg_id_next` is a variable of the +composer's `always_comb`, so a concurrent property samples the preponed +value — which has already fallen back — and reports a value that cannot +violate the bound, one cycle late. It is therefore an *immediate* +assertion at the allocation site (`a_p4_slot_bound`), and the measured +demand is reported at end of sim ("eTIP max slots per beat"). Any new +property in that block must stick to registered state or module inputs. +Because xsim writes assertion failures into the per-leg log and the cli +scripts silence the simulator, `scripts/cli_status_test.sh` scans those +logs and fails the gate on any `Error:`/`Fatal:` line — an assertion +nobody reads is not a gate. + +CAUTION: a bound check is only worth its name if its counter can +*represent* a violation. `msg_id_next` used to be sized +`$clog2(ETIP_PAR_MSG+2)` — three bits, i.e. 0…7, for a profile with nine +simultaneously enabled allocation sites. A beat demanding eight slots +would have wrapped the counter to 0 and passed `a_p4_slot_bound` +unnoticed: the guard would have been exactly as silent as the defect it +guards. The width now follows `ct_pkg::ETIP_SLOT_SITES` (the number of +`msg_id_next = msg_id_next + 1` statements in the composer), and +`formal/composer_slots/run.sh` counts the real sites in the source before +every run, so a newly added arm fails the gate rather than the field. +Generalised: a saturating or wrapping checker variable is a checker +defect, not a rounding detail. + +NOTE: I10 is only worth its cost argument if a leg exists in which the +design really raises DAQ slots — otherwise the implication holds +vacuously. That leg is `wpdaq` in `tests/instruction/31_status_msgs` +(two watchpoint messages and one Data Acquisition message in one run); +removing the watchpoint exclusion from the composer's DAQ arm makes I10 +fire and lifts the reported slot watermark from 1 to 2. + +[#formal-gates] +== Formal property gates (SymbiYosys) + +The three encoder defect classes of the 2026-08 board campaigns +(trap anchor, resume-anchor race, flush clobber) shared one shape: +local cycle collisions with a tiny state space — phase-dependent, +found dynamically only by lucky draws, found formally in seconds. +The emission core therefore carries formal property gates on the +license-free open-source route (sv2v + Yosys/SymbiYosys, smtbmc): + +[cols="1,2,2", options="header"] +|=== +| Target | Properties | Result + +| `ovf_injector` (both variants: parallel P=2 and `SEQ_INJECT` P=1) +| P-INJ-1..4: element conservation (forwarded XOR counted-discarded), + episode debt (each marker exactly once before forwarding resumes), + `inject_done` contract, `inject_hold` semantics — proven as full + functional correspondence against an independent mirror model +| *unbounded* (k-induction) + cover + +| `ct_L23_preproc_sync` +| P-SYNC-1: no PERIODIC sync while a TRACE_ENABLE re-anchor is + outstanding (the class-9 resume-anchor race, fix `335393b6`); + P-SYNC-2: one-shot arming/drop semantics; P-SYNC-3: sync anchors only + on qualified retires; P-SYNC-4: the fix guard cannot starve the + periodic arm (gap bound 64 cycles); P-SYNC-5/6/7: the trace-output + quota (window bound, no lost request, no double request), closed + through the real CDC pairs; P-SYNC-8: completeness — every arming + condition the DUT states really sets its one-shot in the next cycle; + P-SYNC-9/10: the explicit request over the TE register — no lost + request (after a WRITE a message follows within a bounded number of + cycles; the trigger is the software event and only a MESSAGE stops + the clock) and no double request (every message consumes one launched + request). The loop is closed through the CSR shim's real pacing module + `ct_sync_req_pacer` and both real `strobe_cdc` instances, *at equal + clocks* (the single-clock assumption of this environment): what is + proven is the pacing protocol plus the toggle synchronizers, not the + behaviour of a toggle synchronizer between two independent clocks — + that remains a CDC-methodology argument. The rest of the CSR shim + (address decode, generated register block, the field's self-clear) is + covered by simulation, not here. P-SYNC-11: the explicit request and + the trace quota in ONE environment — on a beat where both stand at the + arm the message is the explicit request, and neither source starves + the other +| P-SYNC-1..3 + P-SYNC-8 *unbounded*, P-SYNC-4/5b/6/7/9/10/11 bounded + cover + +| `ct_L2_msg_gen` (abstracted eTIP payload) +| P-MSG-1: a consume beat never coincides with a flush-marker emission + (the class-8 flush clobber, fix `8f8e85aa`); P-MSG-2: backpressure + holds `TraceMsg` bit-stable; P-MSG-3: drain holds emit and never + consume; P-MSG-4: the latched flush debt is never lost and a free + emission slot pays it immediately; plus I6/I7 and the module's + internal drift-guard assertions +| BMC depth 50 + cover + +| MDO/MSEO output stage (msg_buffer -> bit_slicer MDO=6 -> dual MSEO + controller -> ATB chunk packer, glued as in the formatter top) +| P-MDO-1: the reserved dual-pin MSEO code is never emitted; + P-MDO-2: encoding table (EOM=11, end-of-variable-field=01, data=00, + IEEE-ISTO-5001-2012 Table 5-1); P-MDO-3: message conservation (every + accepted non-flush message yields exactly one end-of-message chunk); + P-MDO-4: the CDC seam never overruns; P-MDO-5: beat alignment (lanes + after an EOM lane are align pads — no message starts mid-beat); + P-MDO-6: stall stability; P-MDO-7: flush-marker isolation; plus a + bounded no-starvation guarantee (next EOM within 64 cycles under a + free-flowing sink). Red cross-checks by MUTATION (no historical + defect commit exists for this stage): wrong EOM code, missing + full-gate, suppressed EOM — each must turn its property red. +| BMC depth 40 + cover + bounded liveness (depth 120) + +| `ct_L23_preproc_composer_etip` eTIP slot bound +| P-SLOT-1: `msg_id_next \<= ETIP_PAR_MSG` at the allocation site — the + module's OWN immediate assertion `a_p4_slot_bound`, checked over the + real module with a completely free environment (every tip beat, every + sync verdict, every ACT-ST command, every CSR value), for both + `SPLIT_DATA_ACCESS` settings. An exceeded bound writes out of range, + which writes NOWHERE — messages would be lost silently and without a + wire-visible error, so this constant may not rest on an argument. Red + cross-checks in two directions: one slot below the formula value must + break the assertion (the bound is the minimum, not padding), and + removing the watchpoint exclusion from the DAQ arm must break it too + (the slot-sharing argument is alive). +| *unbounded* (k-induction), both `SPLIT_DATA_ACCESS` settings +|=== + +NOTE: these targets are proved on the committed tree, i.e. at +`ct_pkg::CT_XLEN` = 32, and the formal wrappers re-type the address ports +by hand — so a 32-bit proof says nothing about a 64-bit net. One target, +`nexus_formatter`, therefore also runs as `nexus_formatter_xlen64` +against a source copy with the width flipped; the other targets have no +width leg. This was an audit finding, not a plan: until 2026-08 every +formal gate had only ever seen 32 bit. + +Every regression property carries a *two-sided red counter-proof*: the +property-only build passes on the fixed RTL and fails on a git worktree +of the pre-fix commit (class 9: red at BMC step 6 on `441eac4c`; +class 8: red on `335393b6`) — the formal gate demonstrably catches the +historical defect class. (The two fixes are consecutive commits, which is +why class 8's pre-fix tree carries class 9's fix hash — both entries name +the tree the property is run *against*, not the fix.) Every environment +assumption is enumerated and +justified in link:../formal/README.md[`formal/README.md`]; the same +document records the tool workarounds (sv2v prefix strip, uwire, SVA +re-statement) and the hardening finding F-1 (a saturation escape in +`counter.sv` via the undriven `add` path, unreachable in the real +netlist). + +[NOTE] +==== +*What a one-directional property does and does not prove* (P7 audit +condition A-2). The `A_*_impl` strengthenings and the `A_sync2_*` +obligations of `preproc_sync` carry the wrapper model on their +*conclusion* side (`DUT one-shot -> model armed`). Such a property gets +*weaker*, never stronger, when the model arms in more states, and a DUT +that stops arming altogether satisfies it vacuously: it catches a +*spurious* event, never a *missing* one. Measured, not argued — with the +TCI trigger action removed from the RTL +(`cs_tip.trTeTrigExtInAction0 -> 4'd0`, i.e. the whole action-4 path +dead) the suite still reported `successful proof by k-induction`. + +`P-SYNC-8` supplies the other direction as a bounded next-cycle +obligation, and the same mutation is red on `A_trig_complete`. When a +new event source is added to this module, both directions have to be +extended — the arming term in the model AND the arming condition in the +completeness block. Adding only the first one looks like a +strengthening and is the opposite. +==== + +== Hardware-in-the-loop and SoC integration + +Everything above runs against a scripted `cpu_model`: a stimulus that +does exactly what the test asked for. Three things that model cannot +produce are a real hart's retirement timing, a real memory system's +backpressure, and a real operating system's behaviour — so the encoder +is additionally driven from real cores, in simulation and on a board. +A worked example lives in this repository under `examples/` (the TGC5B +example SoC with its simulation and KV260 board flows); the full +multi-core campaign artefacts and the per-core characterization tables +stay in the Accemic-internal integration project, not here. + +Three ingress adapters exist today, all outside the encoder core: the AMD +MicroBlaze V `TRACE` bus, the CVA6/cv64a6 instruction-trace interface fed +from its RVFI probes, and the Rocket `TraceCoreInterface`. Each was +**characterized before it was trusted**: +a truth table per event class, measured against the core's own retire +stream, is the entry gate for a new adapter — an unverified assumption +about a core's trace signals is a blocker, not a design decision. + +=== Robustness campaign (MicroBlaze V, KV260) + +The campaign drives the encoder on a Kria KV260 +(MicroBlaze V + adapter + `ct_encoder`, URAM ring sink) through a +directed 95-run matrix: overflow regimes R0–R5 (incl. ATB backpressure +profiles), feature sets, workload mixes (calls/loads/traps/random), sync +modes, trace-window and stop/flush edges, IRQ, BTM, one-factor bisection +legs and a determinism pair. Verdicts V1–V8 are machine-judged against an +RV32 reference model (decode integrity, loss accounting, post-recovery +losslessness, counter consistency, liveness, determinism, window +semantics, flush completeness). Deploys are hash-verified at the target +(a silent deploy failure once invalidated a whole campaign's +attribution). + +Result as of 2026-08-01 (campaign `rob_allgreen`, bitstream WNS +2.679 ns +— that slack belongs to the 2026-08-01 bitstream and its tool version, +not to today's encoder; corrected 2026-08-14 from a previously quoted ++2.186 ns, which was Vivado's router estimate rather than the routed +timing summary; the current per-profile figures are below): +**95 PASS / 0 FAIL / 0 invalid**. A full-SoC XSIM twin of the campaign +workload (real MicroBlaze V + adapter at the board's 1:1 clock profile, +343 629 retires, 24 natural overflow recoveries) decodes +transitions-exact as the simulation-side positive control. + +A seed-driven soak campaign on top of the directed matrix is what found +the three 2026-08 encoder defect classes that the formal gates now hold +(trap anchor, resume-anchor race, flush clobber) and the four +pre-existing E-Trace classes named in the honesty note above. The +directed matrix is the regression floor; the soak is what widens the +stimulus surface far enough to hit phase-dependent collisions. + +[#rv64-cores] +=== 64-bit harts: cv64a6 and Rocket (2026-08-08) + +`ct_pkg::CT_XLEN` = 64 is not established by a testbench alone. Two +open-source RV64 harts were brought up in the KV260 PL with the encoder +beside them, each through its own adapter, and both boot Linux +(Buildroot + OpenSBI) to a login prompt: **cv64a6** (CVA6, RV64IMAC, +Sv39, no FPU) and **Rocket** (`Rocket64t1`, RV64IMAC, no FPU). A booting +kernel is a stimulus nobody has to write: virtual Sv39 addresses above +2^32, traps into M-mode at physical addresses, and a preemptive +scheduler, all in one stream. + +*Simulation leg (cv64a6).* The full chain core → RVFI → ITI → shim → +`ct_encoder` (`CT_XLEN` = 64) → ATB → CTTD → scoreboard reconstructs +**10 167 of 10 167 instructions, delta 0**, in the low address window and +again with Sv39 kernel addresses. + +*Board leg (cv64a6).* With a bitstream carrying the 64-bit encoder, a +recorded window of the running kernel decodes to **34 453 instructions, +of which 32 413 have addresses ≥ 2^32**, with **zero error messages**. +The verdict does not rest on the decoder: an independent flow check +walks the decoded PC sequence against the disassembly and requires every +PC to sit on an instruction boundary and every direct edge to follow the +listing. It reports PASS, with five deviations — all five to the same +address, OpenSBI's M-mode trap vector, i.e. the physical trap target of +a virtually-addressed kernel. That check is itself counter-proved: +shifting one instruction by two bytes in the listing turns it red. + +With the current decoder pin (<>) the same recorded stream +decodes **818 663 instructions** uncompressed and **883 577** with the +compression suite armed, both with zero error messages and both PASS on +the independent flow check; the first 34 537 PCs are byte-identical to +the earlier run, so the longer decode extends the old result rather than +replacing it. + +*What bounds these numbers is not the encoder,* and the distinction is +worth keeping: the 1 MiB URAM ring is full, and for the larger DDR window +the *listing* runs out — Linux patches its own text at boot and later +overwrites `.init` with poison, so no single static disassembly can +describe the whole boot. Both limits are properties of the target and +the reference, not of the trace. + +Two honest gaps at the time of writing. **Parallel retirement is not +exercised**: both harts run with a single commit port (Rocket cannot do +more; the cv64a6 build was configured that way), so the multi-retire +path remains a simulation argument. And an E-Trace instance with +`CT_XLEN` = 64 is **rejected at elaboration** rather than truncating +silently — 64-bit E-Trace is not implemented. + +[#process-filter] +=== Tracing one process, end to end + +The per-process filter (`trTeComp[].PInput` = 1 on the context bus, see +link:enhanced-features.adoc#filter-anchoring[Enhanced features]) is +verified as a chain, not as a register: two programs with different ASID +values run on the cv64a6 model, and the decoded PC stream is checked +against *both* programs' address ranges. + +* unfiltered: both processes appear (204 and 168 instructions in their + respective ranges), and the Ownership messages carry both ASIDs; +* filtered to process A: **204 of 204** for A, **0 of 168** for B, and + only A's ASID on the wire; +* filtered to process B: exactly the mirror image. + +The second bullet is the substance of the feature — the filter +**suppresses at the source** instead of marking: a filtered-out +instruction contributes nothing, not even to the instruction count. Two +red counter-proofs keep the statement from being vacuous: making the +filter ineffective returns the full 437-PC stream (so the gate can tell +the two apart), and compiling out the filter anchoring produces a stream +with no `ProgTraceSync` at all, from which the decoder recovers zero +instructions — which is exactly the pre-fix behaviour the anchoring was +added for. + +NOTE: this leg is simulation with real core RTL. Filtering *real Linux +processes* on the board — where the ASID is written by the kernel rather +than by the test — is a follow-on package and is not claimed here. + +[#ooc-timing] +== Timing and resources (out-of-context synthesis) + +The acceptance line is "no timing violation in the target +configuration", so the gate needs a *budget* — a slack figure without +one says nothing. It is run per build profile, at two budgets: + +* **13.333 ns (75 MHz)** — the clock the KV260 reference design is + *constrained* to. This is the pass criterion: every profile must meet + it, with Vivado's own "All user specified timing constraints are met" + and zero failing endpoints in the report. +* **5.0 ns (200 MHz)** — headroom, reported but not required. + +[CAUTION] +==== +*The constrained clock is not automatically the clock the board +delivers.* Measured on 2026-08-08 on the RV64 board designs: loading an +application overlay that names only a firmware file leaves the PS clock +register `PL0_REF_CTRL` at its boot default — IOPLL 1500 MHz / 15 = +**100 MHz** — so the PL ran a third above the frequency every design in +this project is constrained for. Two independent readings agree (the +register value, and a guest-versus-host wall-clock ratio of 1.333 on the +booting kernel), and re-running with the clock explicitly set to 75 MHz +brings that ratio to 1.000 while the recorded trace stays byte-identical. + +Three consequences, stated plainly rather than smoothed over: the 75 MHz +column below is a **constraint met in synthesis**, not a measurement of +what silicon saw; the earlier board campaigns were loaded the same way +and have **not** been re-measured, so they may have been running above +budget (which would make their green verdicts a stronger empirical +result, but not a verified-configuration one); and an integration that +needs the constrained clock has to *set* it when loading the design. This +is a property of the loading mechanism, not of the encoder. +==== + + bash scripts/p10_timing_matrix.sh # all five profiles + +drives `scripts/synth_encoder_ooc_timing.tcl` (the timing variant of the +OOC script: one clock per clock port at the budget, +`set_clock_groups -asynchronous` between them, `report_timing_summary`) +over `voll_gold`, `featparity_gold`, `slimfull_gold` and the two +single-protocol builds, and files every report under +`verification/evidence/P10//` with the verdict in +`verification/evidence/P10/timing.log`. The numbers, and the caveats that belong +to an out-of-context figure, are in +link:integration.adoc#profile-timing[integration, *Timing per profile*]. + +Status 2026-08-06 (commit `7a0b7b2`, Vivado 2022.1.2): **all five +profiles meet the board budget**, smallest margin +1.753 ns; the two +slim profiles also meet 200 MHz, the three full-profile builds do not. +Before this run the project had *no* timing artefact at all — every +package's OOC synthesis used the variant of the script that constrains +no clock and reports no timing, and the timing variant had been unable +to run since an SPDX header entered the file list it reads. + +[#ref-families] +== Reference-stream families and supersession + +The byte-identity gates compare emitted streams against a *pinned +family* of reference md5s (the `REF_FINAL` family: the +`implicit_return_tb` off/on/nots anchors plus the full-suite manifest), +minted by `scripts/r2_final_mint.sh` into `bld/r2_final_manifest.txt` +with a run log in `bld/r2_final_mint.log`. + +Supersession policy — a family is re-minted **only** when the byte +delta against the previous family is *provably explained*, and the +proof is recorded with the new hashes: + +* the delta must be localized (message dump / decode comparison, not + just a differing md5), +* a build with the causing feature compiled **out** must reproduce the + previous family md5-exactly (byte-neutrality cross-check), +* the superseded hashes stay recorded in the mint log — they are + documentation, not garbage. + +Anything short of that full explanation is a FAIL to investigate, not a +re-mint. Wire-neutral RTL work therefore never touches the family; +deliberate wire evolutions (e.g. a CAPS extension of the +self-describing config message) produce exactly one documented +supersession. + +Example (2026-08-03/04): the trace-quota feature widened the TCODE-58 +CAPS/ENAB map append-only from 18 to 19 bits (new CAPS bit 18). The +full-build delta against the previous family was *exclusively* the +config-message bit — byte count identical, PC decode identical — and +the `CT_EN_QUOTA_SYNC = 0` build reproduced the previous family +md5-exactly. On that proof the family was re-minted; the superseded +hashes remain in the mint log. + +Second example (2026-08-04): DF address compression widened the same +map from 19 to 22 bits (CAPS bit 21 plus two reserved placeholders). +Same proof shape — the `CT_EN_DF_ADDR_COMPRESS = 0` build reproduced +the DF reference streams md5-exactly and the full-build delta was the +CAPS field alone (`0x7ffbf` → `0x27ffbf`) — so the family moved once +more. `scripts/r2_final_mint.sh` now records the supersession itself: +it preserves the previous run as `bld/r2_final_mint.prev.log` / +`bld/r2_final_manifest.prev.txt`, carries the previous +`REF_FINAL_06` line into the new log and manifest header, and takes the +justification from `SUPERSEDE_REASON`. A re-mint without that variable +is recorded as `` — visible, not silent. + +Third example (2026-08-08), and the one that shows the rule has a +*negative* branch too: the 64-bit address knob (`ct_pkg::CT_XLEN`) added +CAPS bit 23 (`ADDR64`) and widened the map from 23 to 24 bits — and the +family did **not** move. The CAPS *word* is what selects a family, and +in a 32-bit build bit 23 is 0, so the word stays `0x7fffbf`; the field +is variable-length with leading zeros stripped, so its byte encoding is +unchanged as well. A wider map is therefore not automatically a new +family: only a different *value* is. `scripts/ref_family.py select` +prints both (`FAMILY_WIDTH` 23 vs `BUILD_CAPS_WIDTH` 24) so the +difference is visible rather than assumed. A build with `CT_XLEN` = 64 +does carry the bit and will need its own family when it is first minted. + +Fourth example (2026-08-13), the converse of the third: the AXIS-WP +merge (C0b, merge `22ee86a3`) moved *bytes* without moving the CAPS +word. Deepening the ACT alignment pipes (`PREPROC_DELAY_MAX` 20 → 44) +shifted message positions, and the P0-02 sync-cadence reset +(`InstSyncMax` 0 → 6) rode along — six artefacts of the previous family +drifted, each drift proven benign before the re-mint (tail truncation +under the no-op `wait_cycles` drain; one composition-time `ENAB` +sample). The re-minted family carries the *same* word `0x7fffbf` as its +predecessor, so the archive now legitimately holds two families per +word. `select` resolves that deterministically: among same-word +families the one with the **newest mint stamp** wins, the passed-over +siblings are printed as `FAMILY_SUPERSEDES` in the gate log, and +reproducing an older comparison stays possible through the gates' +`REF=` override. Only a word *mismatch* (P7 A-1) — or two +same-word mints with an identical stamp — remains a hard error. + +[IMPORTANT] +==== +*A family is selected, not inherited* (P7 audit condition A-1). `bld/` +is gitignored and a mint keeps exactly one generation of history, so two +mints in a row destroyed the older family — including the family an +already-closed package had been measured against. That happened on +2026-08-05, two minutes apart: a gate that pinned +`bld/r2_final_manifest.txt` reported `BYTE NEUTRALITY: DRIFT` from then +on for a build that had not drifted at all, because the new family +carried the very CAPS bit that build compiles out. + +Two rules follow, both mechanical: + +. Every minted family is archived append-only in + link:../verification/ref_final/README.md[`verification/ref_final/`], before the next mint + overwrites it and again right after minting. +. A gate picks the family whose *CAPS word* equals the word its own + build emits. The word is a pure function of the `CT_EN_*` switches + (`ct_pkg::ct_cfgmsg_caps`), so `scripts/ref_family.py select` computes + it rather than guessing, and the gate log names the chosen file, its + CAPS and its mint HEAD. A build whose CAPS word matches no archived + family is a hard error — comparing against a foreign CAPS set can + only fail, and it fails for the wrong reason. If several archived + families carry the *same* word (a re-mint whose byte delta was proven + without a CAPS change, fourth example above), the newest mint stamp + wins and the log records the passed-over files + (`FAMILY_SUPERSEDES`); `REF=` pins an older one deliberately. +==== + +[#ci-stages] +== CI stages + +The suite maps onto four tiers, ordered by tooling cost: host-only +checks (`make lint`, `make check-publication`, the decoder corpus — no +EDA tools), the Verilator subset `make sim`, the XSIM gate battery +(`scripts/run_gates.sh`, list in `scripts/gates.list`) incl. byte-identity +legs and optional coverage, and the hardware-in-the-loop campaign on a +lab machine. `scripts/run_formal.sh` runs the formal property gates on the +OSS toolchain (no EDA license; `RED=1` additionally runs the red +counter-proofs against the pre-fix worktrees). One of its targets, +`nexus_formatter_xlen64`, is the same BMC in a 64-bit address net: the +script copies the RTL into `bld/`, sets `ct_pkg::CT_XLEN` to 64 there and +proves against that copy, because the formal wrappers re-type address +ports by hand and had only ever been exercised at 32 bit +(link:../formal/README.md[`formal/README.md`], *Width leg*). The runners +are plain `bash` and runner-agnostic; the GitHub Actions workflows that +drive the license-free tiers are described in +link:../CONTRIBUTING.md[`CONTRIBUTING.md`], *Continuous integration*. +The hardware tier is not carried by this repository: it needs a KV260 +board, and its verdicts are quoted into `verification/evidence/`. + +The host tier also builds the reference decoder from source when one is +available and then runs **the decoder's own five regression runners** +(`run_etrace_ctxp`, `run_callstack`, `run_ctxswitch`, +`run_reserved_tcode`, `run_addr64`, collected behind the fork's +`tests/run_all.sh`). They were reachable from nowhere before 2026-08: +a decoder change could land with every one of its own tests green and +nothing in this pipeline would have noticed — the same failure mode as a +checker that cannot represent a violation, one level up. The step is a +`SKIP`, not a pass, when `NEXRV_SRC` names no source tree; the decoder +source is Accemic-internal and a plain clone of this repository will see +the `SKIP`. + +The host tier carries eight guards. Six are drift guards over the register +map, the profiles and the harness (feature flags, protocol discovery, +profile dependencies, the `xsim` launch check, compiled-out negative legs, +the micro-CSR twin). The other two guard the *evidence itself*, because +the same two findings came back in every package audit of this campaign: + +* `scripts/check_doc_evidence.py` — a doc section quoting CLB LUTs or + flip-flops must name a `.rpt` under `verification/evidence/**`, that file must + exist, and the numbers in the table cells must be the ones in the + report. Twice, one commit apart, a cost table pointed into gitignored + `bld/`, which the next run of the same script overwrote with a + different configuration. A table that also carries a block-RAM column + has its `Block RAM Tile` figure checked the same way — that row was + read by nobody until the R1.1 closing audit showed it: changing the + LUT figure of + link:integration.adoc#xlen-cost[integration, *Address width*] by one + turned the guard red, changing the BRAM figure from 11 to 42 did not + (finding C-1). +* `scripts/check_evidence_stamp.py` — every verdict under + `verification/evidence/**` must carry a `# HEAD` stamp naming a commit that is in + this branch's history, or an explicit `# superseded-by` pointing at a + run that is. Five logs of one fix round were stamped with a + rebased-away commit and nothing showed it. The guard also prints the + inventory (age in commits, which areas moved since) for every verdict, + on every run — taking that inventory by hand is how the defect was + found. + +The header contract both rest on is in +link:../verification/evidence/README.md[`verification/evidence/README.md`]. + +A third rule, not mechanised: a gate reports `SKIP` (77) when an input it +needs is not in this repository, and `TOOL` (78) when the toolchain or the +build tree could not be established. Neither reads as a property failure. +See link:development.adoc#fresh-tree[Development — starting from a fresh +clone or worktree]. diff --git a/examples/README.md b/examples/README.md new file mode 100644 index 0000000..a87da56 --- /dev/null +++ b/examples/README.md @@ -0,0 +1,75 @@ + + +# Worked integrations + +Everything under `examples/` shows the CEDARtools.TraceEncoder (CTTE) IP doing +real work: driven by a real core, captured by a real sink, decoded by the real +decoder. The root of the repository is the IP; this directory is what it can +do. + +Three entry levels, by rising effort: + +1. **Dashboard demo mode** — no hardware, no FPGA tools, stdlib-only Python. + `examples/dashboard/`, three commands, ~2 minutes. +2. **Simulation** — `make sim-examples` runs the examples wired into + `SIM_EXAMPLES` (the variable in the `Makefile`): `tgc5b-soc` from + `kv260/common/tgc5b/`, plus `ddr-sink-window`, `axis-wp-shim`, + `tgc5b2-axis-soc` and `ctte-smoke` from `kv260/` (see + [`kv260/README.md`](kv260/README.md), "Simulation legs of the KV260 + examples"). Needs abc + a simulator; program artifacts are committed, so + no RISC-V toolchain. The MicroBlaze-V-based examples (`mbv`, `duo`, + `trio`) have benches in the tree but cannot run on the default backend + (encrypted core — see [`kv260/mbv/sim/README.md`](kv260/mbv/sim/README.md)); + the CVA6 and Rocket examples have no bench yet. +3. **KV260 board flows** — build a bitstream, deploy, watch live trace. + `examples/kv260/` (all nine examples migrated; four board-gated from this + tree, see status column). Without Vivado: every demo ships its + ready-to-load app under `kv260//fpga/prebuilt/`. + +## Catalog + +| Example | Core(s) | Status | +|---|---|---| +| `dashboard/` | any (consumes captures) | **in tree** — browser dashboard; demo mode replays committed captures without hardware (`py examples/dashboard/server.py --demo`) | +| `kv260/common/` | — (shared board RTL) | **in tree** — trace sinks (URAM ring, DDR sink, PIB), watchpoint shim | +| `kv260/common/tgc5b/` | MINRES TGC5B (RV32) | **in tree** — not an example but the shared library eight examples build on: the vendored core, the AXI-Lite→Wishbone bridge, SoC RAM/CLINT/INTC + their RDL, and the `hello_trace` program. Its own SoC bench is `make sim-tgc5b-soc` ([`kv260/common/tgc5b/README.md`](kv260/common/tgc5b/README.md)) | +| `kv260/mbv/` | AMD MicroBlaze V (RV32) | **in tree, board-gated 2026-08-17** — 11 bare-metal programs, TRACE-bus ingress adapter; bitstream built here (Vivado 2026.1, WNS +2.094), 26772/26772 PCs prefix-identical on KV260 | +| `kv260/cva6_linux/`, `kv260/cva6_linux64/`, `kv260/cva6_2/` | CVA6 (RV32/RV64, AMP pair) | **in tree; cva6_linux boots on the board 2026-08-17** — reference core fetched by pin + local delta patch series (`third_party/patches/cva6/`), Buildroot br2_external sources (payload builds on a Linux host); cva6_linux bitstream built here (WNS +2.265), OpenSBI + kernel captured; the other two: bitstream flows migrated, board leg pending | +| `kv260/rocket_linux/`, `kv260/rocket2/` | Rocket (RV64, 2-hart SMP) | **in tree** — Buildroot br2_external sources, lint 0 errors with core stubs | +| `kv260/duo/`, `kv260/trio/` | MBV+TGC5B (+CVA6) | **in tree; duo board-gated 2026-08-17** — multi-core funnel; duo bitstream built here (WNS +2.188), both streams decoded on KV260 (first-ever duo board run); trio adds the per-instance protocol mix (Nexus next to E-Trace raw in one CTMX container, demux tool vendored), board leg pending | +| `kv260/tgc5b2_axis_wp/` | 2× TGC5B | **in tree, board-gated 2026-08-17** — watchpoint/DAQ testbed; bitstream built here (WNS +1.575), 851/851 watchpoint records per core on KV260, cross-core merge monotone; sw pipeline byte-identical (E0_ALL_PASS, 1023 watchpoints) | + +## Vivado versions, honestly + +Two tool generations are in play, on purpose (no silent unification): + +- **Core simulation and the gate battery** pin **Vivado 2022.1** (xsim, via + `.abc.config` at the repo root). That is the version every core verdict + recorded under `verification/evidence/` is calibrated against. +- **The `kv260/` bitstream flows** are verified with **Vivado 2026.1**; + the 2026-08-17 board gates (mbv, tgc5b2_axis_wp) ran on 2026.1-built + bitstreams. + +The resource cost of the newer tool generation is measured, not assumed: +~2.5x LUT premium between the two on the same RTL (measured in the +internal predecessor repository; that report is not in this tree). A version +bump for either side is a deliberate, measured change — never a side effect. + +## Rules that keep this directory honest + +- Every example that has a simulation leg is wired into `make sim-examples`, + which **refuses to pass over an empty list** — a summary over nothing must + never read as green. `SIM_EXAMPLES` in the `Makefile` is that list (entry + level 2 above names its current contents). A `kv260/` example without a + sim leg is not in it, so `make sim-examples` says nothing about that + example — its evidence is the per-example board gate. +- Vendored third-party cores (`*/cpu/`) and the pinned reference-core material + under `kv260/third_party/` keep their upstream coding style and are excluded + from lint; everything else lints like the core IP. +- No bitstreams, no `.rpt` reports, no measurement logs in git. Build scripts + and small committed program artifacts only. +- Board flows document their deploy traps next to the flow, not in tribal + memory (see `kv260/README.md`). diff --git a/examples/dashboard/README.md b/examples/dashboard/README.md new file mode 100644 index 0000000..c21a078 --- /dev/null +++ b/examples/dashboard/README.md @@ -0,0 +1,166 @@ + + +# CEDARtools.TraceEncoder dashboard + +A browser-based live view of a CEDARtools.TraceEncoder-instrumented RISC-V SoC: register +map, block diagram, PC stream, symbolized coverage, and (where the design carries +it) AXIS watchpoint records — all read straight from the running hardware over +`/dev/mem`, no custom driver. It ships with a **hardware-free demo mode** that +replays real captured board sessions, so the whole thing is inspectable in a +browser without a KV260, without Vivado, and without any third-party Python +packages (stdlib only). + +## Quickstart (hardware-free demo mode) + +``` +py server.py --demo +``` + +Then open in a browser and pick a scenario from the +menu — that's it. Nothing on this path touches real hardware; every register +value, console line and trace byte comes from the recordings under `demo/`. + +## What it shows + +Ten scenarios ship as demo recordings, one per KV260 SoC build this +repository's `examples/kv260/` family produces: + +| Scenario | Cores | What it exercises | +|---|---|---| +| `mbv` | MicroBlaze V | single-core bring-up, the smallest CTRL map | +| `cva6_linux` | CVA6 (RV32) | Linux 6.12 boot over N-Trace | +| `cva6_linux64` | CVA6 (cv64a6, RV64) | RV64 core, Sv39 addressing through the whole display chain | +| `rocket64` | Rocket (RV64) | a second RV64 core family, single hart | +| `rocket2` | 2× Rocket hart | SMP Linux, two harts sharing one encoder pair | +| `cva6_2_rv64` | 2× cv64a6 | AMP (two independent RV64 guests, not one SMP kernel) | +| `cva6_2_rv32` | 2× cv32a6 | AMP at RV32, Linux-capable core (not the trio's cv32a60x) | +| `trio` | MicroBlaze V + TGC5B + CVA6 | three cores, one funnel, N-Trace **and** E-Trace on the same stream (one back end per encoder instance, mixed in one netlist) | +| `duo` | MicroBlaze V + TGC5B | two cores, one funnel, N-Trace only -- the smallest multi-source case: two ISAs told apart by the Nexus SRC field alone (`demo/demo_trace.bin` IS this recording) | +| `tgc5b2_axis_wp` | 2× TGC5B | the AXIS watchpoint testbed (live record table, not trace) | + +Each scenario page shows the live (or replayed) block diagram, the full CSR +map with per-block filtering, the decoded PC stream and symbolized coverage, +and — for `tgc5b2_axis_wp` and `trio` — the AXIS watchpoint record view +(`wp.html`). + +## Running it on real hardware + +The same `server.py` runs unmodified on a KV260 (or KR260): start it without +`--demo` and it opens `/dev/mem`, auto-detects the loaded bitstream from the +active app, and serves live register reads instead of a recording. That needs +the matching bitstream from `examples/kv260/` deployed and running — see that +example's own README for the board-side deploy steps (bitfile, device-tree +overlay, systemd unit via `board_dashboard_install.sh`). + +The live path itself is unchanged from the board-verified version it was +migrated from, but it has not been re-run on hardware from this tree -- +what is exercised here is demo mode and the test sweep below. + +**Security note:** the dashboard has **no authentication**, and its +`/api/write` endpoint is effectively **direct `/dev/mem` write access** on the +host that runs it. It is meant for a lab bench, bound to `127.0.0.1` and +reached over an SSH tunnel, or — if bound to `0.0.0.0` for direct reach — run +only inside an isolated lab network segment. Never expose it to an untrusted +network. + +## Testing + +Every test here is a standalone script (`py .py`, not a pytest +suite with `def test_*` functions) that prints a `PASS`/`FAIL`/`SKIP` verdict +and exits 0 on pass-or-skip, 1 on any real failure: + +``` +for f in test_*.py; do py "$f" || echo "FAILED: $f"; done +node test_addr64.mjs +``` + +None of them need a KV260, and most need nothing beyond the Python standard +library. Two dependencies are **optional** and each test degrades to a clean +`SKIP` (never a `FAIL`) when it is missing: + +- **A RISC-V toolchain** (`riscv64/32-unknown-elf-readelf`/`-objdump`) — only + `test_elf_load.py` and parts of `test_rv64_scenarios.py` use it, to cross- + check `server.py`'s own ELF/disassembly parsing against a reference tool. + Resolved via `RISCV_READELF`/`RISCV_BIN` environment variables or `PATH`; + no path is hardcoded. +- **Node.js** (`node` on `PATH`) — `test_wp_view.py` runs the register-grouping + JavaScript that ships inside `index.html` headlessly, to prove the shipped + code (not a reimplementation of it) groups indexed registers correctly. + This one specific check is a deliberate **exception**: it stays a hard + `FAIL` without `node`, by design (a skipped guard that reports green would + be the more expensive kind of false confidence — see the comment at its + call site in `test_wp_view.py`). It does not affect the demo mode itself. + +A handful of gates also SKIP cleanly when a fixture tree lives elsewhere in +this repository, or nowhere in it at all (the KV260 RTL tops under +`examples/kv260/`, or software-characterization ELF corpora that never +shipped as an example) — each SKIP line names exactly which tree is missing +and why that is expected here. The rule throughout this directory is: a +missing fixture is a named SKIP, never a FAIL, and never a silent pass. + +## `devtools/` — the architecture-diagram round trip + +`devtools/` holds the tooling that keeps the per-scenario block diagrams +(embedded in `index.html` as `ARCH_BY_SCEN`) in sync with hand-edited +[draw.io](https://www.drawio.com/) source files: + +1. `py devtools/compact_layout.py` — derive an initial geometry straight from + `scenarios.json` for a scenario that has none yet, writing + `devtools/ctte_view_.drawio.svg`. +2. Open that `.svg` in draw.io, rearrange it by hand, save. +3. `py server.py --demo --port 8142` — start the server the two measuring + tools talk to, in its own shell, from `examples/dashboard/`. The port has + to be named: `server.py` defaults to **8099**, but `measure_geometry.py` + and `check_themes.py` default to **8142** (`sys.argv[1]` if given). +4. `py devtools/measure_geometry.py 8142` — measure the **rendered** + dashboard against that server — the page scales and lays out arrows at + runtime, so only a measurement gets the real pixel geometry. The port + argument is optional here only because 8142 is also the tool's default; + against a server left on 8099 you would pass `8099` instead. +5. `py devtools/check_congruence.py` — verify the hand-edited drawing and the + measured rendering still agree (block positions, edges). +6. `py devtools/check_themes.py 8142` — verify every colour scheme in + `themes.json` actually reaches the rendered page and meets WCAG contrast. +7. `py devtools/sync_arch_view.py` — write the reconciled geometry back into + `index.html`'s `ARCH_BY_SCEN` blob and `devtools/arch_geometry.json`. +8. Stop the server from step 3. + +`devtools/trio_dual_protocol_view.html` is a separate, self-contained page +documenting the `trio` scenario's N-Trace/E-Trace mixed-protocol funnel (one back end per encoder instance, mixed in one netlist); it +has no dependency on the round trip above. + +## Files + +| Path | Role | +|---|---| +| `server.py` | The dashboard server: HTTP API, `/dev/mem` access, ELF loading, ELF/PC decoding, demo-mode recording playback | +| `index.html`, `wp.html` | Self-contained frontend pages (no build step, no third-party JS) | +| `scenarios.json` | The scenario catalog: one entry per SoC build (cores, CTRL map, sinks, decode config) | +| `regmap.json` | The full CSR register map, generated from `rdl/ct_cs_cpuif.rdl` by `gen_regmap.py` | +| `themes.json`, `block_csrs.json`, `boot.json` | Colour schemes; block→CSR relevance for the detail panel; per-scenario guest boot recipes | +| `plclk.json` | Per-scenario `pl_clk0` label (68/75/100), each entry with the file its value is taken from. The server programs it between `xmutil unloadapp` and `xmutil loadapp` — the only moment a PL clock may change. A scenario without an entry keeps whatever the board has, and the load result says so | +| `demo/` | The hardware-free demo dataset: console captures, ELF/pcinfo metadata, symbol maps, recorded trace streams | +| `wp_view.py` | AXIS watchpoint state machine (live drain + deterministic demo generator); consumes `tools/axis_wp_host` | +| `scenario.py` | The scenario model behind `scenarios.json`: apertures, CTRL map, cores/encoders, sinks, console, decode config | +| `insight.py` | Post-decode analysis of the PC stream: symbolisation from a `System.map`, live window, hot list | +| `gen_regmap.py` | Generates `regmap.json` from `rdl/ct_cs_cpuif.rdl` (full profile) plus the hand-kept SoC CTRL block | +| `dis_to_symbols.py` | Turns objdump `.dis` listings into the symbol and call/return site maps the decoder configs reference | +| `make_demo_console.py` | Rebuilds `demo/console_.txt` from the recorded board captures (reproducible, nothing invented) | +| `record_web_demo.py`, `record_web_replay.py` | Record the dataset for the public website: `_demo` the analysis/window dataset, `_replay` the v2 replay bundle of the original dashboard | +| `check_replay_public.py` | Marker scan over the public replay bundle — refuses commit IDs, internal source paths and RDL line references | +| `run_demo_axis.sh` | One-line launcher: demo mode, scenario `tgc5b2_axis_wp`, port 8151, log to `demo_axis_server.log` | +| `wp_board_start.py` | Starts the AXIS-WP demo program on the board (root, next to `axis_wp_host/`) | +| `boot/` | Per-scenario board boot sequences invoked by the guest-boot recipes in `boot.json`, one per Linux/AMP scenario that can boot a guest: `cva6_linux64_run.sh` (CVA6 RV64), `rocket_linux64_run.sh` (Rocket RV64), `rocket2_linux_run.sh` (two Rocket harts). All three share the same phase interface — `PHASE=prep` loads the payload and verifies it by reading the window back, `start` boots and measures a window, `live` switches to continuous operation — and all three run **on the board**, staged there by `board_dashboard_install.sh` together with `phys_io.py` and `kv260_plclk.sh` | +| `test_*.py`, `test_addr64.mjs` | The gates described above | +| `board_dashboard_install.sh` | Installs the dashboard as a persistent systemd service on the target board | +| `devtools/` | The architecture-diagram round trip described above | + +## Licensing + +Scripts and configuration data are ISC (see the SPDX header in each file, or +`REUSE-additions.toml.txt` for formats that cannot carry one). Captured +CTTE encoder byte streams under `demo/` follow the encoder's own licence, +CERN-OHL-S-2.0 OR LicenseRef-Accemic-Commercial. This file is CC-BY-4.0. diff --git a/examples/dashboard/block_csrs.json b/examples/dashboard/block_csrs.json new file mode 100644 index 0000000..5f50863 --- /dev/null +++ b/examples/dashboard/block_csrs.json @@ -0,0 +1,172 @@ +{ + "_comment": [ + "Block type -> CSR relevance for the detail panel of the architecture view", + "(from an earlier finding, 2026-08-13: 'When I click on a block, I want", + "to see all the CSRs related to that block -- even if only a single bit", + "is relevant to it.'). DATA-DRIVEN: index.html loads this file and", + "resolves the entries against regmap.json + the scenario card -- NO", + "block->register mapping hardcoded in JS.", + "", + "Schema per block (key = diagram block base without row suffix):", + " note: sentence that ALWAYS sits above the list (or alone, if no", + " register resolves) -- for pure wire blocks it says WHERE the", + " control belongs.", + " csrs: list of entries:", + " {\"path\": \"\", \"fields\": [..]}", + " fields = the bit fields relevant to THIS block; they are", + " highlighted in the panel, the remaining fields of the register", + " are collapsed ('N more fields'). Without fields, the whole", + " register counts as relevant.", + " {\"home\": \"\"} adopts an existing", + " register group (filters/comps/wp/df/uram/ddr/pib/atb/ts/pc).", + " Resolution: soc.* entries are DROPPED if the CTRL card of the", + " active scenario does not know the register (the same source of truth", + " as fixSocOffsets -- a register with an MBV offset in a foreign SoC", + " would be a plausible wrong number).", + "", + "scenarios: additive additions/overrides per scenario id,", + " same structure; note overrides, csrs is appended.", + "", + "Domain sources of the mapping: RDL descriptions in regmap.json", + "(generated from ct_cs_cpuif.rdl), FINDINGS_axis_wp_analyse.md part W2,", + "the CSR group chips and the block descriptions (BLOCK_META)." + ], + "blocks": { + "cpu": { + "note": "Core start/stop and run-state live in the SoC wrapper's CTRL window. Since U1 every core has its own release bit (CONTROL b8/b9, trio b10 for the CVA6) and CONTROL b0 is the collective bit: effective = b0 | b(8+i). STATUS mirrors the EFFECTIVE state in the same bit positions, so one read tells which core is actually running. Scenario-specific observation registers (live PC, retire counters, window guards) are listed in the scenario card, not in the RDL regmap.", + "csrs": [ + { "path": "soc.CONTROL", "fields": ["core_run", "core0_run", "core1_run", "cva6_run", "cva6_run2", "irq_gen_en"] }, + { "path": "soc.STATUS" } + ] + }, + "tip": { + "note": "Pure signal adapter (H2E/TCI/ITI -> TIP) — it has no CSRs of its own. What it forwards is qualified on the ENCODER side: trTeControl.InstTracing is the instruction-ingress master switch (highlighted below); filtering happens in the Preproc block. Enable is the second, stronger switch: effective tracing is (Enable AND InstTracing), and Enable is also the swwel write lock of ~500 encoder fields — clear it with the 'TE enabled' switch on the encoder card, 'Encoder trace off' clears InstTracing only.", + "csrs": [ + { "path": "te.trTeControl", "fields": ["Active", "Enable", "InstTracing"] } + ] + }, + "preproc": { + "note": "TIP ingress, instruction typing and qualification: filters, comparators, DF ranges and the watchpoint unit (ACT-ST dispatch) all act HERE.", + "csrs": [ + { "path": "te.trTeControl", "fields": ["InstTracing", "InstMode", "InstSeqSyncEnable", "InstTrigEnable", "InstStallOrOverflow", "InstSyncMode", "InstSyncMax", "InstSyncReq"] }, + { "path": "trTeInstFilters" }, + { "path": "trTeDataControl" }, + { "path": "trTeDataFilters" }, + { "path": "trTeCsrControl" }, + { "path": "trTeSyncStatus" }, + { "home": "filters" }, + { "home": "comps" }, + { "home": "wp" }, + { "home": "df" } + ] + }, + "fifo": { + "csrs": [ + { "path": "TipFifoStatus" }, + { "path": "TipFifoHistCtrl" }, + { "path": "TipFifoHistData" }, + { "path": "te.trTeControl", "fields": ["Empty", "InstStallOrOverflow"] } + ] + }, + "msggen": { + "csrs": [ + { "path": "trTeInstFeatures", "fields": ["InstEnImplicitReturn", "InstEnBranchPrediction", "InstEnJumpTargetCache", "InstEnRepeatedHistory", "InstEnRepeatBranch", "InstEnWideIcnt", "InstEnIbhs", "InstEnRepeatInstr"] }, + { "path": "te.trTeControl", "fields": ["InstMode", "SendConfig", "Context", "InstSyncMode", "InstSyncMax"] }, + { "path": "trTeCsrControl" } + ] + }, + "nexusfmt": { + "csrs": [ + { "path": "trTeInstFeatures", "fields": ["SrcID", "SrcBits"] }, + { "path": "te.trTeControl", "fields": ["InhibitSrc", "SendConfig", "SendDeviceId"] } + ] + }, + "mseomdo": { + "csrs": [ + { "path": "te.trTeControl", "fields": ["Format", "Empty"] } + ] + }, + "teinst": { + "note": "E-Trace backend — active while trTeProtocolSel = 1 (DUAL build; switchable only at Enable = 0).", + "csrs": [ + { "path": "trTeProtocolSel" }, + { "path": "trTeInstFeatures", "fields": ["InstEnImplicitReturn", "InstEnBranchPrediction", "InstEnJumpTargetCache"] } + ] + }, + "tepktz": { + "note": "E-Trace packetizer — shares the protocol switch with the te_inst generator.", + "csrs": [ + { "path": "trTeProtocolSel" }, + { "path": "te.trTeControl", "fields": ["Format"] } + ] + }, + "funnel": { + "note": "Merges the per-encoder ATB streams message-atomically; the streams are told apart downstream by the Nexus SRC field (SrcID/SrcBits, Nexus Fmt block).", + "csrs": [ + { "path": "soc.FUNNEL_CTRL" }, + { "home": "atb" } + ] + }, + "uram": { + "csrs": [ + { "home": "uram" }, + { "path": "soc.CONTROL", "fields": ["trace_clear", "trace_flush"] }, + { "path": "soc.STATUS", "fields": ["trace_wrapped"] }, + { "path": "soc.SINK_CTRL", "fields": ["uram_oneshot"] }, + { "path": "soc.SINK_STAT", "fields": ["uram_stopped"] } + ] + }, + "ddr": { + "csrs": [ + { "path": "soc.SINK_CTRL", "fields": ["ddr_en", "ddr_clear", "ddr_circ"] }, + { "path": "soc.SINK_STAT", "fields": ["ddr_full", "ddr_axi_err", "ddr_wrapped", "ddr_cfg_rej"] }, + { "path": "soc.DDR_BASE" }, + { "path": "soc.DDR_SIZE" }, + { "path": "soc.DDR_WPTR" }, + { "path": "soc.DDR_DROPS" }, + { "path": "soc.DDR_BEATS" } + ] + }, + "pib": { + "csrs": [ + { "path": "soc.SINK_CTRL", "fields": ["pib_en", "pib_clear", "pib_calib", "pib_div", "pib_pattern"] }, + { "path": "soc.PIB_DROPS" } + ] + }, + "axis": { + "note": "ACT-CAP capture sink. The capture COMMANDS live in the watchpoint Cmd words (WP table of the encoder), not in own CSRs.", + "csrs": [ + { "path": "soc.AXIS_BEATS" }, + { "path": "soc.STATUS", "fields": ["axis_overflow"] } + ] + }, + "kriaps": { + "note": "Processor side (Cortex-A53) — no PL CSRs. It programs the encoders through the CSR windows of the aperture table and consumes the sinks (URAM/DDR dumps; WP records via the server-side FIFO drain, /wp.html)." + }, + "wpshim": { + "note": "ct_axis_wp_shim is counter-only: drop/fill/overflow live in the read-only WPCTRL window (shown live on the block and in /api/wp/status; ovf is sticky, cleared only by PL reset). The watchpoint unit that FEEDS the shim is configured below (trWp*); the C0b 1023-slot table is loaded indirectly.", + "csrs": [ + { "home": "wp" } + ] + }, + "wpfifo": { + "note": "axi_fifo_mm_s (PG080). Its register set sits in the fifo0/fifo1 windows and is NOT offered here: RDFD reads are destructive (every read pops a word) — the server drain is the only reader. Rates and backlog: block annotation, /api/wp/status and /wp.html." + } + }, + "scenarios": { + "tgc5b2_axis_wp": { + "cpu": { + "note": "Each TGC5B core starts and stops on its own bit since U1: CONTROL b8 = core 0, b9 = core 1, effective = b0 | b(8+i); b0 stays the collective bit that releases both (kept for every existing script that writes CONTROL=1). STATUS b8/b9 mirror the effective state — on a bitstream before U1 they read 0 while b0 runs the cores, and the dashboard says so instead of showing a wrong lamp. WATCH OUT with the memory windows: RAM0 is accessible only while core 0 is halted, RAM1 only while core 1 is halted, and an access to the window of a RUNNING core never gets ready — the AXI transaction HANGS (SPEC_axis_wp_memory_map.md §10 point 2). The server refuses such reads and writes with HTTP 409 instead of hanging." + }, + "uram": { + "note": "Primary sink of the shared three-sink subsystem (rtl/board_kv260/ct_trace_sinks.sv, T2): always-ready ring on the funnel-merged stream, so it never back-pressures the trace path. Its size is NOT hardcoded anywhere — read TRACE_BUFSZ @0x10 (0x0010_0000 = 1 MiB in the C0B_SINK3 build; the two earlier builds of this scenario have 256 KiB). SINK_CTRL b3 uram_oneshot switches circular (default, keeps the LAST 1 MiB) to one shot (keeps the FIRST 1 MiB); SINK_STAT b3 uram_stopped then reports the stopped ring." + }, + "ddr": { + "note": "DDR4 sink, present only in the C0B_SINK3 bitstream (app tgc5b2_axis_wp_c0b_sink3) — the older builds of this scenario read zeros in this window, which is why the block is hidden for them. WATCH THE OFFSET: DDR_BEATS is at 0x38 here and 0x30 is PIB_DROPS (breaking change against the C0B_DDR build, SPEC §9). Before ddr_en = 1 the boot device tree must carry the reservation ctrace-pl-ddr (no-map 0x5000_0000..0x6FFF_FFFF, vivado/kv260_app/ctrace_resmem.dtso); since package U6 the reset window is DDR_BASE 0x5000_0000 / DDR_SIZE 256 MiB (address plan v4 — at the ~16.7 MB/s measured in U5 the ring now wraps after ~16 s instead of ~4 s). Base and size are READ-ONLY in this dashboard since package U9 (2026-08-16): the panel shows the window instead of offering input fields, and /api/write answers HTTP 403 for DDR_BASE and DDR_SIZE, curl included. The hardware alone is not enough — the U6 interlock refuses a write only while the sink is ARMED (it then latches SINK_STAT b4 ddr_cfg_rej, sticky until ddr_clear, instead of taking a size below the current write offset), whereas at ddr_en = 0 it takes any value: measured on a lab KV260 board on 2026-08-16, DDR_BASE 0x8000_0000 was written and read back, the armed sink then wedged (WPTR 0, every beat dropped, no BRESP) and only a PL app reload recovered it. A base one digit off would have been a DMA write master pointed into the memory of the hosting Linux. Change the window in the bitstream and the device tree, not at run time. Mode (SINK_CTRL b2), ddr_clear and ddr_en stay writable. Additive observer with its own FIFO: on overflow it drops and counts (DDR_DROPS), it never stalls the ring." + }, + "pib": { + "note": "Parallel trace port of the C0B_SINK3 bitstream (hidden for the older builds of this scenario, which have no PIB). Pins on KV260 PMOD J2 (tgc5b2_axis_wp.xdc, pin-compatible with the KR260 reference adapter): pib_clk H12, pib_data[3:0] = E10/B10/E12/D11, LVCMOS33. Port rate = clk/2^(pib_div+1) — at 75 MHz PL clock the 4-bit DDR port is slower than the merged stream, so PIB_DROPS counting up under load is expected, not a defect. pib_calib sends the trPibCalibrate-compatible pattern selected by pib_pattern (0 = STANDARD AA/55/00/FF, 1 = MOVING_ONE, 2 = MOVING_ZERO) instead of trace." + } + } + } +} diff --git a/examples/dashboard/board_dashboard_install.sh b/examples/dashboard/board_dashboard_install.sh new file mode 100644 index 0000000..44b996f --- /dev/null +++ b/examples/dashboard/board_dashboard_install.sh @@ -0,0 +1,248 @@ +#!/bin/bash +# SPDX-FileCopyrightText: 2026 Accemic Technologies GmbH +# SPDX-License-Identifier: ISC +# board_dashboard_install.sh -- set the dashboard up as a PERMANENT SERVICE on +# the KV260: reachable directly in the browser, surviving a reboot. Without it +# the server runs as a *transient* systemd unit (systemd-run) bound to +# 127.0.0.1 -- which together means it is gone after every reboot, and whoever +# wants to see it needs a double SSH tunnel. This script installs instead: +# +# 1. /etc/default/ctrace-dashboard -- the only place holding options +# 2. /usr/local/sbin/ctrace_loadapp.sh -- loads the PL app (idempotent, waits for dfx-mgr) +# 3. ctrace-app.service -- oneshot, loads the app at boot +# 4. ctrace-dashboard.service -- the server, After=ctrace-app, Restart=always +# +# THE ORDER IS THE POINT, not cosmetics: a register read at 0xA000_0000 with an +# unprogrammed PL wedges the AXI interconnect and the board is dead (three +# boards frozen that way). Therefore (a) ctrace-app.service loads the app +# BEFORE the server, and (b) the server only brings its live bus up at all when +# `xmutil listapps` reports a known app in the slot (PL_GUARD in server.py) -- +# if the app load fails, the dashboard comes up in DEMO instead of taking the +# board down with it. +# +# SECURITY: --host 0.0.0.0 makes the API (including /api/write and /api/elf, +# i.e. full /dev/mem access) reachable for ANYONE in the same network segment. +# That is intended for a lab segment and equivalent there to the SSH access +# that is open anyway; the board must therefore not be attached to a corporate +# network or forwarded through a router. If that is not wanted, set +# BIND=127.0.0.1 in /etc/default (and go back to `ssh -L`). There is NO +# authentication. +# +# Call on the board: sudo bash board_dashboard_install.sh [APP] [PORT] +set -eu + +APP="${1:-mbv_ctrace_kv260}" +PORT="${2:-8099}" +DIR="${DASH_DIR:-/home/ubuntu/ctrace_dashboard}" +DEF=/etc/default/ctrace-dashboard +LOADER=/usr/local/sbin/ctrace_loadapp.sh + +[ -f "$DIR/server.py" ] || { echo "ERROR: $DIR/server.py missing"; exit 1; } + +TOOLS=/usr/local/share/ctrace +HERE_SH="$(cd "$(dirname "$0")" && pwd)" + +echo "== 0. Board tools ($TOOLS) ==" +# Two helpers the board side cannot work without, and neither of which was +# staged before 2026-08-19: +# +# kv260_plclk.sh -- programs pl_clk0. Without it the dashboard can only READ +# the clock, never set it. Measured on 2026-08-19: the boot firmware had +# left pl_clk0 at 150 MHz while every design here is constrained to +# 71.114 MHz, so PHASE=prep of every boot recipe aborted with PLCLK_WRONG +# and the Linux scenarios looked "empty" in the dashboard -- the cause was +# the clock, not the payload. +# phys_io.py -- the recipes under boot/ call it as `/tmp/phys_io.py` +# (its own file header said this script stages it there; until now that +# was not true). +# +# Copied to a PERSISTENT place. /tmp is re-populated by the app loader on +# every boot, because /tmp does not survive one. +mkdir -p "$TOOLS" +stage_tool() { + for c in "$DIR/$1" "$HERE_SH/$1" "$HERE_SH/../kv260/common/board/$1" \ + "$DIR/../kv260/common/board/$1"; do + [ -f "$c" ] || continue + install -m 0755 "$c" "$TOOLS/$1" + echo " $1 <- $c" + return 0 + done + echo " WARNING: $1 not found -- looked next to server.py, next to this" + echo " script and under ../kv260/common/board/. Copy it to" + echo " $TOOLS by hand." + return 1 +} +stage_tool kv260_plclk.sh || true +stage_tool phys_io.py || true +[ -f "$TOOLS/phys_io.py" ] && cp -f "$TOOLS/phys_io.py" /tmp/phys_io.py + +echo "== 1. options ($DEF) ==" +# Only created when not already present: a change made on the board (other +# scenario, other pcinfo) must NOT be overwritten by another script run. +if [ -f "$DEF" ]; then + echo " present, left unchanged:" +else + ARGS="--host 0.0.0.0 --port $PORT --scenario mbv" + [ -x "$DIR/NexRv" ] && ARGS="$ARGS --nexrv $DIR/NexRv" + [ -f "$DIR/branch_test.pcinfo" ] && ARGS="$ARGS --pcinfo0 $DIR/branch_test.pcinfo" + [ -f "$DIR/symbols_mbv.map" ] && ARGS="$ARGS --symbols $DIR/symbols_mbv.map" + cat > "$DEF" <:$PORT/), +# 127.0.0.1 = only via ssh -L. There is NO authentication. +DASH_DIR="$DIR" +DASH_ARGS="$ARGS" +# app that ctrace-app.service loads into the PL at boot (empty = none) +CTRACE_APP="$APP" +# only for the self-check of the installer / the unit +CTRACE_PORT="$PORT" +EOF +fi +cat "$DEF" +# shellcheck disable=SC1090 +. "$DEF" + +echo "== 2. app loader ($LOADER) ==" +cat > "$LOADER" <<'LOADEOF' +#!/bin/bash +# ctrace_loadapp.sh -- load the PL app idempotently (boot path of the dashboard). +# Generated by board_dashboard_install.sh; configuration in /etc/default/ctrace-dashboard. +set -u +[ -f /etc/default/ctrace-dashboard ] && . /etc/default/ctrace-dashboard +APP="${CTRACE_APP:-}" +say() { echo "$*"; echo "ctrace_loadapp: $*" > /dev/kmsg 2>/dev/null || true; } +# The boot recipes under boot/ call `/tmp/phys_io.py` and `/tmp/kv260_plclk.sh`, +# and /tmp does not survive a reboot -- re-stage BOTH from the persistent copies +# on every boot. +# +# kv260_plclk.sh was missing from this loop until 2026-08-19 and it cost a +# board session: after a reboot the clock tool was gone, so every recipe's +# prep phase stopped at PLCLK_WRONG (correctly -- the clock really was at the +# boot firmware's 100 MHz) and the fix looked like a design problem instead of +# a missing file. Restoring one of the two tools and not the other is the +# worst of both: the recipe gets far enough to fail somewhere else. +for t in phys_io.py kv260_plclk.sh; do + if [ -f "/usr/local/share/ctrace/$t" ]; then + cp -f "/usr/local/share/ctrace/$t" "/tmp/$t" 2>/dev/null || true + fi +done +[ -n "$APP" ] || { say "no app configured -- nothing to do"; exit 0; } +command -v xmutil >/dev/null || { say "xmutil missing"; exit 1; } + +# After a boot, dfx-mgrd needs a moment before it answers requests; +# `xmutil listapps` fails before that (empty list / rc!=0) and a loadapp +# on top of it runs into nothing. +for i in $(seq 1 60); do + out="$(xmutil listapps 2>&1)" && echo "$out" | grep -q "$APP" && break + sleep 2 +done + +active() { xmutil listapps 2>/dev/null | awk -v a="$APP" '$1==a && $NF!="-1" && $NF!="" {print $NF}'; } +cur="$(active)" +if [ -n "$cur" ]; then say "$APP is already loaded (slot $cur)"; exit 0; fi + +# unloadapp runs ALWAYS -- dfx-mgrd keeps its base design (k26-starter-kits) +# in slot 0 WITHOUT showing it in the slot->handle column; a loadapp on top +# of it fails with "Remove previously loaded accelerator, no empty slot". +# The column therefore proves our apps only, not the state of the slot. +try_load() { + xmutil unloadapp >/dev/null 2>&1 || true + sleep 1 + xmutil loadapp "$APP" || true + for _ in 1 2 3 4 5; do + sleep 1.5 + [ -n "$(active)" ] && return 0 + done + return 1 +} + +say "loadapp $APP" +if ! try_load; then + # dfx-mgrd then reports success without recording the slot; restarting the + # daemon resets it, after which unload+load takes effect. + say "no slot entry -> restart dfx-mgr and retry" + systemctl restart dfx-mgr; sleep 5 + try_load || { say "loadapp $APP FAILED (journalctl -u dfx-mgr)"; exit 1; } +fi +st="$(cat /sys/class/fpga_manager/fpga0/state 2>/dev/null || echo '?')" +say "$APP loaded (slot $(active), fpga_manager=$st)" +exit 0 +LOADEOF +chmod 0755 "$LOADER" + +echo "== 3. ctrace-app.service (app at boot) ==" +cat > /etc/systemd/system/ctrace-app.service < /etc/systemd/system/ctrace-dashboard.service </dev/null || true +systemctl reset-failed ctrace-dashboard.service 2>/dev/null || true +if [ -f /run/systemd/transient/ctrace-dashboard.service ]; then + echo " removed the old transient unit" + rm -f /run/systemd/transient/ctrace-dashboard.service +fi +systemctl daemon-reload +systemctl enable ctrace-app.service ctrace-dashboard.service >/dev/null +test "$(systemctl show -p FragmentPath --value ctrace-dashboard.service)" \ + = /etc/systemd/system/ctrace-dashboard.service \ + || { echo "ERROR: the active unit file is $(systemctl show -p FragmentPath --value ctrace-dashboard.service)"; exit 1; } +systemctl start ctrace-app.service || echo " WARNING: app load failed (dashboard starts in DEMO)" +systemctl restart ctrace-dashboard.service + +echo "== 5. self-check ==" +sleep 3 +systemctl is-enabled ctrace-app.service ctrace-dashboard.service +systemctl is-active ctrace-app.service ctrace-dashboard.service || true +ip="$(ip -4 -o addr show scope global | awk '{print $4}' | cut -d/ -f1 | head -1)" +echo "-- GET /api/mode on $ip:${CTRACE_PORT:-$PORT}" +curl -s -m 10 "http://$ip:${CTRACE_PORT:-$PORT}/api/mode" || echo " (not reachable)" +echo +echo "== DONE -- direct URL: http://$ip:${CTRACE_PORT:-$PORT}/ ==" +echo " logs: journalctl -u ctrace-dashboard -f" +echo " stop: sudo systemctl stop ctrace-dashboard (campaigns need the board exclusively)" diff --git a/examples/dashboard/boot.json b/examples/dashboard/boot.json new file mode 100644 index 0000000..d67af9b --- /dev/null +++ b/examples/dashboard/boot.json @@ -0,0 +1,60 @@ +{ + "_comment": [ + "Guest boot recipes, one per scenario. THIS FILE IS THE ONLY SOURCE OF", + "SCRIPT PATHS -- the browser sends nothing but a scenario id. A path taken", + "from the request would be remote execution of arbitrary commands.", + "", + "Why this exists: the user interface could not start the guest. 'Run' only", + "releases the core and does NOT reload the payload -- a guest that was", + "already running has overwritten its own image and restarts in modified", + "code. Only 'prep' reloads it, including the read-back verification; that", + "verification is never bypassed.", + "", + "PL_MHZ is the pl_clk0 LABEL kv260_plclk.sh understands (68 | 75 | 100),", + "not an exact frequency: the runner turns 68 into 1500000000/22 =", + "68181818 Hz, not 68000000. Which label a scenario needs, and the evidence", + "for it, is kept ONCE in plclk.json -- the value repeated here must match,", + "and test_demo_assets.py checks that it does. Without the right label,", + "prep aborts with PLCLK_WRONG instead of running a design above the", + "frequency it was signed off at.", + "", + "SINK=uram is the 1 MiB URAM ring; the live phase runs it circular, so the", + "display keeps showing traffic. SINK=ddr uses the DDR sink window instead", + "and requires the reserved-memory node from ctrace_resmem.dtso -- the", + "runners check that against the live devicetree and refuse to write into", + "unreserved host RAM.", + "", + "The order is binding: prep loads and verifies, start boots and measures,", + "live switches to continuous operation (ring circular, nothing is switched", + "off again). If a phase aborts, the server does NOT run the next one -- a", + "start on a failed prep produces exactly the dead core this button is", + "meant to prevent." + ], + "rocket2": { + "script": "boot/rocket2_linux_run.sh", + "phases": ["prep", "start", "live"], + "env": { + "PAYLOAD": "/tmp/fw_payload_rocket2.bin", + "SINK": "ddr", + "PL_MHZ": "75" + } + }, + "cva6_linux64": { + "script": "boot/cva6_linux64_run.sh", + "phases": ["prep", "start", "live"], + "env": { + "PAYLOAD": "/tmp/fw_payload64.bin", + "SINK": "uram", + "PL_MHZ": "68" + } + }, + "rocket64": { + "script": "boot/rocket_linux64_run.sh", + "phases": ["prep", "start", "live"], + "env": { + "PAYLOAD": "/tmp/fw_payload_rocket.bin", + "SINK": "uram", + "PL_MHZ": "75" + } + } +} diff --git a/examples/dashboard/boot/cva6_linux64_run.sh b/examples/dashboard/boot/cva6_linux64_run.sh new file mode 100644 index 0000000..f3d253f --- /dev/null +++ b/examples/dashboard/boot/cva6_linux64_run.sh @@ -0,0 +1,467 @@ +# SPDX-FileCopyrightText: 2026 Accemic Technologies GmbH +# SPDX-License-Identifier: ISC +# cva6_linux64_run.sh -- board sequence of the RV64 Linux demonstrator on the +# cv64a6 (package R5a). Runs ON THE BOARD. +# +# sudo PHASE=prep bash cva6_linux64_run.sh # clock, AFIFM, rings, payload + hash +# sudo PHASE=start RUNSEC=3 bash cva6_linux64_run.sh +# sudo PHASE=live bash cva6_linux64_run.sh # continuous mode for the dashboard +# sudo PHASE=con bash cva6_linux64_run.sh # console ring -> /tmp/cva6_linux64_con.bin +# sudo PHASE=login bash cva6_linux64_run.sh # interactive, over the RX path +# sudo PHASE=type CMD='...' bash cva6_linux64_run.sh +# sudo PHASE=trace bash cva6_linux64_run.sh # trace -> /tmp/cva6_linux64_trace.bin +# +# Twin of rocket_linux64_run.sh (package R5b) and sibling of +# rocket2_linux_run.sh (package M5); the three share their phase interface so +# that the dashboard server can call every recipe the same way (boot.json). +# +# ENCODER CONFIGURATION of the start/live phases (package W1): +# SENDCFG=once|onsync config message TCODE 58 (default: once) +# SYNCMAX=<0-15> trTeControl.InstSyncMax[23:20], sync every +# 2^(x+4) instructions (default 6 = every 1024, +# the RDL reset value) +# FEATURES=jtc,bp,ir,rh,wideicnt,rb,ibhs,ri compression suite (default: none) +# TRACE_DELAY= start recording only seconds into the run (0) +# SINK=uram|ddr destination of the stream (default uram = the +# 1 MiB URAM ring) +# +# WHY TRACE_DELAY AND SINK EXIST (a W1 measurement, not convenience): the 1 MiB +# URAM ring in one-shot mode holds the FIRST ~1.1 million instructions -- and +# those lie entirely inside OpenSBI (measured on the R5a capture: 1,102,954 +# decoded PCs, ALL inside the window 0x6400_0000..0x6400_5400, not a single one +# above 2^32). An RV64 address proof needs Sv39 kernel addresses. Two ways to +# get there, both built in: +# * TRACE_DELAY -- the core starts, the encoder only records later. The window +# moves to where the kernel is already running with satp. The config message +# still arrives: CFG_ONCE fires on the RISING EDGE of inst_trace_active +# (ct_L23_preproc_composer_etip.sv:487). +# * SINK=ddr -- instead of 1 MiB of URAM, the DDR sink window (RTL reset +# 0x6000_0000 + 64 MiB, `no-map` reserved and separate from the guest RAM +# at 0x6400_0000). That is ~64x more window, and hence the chance of +# catching the satp transition IN ONE PIECE instead of as two separate cuts. +# +# The config message is MANDATORY on the 64-bit encoder, not optional: the +# decoder reads CAPS bit 23 only from there and sets its address width to 64. +# Without it, it folds the JTC index at bit 25 instead of 63 and aborts in the +# middle of the stream ("VendorJTC references jump-target-cache index N which is +# not yet installed", R2.1c legs L3/L5). SENDCFG=none is therefore refused. +# +# WHY phys_io.py AND NOT `dd of=/dev/mem` (R5a finding): the guest window is +# `no-map` reserved. For such ranges the read()/write() path of /dev/mem +# answers "Bad address" -- only mmap works (measured 2026-07-27, documented in +# the header of examples/kv260/common/board/phys_io.py). +# * Writing into the window: ctypes WORD LOOP (`write`) -- a slice copy faults +# there with SIGBUS (glibc NEON memcpy on a device mapping). +# * READING from the window likewise a word loop (`read`). The header of +# phys_io.py clears the slice copy for reading ("64 MiB in 1.08 s") -- that +# clearance does NOT hold for THIS window: `readbulk 0x64000000` died +# reproducibly with "Bus error (core dumped)". The clearance comes from the +# DDR SINK buffer; the guest window is evidently mapped differently. 32 MB +# of word loop cost ~50 s here -- measured, not estimated. +# * Aperture rings (0xA02.., 0xA03..): ALWAYS the word loop (`read`). +set -e +dm() { busybox devmem "$@"; } + +APP=${APP:-cva6_linux64_x64ctx_ctrace_kv260} +PAYLOAD=${PAYLOAD:-/tmp/fw_payload64.bin} +GUEST=0x64000000 +PHASE=${PHASE:-prep} +SINK=${SINK:-uram} + +CTRL=0xA0000000 +STATUS=0xA0000004 +TR_BEATS=0xA0000008 +TR_BYTES=0xA000000C +CON_BYTES=0xA0000014 +CON_DROPS=0xA0000018 +SINK_CTRL=0xA000001C +DDR_BASE=0xA0000020 +DDR_SIZE=0xA0000024 +DDR_WPTR=0xA0000028 +SINK_STAT=0xA000002C +DDR_DROPS=0xA0000030 +CON_TX=0xA0000034 +CON_RPTR=0xA0000038 +ENC=0xA0010000 +ENC_FEAT=0xA0010008 +TR_RING=0xA0200000 +CON_RING=0xA0300000 + +CONFILE=/tmp/cva6_linux64_con.bin +TRFILE=/tmp/cva6_linux64_trace.bin + +# The aperture is touched ONLY if EXACTLY our app is in the active slot. +# Otherwise the AXI interconnect hangs and the board is dead (2026-07-27/28, +# three frozen boards). fpga_manager "operating" is NOT sufficient as a +# criterion -- the starter-kit app programs the PL as well, but has no slave +# at 0xA000_0000. +if ! xmutil listapps 2>/dev/null | awk -v a="$APP" '$1==a && $NF!="-1" {f=1} END{exit !f}'; then + echo "APP_NOT_ACTIVE ($APP) -- aperture NOT touched" >&2 + xmutil listapps >&2 || true + exit 8 +fi + +# Type one line into the guest console (RX path, b8 = commit). +type_line() { + s="$1"; i=0 + while [ $i -lt ${#s} ]; do + c=$(printf '%s' "$s" | cut -c$((i+1))) + o=$(printf '%d' "'$c") + dm $CON_TX 32 $(printf '0x%08x' $((0x100 | o))) + i=$((i+1)) + done + dm $CON_TX 32 0x10A # newline +} + +# Read the console ring. CAPPED: CON_BYTES is MONOTONIC (it is the write +# position), the ring holds only 65,536 bytes. An uncapped read would run past +# the window -- and a Linux boot followed by a login session passes 64 KiB +# easily. +read_con() { + n=$1 + [ "$n" -gt 65536 ] && n=65536 + [ "$n" -gt 0 ] && python3 /tmp/phys_io.py read $CON_RING $(( (n + 3) / 4 * 4 )) -o $CONFILE + echo "CONFILE $(ls -l $CONFILE 2>/dev/null | awk '{print $5}') (ring position $1)" >&2 +} + +# The DDR window is READ and CHECKED, never resized here. +# +# Two reasons, and both are measured elsewhere in this repository: +# 1. WRITING INTO FOREIGN MEMORY. `reserved-memory` is a BOOT-TIME +# reservation. Without the reboot that carries +# examples/kv260/common/board/ctrace_resmem.dtso, the range belongs to the +# host kernel, and a sink writing there at tens of MB/s corrupts the HOST. +# So the reservation is READ from the LIVE devicetree -- only the live tree +# says what THIS boot actually reserved -- and a window without coverage is +# refused instead of used. +# 2. ct_soc_ddr_sink must NOT have its size shrunk while running (finding +# B-C1-1): `bytes_left = size_i - off_q` is unsigned, and in circular mode +# room1 does not check it at all. This script therefore leaves base and +# size at their RTL reset (0x6000_0000 + 64 MiB, +# examples/kv260/cva6_linux64/rtl/cva6_linux64_soc_top.sv:433) and only +# verifies that the reservation covers them. +ddr_check_window() { + b=$(( $(dm $DDR_BASE) )); s=$(( $(dm $DDR_SIZE) )) + set -- $(python3 - <<'PY' +import glob, struct +f = sorted(glob.glob('/sys/firmware/devicetree/base/reserved-memory/ctrace-pl-ddr@*/reg')) +if not f: + print("0 0") +else: + a, sz = struct.unpack('>QQ', open(f[0], 'rb').read()[:16]) + print(a, sz) +PY +) + res_b=$1; res_s=$2 + printf 'RESMEM 0x%08X + 0x%08X SINK 0x%08X + 0x%08X\n' \ + "$res_b" "$res_s" "$b" "$s" >&2 + if [ "$res_s" -gt 0 ] && [ "$b" -ge "$res_b" ] \ + && [ $(( b + s )) -le $(( res_b + res_s )) ]; then + printf 'DDR_WINDOW 0x%08X + %d MiB (covered by the reservation)\n' \ + "$b" $(( s / 1048576 )) >&2 + else + printf 'DDR_WINDOW_UNRESERVED -- 0x%08X + 0x%08X is NOT no-map reserved.\n' \ + "$b" "$s" >&2 + echo " Writing there would corrupt the host kernel's own RAM. The" >&2 + echo " reservation needs a REBOOT with" >&2 + echo " examples/kv260/common/board/ctrace_resmem.dtso installed." >&2 + echo " Use SINK=uram until then." >&2 + exit 15 + fi +} + +# Encoder control word, assembled FIELD BY FIELD instead of from a hex +# constant. The constants in the archived board scripts carried +# InstSyncMax = 0 (full sync every 16 instructions) without saying so -- that +# is the value which floods the ring with ResourceFull+ProgTraceSync pairs and +# broke decode at the first jalr in fw_platform_init on every bitstream tested +# (2026-08-17). Two wrong fields inside one hex literal mask each other; named +# fields do not. +# +# trTeControl: b0 Active, b1 Enable, b2 InstTracing, [6:4] InstMode, +# [8:7] SendConfig, b9 Context, b15 InhibitSrc, [19:16] InstSyncMode, +# [23:20] InstSyncMax, [26:24] Format. +enc_words() { + SENDCFG=${SENDCFG:-once} + SYNCMAX=${SYNCMAX:-6} + case "$SENDCFG" in + once) cfg=1 ;; + onsync) cfg=2 ;; + none) + echo "SENDCFG_REQUIRED: this app carries the 64-bit encoder -- without the" >&2 + echo " config message (SENDCFG=once) the stream is not decodable." >&2 + exit 10 ;; + *) echo "unknown SENDCFG=$SENDCFG (once|onsync)" >&2; exit 2 ;; + esac + base=$(( (0x01060063 & ~0x180) | (cfg << 7) )) + base=$(( (base & ~0x00F00000) | ((SYNCMAX & 0xF) << 20) )) + ctrl_on=$(( base | 0x4 )) # b2 InstTracing +} + +# Feature register: SrcBits [31:28], SrcID [27:16], compression suite [15:0]. +# The word is written IN FULL rather than read-modify-written, so that the +# configuration does not depend on whatever a previous run left behind: two +# consecutive runs would otherwise not be comparable. With FEATURES="" the +# result is the same word the archived script wrote (0x2002_0000). +enc_feat() { + SRC=${SRC:-2} + feat=0 + for ft in $(printf '%s' "${FEATURES:-}" | tr ',' ' '); do + case "$ft" in + ir) b=3 ;; + bp) b=4 ;; + jtc) b=5 ;; + rh) b=8 ;; + rb) b=11 ;; + wideicnt) b=12 ;; + ibhs) b=13 ;; + ri) b=14 ;; + *) echo "unknown FEATURE '$ft' (ir bp jtc rh rb wideicnt ibhs ri)" >&2; exit 2 ;; + esac + feat=$(( feat | (1 << b) )) + done + dm $ENC_FEAT 32 $(printf '0x%08x' $(( 0x20000000 | (SRC << 16) | feat ))) + echo "FEAT $(dm $ENC_FEAT) (SrcID $SRC, FEATURES='${FEATURES:-none}')" >&2 +} + +case "$PHASE" in +prep) + # --- set pl_clk0 deliberately, do not just find it ------------------------ + # The PS controls the PL clock through PL0_REF_CTRL (CRL_APB). An xmutil + # overlay carrying only `firmware-name` does NOT touch it -- a freshly + # loaded design therefore runs at whatever the boot firmware left behind + # (found on this board: 100 MHz, and 150 MHz on 2026-08-19). + # + # CHECK ONLY, never set (B-W1-1): kv260_plclk.sh refuses any change while an + # app occupies the active slot -- and that is ALWAYS the case here, otherwise + # the aperture clamp above would not have let this script get this far. An + # unconditional call would be a guaranteed PLCLK_FAILED. The change itself + # belongs BETWEEN unloadapp and loadapp; the dashboard server does it there + # (server.py load_app(), driven by plclk.json). + PL_MHZ=${PL_MHZ:-75} + if [ "$PL_MHZ" != "skip" ]; then + _cur=$(dm 0xFF5E00C0); _v=$((_cur)) + _d0=$(( (_v >> 8) & 0x3F )); _d1=$(( (_v >> 16) & 0x3F )) + _hz=0 + [ "$_d0" -gt 0 ] && [ "$_d1" -gt 0 ] && _hz=$(( 1500000000 / (_d0 * _d1) )) + # PL_MHZ is a LABEL, not an exact frequency: f = 1500 MHz / DIVISOR0 is not + # freely choosable with integer dividers. Divider 22 gives 68181818 Hz -- + # NOT 68000000. The target hertz are therefore formed exactly as in + # kv260_plclk.sh, otherwise the check fails on a rounding instead of on an + # error. + case "$PL_MHZ" in + 68) _want=$(( 1500000000 / 22 )) ;; + 75) _want=$(( 1500000000 / 20 )) ;; + 100) _want=$(( 1500000000 / 15 )) ;; + *) _want=$(( PL_MHZ * 1000000 )) ;; + esac + if [ "$_hz" = "$_want" ]; then + echo "PLCLK OK: pl_clk0 = $_hz Hz (PL0_REF_CTRL=$_cur)" >&2 + else + echo "PLCLK_WRONG: pl_clk0 = $_hz Hz, wanted $_want Hz -- the change" >&2 + echo " belongs BETWEEN unloadapp and loadapp (see plclk.json)." >&2 + exit 9 + fi + fi + # PS AFIFM port widths (reset = 128 bit, needed once per boot): + # HP0/AFIFM2 -> 32 bit (trace sink), HP1/AFIFM3 -> 64 bit (guest memory). +# FABRIC_WIDTH is bits [1:0] of RDCTRL/WRCTRL, and the reset value of those +# registers is 0x3B0 -- several bits above [1:0] are marked reserved but are +# RW and set out of reset (UG1087). Writing the whole register with the width +# code therefore clears them. Read-modify-write instead; pointed out +# 2026-08-21 while the AMP core-1 defect was being tracked down, and +# corrected everywhere the same day. +afifm_width() { # $1 = AFIFM base, $2 = FABRIC_WIDTH code (0=128, 1=64, 2=32) + for _o in 0x0 0x14; do + _a=$(printf '0x%08X' $(( $1 + $_o ))) + _v=$(( $(dm $_a) )) + dm $_a 32 $(printf '0x%08X' $(( (_v & ~0x3) | $2 ))) + done +} + # Without this the first fetch of the core hangs (finding C6). + afifm_width 0xFD380000 2 + afifm_width 0xFD390000 1 + echo "AFIFM HP0=$(dm 0xFD380000)/$(dm 0xFD380014) HP1=$(dm 0xFD390000)/$(dm 0xFD390014)" >&2 + dm $CTRL 32 0x6 # core in reset, clear trace ring and console ring + dm $CTRL 32 0x0 + dm $CON_RPTR 32 0x0 + case "$SINK" in + uram) + # URAM one-shot (SINK_CTRL b3): the ring holds the FIRST 1 MiB from the + # moment recording is switched on. Without one-shot it wraps, and the + # beginning of the window would be overwritten. + dm $SINK_CTRL 32 0x8 ;; + ddr) + ddr_check_window + # DDR sink linear (b0 enable, b2=0 not circular) + clear pulse b1, AND the + # URAM one-shot (b3) alongside: the two sinks are independent and run in + # parallel, so one run yields BOTH windows -- 1 MiB of URAM and up to + # 64 MiB of DDR out of the same stream. b1 does not latch (write mask + # 0xFFFF_FFDD), the register reads back 0x9. + dm $SINK_CTRL 32 0x0B + echo "SINK=ddr SINK_CTRL=$(dm $SINK_CTRL) DDR_BASE=$(dm $DDR_BASE) DDR_SIZE=$(dm $DDR_SIZE) WPTR=$(dm $DDR_WPTR)" >&2 ;; + *) echo "unknown SINK=$SINK (uram|ddr)" >&2; exit 2 ;; + esac + sz=$(stat -c%s "$PAYLOAD") + src_md5=$(md5sum "$PAYLOAD" | cut -d' ' -f1) + echo "PAYLOAD $PAYLOAD $sz B md5=$src_md5" >&2 + t0=$(date +%s) + python3 /tmp/phys_io.py write $GUEST "$PAYLOAD" + echo "WRITE_SECONDS $(( $(date +%s) - t0 ))" >&2 + # LOAD PROOF = the md5 READ BACK OUT OF THE WINDOW. A byte counter or a word + # sample is not one (either could come from a previous run). + python3 /tmp/phys_io.py read $GUEST "$sz" -o /tmp/cva6_linux64_rb.bin + tgt_md5=$(md5sum /tmp/cva6_linux64_rb.bin | cut -d' ' -f1) + rm -f /tmp/cva6_linux64_rb.bin + echo "TARGET_MD5 $tgt_md5" >&2 + # ...and the comparison is actually DRAWN. Two sums printed underneath each + # other while the script continues in every case would be an eye check, not + # a check (the same correction rocket2_linux_run.sh carries since + # 2026-08-10). + if [ "$tgt_md5" != "$src_md5" ]; then + echo "PREP_MD5_MISMATCH -- window $tgt_md5 != file $src_md5" >&2 + exit 11 + fi + echo "PREP_DONE" >&2 + ;; +start) + enc_feat + enc_words + TRACE_DELAY=${TRACE_DELAY:-0} + if [ "$TRACE_DELAY" = "0" ]; then + dm $ENC 32 $(printf '0x%08x' $ctrl_on) + echo "ENC_CTRL $(dm $ENC) (SENDCFG=$SENDCFG SYNCMAX=$SYNCMAX, recording from core start)" >&2 + dm $CTRL 32 0x1 # core released -- OpenSBI runs from here + echo "CORE_STARTED $(dm $CTRL)" >&2 + else + # During the wait the encoder is COMPLETELY OFF (trTeControl = 0), not just + # "InstTracing = 0". Reason, measured 2026-08-08 19:52: with Active/Enable + # = 1 and only the emission disabled, the compression models inside the + # encoder (JTC cache, BP table) KEEP RUNNING. When emission is switched on, + # the encoder cache is warm while the decoder cache is empty -- and the + # decode aborts after a few thousand instructions with "resolved source + # PC ... to a non-indirect instruction ... decoder desynchronization". Out + # of reset, both sides start empty. The config message still arrives + # (CFG_ONCE fires on the rising edge of inst_trace_active). + dm $ENC 32 0x00000000 + echo "ENC_CTRL $(dm $ENC) (encoder OFF during the wait)" >&2 + dm $CTRL 32 0x1 + echo "CORE_STARTED $(dm $CTRL) -- waiting ${TRACE_DELAY}s before recording" >&2 + sleep "$TRACE_DELAY" + dm $ENC 32 $(printf '0x%08x' $ctrl_on) + echo "TRACE_ON at t=+${TRACE_DELAY}s: ENC_CTRL $(dm $ENC) (SENDCFG=$SENDCFG SYNCMAX=$SYNCMAX)" >&2 + fi + sleep ${RUNSEC:-3} + dm $ENC 32 $(printf '0x%08x' $base) # tracing off, core KEEPS RUNNING + sleep 0.3 + # Encoder fully off -- that closes the message in flight instead of letting + # it end in the middle of a field. + dm $ENC 32 0x0 + sleep 0.3 + [ "$SINK" = "ddr" ] && dm $SINK_CTRL 32 0x0 + echo "TRACE_BEATS $(dm $TR_BEATS) TRACE_BYTES $(dm $TR_BYTES)" >&2 + [ "$SINK" = "ddr" ] && echo "DDR wptr=$(dm $DDR_WPTR) stat=$(dm $SINK_STAT) drops=$(dm $DDR_DROPS)" >&2 + echo "CON_BYTES $(dm $CON_BYTES) CON_DROPS $(dm $CON_DROPS)" >&2 + echo "STATUS $(dm $STATUS)" >&2 + echo "START_DONE" >&2 + ;; +live) + # CONTINUOUS MODE for the dashboard view. Difference to `start`: NOTHING is + # switched off again. The encoder stays armed, the core keeps running, and + # the ring runs CIRCULAR instead of one-shot -- otherwise the display stands + # still after the first MiB and shows a freeze frame instead of traffic. + # + # b2 is the circular bit of ct_soc_ddr_sink (circ_i, wired in + # examples/kv260/cva6_linux64/rtl/cva6_linux64_soc_top.sv:348); b3 = 0 lets + # the URAM ring run circular as well, so both sink cards show traffic. + if [ "$SINK" = "ddr" ]; then + ddr_check_window + dm $SINK_CTRL 32 0x5 # b0 DDR on, b2 circular, b3=0 URAM circular + else + dm $SINK_CTRL 32 0x0 # URAM circular (one-shot off) + fi + dm $CTRL 32 0x3 # b1 trace_clear (pulse) with the core running + dm $CTRL 32 0x1 + enc_feat + enc_words + dm $ENC 32 $(printf '0x%08x' $ctrl_on) + sleep 1 + echo "LIVE ENC_CTRL $(dm $ENC) SENDCFG=$SENDCFG SYNCMAX=$SYNCMAX" >&2 + echo "LIVE SINK_CTRL $(dm $SINK_CTRL) SINK=$SINK" >&2 + [ "$SINK" = "ddr" ] && echo "LIVE DDR base=$(dm $DDR_BASE) size=$(dm $DDR_SIZE) wptr=$(dm $DDR_WPTR)" >&2 + b1=$(( $(dm $TR_BYTES) )); sleep 2; b2=$(( $(dm $TR_BYTES) )) + echo "LIVE TRACE_BYTES $b1 -> $b2 (+$((b2 - b1)) in 2 s)" >&2 + echo "LIVE STATUS $(dm $STATUS) CON_BYTES $(dm $CON_BYTES)" >&2 + # The proof the display needs: is anything actually flowing? A freeze frame + # would otherwise be indistinguishable from a hung core. + if [ "$((b2 - b1))" -gt 0 ]; then + echo "LIVE_OK -- stream is running" >&2 + else + echo "LIVE_STALLED -- bytes +$((b2 - b1)) in 2 s" >&2 + fi + echo "LIVE_DONE" >&2 + ;; +login) + # Interactive guest console over the RX path (CON_TX 0x34: b8 = commit, + # b7:0 = character). The ring is 64 KiB and CON_BYTES is MONOTONIC (= the + # write position); CON_RPTR is only tracked so that con_used = wr - rd does + # not reach the drop threshold -- it does not change the read address + # (pos mod 64 KiB). + before=$(dm $CON_BYTES); before=$((before)) + dm $CON_RPTR 32 $(printf '0x%08x' $before) + echo "CON_BEFORE $before RX_USED $(dm $CON_TX)" >&2 + type_line "${LOGIN:-root}" + sleep 4 + echo "RX_USED after the login input: $(dm $CON_TX) (0 = the guest took it all)" >&2 + # One line per command -- NOT "for c in $CMDS": word splitting would tear + # "uname -a" into two commands. + printf '%s\n' "uname -a" "cat /proc/cpuinfo" "free -m" "echo R5A_ENV_OK" | + while IFS= read -r c; do + type_line "$c" + sleep 4 + done + now=$(dm $CON_BYTES); now=$((now)) + echo "CON_AFTER $now (+$((now - before))) DROPS $(dm $CON_DROPS)" >&2 + read_con "$now" + ;; +type) + before=$(dm $CON_BYTES); before=$((before)) + dm $CON_RPTR 32 $(printf '0x%08x' $before) + type_line "$CMD" + sleep ${WAIT:-4} + now=$(dm $CON_BYTES); now=$((now)) + echo "CON_AFTER $now (+$((now - before))) DROPS $(dm $CON_DROPS)" >&2 + read_con "$now" + ;; +con) + n=$(dm $CON_BYTES); n=$((n)) + echo "CON_BYTES $n DROPS $(dm $CON_DROPS)" >&2 + read_con "$n" + ;; +trace) + if [ "$SINK" = "ddr" ]; then + # DDR_WPTR (0x28) = bytes written since the clear pulse; SINK_STAT (0x2C) + # carries b0 ddr_full / b1 ddr_axi_err / b2 ddr_wrapped. + n=$(( $(dm $DDR_WPTR) )); sz=$(( $(dm $DDR_SIZE) )) + [ "$n" -gt "$sz" ] && n=$sz + src=$(dm $DDR_BASE) + echo "DDR_WPTR $(dm $DDR_WPTR) SINK_STAT $(dm $SINK_STAT) DDR_DROPS $(dm $DDR_DROPS)" >&2 + else + # The URAM ring is always readable (it runs along in both SINK modes). + n=$(( $(dm $TR_BYTES) )) + [ "$n" -gt 1048576 ] && n=1048576 + src=$TR_RING + fi + # Cap against an accidentally huge read. If it bites, that is ANNOUNCED -- a + # silently truncated stream would have fewer bytes AND fewer instructions, + # and every number computed from it would still look plausible. + MAXB=${MAXB:-4194304} + cap=0 + if [ "$n" -gt "$MAXB" ]; then n=$MAXB; cap=1; fi + echo "TRACE_BYTES $n (beats=$(dm $TR_BEATS) status=$(dm $STATUS) capped=$cap)" >&2 + [ "$n" -gt 0 ] && python3 /tmp/phys_io.py read $src $(( (n + 3) / 4 * 4 )) -o $TRFILE + echo "TRACEFILE $(ls -l $TRFILE 2>/dev/null | awk '{print $5}')" >&2 + ;; +*) + echo "unknown PHASE=$PHASE" >&2; exit 2 ;; +esac diff --git a/examples/dashboard/boot/rocket2_linux_run.sh b/examples/dashboard/boot/rocket2_linux_run.sh new file mode 100644 index 0000000..e0813aa --- /dev/null +++ b/examples/dashboard/boot/rocket2_linux_run.sh @@ -0,0 +1,770 @@ +# SPDX-FileCopyrightText: 2026 Accemic Technologies GmbH +# SPDX-License-Identifier: ISC +# rocket2_linux_run.sh -- board sequence of the TWO-HART Rocket demonstrator. +# Runs ON THE BOARD. +# +# sudo PHASE=prep bash rocket2_linux_run.sh # clock, AFIFM, rings, payload + hash +# sudo PHASE=diag bash rocket2_linux_run.sh # signs of life from BOTH harts +# sudo PHASE=start RUNSEC=3 bash rocket2_linux_run.sh +# sudo PHASE=con bash rocket2_linux_run.sh # console ring -> /tmp/r2_con.bin +# sudo PHASE=login bash rocket2_linux_run.sh # interactive over the RX path +# sudo PHASE=type CMD='...' bash rocket2_linux_run.sh +# sudo PHASE=trace bash rocket2_linux_run.sh # trace -> /tmp/r2_trace.bin +# +# Twin of rocket_linux64_run.sh. It was deliberately NOT extended but +# duplicated: the single-hart app stays operable unchanged, and a script that +# writes ENC1 @0x02_0000 cannot accidentally run against the single-hart app +# (where nothing answers at that address). +# +# FOUR differences, and every single one is a place where the proof would +# otherwise fail SILENTLY: +# +# 1. TWO encoder windows, with DIFFERENT SrcIDs. +# ENC0 0xA0010000 -> SrcBits 2 / SrcID 0 (hart 0) +# ENC1 0xA0020000 -> SrcBits 2 / SrcID 1 (hart 1) +# Without different SrcIDs the merged stream carries only one source and +# `NexRv -target 1` returns zero instructions -- on the board that looks +# like "the funnel does not separate" (counter-check P-1). +# +# 2. trTeControl with THREE bits that the older scripts do NOT set: +# b9 Context -- without this bit the composer produces NO +# ownership message (TCODE 2). Exactly this one bit +# was the difference between 13 and 0 messages. +# b15 InhibitSrc=0 -- otherwise the SRC field is missing in the frame. +# [23:20] InstSyncMax -- the default 0 means full synchronization every +# 16 instructions. Measured: 221-359 error messages +# and gaps in BOTH sequences; on real software the +# same effect costs a factor of 3.9 in bandwidth. +# The value proven in simulation is 0x016602E7 (SYNCMAX=6). +# +# 3. Observation channel PER HART (0x4C/0x50/0x54 and 0x5C/0x60/0x64) plus +# STATUS b18/b19 (retire_seen per hart) and b[14:12]/b[22:20] (privilege +# level per hart). That is the proof "two harts really run" which does NOT +# go through the trace -- so it does not share the failure domain of the +# thing it is meant to prove. +# +# 4. FUNNEL_CTRL 0xA0000058 is read and logged (reset 0x11 = round robin). An +# arbitration that starves one channel would look, in the result, exactly +# like "hart 1 is not running". +# +# WHY phys_io.py AND NOT `dd of=/dev/mem`: the window is reserved `no-map`, the +# read()/write() path returns "Bad address" there, only mmap works. And the +# slice copy (`readbulk`) faults on THIS board even on the DDR sink buffer with +# "Bus error" (open issue) -- hence the ctypes word loop everywhere. +set -e +dm() { busybox devmem "$@"; } + +APP=${APP:-rocket2_ctrace_kv260} +PAYLOAD=${PAYLOAD:-/tmp/fw_payload_rocket2.bin} +GUEST=0x64000000 # PS view; the Rocket harts see this as 0x8000_0000 +PHASE=${PHASE:-prep} + +CTRL=0xA0000000 +STATUS=0xA0000004 +TR_BEATS=0xA0000008 +TR_BYTES=0xA000000C +CON_BYTES=0xA0000014 +CON_DROPS=0xA0000018 +SINK_CTRL=0xA000001C +DDR_BASE=0xA0000020 +DDR_SIZE=0xA0000024 +DDR_WPTR=0xA0000028 +SINK_STAT=0xA000002C +DDR_DROPS=0xA0000030 +CON_TX=0xA0000034 +CON_RPTR=0xA0000038 +WIN_ERR_CNT=0xA000003C +WIN_ERR_LO=0xA0000040 +WIN_ERR_HI=0xA0000044 +PC0_LO=0xA000004C +PC0_HI=0xA0000050 +RETIRES0=0xA0000054 +FUNNEL_CTRL=0xA0000058 +PC1_LO=0xA000005C +PC1_HI=0xA0000060 +RETIRES1=0xA0000064 +ENC0=0xA0010000 +ENC0_FEAT=0xA0010008 +ENC1=0xA0020000 +ENC1_FEAT=0xA0020008 +TR_RING=0xA0200000 +CON_RING=0xA0300000 + +# --- OpenSBI cold-boot arbiters IN THE GUEST IMAGE ------------------------ +# FOUR words decide whether a released core boots COLD or falls into the warm +# path. Offsets relative to the start of the image (guest 0x8000_0000 = +# PS $GUEST), addresses from `nm fw_payload.elf`: +# 0x40000 _boot_lottery (.data) asm lottery in fw_base.S +# 0x40008 _boot_status (.data) asm progress marker +# 0x43000 coldboot_lottery (.bss) C lottery in sbi_init() +# 0x43018 coldboot_done (.bss) +# +# In the FILE all four are 0. A booted guest sets all four to 1 -- and they +# survive ITS OWN RESET, because the reset only hits the cores, not the DDR. +# If it is then released again without reloading, hart 0 reads "somebody has +# already done the cold boot", takes the warm path and parks in +# sbi_hsm_hart_wait() on an IPI that nobody sends; hart 1 meanwhile stays in +# the park loop of the boot ROM waiting for exactly that IPI. Both wait for +# each other and the console stays at 0 bytes. +# +# THAT is the "it worked the first time, not afterwards" failure: hart0 +# 0x8001_077E (a `wfi`, resolved against sbi.dis), hart1 0x0001_0064 (likewise +# `wfi`, rom_patched.dis:31), STATUS 0x003C_3701. It was triggered from the +# UI: `ctl stop` writes CONTROL=0 (that is NOT a pause, b0 is core_rst_hold) +# and `ctl run` releases again WITHOUT reloading the payload. Reproduced +# bit-identically. +ARB="_boot_lottery:0x40000 _boot_status:0x40008 coldboot_lottery:0x43000 coldboot_done:0x43018" + +arb_show() { + s="" + for e in $ARB; do + s="$s ${e%%:*}=$(dm $(printf '0x%08x' $(( GUEST + ${e#*:} ))))" + done + echo "ARB $1:$s" >&2 +} + +# True (0) when AT LEAST ONE arbiter is set -- the image is then used and a +# core release on top of it can no longer boot cold. +arb_used() { + for e in $ARB; do + if [ $(( $(dm $(printf '0x%08x' $(( GUEST + ${e#*:} )))) )) -ne 0 ]; then + return 0 + fi + done + return 1 +} + +# Before EVERY release from reset. If the cores already run, set arbiters are +# the normal case (the guest is running) and no error -- the check therefore +# only applies when b0 really is 0. +arb_gate() { + if [ $(( $(dm $CTRL) & 1 )) -ne 0 ]; then return 0; fi + if ! arb_used; then return 0; fi + arb_show "before the release" + echo "GUEST_IMAGE_USED -- the image in DDR is used: a booted OpenSBI has set" >&2 + echo " the cold-boot arbiters. Releasing on top of that ends in hart0 =" >&2 + echo " sbi_hsm_hart_wait and hart1 = boot-ROM park, both waiting for each" >&2 + echo " other, and the console stays silent." >&2 + echo " Remedy: PHASE=prep -- reloads the payload AND verifies it." >&2 + echo " Merely releasing again cannot heal this (measured: a partial restore" >&2 + echo " is not enough either, the core then hangs at the kernel entry" >&2 + echo " 0x8020_00F4 instead of at the warm path)." >&2 + exit 14 +} + +LABEL=${LABEL:-m5} +SINK=${SINK:-ddr} # ddr (256 MiB, default) | uram (1 MiB one-shot) +# Default: DDR4 rather than URAM. The URAM ring holds 1 MiB and is full after +# 35 ms at the MEASURED 29.7 MB/s -- too small as the default for a view that +# is supposed to show traffic. +# +# ADDRESS PLAN v4 ("256 MB of trace memory, otherwise the write pointer runs +# through too fast"): +# 0x5000_0000 +256 MiB trace sink <- HERE +# 0x6000_0000 +64 MiB GAP (the old trace window) +# 0x6400_0000 +192 MiB guest <- unchanged +# Measured: 64 MiB wrap every 2.3 s, 256 MiB every 9.0 s. The encoder is NO +# lever for this -- InstSyncMax 6 -> 15 changes the byte rate by 0.3 %. +DDR_WIN_BASE=${DDR_WIN_BASE:-0x50000000} +DDR_WIN_SIZE=${DDR_WIN_SIZE:-0x10000000} + +# The aperture is touched ONLY when EXACTLY our app owns the active slot. +# Otherwise the AXI interconnect wedges and the board is dead (three boards +# frozen that way). fpga_manager "operating" is NOT a sufficient criterion. +if ! xmutil listapps 2>/dev/null | awk -v a="$APP" '$1==a && $NF!="-1" {f=1} END{exit !f}'; then + echo "APP_NOT_ACTIVE ($APP) -- aperture NOT touched" >&2 + xmutil listapps >&2 || true + exit 8 +fi + +# A diagnostic line that names BOTH harts. A shared counter would happily keep +# running while ONE hart stands still -- with two harts, "is the core making +# progress?" is no longer one question but two. +diag_line() { + st=$(dm $STATUS); stv=$((st)) + echo " STATUS=$st [retire0=$(( (stv >> 18) & 1 )) retire1=$(( (stv >> 19) & 1 ))" \ + "priv0=$(( (stv >> 12) & 7 )) priv1=$(( (stv >> 20) & 7 ))]" >&2 + echo " HART0 RETIRES=$(dm $RETIRES0) PC=$(dm $PC0_HI):$(dm $PC0_LO)" >&2 + echo " HART1 RETIRES=$(dm $RETIRES1) PC=$(dm $PC1_HI):$(dm $PC1_LO)" >&2 + echo " WIN_ERR=$(dm $WIN_ERR_CNT)@$(dm $WIN_ERR_HI):$(dm $WIN_ERR_LO)" \ + "CON=$(dm $CON_BYTES)/$(dm $CON_DROPS) TR=$(dm $TR_BYTES) FUNNEL=$(dm $FUNNEL_CTRL)" >&2 +} + +# --- set the trace window -- WITH a coverage check against the live devicetree +# +# TWO traps live here, and both are expensive: +# +# 1. WRITING INTO FOREIGN MEMORY. `reserved-memory` is a BOOT-TIME +# reservation. As long as the reboot with the new ctrace_resmem.dtso has +# not happened, 0x5000_0000..0x5FFF_FFFF belongs to the Ubuntu kernel +# (`/proc/iomem`: "00000000-5fffffff : System RAM"). A sink writing there +# at 29.7 MB/s corrupts the HOST. The reservation is therefore READ, not +# assumed, and without coverage the RTL reset value stays in place. +# +# 2. ct_soc_ddr_sink must NOT have its size reduced while running. +# `bytes_left = size_i - off_q` is unsigned (ct_soc_ddr_sink.sv:99), and in +# circular mode room1 does not check it at all (:101). If off_q is above +# the new size, the difference underflows and exactly ONE transfer goes to +# base+off_q -- outside the window. Measured byte-exactly: 4 bytes at +# 0x63F0_022C with off_q=0x03F0_022C, red counter-probe with a clear pulse +# at 0 bytes. The order below -- switch off, CLEAR, set, switch on -- is +# therefore not caution but the measured condition for this not happening. +ddr_window_setup() { + want_b=$(( DDR_WIN_BASE )); want_s=$(( DDR_WIN_SIZE )) + # Reservation from the LIVE devicetree, not from the source file: only the + # live tree says what this boot actually reserved. + set -- $(python3 - <<'PY' +import glob, struct +f = sorted(glob.glob('/sys/firmware/devicetree/base/reserved-memory/ctrace-pl-ddr@*/reg')) +if not f: + print("0 0") +else: + a, s = struct.unpack('>QQ', open(f[0], 'rb').read()[:16]) + print(a, s) +PY +) + res_b=$1; res_s=$2 + printf 'RESMEM 0x%08X + 0x%08X WANTED 0x%08X + 0x%08X\n' \ + "$res_b" "$res_s" "$want_b" "$want_s" >&2 + if [ "$res_s" -gt 0 ] && [ "$want_b" -ge "$res_b" ] \ + && [ $(( want_b + want_s )) -le $(( res_b + res_s )) ]; then + # Covered. Set the window -- in the order the underflow trap enforces. + dm $SINK_CTRL 32 0x0 + dm $SINK_CTRL 32 0x2 # clear -> off_q = 0 + dm $DDR_BASE 32 $(printf '0x%08X' $want_b) + dm $DDR_SIZE 32 $(printf '0x%08X' $want_s) + got_b=$(( $(dm $DDR_BASE) )); got_s=$(( $(dm $DDR_SIZE) )) + if [ "$got_b" != "$want_b" ] || [ "$got_s" != "$want_s" ]; then + printf 'DDR_WINDOW_REJECTED register 0x%08X+0x%08X instead of 0x%08X+0x%08X\n' \ + "$got_b" "$got_s" "$want_b" "$want_s" >&2 + exit 15 + fi + printf 'DDR_WINDOW 0x%08X + %d MiB (wrap ~%d.%d s at 29.7 MB/s)\n' \ + "$got_b" $(( got_s / 1048576 )) \ + $(( got_s / 29700000 )) $(( (got_s * 10 / 29700000) % 10 )) >&2 + else + # NOT covered -> change nothing. The RTL reset value lies in the old, + # provably reserved window; a short wrap is better than a corrupted host. + printf 'DDR_WINDOW_UNRESERVED -- 0x%08X + 0x%08X is NOT reserved no-map.\n' \ + "$want_b" "$want_s" >&2 + echo " The RTL reset value stays. The large window needs the REBOOT" >&2 + echo " with the new ctrace_resmem.dtso device-tree overlay" >&2 + echo " (see the board memory map in the documentation)." >&2 + printf 'DDR_WINDOW (reset) 0x%08X + %d MiB\n' \ + $(( $(dm $DDR_BASE) )) $(( $(dm $DDR_SIZE) / 1048576 )) >&2 + fi +} + +# Read the console ring. CAPPED: CON_BYTES is MONOTONIC (a write position), +# but the ring holds only 65,536 bytes. An uncapped read would run past the +# window -- and a Linux boot plus a login session exceeds 64 KiB easily. +read_con() { + n=$1 + [ "$n" -gt 65536 ] && n=65536 + [ "$n" -gt 0 ] && python3 /tmp/phys_io.py read $CON_RING $(( (n + 3) / 4 * 4 )) -o /tmp/r2_con.bin + echo "CONFILE $(ls -l /tmp/r2_con.bin 2>/dev/null | awk '{print $5}') (ring position $1)" >&2 +} + +type_line() { + s="$1"; i=0 + while [ $i -lt ${#s} ]; do + c=$(printf '%s' "$s" | cut -c$((i+1))) + o=$(printf '%d' "'$c") + dm $CON_TX 32 $(printf '0x%08x' $((0x100 | o))) + i=$((i+1)) + done + dm $CON_TX 32 0x10A # '\n' +} + +case "$PHASE" in +prep) + # --- pin pl_clk0 down instead of taking it as found ---------------------- + # CHECK first, set only if needed: kv260_plclk.sh refuses every change while + # an app owns the active slot -- and that is ALWAYS the case here, otherwise + # the script would not have got this far. An unconditional call would be a + # guaranteed PLCLK_FAILED. The change itself therefore belongs BETWEEN + # unloadapp and loadapp (host script). + PL_MHZ=${PL_MHZ:-75} + if [ "$PL_MHZ" != "skip" ]; then + _cur=$(dm 0xFF5E00C0); _v=$((_cur)) + _d0=$(( (_v >> 8) & 0x3F )); _d1=$(( (_v >> 16) & 0x3F )) + _hz=0 + [ "$_d0" -gt 0 ] && [ "$_d1" -gt 0 ] && _hz=$(( 1500000000 / (_d0 * _d1) )) + # PL_MHZ is a LABEL, not an exact frequency: f = 1500 MHz / DIVISOR0 is not + # freely choosable with integer divisors. Divisor 22 gives 68181818 Hz -- + # NOT 68000000. The target hertz are therefore formed exactly as in + # kv260_plclk.sh, otherwise the check fails on a rounding instead of on an + # error. + case "$PL_MHZ" in + 68) _want=$(( 1500000000 / 22 )) ;; + 75) _want=$(( 1500000000 / 20 )) ;; + 100) _want=$(( 1500000000 / 15 )) ;; + *) _want=$(( PL_MHZ * 1000000 )) ;; + esac + if [ "$_hz" = "$_want" ]; then + echo "PLCLK OK: pl_clk0 = $_hz Hz (PL0_REF_CTRL=$_cur)" >&2 + else + echo "PLCLK_WRONG: pl_clk0 = $_hz Hz, wanted $_want Hz -- the change" >&2 + echo " belongs BETWEEN unloadapp and loadapp (host script)." >&2 + exit 9 + fi + fi + # PS AFIFM port widths (reset = 128 bit, needed once per boot): + # HP0/AFIFM2 -> 32 bit (trace sink), HP1/AFIFM3 -> 64 bit (guest memory). +# FABRIC_WIDTH is bits [1:0] of RDCTRL/WRCTRL, and the reset value of those +# registers is 0x3B0 -- several bits above [1:0] are marked reserved but are +# RW and set out of reset (UG1087). Writing the whole register with the width +# code therefore clears them. Read-modify-write instead; pointed out +# 2026-08-21 while the AMP core-1 defect was being tracked down, and +# corrected everywhere the same day. +afifm_width() { # $1 = AFIFM base, $2 = FABRIC_WIDTH code (0=128, 1=64, 2=32) + for _o in 0x0 0x14; do + _a=$(printf '0x%08X' $(( $1 + $_o ))) + _v=$(( $(dm $_a) )) + dm $_a 32 $(printf '0x%08X' $(( (_v & ~0x3) | $2 ))) + done +} + # Without it the first fetch of the cores hangs. + afifm_width 0xFD380000 2 + afifm_width 0xFD390000 1 + echo "AFIFM HP0=$(dm 0xFD380000)/$(dm 0xFD380014) HP1=$(dm 0xFD390000)/$(dm 0xFD390014)" >&2 + # Both harts in reset; clear rings, window-guard diagnostics and the + # observation sticky bits (b1|b2|b3|b4 = 0x1E, level triggered). + dm $CTRL 32 0x1E + dm $CTRL 32 0x0 + dm $CON_RPTR 32 0x0 + echo "FUNNEL_CTRL $(dm $FUNNEL_CTRL) (reset 0x11 = round robin)" >&2 + sz=$(stat -c%s "$PAYLOAD") + src_md5=$(md5sum "$PAYLOAD" | cut -d' ' -f1) + echo "PAYLOAD $PAYLOAD $sz B md5=$src_md5" >&2 + arb_show "before the load" + t0=$(date +%s) + # Word loop, NO writebulk: the slice copy faults on this `no-map` window + # with "Bus error". Measured rather than believed (the run died after 1 s) -- + # 42 s per restart hang on this note. + python3 /tmp/phys_io.py write $GUEST "$PAYLOAD" + echo "WRITE_SECONDS $(( $(date +%s) - t0 ))" >&2 + # LOAD EVIDENCE = md5 READ BACK FROM THE WINDOW. A byte counter or a word + # sample is none (it can just as well come from an earlier run). + python3 /tmp/phys_io.py read $GUEST "$sz" -o /tmp/r2_rbr.bin + tgt_md5=$(md5sum /tmp/r2_rbr.bin | cut -d' ' -f1) + rm -f /tmp/r2_rbr.bin + echo "TARGET_MD5 $tgt_md5" >&2 + # ...and the comparison is actually DRAWN. Previously two sums stood here + # below each other and the script continued in EVERY case -- an eyeball + # check, not a check. "TARGET_MD5 is right" was thus a statement about the + # reader, not about the board. + if [ "$tgt_md5" != "$src_md5" ]; then + echo "PREP_MD5_MISMATCH -- window $tgt_md5 != file $src_md5" >&2 + exit 11 + fi + # And the evidence that matters on the SECOND start: are the four cold-boot + # arbiters 0 again? It follows from the md5 equality, but only stated + # explicitly is it visible -- and exactly this property is the difference + # between "boots" and "hangs". + arb_show "after the load" + if arb_used; then + echo "PREP_GUEST_NOT_PRISTINE -- arbiters set despite md5 equality." >&2 + echo " That is a contradiction: either somebody writes into the guest" >&2 + echo " window in parallel, or the cores were running during the load" >&2 + echo " (CTRL b0). CTRL=$(dm $CTRL)" >&2 + exit 12 + fi + echo "PREP_DONE" >&2 + ;; +diag) + echo "DIAG t0:" >&2; diag_line + sleep 2 + echo "DIAG t1 (+2 s):" >&2; diag_line + ;; +start) + # First the question that decides the whole run: can this image still boot + # at all? Before the sink dance, so that a hopeless run does not first + # collect a second of trace and then wedge silently. + arb_gate + # --- prepare the sink ----------------------------------------------------- + # STALE BYTES are a real problem here, not a precaution: the beat FIFO in + # front of the sink holds the remainder of the previous run, and a window + # then begins with the END of its predecessor (measured: 3,528 B of residual + # surge, gone after ~1 s). In the stream that looks like a framing error and + # is none. + if [ "$SINK" = "ddr" ]; then + ddr_window_setup # window BEFORE arming for the first time + dm $SINK_CTRL 32 0x1 # sink on, so the residual surge drains + prev=-1; i=0 + while [ $i -lt 20 ]; do + sleep 0.2 + cur=$(( $(dm $DDR_WPTR) )) + [ "$cur" = "$prev" ] && break + prev=$cur; i=$((i+1)) + done + dm $SINK_CTRL 32 0x0 + echo "DRAIN $prev B after $i rounds" >&2 + dm $SINK_CTRL 32 0x2 # ddr_clear (pulse) + # The loop above is INEFFECTIVE on its own: it waits for a standing + # DDR_WPTR -- but the residual surge only runs into the fresh buffer AFTER + # the clear. Consequence: every capture begins with the end of its + # predecessor, the seam sits in the middle of a message, and the decoder + # aborts the WHOLE run on it. The position is exactly predictable + # (DDR_WPTR right before arming, 5 of 5 windows), and at the 2 KiB + # boundary the surge is additionally written twice. Therefore: after the + # clear, let it drain AGAIN and clear a SECOND time. Measured: 0 of 8 + # arming events broken, 0 damaged spots in 351,496 messages (without + # RECLEAR: 5 of 5). + dm $SINK_CTRL 32 0x1 + prev2=-1; j=0 + while [ $j -lt 20 ]; do + sleep 0.2 + cur=$(( $(dm $DDR_WPTR) )) + [ "$cur" = "$prev2" ] && break + prev2=$cur; j=$((j+1)) + done + dm $SINK_CTRL 32 0x0 + echo "RECLEAR $prev2 B after $j rounds" >&2 + dm $SINK_CTRL 32 0x2 # second ddr_clear + w0=$(dm $DDR_WPTR) + [ $(( w0 )) -eq 0 ] || { echo "DDR_NOT_CLEARED ($w0)" >&2; exit 13; } + dm $SINK_CTRL 32 0x1 # linear (b2 = 0), 64 MiB + else + dm $CTRL 32 0x2; dm $CTRL 32 0x0 # empty the URAM ring + dm $SINK_CTRL 32 0x8 # URAM one-shot: the FIRST 1 MiB + fi + echo "SINK=$SINK SINK_CTRL=$(dm $SINK_CTRL) base=$(dm $DDR_BASE) size=$(dm $DDR_SIZE)" >&2 + + # --- encoder configuration ------------------------------------------------ + # Features register: SrcBits [31:28] = 2, SrcID [27:16]; the lower 16 bits + # are the compression suite and are preserved by read-modify-write. + # SrcID 0 for hart 0, SrcID 1 for hart 1 -- THAT is the separation. + feat=0 + for ft in $(printf '%s' "${FEATURES:-}" | tr ',' ' '); do + case "$ft" in + ir) b=3 ;; bp) b=4 ;; jtc) b=5 ;; rh) b=8 ;; + rb) b=11 ;; wideicnt) b=12 ;; ibhs) b=13 ;; ri) b=14 ;; + *) echo "unknown FEATURE '$ft'" >&2; exit 2 ;; + esac + feat=$(( feat | (1 << b) )) + done + SRC0=${SRC0:-0}; SRC1=${SRC1:-1} + dm $ENC0_FEAT 32 $(printf '0x%08x' $(( 0x20000000 | (SRC0 << 16) | feat ))) + dm $ENC1_FEAT 32 $(printf '0x%08x' $(( 0x20000000 | (SRC1 << 16) | feat ))) + echo "FEAT0 $(dm $ENC0_FEAT) FEAT1 $(dm $ENC1_FEAT) (SrcID $SRC0/$SRC1, FEATURES='${FEATURES:-none}')" >&2 + + # trTeControl: b0 Active, b1 Enable, b2 InstTracing, [6:4] InstMode, + # [8:7] SendConfig, b9 Context, b15 InhibitSrc, [19:16] InstSyncMode, + # [23:20] InstSyncMax, [26:24] Format. + SENDCFG=${SENDCFG:-once} + SYNCMAX=${SYNCMAX:-6} + case "$SENDCFG" in none) cfg=0 ;; once) cfg=1 ;; onsync) cfg=2 ;; + *) echo "unknown SENDCFG=$SENDCFG (none|once|onsync)" >&2; exit 2 ;; esac + # SENDCFG is MANDATORY on the 64-bit encoder: only from the config message + # does the decoder read CAPS bit 23 and switch its address width to 64. + # Without it, it folds the index at bit 25 and aborts. + if [ "$cfg" = "0" ]; then + echo "SENDCFG_REQUIRED: CT_XLEN=64 -- without the config message the" >&2 + echo " stream is not decodable (SENDCFG=once)." >&2 + exit 10 + fi + base=$(( (0x01060063 & ~0x180) | (cfg << 7) | 0x200 )) # b9 Context ON + base=$(( base & ~0x8000 )) # b15 InhibitSrc OFF + base=$(( (base & ~0x00F00000) | ((SYNCMAX & 0xF) << 20) )) + ctrl_on=$(( base | 0x4 )) # b2 InstTracing + dm $ENC0 32 $(printf '0x%08x' $ctrl_on) + dm $ENC1 32 $(printf '0x%08x' $ctrl_on) + echo "ENC_CTRL0 $(dm $ENC0) ENC_CTRL1 $(dm $ENC1) SYNCMAX=$SYNCMAX (sync every $((1 << (SYNCMAX + 4))) instr) SENDCFG=$SENDCFG" >&2 + + # --- release the cores ---------------------------------------------------- + dm $CTRL 32 0x1 # b0 releases BOTH harts + echo "CORE_STARTED $(dm $CTRL)" >&2 + t0=$(date +%s%N) + sleep ${RUNSEC:-3} + dm $ENC0 32 $(printf '0x%08x' $base) # InstTracing off, cores KEEP running + dm $ENC1 32 $(printf '0x%08x' $base) + t1=$(date +%s%N) + sleep 0.3 + # Encoder fully off -- that completes the message in flight instead of + # ending it in the middle of a field. + dm $ENC0 32 0x0 + dm $ENC1 32 0x0 + sleep 0.3 + [ "$SINK" = "ddr" ] && dm $SINK_CTRL 32 0x0 + echo "M5_US $(( (t1 - t0) / 1000 ))" >&2 + echo "TRACE_BEATS $(dm $TR_BEATS) TRACE_BYTES $(dm $TR_BYTES)" >&2 + echo "DDR wptr=$(dm $DDR_WPTR) stat=$(dm $SINK_STAT) drops=$(dm $DDR_DROPS)" >&2 + echo "CON_BYTES $(dm $CON_BYTES) CON_DROPS $(dm $CON_DROPS)" >&2 + echo "WIN_ERR_CNT $(dm $WIN_ERR_CNT) @ $(dm $WIN_ERR_HI):$(dm $WIN_ERR_LO)" >&2 + echo "FUNNEL_CTRL $(dm $FUNNEL_CTRL)" >&2 + diag_line + # THE hardware proof that does NOT go through the trace: two separate + # retire counters, both non-zero and different from each other. + r0=$(( $(dm $RETIRES0) )); r1=$(( $(dm $RETIRES1) )) + # BLIND CHECK FIXED: this used to be `r0 > 0 && r1 > 0` on CUMULATIVE + # counters that no reset clears. After the first real boot the check + # therefore ALWAYS passed -- the last run reported PASS with hart0=1793832784 + # and hart1=18, both frozen. A measurement that cannot measure after the + # first time is worse than none: it colours a dead core green. What is + # checked now is the INCREASE over a time window. + sleep 1 + r0b=$(( $(dm $RETIRES0) )); r1b=$(( $(dm $RETIRES1) )) + d0=$(( r0b - r0 )); d1=$(( r1b - r1 )) + echo "M5_RETIRES hart0=$r0 (+$d0 in 1 s) hart1=$r1 (+$d1 in 1 s)" >&2 + if [ "$d0" -gt 0 ] && [ "$d1" -gt 0 ]; then + echo "M5_TWOHART_HW PASS -- both harts are retiring NOW (+$d0/+$d1)" >&2 + else + echo "M5_TWOHART_HW FAIL -- increase hart0=+$d0 hart1=+$d1 (at $r0/$r1)" >&2 + echo "M5_HINT PC hart0=$(dm $PC0_HI):$(dm $PC0_LO) hart1=$(dm $PC1_HI):$(dm $PC1_LO)" >&2 + # The one signature we can name, instead of leaving the reader to look for + # it. Deliberately phrased STRUCTURALLY (hart 1 below the guest memory, + # i.e. still in the boot ROM) and not pinned to the address 0x0001_0064: a + # newly built payload would move the address, and a hint that then silently + # stops firing is worse than none. + if [ $(( $(dm $PC1_LO) )) -lt $(( 0x80000000 )) ] && [ "$d1" -eq 0 ]; then + echo "M5_HINT hart1 is still in the boot ROM (PC < 0x8000_0000) waiting" >&2 + echo " for an IPI. Typical for a USED guest image: hart0 falls into the" >&2 + echo " warm path (sbi_hsm_hart_wait) and never sends it. Remedy:" >&2 + echo " PHASE=prep. The console stands at $(dm $CON_BYTES) B." >&2 + arb_show "in the failing case" + fi + fi + echo "START_DONE" >&2 + ;; +live) + # CONTINUOUS OPERATION for the dashboard view. Difference to + # `start`/`window`: NOTHING is switched off again here. The encoders stay + # armed, the cores keep running, and the URAM ring runs CIRCULAR instead of + # one-shot -- otherwise the display freezes after the first MiB and shows a + # still image instead of traffic. + # + # The register values are LITERALLY those from `start`; typing them out here + # would build a second place of truth for the same configuration. + # DDR4 is the default sink: b0 sink on, b2 CIRCULAR. That b2 is not a detail + # here but the condition for continuous operation -- linear, the 64 MiB + # window would be full after three seconds at ~22 MB/s and the display would + # stand still. Bit 2 is proven in the RTL: rocket2_soc_top.sv:327 wires + # circ_i (sink_ctrl_reg[2]). b3=0 lets the URAM ring run circular as well, so + # that both sink cards show traffic. + # Here too: `live` sets b0 and thereby releases a core standing in reset. On + # a used image the result would be a still image reporting LIVE_STALLED + # without naming the reason. + arb_gate + ddr_window_setup # sets base/size and switches off + + # clears on the way -- MUST come before + # arming, not after + dm $SINK_CTRL 32 0x5 # b0 DDR on, b2 circular, URAM circular + dm $CTRL 32 0x3 # b1 trace_clear (pulse) with cores running + dm $CTRL 32 0x1 + feat=0 + for ft in $(printf '%s' "${FEATURES:-}" | tr ',' ' '); do + case "$ft" in + ir) b=3 ;; bp) b=4 ;; jtc) b=5 ;; rh) b=8 ;; + rb) b=11 ;; wideicnt) b=12 ;; ibhs) b=13 ;; ri) b=14 ;; + *) echo "unknown FEATURE '$ft'" >&2; exit 2 ;; + esac + feat=$(( feat | (1 << b) )) + done + SRC0=${SRC0:-0}; SRC1=${SRC1:-1} + dm $ENC0_FEAT 32 $(printf '0x%08x' $(( 0x20000000 | (SRC0 << 16) | feat ))) + dm $ENC1_FEAT 32 $(printf '0x%08x' $(( 0x20000000 | (SRC1 << 16) | feat ))) + SYNCMAX=${SYNCMAX:-6} + # SENDCFG=once is mandatory at CT_XLEN=64: only from the config message does + # the decoder read CAPS bit 23 and switch to 64 bit. + base=$(( (0x01060063 & ~0x180) | (1 << 7) | 0x200 )) + base=$(( base & ~0x8000 )) + base=$(( (base & ~0x00F00000) | ((SYNCMAX & 0xF) << 20) )) + ctrl_on=$(( base | 0x4 )) + dm $ENC0 32 $(printf '0x%08x' $ctrl_on) + dm $ENC1 32 $(printf '0x%08x' $ctrl_on) + sleep 1 + echo "LIVE ENC_CTRL0 $(dm $ENC0) ENC_CTRL1 $(dm $ENC1) SYNCMAX=$SYNCMAX" >&2 + echo "LIVE FEAT0 $(dm $ENC0_FEAT) FEAT1 $(dm $ENC1_FEAT) (SrcID $SRC0/$SRC1)" >&2 + echo "LIVE SINK_CTRL $(dm $SINK_CTRL) (b0 DDR on, b2 circular, b3=0 URAM circular)" >&2 + echo "LIVE DDR base=$(dm $DDR_BASE) size=$(dm $DDR_SIZE) wptr=$(dm $DDR_WPTR)" >&2 + b1=$(( $(dm $TR_BYTES) )); sleep 2; b2=$(( $(dm $TR_BYTES) )) + echo "LIVE TRACE_BYTES $b1 -> $b2 (+$((b2 - b1)) in 2 s)" >&2 + r0=$(( $(dm $RETIRES0) )); r1=$(( $(dm $RETIRES1) )) + sleep 1 + r0b=$(( $(dm $RETIRES0) )); r1b=$(( $(dm $RETIRES1) )) + echo "LIVE RETIRES hart0 +$((r0b - r0)) hart1 +$((r1b - r1))" >&2 + echo "LIVE STATUS $(dm $STATUS) FUNNEL_CTRL $(dm $FUNNEL_CTRL) CON_BYTES $(dm $CON_BYTES)" >&2 + # The evidence the display needs: is anything really flowing, and are BOTH + # harts retiring? A still image would otherwise be indistinguishable from a + # hanging core. + # The DEFAULT SINK belongs in the gate. Without it, "DDR4 by default" would + # be exactly the failure class that costs the most time: the setup loses data + # without saying so. The comparison is on CHANGED, not on grown -- at 64 MiB + # and ~22 MB/s the ring wraps in ~3 s. + w1=$(dm $DDR_WPTR); sleep 1; w2=$(dm $DDR_WPTR) + ddr_moves=0; [ "$w1" != "$w2" ] && ddr_moves=1 + echo "LIVE DDR_WPTR $w1 -> $w2 (moved=$ddr_moves)" >&2 + if [ "$((b2 - b1))" -gt 0 ] && [ "$((r0b - r0))" -gt 0 ] && [ "$((r1b - r1))" -gt 0 ] \ + && [ "$ddr_moves" -eq 1 ]; then + echo "LIVE_OK -- stream running, both harts retiring, DDR4 writing" >&2 + else + echo "LIVE_STALLED -- bytes+$((b2 - b1)) hart0+$((r0b - r0)) hart1+$((r1b - r1)) ddr=$ddr_moves" >&2 + fi + echo "LIVE_DONE" >&2 + ;; +window) + # ANOTHER trace window while the cores KEEP RUNNING (CTRL b0 stays + # untouched). Needed for the case `start` cannot deliver: + # + # `start` records from reset. In that phase hart 1 sits in the HSM wait + # loop of OpenSBI executing `wfi` -- so it retires almost nothing. A window + # meant to show the separation on TWO working harts has to lie AFTER the + # SMP boot, and by then the cores are already running. + # + # Same order as in `start`: empty the sink first (stale bytes!), then arm. + if [ "$SINK" = "ddr" ]; then + ddr_window_setup + dm $SINK_CTRL 32 0x1 + prev=-1; i=0 + while [ $i -lt 20 ]; do + sleep 0.2; cur=$(( $(dm $DDR_WPTR) )) + [ "$cur" = "$prev" ] && break + prev=$cur; i=$((i+1)) + done + dm $SINK_CTRL 32 0x0 + echo "DRAIN $prev B after $i rounds" >&2 + dm $SINK_CTRL 32 0x2 + # Second place of the same trap -- see the detailed reasoning in `start`. + # The residual surge only runs AFTER the clear; without this second + # drain-and-clear every window carries a broken message at its start, and + # the decoder aborts the whole run on it. + dm $SINK_CTRL 32 0x1 + prev2=-1; j=0 + while [ $j -lt 20 ]; do + sleep 0.2; cur=$(( $(dm $DDR_WPTR) )) + [ "$cur" = "$prev2" ] && break + prev2=$cur; j=$((j+1)) + done + dm $SINK_CTRL 32 0x0 + echo "RECLEAR $prev2 B after $j rounds" >&2 + dm $SINK_CTRL 32 0x2 + w0=$(dm $DDR_WPTR) + [ $(( w0 )) -eq 0 ] || { echo "M5_INVALID DDR_NOT_CLEARED ($w0)" >&2; exit 13; } + dm $SINK_CTRL 32 0x1 + else + # Clear ONLY the trace ring (b1). NOT 0x1E -- b0 has to stay set, otherwise + # the core drops into reset in the middle of operation. + dm $CTRL 32 0x3 + dm $CTRL 32 0x1 + dm $SINK_CTRL 32 0x8 + fi + feat=0 + for ft in $(printf '%s' "${FEATURES:-}" | tr ',' ' '); do + case "$ft" in + ir) b=3 ;; bp) b=4 ;; jtc) b=5 ;; rh) b=8 ;; + rb) b=11 ;; wideicnt) b=12 ;; ibhs) b=13 ;; ri) b=14 ;; + *) echo "unknown FEATURE '$ft'" >&2; exit 2 ;; + esac + feat=$(( feat | (1 << b) )) + done + SRC0=${SRC0:-0}; SRC1=${SRC1:-1} + dm $ENC0_FEAT 32 $(printf '0x%08x' $(( 0x20000000 | (SRC0 << 16) | feat ))) + dm $ENC1_FEAT 32 $(printf '0x%08x' $(( 0x20000000 | (SRC1 << 16) | feat ))) + SYNCMAX=${SYNCMAX:-6} + base=$(( (0x01060063 & ~0x180) | (1 << 7) | 0x200 )) + base=$(( base & ~0x8000 )) + base=$(( (base & ~0x00F00000) | ((SYNCMAX & 0xF) << 20) )) + r0a=$(( $(dm $RETIRES0) )); r1a=$(( $(dm $RETIRES1) )) + dm $ENC0 32 $(printf '0x%08x' $(( base | 0x4 ))) + dm $ENC1 32 $(printf '0x%08x' $(( base | 0x4 ))) + echo "ENC_CTRL0 $(dm $ENC0) ENC_CTRL1 $(dm $ENC1) FEAT0 $(dm $ENC0_FEAT) FEAT1 $(dm $ENC1_FEAT)" >&2 + t0=$(date +%s%N) + sleep ${RUNSEC:-0.2} + dm $ENC0 32 $(printf '0x%08x' $base) + dm $ENC1 32 $(printf '0x%08x' $base) + t1=$(date +%s%N) + sleep 0.2 + dm $ENC0 32 0x0 + dm $ENC1 32 0x0 + sleep 0.2 + [ "$SINK" = "ddr" ] && dm $SINK_CTRL 32 0x0 + r0b=$(( $(dm $RETIRES0) )); r1b=$(( $(dm $RETIRES1) )) + echo "M5_WINDOW $LABEL SYNCMAX=$SYNCMAX RUNSEC=${RUNSEC:-0.2} us=$(( (t1 - t0) / 1000 ))" >&2 + # Retires IN THE WINDOW, not since the start. Only this difference answers + # whether BOTH harts worked during THIS window. + echo "M5_WIN_RETIRES hart0=+$(( r0b - r0a )) hart1=+$(( r1b - r1a ))" >&2 + echo "TRACE_BEATS $(dm $TR_BEATS) TRACE_BYTES $(dm $TR_BYTES) STATUS $(dm $STATUS)" >&2 + echo "DDR wptr=$(dm $DDR_WPTR) stat=$(dm $SINK_STAT) drops=$(dm $DDR_DROPS)" >&2 + st=$(( $(dm $SINK_STAT) )) + [ $(( st & 0x1 )) -ne 0 ] && echo "M5_INVALID ddr_full -- shorten the window" >&2 + [ $(( st & 0x2 )) -ne 0 ] && echo "M5_INVALID ddr_axi_err" >&2 + [ $(( $(dm $DDR_DROPS) )) -ne 0 ] && echo "M5_INVALID DDR_DROPS" >&2 + echo "WINDOW_DONE" >&2 + ;; +load) + # Keep both harts busy. Without load the second hart idles (wfi) and retires + # nothing -- a window on that would show "hart 1 is not running" although it + # simply has nothing to do. + before=$(dm $CON_BYTES); before=$((before)) + dm $CON_RPTR 32 $(printf '0x%08x' $before) + printf '%s\n' "${LOADCMD0:-while true; do :; done &}" \ + "${LOADCMD1:-while true; do :; done &}" \ + "nproc" "cat /proc/interrupts" | + while IFS= read -r c; do + type_line "$c" + sleep 2 + done + sleep 2 + now=$(dm $CON_BYTES); now=$((now)) + echo "CON_AFTER $now (+$((now - before))) DROPS $(dm $CON_DROPS)" >&2 + read_con "$now" + diag_line + echo "LOAD_DONE" >&2 + ;; +login) + before=$(dm $CON_BYTES); before=$((before)) + dm $CON_RPTR 32 $(printf '0x%08x' $before) + echo "CON_BEFORE $before RX_USED $(dm $CON_TX)" >&2 + type_line "${LOGIN:-root}" + sleep 4 + echo "RX_USED after the login input: $(dm $CON_TX) (0 = guest fetched everything)" >&2 + # One line per command -- NO "for c in $CMDS": word splitting would break + # "uname -a" into two commands. + printf '%s\n' "uname -a" "nproc" "cat /proc/cpuinfo" "cat /proc/interrupts" "echo M5_ENV_OK" | + while IFS= read -r c; do + type_line "$c" + sleep 4 + done + now=$(dm $CON_BYTES); now=$((now)) + echo "CON_AFTER $now (+$((now - before))) DROPS $(dm $CON_DROPS)" >&2 + read_con "$now" + ;; +type) + before=$(dm $CON_BYTES); before=$((before)) + dm $CON_RPTR 32 $(printf '0x%08x' $before) + type_line "$CMD" + sleep ${WAIT:-4} + now=$(dm $CON_BYTES); now=$((now)) + echo "CON_AFTER $now (+$((now - before))) DROPS $(dm $CON_DROPS)" >&2 + read_con "$now" + ;; +con) + n=$(dm $CON_BYTES); n=$((n)) + echo "CON_BYTES $n DROPS $(dm $CON_DROPS)" >&2 + read_con "$n" + ;; +trace) + if [ "$SINK" = "ddr" ]; then + n=$(dm $DDR_WPTR); n=$((n)) + sz=$(dm $DDR_SIZE); sz=$((sz)) + [ "$n" -gt "$sz" ] && n=$sz + src=$(dm $DDR_BASE) + else + n=$(dm $TR_BYTES); n=$((n)) + [ "$n" -gt 1048576 ] && n=1048576 + src=$TR_RING + fi + # Cap against an accidentally huge read. If it takes effect, that is SAID -- + # a silently truncated stream would have fewer bytes AND fewer instructions, + # and every number computed from it would still look plausible. + MAXB=${MAXB:-4194304} + cap=0 + if [ "$n" -gt "$MAXB" ]; then n=$MAXB; cap=1; fi + echo "TRACE_BYTES $n (beats=$(dm $TR_BEATS) status=$(dm $STATUS) sinkstat=$(dm $SINK_STAT) capped=$cap)" >&2 + [ "$n" -gt 0 ] && python3 /tmp/phys_io.py read $src $(( (n + 3) / 4 * 4 )) -o /tmp/r2_trace_$LABEL.bin + echo "TRACEFILE $(ls -l /tmp/r2_trace_$LABEL.bin 2>/dev/null | awk '{print $5}')" >&2 + ;; +*) + echo "unknown PHASE=$PHASE" >&2; exit 2 ;; +esac diff --git a/examples/dashboard/boot/rocket_linux64_run.sh b/examples/dashboard/boot/rocket_linux64_run.sh new file mode 100644 index 0000000..0c7df26 --- /dev/null +++ b/examples/dashboard/boot/rocket_linux64_run.sh @@ -0,0 +1,455 @@ +# SPDX-FileCopyrightText: 2026 Accemic Technologies GmbH +# SPDX-License-Identifier: ISC +# rocket_linux64_run.sh -- board sequence of the Rocket RV64 Linux +# demonstrator (package R5b). Runs ON THE BOARD. +# +# sudo PHASE=prep bash rocket_linux64_run.sh # clock, AFIFM, rings, payload + hash +# sudo PHASE=diag bash rocket_linux64_run.sh # sign of life (2 reads, 2 s apart) +# sudo PHASE=start RUNSEC=3 bash rocket_linux64_run.sh +# sudo PHASE=live bash rocket_linux64_run.sh # continuous mode for the dashboard +# sudo PHASE=con bash rocket_linux64_run.sh # console ring -> /tmp/rocket64_con.bin +# sudo PHASE=login bash rocket_linux64_run.sh # interactive, over the RX path +# sudo PHASE=type CMD='...' bash rocket_linux64_run.sh +# sudo PHASE=trace bash rocket_linux64_run.sh # trace -> /tmp/rocket64_trace.bin +# +# ENCODER CONFIGURATION of the start/live phases (package W1): +# SENDCFG=once|onsync config message TCODE 58 (default: once) +# SYNCMAX=<0-15> trTeControl.InstSyncMax[23:20], sync every +# 2^(x+4) instructions (default 6 = every 1024, +# the RDL reset value) +# FEATURES=jtc,bp,ir,rh,wideicnt,rb,ibhs,ri compression suite (default: none) +# SINK=uram|ddr destination of the stream (default uram) +# +# The config message is MANDATORY on the 64-bit encoder, not optional: the +# decoder reads CAPS bit 23 only from there and sets its address width to 64. +# Without it, it folds the JTC index at bit 25 instead of 63 and aborts +# (R2.1c legs L3/L5). SENDCFG=none is therefore refused. +# +# Modelled on cva6_linux64_run.sh (package R5a, proven on the board) and +# sharing its phase interface with rocket2_linux_run.sh (package M5), so that +# the dashboard server can call every recipe the same way (boot.json). THREE +# differences, all of them from the Rocket topology (packages L2/L4/R4a): +# +# 1. THE LOAD TARGET IS THE PS ADDRESS, NOT THE GUEST ADDRESS. The Rocket bus +# decodes memory exclusively from 0x8000_0000 (finding D-L2-1, three fixed +# places in the generated netlist); on ZynqMP there is no PS DDR there. The +# window guard rocket_mem_window in the PL maps 0x8000_0000 (guest) onto +# 0x6400_0000 (PS). The payload is therefore written to 0x6400_0000 and the +# core sees the same content at 0x8000_0000. The payload is linked against +# 0x8000_0000 (FW_TEXT_START), which is consistent. +# 2. The window guard is readable over devmem (WIN_ERR_CNT/LO/HI, STATUS +# b2/b3). A stray access is rejected with DECERR AND recorded -- which makes +# "the guard has tripped" distinguishable from "the core hangs" without +# changing the bitstream. +# 3. Observation channel: PC_LO/PC_HI/RETIRES + STATUS b[10:8]/b[14:12]. Two +# reads two seconds apart answer the first question of any bring-up +# diagnosis (is the core making progress?) -- PHASE=diag. +# +# WHY phys_io.py AND NOT `dd of=/dev/mem` (R5a finding, unchanged): the window +# is `no-map` reserved; the read()/write() path of /dev/mem answers "Bad +# address" there, only mmap works. And the slice copy (`readbulk`) faults on +# THIS window with "Bus error" -- the clearance in the header of phys_io.py +# applies to the DDR SINK buffer. Hence the ctypes word loop (`write`/`read`) +# everywhere. +set -e +dm() { busybox devmem "$@"; } + +APP=${APP:-rocket_x64_ctrace_kv260} +PAYLOAD=${PAYLOAD:-/tmp/fw_payload_rocket.bin} +GUEST=0x64000000 # PS view; the Rocket sees this as 0x8000_0000 +PHASE=${PHASE:-prep} +SINK=${SINK:-uram} + +CTRL=0xA0000000 +STATUS=0xA0000004 +TR_BEATS=0xA0000008 +TR_BYTES=0xA000000C +CON_BYTES=0xA0000014 +CON_DROPS=0xA0000018 +SINK_CTRL=0xA000001C +DDR_BASE=0xA0000020 +DDR_SIZE=0xA0000024 +DDR_WPTR=0xA0000028 +SINK_STAT=0xA000002C +DDR_DROPS=0xA0000030 +CON_TX=0xA0000034 +CON_RPTR=0xA0000038 +WIN_ERR_CNT=0xA000003C +WIN_ERR_LO=0xA0000040 +WIN_ERR_HI=0xA0000044 +PC_LO=0xA000004C +PC_HI=0xA0000050 +RETIRES=0xA0000054 +ENC=0xA0010000 +ENC_FEAT=0xA0010008 +TR_RING=0xA0200000 +CON_RING=0xA0300000 + +CONFILE=/tmp/rocket64_con.bin +TRFILE=/tmp/rocket64_trace.bin + +# The aperture is touched ONLY if EXACTLY our app is in the active slot. +# Otherwise the AXI interconnect hangs and the board is dead (2026-07-27/28, +# three frozen boards). fpga_manager "operating" is NOT sufficient as a +# criterion. +if ! xmutil listapps 2>/dev/null | awk -v a="$APP" '$1==a && $NF!="-1" {f=1} END{exit !f}'; then + echo "APP_NOT_ACTIVE ($APP) -- aperture NOT touched" >&2 + xmutil listapps >&2 || true + exit 8 +fi + +diag_line() { + echo " STATUS=$(dm $STATUS) RETIRES=$(dm $RETIRES) PC=$(dm $PC_HI):$(dm $PC_LO)" \ + "WIN_ERR=$(dm $WIN_ERR_CNT)@$(dm $WIN_ERR_HI):$(dm $WIN_ERR_LO)" \ + "CON=$(dm $CON_BYTES)/$(dm $CON_DROPS) TR=$(dm $TR_BYTES)" >&2 +} + +# Type one line into the guest console (RX path, b8 = commit). +type_line() { + s="$1"; i=0 + while [ $i -lt ${#s} ]; do + c=$(printf '%s' "$s" | cut -c$((i+1))) + o=$(printf '%d' "'$c") + dm $CON_TX 32 $(printf '0x%08x' $((0x100 | o))) + i=$((i+1)) + done + dm $CON_TX 32 0x10A # newline +} + +# Read the console ring. CAPPED: CON_BYTES is MONOTONIC (the write position), +# the ring holds only 65,536 bytes; an uncapped read would run past the window. +read_con() { + n=$1 + [ "$n" -gt 65536 ] && n=65536 + [ "$n" -gt 0 ] && python3 /tmp/phys_io.py read $CON_RING $(( (n + 3) / 4 * 4 )) -o $CONFILE + echo "CONFILE $(ls -l $CONFILE 2>/dev/null | awk '{print $5}') (ring position $1)" >&2 +} + +# The DDR window is READ and CHECKED, never resized here -- same reasoning as +# in cva6_linux64_run.sh: `reserved-memory` is a BOOT-TIME reservation, so the +# live devicetree is asked what THIS boot actually reserved (writing outside it +# would corrupt the host kernel's RAM), and ct_soc_ddr_sink must not have its +# size shrunk while running (finding B-C1-1). Base and size stay at their RTL +# reset (0x6000_0000 + 64 MiB, +# examples/kv260/rocket_linux/rtl/rocket_soc_top.sv:422). +ddr_check_window() { + b=$(( $(dm $DDR_BASE) )); s=$(( $(dm $DDR_SIZE) )) + set -- $(python3 - <<'PY' +import glob, struct +f = sorted(glob.glob('/sys/firmware/devicetree/base/reserved-memory/ctrace-pl-ddr@*/reg')) +if not f: + print("0 0") +else: + a, sz = struct.unpack('>QQ', open(f[0], 'rb').read()[:16]) + print(a, sz) +PY +) + res_b=$1; res_s=$2 + printf 'RESMEM 0x%08X + 0x%08X SINK 0x%08X + 0x%08X\n' \ + "$res_b" "$res_s" "$b" "$s" >&2 + if [ "$res_s" -gt 0 ] && [ "$b" -ge "$res_b" ] \ + && [ $(( b + s )) -le $(( res_b + res_s )) ]; then + printf 'DDR_WINDOW 0x%08X + %d MiB (covered by the reservation)\n' \ + "$b" $(( s / 1048576 )) >&2 + else + printf 'DDR_WINDOW_UNRESERVED -- 0x%08X + 0x%08X is NOT no-map reserved.\n' \ + "$b" "$s" >&2 + echo " Writing there would corrupt the host kernel's own RAM. The" >&2 + echo " reservation needs a REBOOT with" >&2 + echo " examples/kv260/common/board/ctrace_resmem.dtso installed." >&2 + echo " Use SINK=uram until then." >&2 + exit 15 + fi +} + +# Encoder control word, assembled FIELD BY FIELD instead of from a hex +# constant. The constant in the archived board script carried InstSyncMax = 0 +# (full sync every 16 instructions) without saying so -- the value that floods +# the ring with ResourceFull+ProgTraceSync pairs and broke decode at the first +# jalr in fw_platform_init on every bitstream tested (2026-08-17). Two wrong +# fields inside one hex literal mask each other; named fields do not. +# +# trTeControl: b0 Active, b1 Enable, b2 InstTracing, [6:4] InstMode, +# [8:7] SendConfig, b9 Context, b15 InhibitSrc, [19:16] InstSyncMode, +# [23:20] InstSyncMax, [26:24] Format. +enc_words() { + SENDCFG=${SENDCFG:-once} + SYNCMAX=${SYNCMAX:-6} + case "$SENDCFG" in + once) cfg=1 ;; + onsync) cfg=2 ;; + none) + echo "SENDCFG_REQUIRED: this app carries the 64-bit encoder -- without the" >&2 + echo " config message (SENDCFG=once) the stream is not decodable." >&2 + exit 10 ;; + *) echo "unknown SENDCFG=$SENDCFG (once|onsync)" >&2; exit 2 ;; + esac + base=$(( (0x01060063 & ~0x180) | (cfg << 7) )) + base=$(( (base & ~0x00F00000) | ((SYNCMAX & 0xF) << 20) )) + ctrl_on=$(( base | 0x4 )) # b2 InstTracing +} + +# Feature register: SrcBits [31:28], SrcID [27:16], compression suite [15:0]. +# Written IN FULL rather than read-modify-written, so that the configuration +# does not depend on what a previous run left behind. With FEATURES="" the +# result is the same word the archived script wrote (0x2002_0000). +# +# trTeProtocolSel is deliberately NOT written: the R4a bitstream is dual +# (EN_ETRACE=1) but its reset is 0 = N-Trace, and the W1 bitstream (CT_XLEN=64) +# is N-only, where the register does not exist at all. +enc_feat() { + SRC=${SRC:-2} + feat=0 + for ft in $(printf '%s' "${FEATURES:-}" | tr ',' ' '); do + case "$ft" in + ir) b=3 ;; + bp) b=4 ;; + jtc) b=5 ;; + rh) b=8 ;; + rb) b=11 ;; + wideicnt) b=12 ;; + ibhs) b=13 ;; + ri) b=14 ;; + *) echo "unknown FEATURE '$ft' (ir bp jtc rh rb wideicnt ibhs ri)" >&2; exit 2 ;; + esac + feat=$(( feat | (1 << b) )) + done + dm $ENC_FEAT 32 $(printf '0x%08x' $(( 0x20000000 | (SRC << 16) | feat ))) + echo "FEAT $(dm $ENC_FEAT) (SrcID $SRC, FEATURES='${FEATURES:-none}')" >&2 +} + +case "$PHASE" in +prep) + # --- set pl_clk0 deliberately, do not just find it ------------------------ + # The PS controls the PL clock through PL0_REF_CTRL (CRL_APB). An xmutil + # overlay carrying only `firmware-name` does NOT touch it -- a freshly loaded + # design runs at whatever the boot firmware left behind (found on this board: + # 100 MHz, and 150 MHz on 2026-08-19). + # + # CHECK ONLY, never set (B-W1-1): kv260_plclk.sh refuses any change while an + # app occupies the active slot -- always the case here, otherwise the aperture + # clamp above would not have let this script get this far. The change itself + # belongs BETWEEN unloadapp and loadapp; the dashboard server does it there + # (server.py load_app(), driven by plclk.json). + PL_MHZ=${PL_MHZ:-75} + if [ "$PL_MHZ" != "skip" ]; then + _cur=$(dm 0xFF5E00C0); _v=$((_cur)) + _d0=$(( (_v >> 8) & 0x3F )); _d1=$(( (_v >> 16) & 0x3F )) + _hz=0 + [ "$_d0" -gt 0 ] && [ "$_d1" -gt 0 ] && _hz=$(( 1500000000 / (_d0 * _d1) )) + # PL_MHZ is a LABEL, not an exact frequency: divider 22 gives 68181818 Hz, + # NOT 68000000. The target hertz are formed exactly as in kv260_plclk.sh, + # otherwise the check fails on a rounding instead of on an error. + case "$PL_MHZ" in + 68) _want=$(( 1500000000 / 22 )) ;; + 75) _want=$(( 1500000000 / 20 )) ;; + 100) _want=$(( 1500000000 / 15 )) ;; + *) _want=$(( PL_MHZ * 1000000 )) ;; + esac + if [ "$_hz" = "$_want" ]; then + echo "PLCLK OK: pl_clk0 = $_hz Hz (PL0_REF_CTRL=$_cur)" >&2 + else + echo "PLCLK_WRONG: pl_clk0 = $_hz Hz, wanted $_want Hz -- the change" >&2 + echo " belongs BETWEEN unloadapp and loadapp (see plclk.json)." >&2 + exit 9 + fi + fi + # PS AFIFM port widths (reset = 128 bit, needed once per boot): + # HP0/AFIFM2 -> 32 bit (trace sink), HP1/AFIFM3 -> 64 bit (guest memory). +# FABRIC_WIDTH is bits [1:0] of RDCTRL/WRCTRL, and the reset value of those +# registers is 0x3B0 -- several bits above [1:0] are marked reserved but are +# RW and set out of reset (UG1087). Writing the whole register with the width +# code therefore clears them. Read-modify-write instead; pointed out +# 2026-08-21 while the AMP core-1 defect was being tracked down, and +# corrected everywhere the same day. +afifm_width() { # $1 = AFIFM base, $2 = FABRIC_WIDTH code (0=128, 1=64, 2=32) + for _o in 0x0 0x14; do + _a=$(printf '0x%08X' $(( $1 + $_o ))) + _v=$(( $(dm $_a) )) + dm $_a 32 $(printf '0x%08X' $(( (_v & ~0x3) | $2 ))) + done +} + # Without this the first fetch of the core hangs (finding C6). + afifm_width 0xFD380000 2 + afifm_width 0xFD390000 1 + echo "AFIFM HP0=$(dm 0xFD380000)/$(dm 0xFD380014) HP1=$(dm 0xFD390000)/$(dm 0xFD390014)" >&2 + # Core in reset; clear the trace ring, the console ring, the guard diagnosis + # and the observation sticky bits (b1|b2|b3|b4 = 0x1E, level triggered). + dm $CTRL 32 0x1E + dm $CTRL 32 0x0 + dm $CON_RPTR 32 0x0 + case "$SINK" in + uram) + # URAM one-shot (SINK_CTRL b3): the ring holds the FIRST 1 MiB of the boot. + dm $SINK_CTRL 32 0x8 ;; + ddr) + ddr_check_window + # DDR sink linear (b0 enable, b2=0 not circular) + clear pulse b1, plus the + # URAM one-shot (b3): the two sinks are independent and run in parallel, so + # one run yields both windows. b1 does not latch (write mask 0xFFFF_FFDD), + # the register reads back 0x9. + dm $SINK_CTRL 32 0x0B + echo "SINK=ddr SINK_CTRL=$(dm $SINK_CTRL) DDR_BASE=$(dm $DDR_BASE) DDR_SIZE=$(dm $DDR_SIZE) WPTR=$(dm $DDR_WPTR)" >&2 ;; + *) echo "unknown SINK=$SINK (uram|ddr)" >&2; exit 2 ;; + esac + sz=$(stat -c%s "$PAYLOAD") + src_md5=$(md5sum "$PAYLOAD" | cut -d' ' -f1) + echo "PAYLOAD $PAYLOAD $sz B md5=$src_md5" >&2 + t0=$(date +%s) + python3 /tmp/phys_io.py write $GUEST "$PAYLOAD" + echo "WRITE_SECONDS $(( $(date +%s) - t0 ))" >&2 + # LOAD PROOF = the md5 READ BACK OUT OF THE WINDOW. A byte counter or a word + # sample is not one (either could come from a previous run). + python3 /tmp/phys_io.py read $GUEST "$sz" -o /tmp/rocket64_rb.bin + tgt_md5=$(md5sum /tmp/rocket64_rb.bin | cut -d' ' -f1) + rm -f /tmp/rocket64_rb.bin + echo "TARGET_MD5 $tgt_md5" >&2 + # ...and the comparison is actually DRAWN (the same correction + # rocket2_linux_run.sh carries since 2026-08-10): two sums printed underneath + # each other while the script continues regardless would be an eye check. + if [ "$tgt_md5" != "$src_md5" ]; then + echo "PREP_MD5_MISMATCH -- window $tgt_md5 != file $src_md5" >&2 + exit 11 + fi + echo "PREP_DONE" >&2 + ;; +diag) + echo "DIAG t0:" >&2; diag_line + sleep 2 + echo "DIAG t1 (+2 s):" >&2; diag_line + ;; +start) + enc_feat + enc_words + dm $ENC 32 $(printf '0x%08x' $ctrl_on) + echo "ENC_CTRL $(dm $ENC) (SENDCFG=$SENDCFG SYNCMAX=$SYNCMAX)" >&2 + dm $CTRL 32 0x1 # core released -- OpenSBI runs from here + echo "CORE_STARTED $(dm $CTRL)" >&2 + sleep ${RUNSEC:-3} + dm $ENC 32 $(printf '0x%08x' $base) # tracing off, core KEEPS RUNNING + sleep 0.3 + # Encoder fully off -- that closes the message in flight instead of letting + # it end in the middle of a field. + dm $ENC 32 0x0 + sleep 0.3 + [ "$SINK" = "ddr" ] && dm $SINK_CTRL 32 0x0 + echo "TRACE_BEATS $(dm $TR_BEATS) TRACE_BYTES $(dm $TR_BYTES)" >&2 + [ "$SINK" = "ddr" ] && echo "DDR wptr=$(dm $DDR_WPTR) stat=$(dm $SINK_STAT) drops=$(dm $DDR_DROPS)" >&2 + echo "CON_BYTES $(dm $CON_BYTES) CON_DROPS $(dm $CON_DROPS)" >&2 + echo "STATUS $(dm $STATUS)" >&2 + echo "WIN_ERR_CNT $(dm $WIN_ERR_CNT) @ $(dm $WIN_ERR_HI):$(dm $WIN_ERR_LO)" >&2 + echo "RETIRES $(dm $RETIRES) PC $(dm $PC_HI):$(dm $PC_LO)" >&2 + echo "START_DONE" >&2 + ;; +live) + # CONTINUOUS MODE for the dashboard view. Difference to `start`: NOTHING is + # switched off again. The encoder stays armed, the core keeps running, and the + # ring runs CIRCULAR instead of one-shot -- otherwise the display stands still + # after the first MiB and shows a freeze frame instead of traffic. + # + # b2 is the circular bit of ct_soc_ddr_sink (circ_i, wired in + # examples/kv260/rocket_linux/rtl/rocket_soc_top.sv:335); b3 = 0 lets the URAM + # ring run circular as well, so both sink cards show traffic. + if [ "$SINK" = "ddr" ]; then + ddr_check_window + dm $SINK_CTRL 32 0x5 # b0 DDR on, b2 circular, b3=0 URAM circular + else + dm $SINK_CTRL 32 0x0 # URAM circular (one-shot off) + fi + # ONLY the trace ring is cleared (b1). NOT 0x1E -- b0 must stay set, otherwise + # a running core would fall back into reset mid-operation. + dm $CTRL 32 0x3 + dm $CTRL 32 0x1 + enc_feat + enc_words + dm $ENC 32 $(printf '0x%08x' $ctrl_on) + sleep 1 + echo "LIVE ENC_CTRL $(dm $ENC) SENDCFG=$SENDCFG SYNCMAX=$SYNCMAX" >&2 + echo "LIVE SINK_CTRL $(dm $SINK_CTRL) SINK=$SINK" >&2 + [ "$SINK" = "ddr" ] && echo "LIVE DDR base=$(dm $DDR_BASE) size=$(dm $DDR_SIZE) wptr=$(dm $DDR_WPTR)" >&2 + b1=$(( $(dm $TR_BYTES) )); sleep 2; b2=$(( $(dm $TR_BYTES) )) + echo "LIVE TRACE_BYTES $b1 -> $b2 (+$((b2 - b1)) in 2 s)" >&2 + r0=$(( $(dm $RETIRES) )); sleep 1; r1=$(( $(dm $RETIRES) )) + echo "LIVE RETIRES $r0 (+$((r1 - r0)) in 1 s) PC $(dm $PC_HI):$(dm $PC_LO)" >&2 + echo "LIVE STATUS $(dm $STATUS) WIN_ERR_CNT $(dm $WIN_ERR_CNT) CON_BYTES $(dm $CON_BYTES)" >&2 + # The proof the display needs: is anything flowing, and is the core making + # progress? A freeze frame would otherwise be indistinguishable from a hung + # core. The RETIRES check is a DIFFERENCE, not an absolute value: the counter + # is cumulative and no reset clears it, so "greater than zero" would pass + # forever after the first successful boot (the blind check corrected in + # rocket2_linux_run.sh on 2026-08-10). + if [ "$((b2 - b1))" -gt 0 ] && [ "$((r1 - r0))" -gt 0 ]; then + echo "LIVE_OK -- stream is running and the core is retiring" >&2 + else + echo "LIVE_STALLED -- bytes +$((b2 - b1)) retires +$((r1 - r0))" >&2 + fi + echo "LIVE_DONE" >&2 + ;; +login) + # Interactive guest console over the RX path (CON_TX 0x34: b8 = commit, + # b7:0 = character). CON_BYTES is MONOTONIC (= the write position); CON_RPTR + # is only tracked so that con_used does not reach the drop threshold. + before=$(dm $CON_BYTES); before=$((before)) + dm $CON_RPTR 32 $(printf '0x%08x' $before) + echo "CON_BEFORE $before RX_USED $(dm $CON_TX)" >&2 + type_line "${LOGIN:-root}" + sleep 4 + echo "RX_USED after the login input: $(dm $CON_TX) (0 = the guest took it all)" >&2 + # One line per command -- NOT "for c in $CMDS": word splitting would tear + # "uname -a" into two commands. + printf '%s\n' "uname -a" "cat /proc/cpuinfo" "free -m" "echo R5B_ENV_OK" | + while IFS= read -r c; do + type_line "$c" + sleep 4 + done + now=$(dm $CON_BYTES); now=$((now)) + echo "CON_AFTER $now (+$((now - before))) DROPS $(dm $CON_DROPS)" >&2 + read_con "$now" + ;; +type) + # Type a single command into the running guest shell. Needed for the POSITIVE + # PROBE of the window guard: WIN_ERR_CNT=0 is only evidence if the register + # CAN become non-zero (audit the auditor). + # sudo PHASE=type CMD='busybox devmem 0x90000000' bash rocket_linux64_run.sh + before=$(dm $CON_BYTES); before=$((before)) + dm $CON_RPTR 32 $(printf '0x%08x' $before) + echo "BEFORE:" >&2; diag_line + type_line "$CMD" + sleep ${WAIT:-4} + echo "AFTER :" >&2; diag_line + now=$(dm $CON_BYTES); now=$((now)) + echo "CON_AFTER $now (+$((now - before))) DROPS $(dm $CON_DROPS)" >&2 + read_con "$now" + ;; +con) + n=$(dm $CON_BYTES); n=$((n)) + echo "CON_BYTES $n DROPS $(dm $CON_DROPS)" >&2 + read_con "$n" + ;; +trace) + if [ "$SINK" = "ddr" ]; then + # DDR_WPTR (0x28) = bytes written since the clear pulse; SINK_STAT (0x2C) + # carries b0 ddr_full / b1 ddr_axi_err / b2 ddr_wrapped. + n=$(( $(dm $DDR_WPTR) )); sz=$(( $(dm $DDR_SIZE) )) + [ "$n" -gt "$sz" ] && n=$sz + src=$(dm $DDR_BASE) + echo "DDR_WPTR $(dm $DDR_WPTR) SINK_STAT $(dm $SINK_STAT) DDR_DROPS $(dm $DDR_DROPS)" >&2 + else + # The URAM ring is always readable (it runs along in both SINK modes). + n=$(( $(dm $TR_BYTES) )) + [ "$n" -gt 1048576 ] && n=1048576 + src=$TR_RING + fi + # Cap against an accidentally huge read. If it bites, that is ANNOUNCED -- a + # silently truncated stream would have fewer bytes AND fewer instructions, + # and every number computed from it would still look plausible. + MAXB=${MAXB:-4194304} + cap=0 + if [ "$n" -gt "$MAXB" ]; then n=$MAXB; cap=1; fi + echo "TRACE_BYTES $n (beats=$(dm $TR_BEATS) status=$(dm $STATUS) capped=$cap)" >&2 + [ "$n" -gt 0 ] && python3 /tmp/phys_io.py read $src $(( (n + 3) / 4 * 4 )) -o $TRFILE + echo "TRACEFILE $(ls -l $TRFILE 2>/dev/null | awk '{print $5}')" >&2 + ;; +*) + echo "unknown PHASE=$PHASE" >&2; exit 2 ;; +esac diff --git a/examples/dashboard/check_replay_public.py b/examples/dashboard/check_replay_public.py new file mode 100644 index 0000000..9102c8c --- /dev/null +++ b/examples/dashboard/check_replay_public.py @@ -0,0 +1,436 @@ +#!/usr/bin/env python3 +# SPDX-FileCopyrightText: 2026 Accemic Technologies GmbH +# SPDX-License-Identifier: ISC +"""U12: marker scan for the PUBLIC replay bundle (R2 finding A-05). + +The bundle under `assets/ctte-demo/dashboard/` goes public with the CTTE +release. An external review found internals in it: commit ids +(`ctrace_mbv@660d5b94...`), internal source paths +(`vivado/kv260_app/duo_pib_pmod.xdc`), RDL line references +(`ct_cs_cpuif.rdl:1440-1493`), review markers ("AW-Befund 2026-07-29") and +per-file hashes of internal paths. + +This script is the EVIDENCE, not the claim: it reads a finished bundle +(directory or single file) and reports every hit with its file, location +(JSON path or line), pattern id and the text found. One hit is a FAIL +(exit 1) -- `record_web_replay.py --public` runs the scan itself and refuses +to emit the output if it is red. + + py check_replay_public.py + py check_replay_public.py --json report.json + +The patterns sit as a maintainable list in PATTERNS, each with a comment +saying WHY it is a marker and WHERE it actually occurred. The (few) +exemptions sit just as visibly in EXEMPTIONS and are ALWAYS printed with the +report -- a silent exemption would be worse than the finding. + +Delimiting false positives (U12 point 5): payload data contain masses of +legitimate hex strings (PC values, packet dumps, symbol addresses). The +commit pattern therefore only fires in context -- `repo@`, a keyword +(commit/sha/rev/build/git) immediately in front of it, or a JSON key whose +name announces a build/commit id. A bare hex string in the payload is not a +finding (test: test_replay_public.py). +""" +from __future__ import annotations + +import argparse +import fnmatch +import json +import re +import sys +from pathlib import Path + +# -------------------------------------------------------------------------- +# Patterns. Order = reporting order; one sentence of WHY per pattern. +# -------------------------------------------------------------------------- +PATTERNS: list[dict] = [ + { + "id": "repo_path", + # Paths into the work tree. A-05 named vivado/kv260_app/duo_pib_pmod.xdc; + # the bundle also carried docs/SPEC_*, rtl/*, third_party/*, tools/*. + "why": "path into the internal source tree", + "rx": re.compile( + r"(?@ -- the finding from A-05 + # 2. a keyword in front of it (commit/sha/rev/git/build) + # 3. a full 40-digit SHA-1 as a word of its own + # Deliberately NOT every "@": the Linux boot log carries + # device-tree nodes such as "mmode_resv1@64000000" and + # "interrupt-controller@c000000". Those are the payload of a + # recording, not commits (false positive, measured on the existing + # bundle; counter-check in test_replay_public.py). + "why": "commit/build id", + "rx": re.compile( + r"(?:(?:ctrace_mbv|C-Trace|CTTE|TraceEncoder|CEDARtools[A-Za-z.]*" + r"|nexrv-for-c-trace|[A-Za-z0-9_-]+_mvp)@[0-9a-f]{7,40}\b" + r"|(?:commit|sha1?|revision|rev|git|build)" + r"[\s:=#-]{1,3}[0-9a-f]{7,40}\b" + r"|(? hash": exactly the per-file hash table from A-05. +FILEISH = re.compile(r"^[A-Za-z0-9_.-]+\.[A-Za-z0-9]{1,6}$") + + +class Finding: + __slots__ = ("file", "where", "pid", "why", "text") + + def __init__(self, file: str, where: str, pid: str, why: str, text: str): + self.file, self.where, self.pid = file, where, pid + self.why, self.text = why, text + + def as_dict(self) -> dict: + return {"file": self.file, "where": self.where, "pattern": self.pid, + "why": self.why, "text": self.text} + + +def _exempt(file: str, where: str, pid: str): + for ex in EXEMPTIONS: + if (ex["id"] == pid and fnmatch.fnmatch(file, ex["file"]) + and fnmatch.fnmatch(where, ex["where"])): + return ex + return None + + +def string_findings(s: str, file: str, where: str, used: dict | None = None): + """All patterns against ONE string -> list of findings (exemptions removed). + + The public export uses exactly this function too, so that sanitising and + checking can never drift apart. + """ + out: list[Finding] = [] + for pat in PATTERNS: + for m in pat["rx"].finditer(s): + ex = _exempt(file, where, pat["id"]) + if ex is not None: + if used is not None: + used[id(ex)] = used.get(id(ex), 0) + 1 + continue + start = max(0, m.start() - 30) + ctx = s[start:m.end() + 30].replace("\n", " ") + out.append(Finding(file, where, pat["id"], pat["why"], + "%s [...%s...]" % (m.group(0)[:80], ctx[:110]))) + return out + + +def scan_text(s: str, file: str, where: str, findings, used): + """All patterns against one string; collect hits or book an exemption.""" + findings.extend(string_findings(s, file, where, used)) + + +def scan_json_value(o, file: str, where: str, findings, used): + if isinstance(o, dict): + # per-File-Hash-Tabelle (A-05: provenance.files) + if o and all(isinstance(k, str) and FILEISH.match(k) for k in o) \ + and all(isinstance(v, str) and HEX_ONLY.match(v) for v in o.values()): + findings.append(Finding(file, where, "file_hash_map", + "hash table per internal file", + "%d Eintraege: %s" % (len(o), ", ".join(list(o)[:4])))) + for k, v in o.items(): + sub = "%s.%s" % (where, k) + scan_text(str(k), file, sub, findings, used) + if isinstance(v, str) and HASHY_KEYS.match(str(k)) and HEX_ONLY.match(v): + findings.append(Finding(file, sub, "git_commit", + "Commit-/Build-Kennung (Schluesselname)", + "%s = %s" % (k, v))) + scan_json_value(v, file, sub, findings, used) + elif isinstance(o, list): + for i, v in enumerate(o): + scan_json_value(v, file, "%s[%d]" % (where, i), findings, used) + elif isinstance(o, str): + scan_text(o, file, where, findings, used) + + +def scan_file(p: Path, root: Path, findings, used): + rel = p.name if p.parent == root else str(p.relative_to(root)).replace("\\", "/") + if p.suffix.lower() in SKIP_SUFFIXES: + return + if p.suffix.lower() in JSON_SUFFIXES: + try: + doc = json.loads(p.read_text(encoding="utf-8")) + except Exception as e: # noqa: BLE001 + findings.append(Finding(rel, "$", "unreadable", + "file not readable", str(e))) + return + scan_json_value(doc, rel, "$", findings, used) + return + if p.suffix.lower() not in TEXT_SUFFIXES: + return + text = p.read_text(encoding="utf-8", errors="replace") + for n, line in enumerate(text.split("\n"), 1): + scan_text(line, rel, "line %d" % n, findings, used) + + +def scan_bundle(target: Path): + """-> (findings, used_exemptions, gescannte Dateien)""" + findings: list[Finding] = [] + used: dict[int, int] = {} + files: list[Path] = [] + if target.is_dir(): + files = sorted(q for q in target.rglob("*") if q.is_file()) + root = target + else: + files = [target] + root = target.parent + for q in files: + scan_file(q, root, findings, used) + return findings, used, files + + +# -------------------------------------------------------------------------- +# Neutrality probe: hold the public bundle against the internal one. The +# replay must NOT change -- so the sanitising must not have touched numbers, +# list lengths or time series. Allowed are exclusively: removed strings (or +# string containers) and rewritten strings. If a number comes out different +# or a list gets shorter, the replay is no longer the same. +# -------------------------------------------------------------------------- +_MISSING = object() + + +def _stringy(o) -> bool: + """Strings/null only (also inside lists/dicts) -- so no payload.""" + if isinstance(o, str) or o is None: + return True + if isinstance(o, list): + return all(_stringy(x) for x in o) + if isinstance(o, dict): + return all(_stringy(v) for v in o.values()) + return False + + +def compare_payload(old, new, where="$", diffs=None): + if diffs is None: + diffs = {"removed": [], "added": [], "changed": [], + "numeric": [], "length": []} + if isinstance(old, dict) and isinstance(new, dict): + for k in old: + if k not in new: + diffs["removed"].append((where + "." + str(k), + "string" if _stringy(old[k]) else "DATEN")) + else: + compare_payload(old[k], new[k], where + "." + str(k), diffs) + for k in new: + if k not in old: + diffs["added"].append(where + "." + str(k)) + return diffs + if isinstance(old, list) and isinstance(new, list): + if len(old) != len(new): + diffs["length"].append((where, len(old), len(new))) + return diffs + for i, (a, b) in enumerate(zip(old, new)): + compare_payload(a, b, "%s[%d]" % (where, i), diffs) + return diffs + if old == new and type(old) is type(new): + return diffs + if isinstance(old, str) and isinstance(new, str): + diffs["changed"].append((where, old[:70], new[:70])) + else: + diffs["numeric"].append((where, repr(old)[:40], repr(new)[:40])) + return diffs + + +def neutrality(internal: Path, public: Path, maxlist=25) -> int: + old = json.loads((internal / "replay.json").read_text(encoding="utf-8")) + new = json.loads((public / "replay.json").read_text(encoding="utf-8")) + # provenance is deliberately rebuilt -- it is not payload. + old.pop("provenance", None) + new.pop("provenance", None) + d = compare_payload(old, new) + hard = [x for x in d["removed"] if x[1] == "DATEN"] + print("Neutralitaets-Probe intern=%s oeffentlich=%s" % (internal, public)) + print(" entfernte Strings/String-Behaelter : %d" % (len(d["removed"]) - len(hard))) + print(" entfernte NUTZDATEN : %d" % len(hard)) + print(" neue Schluessel : %d %s" + % (len(d["added"]), ", ".join(d["added"][:6]))) + print(" umgeschriebene Strings : %d" % len(d["changed"])) + print(" geaenderte Zahlen/Typen : %d" % len(d["numeric"])) + print(" geaenderte Listenlaengen : %d" % len(d["length"])) + for w, a, b in d["changed"][:maxlist]: + print(" ~ %s\n alt: %s\n neu: %s" % (w, a, b)) + if len(d["changed"]) > maxlist: + print(" ... %d more" % (len(d["changed"]) - maxlist)) + for w, t in hard[:maxlist]: + print(" - %s (%s)" % (w, t)) + for w, a, b in d["numeric"][:maxlist]: + print(" ! %s %s -> %s" % (w, a, b)) + for w, a, b in d["length"][:maxlist]: + print(" ! %s length %d -> %d" % (w, a, b)) + ok = not hard and not d["numeric"] and not d["length"] + print("\nPAYLOAD_NEUTRAL_%s no number, no list length, no payload " + "value changed" % ("PASS" if ok else "FAIL")) + return 0 if ok else 1 + + +def main() -> int: + ap = argparse.ArgumentParser(description=__doc__, + formatter_class=argparse.RawDescriptionHelpFormatter) + ap.add_argument("target", help="bundle directory or single file") + ap.add_argument("--json", help="additionally write the report as JSON") + ap.add_argument("--max", type=int, default=60, + help="print at most this many findings (default 60)") + ap.add_argument("--against", + help="internal bundle: additionally run the payload " + "neutrality probe") + args = ap.parse_args() + if args.against: + rc = neutrality(Path(args.against), Path(args.target)) + print() + if rc: + return rc + target = Path(args.target) + if not target.exists(): + print("PUBLIC_SCAN_ERROR does not exist: %s" % target) + return 2 + + findings, used, files = scan_bundle(target) + + print("Bundle : %s" % target) + print("files : %d (%s)" % (len(files), ", ".join(p.name for p in files[:8]))) + for ex in EXEMPTIONS: + n = used.get(id(ex), 0) + print("exemption: %-12s %-32s %s -> %d hit(s) allowed" + % (ex["id"], ex["where"], ex["file"], n)) + print(" reason: %s" % ex["why"]) + + by_pat: dict[str, int] = {} + for f in findings: + by_pat[f.pid] = by_pat.get(f.pid, 0) + 1 + + if args.json: + Path(args.json).write_text(json.dumps( + {"target": str(target), "files": [p.name for p in files], + "counts": by_pat, "findings": [f.as_dict() for f in findings]}, + indent=1, ensure_ascii=False), encoding="utf-8") + + if not findings: + print("\nPUBLIC_SCAN_PASS no internal markers (%d patterns checked)" + % len(PATTERNS)) + return 0 + + print("\nfinding classes:") + for pid, n in sorted(by_pat.items(), key=lambda kv: -kv[1]): + print(" %-14s %4d" % (pid, n)) + print("\nfindings (max %d):" % args.max) + for f in findings[:args.max]: + print(" %-12s %-11s %s" % (f.pid, f.file, f.where)) + print(" %s" % f.text) + if len(findings) > args.max: + print(" ... %d more" % (len(findings) - args.max)) + print("\nPUBLIC_SCAN_FAIL %d findings in %d classes" + % (len(findings), len(by_pat))) + return 1 + + +if __name__ == "__main__": + sys.exit(main()) diff --git a/examples/dashboard/demo/README.md b/examples/dashboard/demo/README.md new file mode 100644 index 0000000..5fc7c5d --- /dev/null +++ b/examples/dashboard/demo/README.md @@ -0,0 +1,134 @@ + +# The hardware-free demo dataset + +Every file here is a **recording**, not a construction. The dashboard replays +them when no board is attached, and `insight.py` decodes them with the same +CTTD build the board uses -- so the numbers a visitor sees in demo mode are +the numbers the hardware produced. + +## Where each dataset comes from + +Recorded 2026-08-19 on a Kria KV260, PL clock **68.181818 MHz** (the only +label at or below the 71.114 MHz sign-off constraint that every design in +this repository is routed against -- see `../plclk.json`). The guest images +are the OpenSBI+Linux payloads built from the RV64 Buildroot output; the +`.pcinfo` listings are generated from **those same images**, not from a +similar build. + +| Scenario | Trace | Listing | Console | Instructions decoded | Decode errors | +|---|---|---|---|---:|---:| +| `cva6_linux` | `demo_trace_cva6_linux.bin` | `cva6_linux.pcinfo` | `console_cva6_linux.txt` | 1,218,940 | 0 | +| `rocket2` | `demo_trace_rocket2.bin` | `rocket2.pcinfo` | `console_rocket2.txt` | 1,708,826 | 0 | +| `rocket64` | `demo_trace_rocket64.bin` | `rocket64.pcinfo` | `console_rocket64.txt` | 278,672 | 0 | +| `cva6_linux64` | `demo_trace_cva6_linux64.bin` | `cva6_linux64.pcinfo` | `console_cva6_linux64.txt` | 276,138 | 0 | +| `cva6_2_rv64` | `demo_trace_cva6_2_rv64.bin` | `cva6_linux64.pcinfo` | -- | 446,774 | 0 | +| `trio` | `demo_trace_trio.bin` | `mbv.pcinfo` + `tgc.pcinfo` | -- | 2,804,391 (MBV 1,602,399 + TGC5B 1,201,992) | 0 | +| `duo` | `demo_trace_duo.bin` | `mbv.pcinfo` + `tgc.pcinfo` | -- | 2,804,648 (MBV 1,602,656 + TGC5B 1,201,992) | 0 | + +File sizes and checksums (sha256, first 16 hex digits): + +| File | Bytes | sha256 | +|---|---:|---| +| `cva6_linux64.pcinfo` | 773,634 | `0e99e553e9952e8c...` | +| `demo_trace_cva6_2_rv64.bin` | 66,720 | `09cf0b4ff7b620fa...` | +| `demo_trace_cva6_linux64.bin` | 262,144 | `6cfd16a63e66a080...` | +| `demo_trace_rocket2.bin` | 262,144 | `b0e30c3edf778a05...` | +| `demo_trace_rocket64.bin` | 262,144 | `d239cc277b482a40...` | +| `rocket2.pcinfo` | 870,367 | `3727772eb187cacb...` | +| `rocket64.pcinfo` | 863,550 | `b274f504297f16af...` | + +## How to reproduce a dataset + +1. Build the guest image on a Linux build host -- `examples/kv260/cva6_linux64/sw/build_payload_rv64.sh` + for the CVA6 RV64 guest, `examples/kv260/rocket2/sw/build_payload_rocket2_rv64.sh` + for the two-hart Rocket, `examples/kv260/cva6_2/sw/build_payload_cva6_2.sh` + for the AMP pair. +2. Stage the payload on the board and run the board recipe under + `../boot/` with `PHASE=prep`, then `PHASE=start`, then `PHASE=trace` + and `PHASE=con`. The recipes verify the payload by reading it back and + comparing checksums; they refuse to start when `pl_clk0` is wrong. +3. Build the listing from the **same** `fw_payload.elf`: + `objdump -d --start-address= --stop-address=`, + then `cttd -conv -objd -pcinfo `. For the Rocket designs + prepend a disassembly of the boot ROM at `0x1_0000` -- the capture starts + there, not in OpenSBI. +4. Verify before committing: `cttd -deco -pcinfo -pcout /dev/null -stat` + must report **0 error messages**. + +## What these recordings do and do not show + +* **`rocket2`** is the boot from reset of the two-hart Rocket. The URAM ring + is a 1 MiB one-shot, and it fills during hart 0's pre-SMP phase -- so the + capture carries **SRC 0 only**. Hart 1 has not been released by the SMP + bring-up at that point. That is the ordering of an SMP boot, not a gap in + the funnel; the console capture reaches `smp: Brought up 1 node, 2 CPUs` + because the console ring keeps running after the trace ring is full. +* **`cva6_2_rv64`** shows something the console cannot: the AMP guest emits + **no console output at all**, and the trace still carries 446,774 decoded + instructions of core 0 -- `_try_lottery` through `generic_early_init` into + OpenSBI's device-tree scan, with 257,516 instructions in `fdt_offset_ptr` + alone. The core-0 PC register reads `sbi_hart_hang` afterwards, and core 1 + retires 14 instructions and stops. **The bring-up of the AMP guests is an + open item**; what the window shows is where execution was when the ring + filled, which is not the same as where it stopped. The dataset is included + because it is a real capture and because this is precisely the situation a + trace is for -- a target that dies silently. +* **`rocket64`** and **`cva6_linux64`** boot Linux; their consoles run from + the OpenSBI banner into the kernel's I/O scheduler registration. + +### Why `trio` and `duo` were re-recorded + +Their previous streams could not be split by source. The live path never +programmed the encoders' `SrcBits`/`SrcID` fields and never cleared +`InhibitSrc` -- and the RDL reset of `trTeControl` has that bit **set**, i.e. +SRC off. A multi-source capture taken from the dashboard therefore carried no +SRC field at all. It decoded cleanly -- 49,135 messages, zero errors -- and +attributed **zero** instructions to either target, because there was nothing +to attribute by. The demo bus had been faking the correct register values all +along, so the UI showed "SRC on" while the hardware had it off: the mock was +more correct than the machine. + +Fixed 2026-08-19 in `trace_on` (the same `Enable = 0` window the sync fields +are written in, because both are swwel-locked). The capture above is from +after that change: `FEAT0 = 0x20000000`, `FEAT1 = 0x20010000`, +`FEAT2 = 0x20020000`, `trTeControl` bit 15 clear -- the values the board +runners program. The previous `duo` recording (`demo_trace.bin`, kept as the +fallback stream) decodes 35,341 instructions; the new one 2,804,648. + +### The one dataset that predated this round + +`cva6_linux` was the only demo capture in the repository before 2026-08-19, +and it was the only one that did **not** decode cleanly: it stopped after +53,075 PCs with `ERROR EmitICNT with n=34`. Nothing flagged that, because the +only check in place asked whether the files exist. It was re-recorded with the +rest -- 1,218,940 instructions, zero errors -- and `../test_demo_decode.py` +now runs the decoder over every shipped capture on every CI run, so a capture +and its listing cannot drift apart unnoticed again. + +## Program images + +`trace_test.elf` and `hello_trace.hex` are the guest programs the bare-metal +scenarios stage into their cores' RAM windows (`preload` in +`../scenarios.json`). They live **here**, not in the example directories they +were built in, for one reason: the board rollout copies this directory and +nothing else. A `preload` path pointing outside it resolves into nothing on +the board, and the failure is silent -- the cores then run whatever the +fabric powered up with. Measured 2026-08-19: `hello_trace.hex` sat outside +and a `trio` run produced **40 bytes** of trace instead of 7,475,444. +`../test_demo_assets.py` fails on any `preload` path that leaves this tree. + +Source of record: `hello_trace.hex` is a copy of +`../../kv260/common/tgc5b/prog/hello_trace.hex`, `trace_test.elf` of the MicroBlaze V +example's `sw/build/trace_test.elf`. + +## Raw material + +`raw/` holds the untouched console ring dumps. `../make_demo_console.py` +derives the `.txt` files from them, removing capture artefacts only (paired +duplicate lines from earlycon and console writing to the same UART, trailing +NUL padding from the ring). Keeping the raw dumps in the repository is what +makes that script reproducible -- its earlier sources pointed into build +trees that do not exist here. diff --git a/examples/dashboard/demo/console_cva6_linux.txt b/examples/dashboard/demo/console_cva6_linux.txt new file mode 100644 index 0000000..831598a --- /dev/null +++ b/examples/dashboard/demo/console_cva6_linux.txt @@ -0,0 +1,144 @@ + +OpenSBI 2025.02 + ____ _____ ____ _____ + / __ \ / ____| _ \_ _| + | | | |_ __ ___ _ __ | (___ | |_) || | + | | | | '_ \ / _ \ '_ \ \___ \| _ < | | + | |__| | |_) | __/ | | |____) | |_) || |_ + \____/| .__/ \___|_| |_|_____/|____/_____| + | | + |_| + +Platform Name : Accemic CVA6 C-Trace Demonstrator (KV260 PL) +Platform Features : medeleg +Platform HART Count : 1 +Platform IPI Device : aclint-mswi +Platform Timer Device : aclint-mtimer @ 1000000Hz +Platform Console Device : uart8250 +Platform HSM Device : --- +Platform PMU Device : --- +Platform Reboot Device : --- +Platform Shutdown Device : --- +Platform Suspend Device : --- +Platform CPPC Device : --- +Firmware Base : 0x64000000 +Firmware Size : 321 KB +Firmware RW Offset : 0x40000 +Firmware RW Size : 65 KB +Firmware Heap Offset : 0x47000 +Firmware Heap Size : 37 KB (total), 2 KB (reserved), 10 KB (used), 24 KB (free) +Firmware Scratch Size : 4096 B (total), 252 B (used), 3844 B (free) +Runtime SBI Version : 2.0 +Standard SBI Extensions : time,rfnc,ipi,base,hsm,pmu,dbcn,legacy +Experimental SBI Extensions : fwft,sse + +Domain0 Name : root +Domain0 Boot HART : 0 +Domain0 HARTs : 0* +Domain0 Region00 : 0x10000000-0x10000fff M: (I,R,W) S/U: (R,W) +Domain0 Region01 : 0x02000000-0x0200ffff M: (I,R,W) S/U: () +Domain0 Region02 : 0x64040000-0x6405ffff M: (R,W) S/U: () +Domain0 Region03 : 0x64000000-0x6403ffff M: (R,X) S/U: () +Domain0 Region04 : 0x00000000-0xffffffff M: () S/U: (R,W,X) +Domain0 Next Address : 0x64400000 +Domain0 Next Arg1 : 0x66200000 +Domain0 Next Mode : S-mode +Domain0 SysReset : yes +Domain0 SysSuspend : yes + +Boot HART ID : 0 +Boot HART Domain : root +Boot HART Priv Version : v1.12 +Boot HART Base ISA : rv32ima +Boot HART ISA Extensions : none +Boot HART PMP Count : 0 +Boot HART PMP Granularity : 0 bits +Boot HART PMP Address Bits : 0 +Boot HART MHPM Info : 0 (0x00000000) +Boot HART Debug Triggers : 0 triggers +Boot HART MIDELEG : 0x00000222 +Boot HART MEDELEG : 0x0000b109 +[ 0.000000] Linux version 6.12.19 (aweiss@panama) (riscv32-buildroot-linux-gnu-gcc.br_real (Buildroot 2025.02) 13.3.0, GNU ld (GNU Binutils) 2.43.1) #3 SMP Mon Jul 27 04:10:39 CEST 2026 +[ 0.000000] OF: fdt: Ignoring memory range 0x64000000 - 0x64400000 +[ 0.000000] Machine model: Accemic CVA6 C-Trace Demonstrator (KV260 PL) +[ 0.000000] SBI specification v2.0 detected +[ 0.000000] SBI implementation ID=0x1 Version=0x10006 +[ 0.000000] SBI TIME extension detected +[ 0.000000] SBI IPI extension detected +[ 0.000000] SBI RFENCE extension detected +[ 0.000000] SBI DBCN extension detected +[ 0.000000] earlycon: uart8250 at MMIO32 0x10000000 (options '') +[ 0.000000] printk: legacy bootconsole [uart8250] enabled +[ 0.000000] printk: debug: skip boot console de-registration. +[ 0.000000] OF: reserved mem: 0x64000000..0x6403ffff (256 KiB) nomap non-reusable mmode_resv1@64000000 +[ 0.000000] OF: reserved mem: 0x64040000..0x6405ffff (128 KiB) nomap non-reusable mmode_resv0@64040000 +[ 0.000000] Zone ranges: +[ 0.000000] Normal [mem 0x0000000064400000-0x000000006fffffff] +[ 0.000000] Movable zone start for each node +[ 0.000000] Early memory node ranges +[ 0.000000] node 0: [mem 0x0000000064400000-0x000000006fffffff] +[ 0.000000] Initmem setup node 0 [mem 0x0000000064400000-0x000000006fffffff] +[ 0.000000] On node 0, zone Normal: 17408 pages in unavailable ranges +[ 0.000000] SBI HSM extension detected +[ 0.000000] riscv: base ISA extensions aim +[ 0.000000] riscv: ELF capabilities aim +[ 0.000000] percpu: Embedded 17 pages/cpu s37208 r8192 d24232 u69632 +[ 0.000000] Kernel command line: earlycon=uart8250,mmio32,0x10000000 keep_bootcon console=ttyS0 rdinit=/sbin/init +[ 0.000000] Dentry cache hash table entries: 32768 (order: 5, 131072 bytes, linear) +[ 0.000000] Inode-cache hash table entries: 16384 (order: 4, 65536 bytes, linear) +[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 48128 +[ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off +[ 0.000000] Virtual kernel memory layout: +[ 0.000000] fixmap : 0x9c800000 - 0x9d000000 (8192 kB) +[ 0.000000] pci io : 0x9d000000 - 0x9e000000 ( 16 MB) +[ 0.000000] vmemmap : 0x9e000000 - 0xa0000000 ( 32 MB) +[ 0.000000] vmalloc : 0xa0000000 - 0xc0000000 ( 512 MB) +[ 0.000000] lowmem : 0xc0000000 - 0xcbc00000 ( 188 MB) +[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1 +[ 0.000000] rcu: Hierarchical RCU implementation. +[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=64 to nr_cpu_ids=1. +[ 0.000000] rcu: RCU debug extended QS entry/exit. +[ 0.000000] Tracing variant of Tasks RCU enabled. +[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies. +[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=1 +[ 0.000000] RCU Tasks Trace: Setting shift to 0 and lim to 1 rcu_task_cb_adjust=1 rcu_task_cpu_ids=1. +[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0 +[ 0.000000] riscv-intc: 32 local interrupts mapped +[ 0.000000] riscv: providing IPIs using SBI IPI extension +[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention. +[ 0.000000] clocksource: riscv_clocksource: mask: 0xffffffffffffffff max_cycles: 0x1d854df40, max_idle_ns: 3526361616960 ns +[ 0.000121] sched_clock: 64 bits at 1000kHz, resolution 1000ns, wraps every 2199023255500ns +[ 0.008352] Console: colour dummy device 80x25 +[ 0.011124] Calibrating delay loop (skipped), value calculated using timer frequency.. 2.00 BogoMIPS (lpj=4000) +[ 0.012628] pid_max: default: 32768 minimum: 301 +[ 0.017797] LSM: initializing lsm=capability +[ 0.026487] Mount-cache hash table entries: 1024 (order: 0, 4096 bytes, linear) +[ 0.027893] Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes, linear) +[ 0.182391] ASID allocator disabled (1 bits) +[ 0.198526] rcu: Hierarchical SRCU implementation. +[ 0.199364] rcu: Max phase no-delay instances is 1000. +[ 0.255015] smp: Bringing up secondary CPUs ... +[ 0.256180] smp: Brought up 1 node, 1 CPU +[ 0.261333] Memory: 146920K/192512K available (12835K kernel code, 8940K rwdata, 4096K rodata, 12352K init, 332K bss, 44876K reserved, 0K cma-reserved) +[ 0.285192] devtmpfs: initialized +[ 0.360580] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns +[ 0.363013] futex hash table entries: 256 (order: 2, 16384 bytes, linear) +[ 0.373969] pinctrl core: initialized pinctrl subsystem +[ 0.455811] NET: Registered PF_NETLINK/PF_ROUTE protocol family +[ 0.501108] DMA: preallocated 128 KiB GFP_KERNEL pool for atomic allocations +[ 0.504763] audit: initializing netlink subsys (disabled) +[ 0.548566] thermal_sys: Registered thermal governor 'step_wise' +[ 0.551190] audit: type=2000 audit(0.428:1): state=initialized audit_enabled=0 res=1 +[ 0.555287] cpuidle: using governor menu +[ 0.778415] cpu0: Ratio of byte access time to unaligned word access is 0.01, unaligned accesses are slow +[ 0.870745] HugeTLB: registered 4.00 MiB page size, pre-allocated 0 pages +[ 0.871746] HugeTLB: 0 KiB vmemmap can be freed for a 4.00 MiB page +[ 0.921980] iommu: Default domain type: Translated +[ 0.923751] iommu: DMA domain TLB invalidation policy: strict mode +[ 0.948544] SCSI subsystem initialized +[ 0.974281] usbcore: registered new interface driver usbfs +[ 0.977889] usbcore: registered new interface driver hub +[ 0.980536] usbcore: registered new device driver usb +[ 1.024230] Advanced Linux Sound Architecture Driver Initialized. +[ 1.074681] vgaarb: loaded +[ 1.091248] clocksource: Switched to clocksource riscv_clocksource diff --git a/examples/dashboard/demo/console_cva6_linux64.txt b/examples/dashboard/demo/console_cva6_linux64.txt new file mode 100644 index 0000000..c3d3259 --- /dev/null +++ b/examples/dashboard/demo/console_cva6_linux64.txt @@ -0,0 +1,178 @@ + +OpenSBI v1.6 + ____ _____ ____ _____ + / __ \ / ____| _ \_ _| + | | | |_ __ ___ _ __ | (___ | |_) || | + | | | | '_ \ / _ \ '_ \ \___ \| _ < | | + | |__| | |_) | __/ | | |____) | |_) || |_ + \____/| .__/ \___|_| |_|_____/|____/_____| + | | + |_| + +Platform Name : Accemic CVA6 RV64 CTTE Demonstrator (KV260 PL) +Platform Features : medeleg +Platform HART Count : 1 +Platform IPI Device : aclint-mswi +Platform Timer Device : aclint-mtimer @ 1000000Hz +Platform Console Device : uart8250 +Platform HSM Device : --- +Platform PMU Device : --- +Platform Reboot Device : --- +Platform Shutdown Device : --- +Platform Suspend Device : --- +Platform CPPC Device : --- +Firmware Base : 0x64000000 +Firmware Size : 325 KB +Firmware RW Offset : 0x40000 +Firmware RW Size : 69 KB +Firmware Heap Offset : 0x48000 +Firmware Heap Size : 37 KB (total), 2 KB (reserved), 11 KB (used), 23 KB (free) +Firmware Scratch Size : 4096 B (total), 424 B (used), 3672 B (free) +Runtime SBI Version : 2.0 +Standard SBI Extensions : time,rfnc,ipi,base,hsm,pmu,dbcn,legacy +Experimental SBI Extensions : fwft,sse + +Domain0 Name : root +Domain0 Boot HART : 0 +Domain0 HARTs : 0* +Domain0 Region00 : 0x0000000010000000-0x0000000010000fff M: (I,R,W) S/U: (R,W) +Domain0 Region01 : 0x0000000002000000-0x000000000200ffff M: (I,R,W) S/U: () +Domain0 Region02 : 0x0000000064040000-0x000000006405ffff M: (R,W) S/U: () +Domain0 Region03 : 0x0000000064000000-0x000000006403ffff M: (R,X) S/U: () +Domain0 Region04 : 0x0000000000000000-0xffffffffffffffff M: () S/U: (R,W,X) +Domain0 Next Address : 0x0000000064200000 +Domain0 Next Arg1 : 0x0000000066200000 +Domain0 Next Mode : S-mode +Domain0 SysReset : yes +Domain0 SysSuspend : yes + +Boot HART ID : 0 +Boot HART Domain : root +Boot HART Priv Version : v1.12 +Boot HART Base ISA : rv64imac +Boot HART ISA Extensions : zihpm +Boot HART PMP Count : 8 +Boot HART PMP Granularity : 3 bits +Boot HART PMP Address Bits : 54 +Boot HART MHPM Info : 6 (0x000001f8) +Boot HART Debug Triggers : 0 triggers +Boot HART MIDELEG : 0x0000000000000222 +Boot HART MEDELEG : 0x000000000000b109 +[ 0.000000] Linux version 6.12.19 (aweiss@panama) (riscv64-buildroot-linux-gnu-gcc.br_real (Buildroot 2025.02) 13.3.0, GNU ld (GNU Binutils) 2.43.1) #4 SMP Sat Aug 8 08:11:20 CEST 2026 +[ 0.000000] Machine model: Accemic CVA6 RV64 CTTE Demonstrator (KV260 PL) +[ 0.000000] SBI specification v2.0 detected +[ 0.000000] SBI implementation ID=0x1 Version=0x10006 +[ 0.000000] SBI TIME extension detected +[ 0.000000] SBI IPI extension detected +[ 0.000000] SBI RFENCE extension detected +[ 0.000000] SBI DBCN extension detected +[ 0.000000] earlycon: uart8250 at MMIO32 0x0000000010000000 (options '') +[ 0.000000] printk: legacy bootconsole [uart8250] enabled +[ 0.000000] printk: debug: skip boot console de-registration. +[ 0.000000] Disabled 4-level and 5-level paging +[ 0.000000] OF: reserved mem: 0x0000000064000000..0x000000006403ffff (256 KiB) nomap non-reusable mmode_resv1@64000000 +[ 0.000000] OF: reserved mem: 0x0000000064040000..0x000000006405ffff (128 KiB) nomap non-reusable mmode_resv0@64040000 +[ 0.000000] Zone ranges: +[ 0.000000] DMA32 [mem 0x0000000064000000-0x000000006fffffff] +[ 0.000000] Normal empty +[ 0.000000] Movable zone start for each node +[ 0.000000] Early memory node ranges +[ 0.000000] node 0: [mem 0x0000000064000000-0x000000006405ffff] +[ 0.000000] node 0: [mem 0x0000000064060000-0x000000006fffffff] +[ 0.000000] Initmem setup node 0 [mem 0x0000000064000000-0x000000006fffffff] +[ 0.000000] On node 0, zone DMA32: 16384 pages in unavailable ranges +[ 0.000000] SBI HSM extension detected +[ 0.000000] riscv: base ISA extensions acim +[ 0.000000] riscv: ELF capabilities acim +[ 0.000000] percpu: Embedded 21 pages/cpu s48872 r8192 d28952 u86016 +[ 0.000000] Kernel command line: earlycon=uart8250,mmio32,0x10000000 keep_bootcon console=ttyS0 no4lvl rdinit=/sbin/init +[ 0.000000] Dentry cache hash table entries: 32768 (order: 6, 262144 bytes, linear) +[ 0.000000] Inode-cache hash table entries: 16384 (order: 5, 131072 bytes, linear) +[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 49152 +[ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off +[ 0.000000] Virtual kernel memory layout: +[ 0.000000] fixmap : 0xffffffc4fea00000 - 0xffffffc4ff000000 (6144 kB) +[ 0.000000] pci io : 0xffffffc4ff000000 - 0xffffffc500000000 ( 16 MB) +[ 0.000000] vmemmap : 0xffffffc500000000 - 0xffffffc600000000 (4096 MB) +[ 0.000000] vmalloc : 0xffffffc600000000 - 0xffffffd600000000 ( 64 GB) +[ 0.000000] modules : 0xffffffff01d8a000 - 0xffffffff80000000 (2018 MB) +[ 0.000000] lowmem : 0xffffffd600000000 - 0xffffffd60c000000 ( 192 MB) +[ 0.000000] kernel : 0xffffffff80000000 - 0xffffffffffffffff (2047 MB) +[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1 +[ 0.000000] rcu: Hierarchical RCU implementation. +[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=64 to nr_cpu_ids=1. +[ 0.000000] rcu: RCU debug extended QS entry/exit. +[ 0.000000] Tracing variant of Tasks RCU enabled. +[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies. +[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=1 +[ 0.000000] RCU Tasks Trace: Setting shift to 0 and lim to 1 rcu_task_cb_adjust=1 rcu_task_cpu_ids=1. +[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0 +[ 0.000000] riscv-intc: 64 local interrupts mapped +[ 0.000000] riscv: providing IPIs using SBI IPI extension +[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention. +[ 0.000000] clocksource: riscv_clocksource: mask: 0xffffffffffffffff max_cycles: 0x1d854df40, max_idle_ns: 3526361616960 ns +[ 0.000060] sched_clock: 64 bits at 1000kHz, resolution 1000ns, wraps every 2199023255500ns +[ 0.005030] Console: colour dummy device 80x25 +[ 0.007002] Calibrating delay loop (skipped), value calculated using timer frequency.. 2.00 BogoMIPS (lpj=4000) +[ 0.008020] pid_max: default: 32768 minimum: 301 +[ 0.011118] LSM: initializing lsm=capability +[ 0.016967] Mount-cache hash table entries: 512 (order: 0, 4096 bytes, linear) +[ 0.017929] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes, linear) +[ 0.115906] riscv: ELF compat mode unsupported +[ 0.116711] ASID allocator using 16 bits (65536 entries) +[ 0.126912] rcu: Hierarchical SRCU implementation. +[ 0.127507] rcu: Max phase no-delay instances is 1000. +[ 0.161921] smp: Bringing up secondary CPUs ... +[ 0.162806] smp: Brought up 1 node, 1 CPU +[ 0.166481] Memory: 142832K/196608K available (9655K kernel code, 5102K rwdata, 4096K rodata, 10331K init, 473K bss, 52092K reserved, 0K cma-reserved) +[ 0.183627] devtmpfs: initialized +[ 0.229149] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns +[ 0.230369] futex hash table entries: 256 (order: 2, 16384 bytes, linear) +[ 0.238513] pinctrl core: initialized pinctrl subsystem +[ 0.285129] NET: Registered PF_NETLINK/PF_ROUTE protocol family +[ 0.310892] DMA: preallocated 128 KiB GFP_KERNEL pool for atomic allocations +[ 0.312984] DMA: preallocated 128 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations +[ 0.315338] audit: initializing netlink subsys (disabled) +[ 0.340436] thermal_sys: Registered thermal governor 'step_wise' +[ 0.341850] audit: type=2000 audit(0.288:1): state=initialized audit_enabled=0 res=1 +[ 0.344324] cpuidle: using governor menu +[ 0.459776] cpu0: Ratio of byte access time to unaligned word access is 0.00, unaligned accesses are slow +[ 0.516168] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages +[ 0.516870] HugeTLB: 28 KiB vmemmap can be freed for a 2.00 MiB page +[ 0.550216] iommu: Default domain type: Translated +[ 0.550827] iommu: DMA domain TLB invalidation policy: strict mode +[ 0.571540] SCSI subsystem initialized +[ 0.587114] usbcore: registered new interface driver usbfs +[ 0.589416] usbcore: registered new interface driver hub +[ 0.591182] usbcore: registered new device driver usb +[ 0.617130] Advanced Linux Sound Architecture Driver Initialized. +[ 0.649978] vgaarb: loaded +[ 0.661004] clocksource: Switched to clocksource riscv_clocksource +[ 1.106276] NET: Registered PF_INET protocol family +[ 1.113563] IP idents hash table entries: 4096 (order: 3, 32768 bytes, linear) +[ 1.141839] tcp_listen_portaddr_hash hash table entries: 128 (order: 0, 4096 bytes, linear) +[ 1.143039] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear) +[ 1.144095] TCP established hash table entries: 2048 (order: 2, 16384 bytes, linear) +[ 1.146149] TCP bind hash table entries: 2048 (order: 5, 131072 bytes, linear) +[ 1.150891] TCP: Hash tables configured (established 2048 bind 2048) +[ 1.154806] UDP hash table entries: 256 (order: 2, 24576 bytes, linear) +[ 1.157075] UDP-Lite hash table entries: 256 (order: 2, 24576 bytes, linear) +[ 1.162516] NET: Registered PF_UNIX/PF_LOCAL protocol family +[ 1.189956] RPC: Registered named UNIX socket transport module. +[ 1.190640] RPC: Registered udp transport module. +[ 1.191150] RPC: Registered tcp transport module. +[ 1.191641] RPC: Registered tcp-with-tls transport module. +[ 1.192162] RPC: Registered tcp NFSv4.1 backchannel transport module. +[ 1.193557] PCI: CLS 0 bytes, default 64 +[ 1.267008] workingset: timestamp_bits=46 max_order=16 bucket_order=0 +[ 1.312149] NFS: Registering the id_resolver key type +[ 1.314698] Key type id_resolver registered +[ 1.315295] Key type id_legacy registered +[ 1.317421] nfs4filelayout_init: NFSv4 File Layout Driver Registering... +[ 1.318170] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering... +[ 1.345406] 9p: Installing v9fs 9p2000 file system support +[ 1.355028] NET: Registered PF_ALG protocol family +[ 1.358302] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 245) +[ 1.386152] io scheduler mq-deadline registered +[ 1.386843] io scheduler kyber registered +[ 1.389130] io scheduler bfq registered diff --git a/examples/dashboard/demo/console_linux.txt b/examples/dashboard/demo/console_linux.txt new file mode 100644 index 0000000..7ee1ce7 --- /dev/null +++ b/examples/dashboard/demo/console_linux.txt @@ -0,0 +1,249 @@ + +OpenSBI 2025.02 + ____ _____ ____ _____ + / __ \ / ____| _ \_ _| + | | | |_ __ ___ _ __ | (___ | |_) || | + | | | | '_ \ / _ \ '_ \ \___ \| _ < | | + | |__| | |_) | __/ | | |____) | |_) || |_ + \____/| .__/ \___|_| |_|_____/|____/_____| + | | + |_| + +Platform Name : Accemic CVA6 C-Trace Demonstrator (KV260 PL) +Platform Features : medeleg +Platform HART Count : 1 +Platform IPI Device : aclint-mswi +Platform Timer Device : aclint-mtimer @ 1000000Hz +Platform Console Device : uart8250 +Platform HSM Device : --- +Platform PMU Device : --- +Platform Reboot Device : --- +Platform Shutdown Device : --- +Platform Suspend Device : --- +Platform CPPC Device : --- +Firmware Base : 0x64000000 +Firmware Size : 321 KB +Firmware RW Offset : 0x40000 +Firmware RW Size : 65 KB +Firmware Heap Offset : 0x47000 +Firmware Heap Size : 37 KB (total), 2 KB (reserved), 10 KB (used), 24 KB (free) +Firmware Scratch Size : 4096 B (total), 252 B (used), 3844 B (free) +Runtime SBI Version : 2.0 +Standard SBI Extensions : time,rfnc,ipi,base,hsm,pmu,dbcn,legacy +Experimental SBI Extensions : fwft,sse + +Domain0 Name : root +Domain0 Boot HART : 0 +Domain0 HARTs : 0* +Domain0 Region00 : 0x10000000-0x10000fff M: (I,R,W) S/U: (R,W) +Domain0 Region01 : 0x02000000-0x0200ffff M: (I,R,W) S/U: () +Domain0 Region02 : 0x64040000-0x6405ffff M: (R,W) S/U: () +Domain0 Region03 : 0x64000000-0x6403ffff M: (R,X) S/U: () +Domain0 Region04 : 0x00000000-0xffffffff M: () S/U: (R,W,X) +Domain0 Next Address : 0x64400000 +Domain0 Next Arg1 : 0x66200000 +Domain0 Next Mode : S-mode +Domain0 SysReset : yes +Domain0 SysSuspend : yes + +Boot HART ID : 0 +Boot HART Domain : root +Boot HART Priv Version : v1.12 +Boot HART Base ISA : rv32ima +Boot HART ISA Extensions : none +Boot HART PMP Count : 0 +Boot HART PMP Granularity : 0 bits +Boot HART PMP Address Bits : 0 +Boot HART MHPM Info : 0 (0x00000000) +Boot HART Debug Triggers : 0 triggers +Boot HART MIDELEG : 0x00000222 +Boot HART MEDELEG : 0x0000b109 +[ 0.000000] Linux version 6.12.19 (builder@buildhost) (riscv32-buildroot-linux-gnu-gcc.br_real (Buildroot 2025.02) 13.3.0, GNU ld (GNU Binutils) 2.43.1) #3 SMP Mon Jul 27 04:10:39 CEST 2026 +[ 0.000000] OF: fdt: Ignoring memory range 0x64000000 - 0x64400000 +[ 0.000000] Machine model: Accemic CVA6 C-Trace Demonstrator (KV260 PL) +[ 0.000000] SBI specification v2.0 detected +[ 0.000000] SBI implementation ID=0x1 Version=0x10006 +[ 0.000000] SBI TIME extension detected +[ 0.000000] SBI IPI extension detected +[ 0.000000] SBI RFENCE extension detected +[ 0.000000] SBI DBCN extension detected +[ 0.000000] earlycon: uart8250 at MMIO32 0x10000000 (options '') +[ 0.000000] printk: legacy bootconsole [uart8250] enabled +[ 0.000000] printk: debug: skip boot console de-registration. +[ 0.000000] OF: reserved mem: 0x64000000..0x6403ffff (256 KiB) nomap non-reusable mmode_resv1@64000000 +[ 0.000000] OF: reserved mem: 0x64040000..0x6405ffff (128 KiB) nomap non-reusable mmode_resv0@64040000 +[ 0.000000] Zone ranges: +[ 0.000000] Normal [mem 0x0000000064400000-0x000000006fffffff] +[ 0.000000] Movable zone start for each node +[ 0.000000] Early memory node ranges +[ 0.000000] node 0: [mem 0x0000000064400000-0x000000006fffffff] +[ 0.000000] Initmem setup node 0 [mem 0x0000000064400000-0x000000006fffffff] +[ 0.000000] On node 0, zone Normal: 17408 pages in unavailable ranges +[ 0.000000] SBI HSM extension detected +[ 0.000000] riscv: base ISA extensions aim +[ 0.000000] riscv: ELF capabilities aim +[ 0.000000] percpu: Embedded 17 pages/cpu s37208 r8192 d24232 u69632 +[ 0.000000] Kernel command line: earlycon=uart8250,mmio32,0x10000000 keep_bootcon console=ttyS0 rdinit=/sbin/init +[ 0.000000] Dentry cache hash table entries: 32768 (order: 5, 131072 bytes, linear) +[ 0.000000] Inode-cache hash table entries: 16384 (order: 4, 65536 bytes, linear) +[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 48128 +[ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off +[ 0.000000] Virtual kernel memory layout: +[ 0.000000] fixmap : 0x9c800000 - 0x9d000000 (8192 kB) +[ 0.000000] pci io : 0x9d000000 - 0x9e000000 ( 16 MB) +[ 0.000000] vmemmap : 0x9e000000 - 0xa0000000 ( 32 MB) +[ 0.000000] vmalloc : 0xa0000000 - 0xc0000000 ( 512 MB) +[ 0.000000] lowmem : 0xc0000000 - 0xcbc00000 ( 188 MB) +[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1 +[ 0.000000] rcu: Hierarchical RCU implementation. +[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=64 to nr_cpu_ids=1. +[ 0.000000] rcu: RCU debug extended QS entry/exit. +[ 0.000000] Tracing variant of Tasks RCU enabled. +[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies. +[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=1 +[ 0.000000] RCU Tasks Trace: Setting shift to 0 and lim to 1 rcu_task_cb_adjust=1 rcu_task_cpu_ids=1. +[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0 +[ 0.000000] riscv-intc: 32 local interrupts mapped +[ 0.000000] riscv: providing IPIs using SBI IPI extension +[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention. +[ 0.000000] clocksource: riscv_clocksource: mask: 0xffffffffffffffff max_cycles: 0x1d854df40, max_idle_ns: 3526361616960 ns +[ 0.000141] sched_clock: 64 bits at 1000kHz, resolution 1000ns, wraps every 2199023255500ns +[ 0.009695] Console: colour dummy device 80x25 +[ 0.012967] Calibrating delay loop (skipped), value calculated using timer frequency.. 2.00 BogoMIPS (lpj=4000) +[ 0.014696] pid_max: default: 32768 minimum: 301 +[ 0.021526] LSM: initializing lsm=capability +[ 0.031779] Mount-cache hash table entries: 1024 (order: 0, 4096 bytes, linear) +[ 0.033386] Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes, linear) +[ 0.220771] ASID allocator disabled (1 bits) +[ 0.237077] rcu: Hierarchical SRCU implementation. +[ 0.239078] rcu: Max phase no-delay instances is 1000. +[ 0.299346] smp: Bringing up secondary CPUs ... +[ 0.300686] smp: Brought up 1 node, 1 CPU +[ 0.308016] Memory: 146920K/192512K available (12835K kernel code, 8940K rwdata, 4096K rodata, 12352K init, 332K bss, 44876K reserved, 0K cma-reserved) +[ 0.337576] devtmpfs: initialized +[ 0.426685] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns +[ 0.429452] futex hash table entries: 256 (order: 2, 16384 bytes, linear) +[ 0.441990] pinctrl core: initialized pinctrl subsystem +[ 0.534341] NET: Registered PF_NETLINK/PF_ROUTE protocol family +[ 0.585710] DMA: preallocated 128 KiB GFP_KERNEL pool for atomic allocations +[ 0.589814] audit: initializing netlink subsys (disabled) +[ 0.639707] thermal_sys: Registered thermal governor 'step_wise' +[ 0.643419] audit: type=2000 audit(0.480:1): state=initialized audit_enabled=0 res=1 +[ 0.648141] cpuidle: using governor menu +[ 0.901104] cpu0: Ratio of byte access time to unaligned word access is 0.01, unaligned accesses are slow +[ 1.008889] HugeTLB: registered 4.00 MiB page size, pre-allocated 0 pages +[ 1.010013] HugeTLB: 0 KiB vmemmap can be freed for a 4.00 MiB page +[ 1.074858] iommu: Default domain type: Translated +[ 1.076907] iommu: DMA domain TLB invalidation policy: strict mode +[ 1.104961] SCSI subsystem initialized +[ 1.136350] usbcore: registered new interface driver usbfs +[ 1.139441] usbcore: registered new interface driver hub +[ 1.143648] usbcore: registered new device driver usb +[ 1.194378] Advanced Linux Sound Architecture Driver Initialized. +[ 1.253485] vgaarb: loaded +[ 1.273674] clocksource: Switched to clocksource riscv_clocksource +[ 2.314237] NET: Registered PF_INET protocol family +[ 2.331837] IP idents hash table entries: 4096 (order: 3, 32768 bytes, linear) +[ 2.383266] tcp_listen_portaddr_hash hash table entries: 256 (order: 0, 5120 bytes, linear) +[ 2.386771] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear) +[ 2.390029] TCP established hash table entries: 2048 (order: 1, 8192 bytes, linear) +[ 2.394098] TCP bind hash table entries: 2048 (order: 4, 81920 bytes, linear) +[ 2.403368] TCP: Hash tables configured (established 2048 bind 2048) +[ 2.410814] UDP hash table entries: 256 (order: 1, 12288 bytes, linear) +[ 2.414720] UDP-Lite hash table entries: 256 (order: 1, 12288 bytes, linear) +[ 2.427579] NET: Registered PF_UNIX/PF_LOCAL protocol family +[ 2.487359] RPC: Registered named UNIX socket transport module. +[ 2.489929] RPC: Registered udp transport module. +[ 2.490898] RPC: Registered tcp transport module. +[ 2.491841] RPC: Registered tcp-with-tls transport module. +[ 2.494316] RPC: Registered tcp NFSv4.1 backchannel transport module. +[ 2.495670] PCI: CLS 0 bytes, default 64 +[ 2.671925] workingset: timestamp_bits=14 max_order=16 bucket_order=2 +[ 2.774507] NFS: Registering the id_resolver key type +[ 2.778491] Key type id_resolver registered +[ 2.779491] Key type id_legacy registered +[ 2.783370] nfs4filelayout_init: NFSv4 File Layout Driver Registering... +[ 2.786075] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering... +[ 2.842872] 9p: Installing v9fs 9p2000 file system support +[ 2.863446] NET: Registered PF_ALG protocol family +[ 2.870763] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 247) +[ 2.925619] io scheduler mq-deadline registered +[ 2.926770] io scheduler kyber registered +[ 2.930973] io scheduler bfq registered +[ 14.966345] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled +[ 15.228122] of_serial 10000000.serial: error -ENXIO: IRQ index 0 not found +[ 15.299289] printk: legacy console [ttyS0] disabled +[ 15.331478] 10000000.serial: ttyS0 at MMIO 0x10000000 (irq = 0, base_baud = 4687500) is a 16550A +[ 15.335069] printk: legacy console [ttyS0] enabled +[ 15.335069] printk: legacy console [ttyS0] enabled +[ 16.590520] loop: module loaded +[ 16.590520] loop: module loaded +[ 16.862439] e1000e: Intel(R) PRO/1000 Network Driver +[ 16.862439] e1000e: Intel(R) PRO/1000 Network Driver +[ 16.864018] e1000e: Copyright(c) 1999 - 2015 Intel Corporation. +[ 16.864018] e1000e: Copyright(c) 1999 - 2015 Intel Corporation. +[ 17.267229] usbcore: registered new interface driver uas +[ 17.267229] usbcore: registered new interface driver uas +[ 17.274510] usbcore: registered new interface driver usb-storage +[ 17.274510] usbcore: registered new interface driver usb-storage +[ 17.335337] mousedev: PS/2 mouse device common for all mice +[ 17.335337] mousedev: PS/2 mouse device common for all mice +[ 17.399584] sdhci: Secure Digital Host Controller Interface driver +[ 17.399584] sdhci: Secure Digital Host Controller Interface driver +[ 17.402847] sdhci: Copyright(c) Pierre Ossman +[ 17.402847] sdhci: Copyright(c) Pierre Ossman +[ 17.407761] Synopsys Designware Multimedia Card Interface Driver +[ 17.407761] Synopsys Designware Multimedia Card Interface Driver +[ 17.421703] sdhci-pltfm: SDHCI platform and OF driver helper +[ 17.421703] sdhci-pltfm: SDHCI platform and OF driver helper +[ 17.443919] usbcore: registered new interface driver usbhid +[ 17.443919] usbcore: registered new interface driver usbhid +[ 17.447124] usbhid: USB HID core driver +[ 17.447124] usbhid: USB HID core driver +[ 17.466590] riscv-pmu-sbi: SBI PMU extension is available +[ 17.466590] riscv-pmu-sbi: SBI PMU extension is available +[ 17.470510] riscv-pmu-sbi: 16 firmware and 2 hardware counters +[ 17.470510] riscv-pmu-sbi: 16 firmware and 2 hardware counters +[ 17.473740] riscv-pmu-sbi: Perf sampling/filtering is not supported as sscof extension is not available +[ 17.473740] riscv-pmu-sbi: Perf sampling/filtering is not supported as sscof extension is not available +[ 17.706758] NET: Registered PF_INET6 protocol family +[ 17.706758] NET: Registered PF_INET6 protocol family +[ 17.875527] Segment Routing with IPv6 +[ 17.875527] Segment Routing with IPv6 +[ 17.885958] In-situ OAM (IOAM) with IPv6 +[ 17.885958] In-situ OAM (IOAM) with IPv6 +[ 17.891264] sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver +[ 17.891264] sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver +[ 17.938156] NET: Registered PF_PACKET protocol family +[ 17.938156] NET: Registered PF_PACKET protocol family +[ 17.946410] 9pnet: Installing 9P2000 support +[ 17.946410] 9pnet: Installing 9P2000 support +[ 17.954359] Key type dns_resolver registered +[ 17.954359] Key type dns_resolver registered +[ 21.666009] debug_vm_pgtable: [debug_vm_pgtable ]: Validating architecture page table helpers +[ 21.666009] debug_vm_pgtable: [debug_vm_pgtable ]: Validating architecture page table helpers +[ 22.642027] clk: Disabling unused clocks +[ 22.642027] clk: Disabling unused clocks +[ 22.643644] PM: genpd: Disabling unused power domains +[ 22.643644] PM: genpd: Disabling unused power domains +[ 22.647136] ALSA device list: +[ 22.647136] ALSA device list: +[ 22.649958] No soundcards found. +[ 22.649958] No soundcards found. +[ 46.666539] Freeing unused kernel image (initmem) memory: 12352K +[ 46.666539] Freeing unused kernel image (initmem) memory: 12352K +[ 46.674507] Run /sbin/init as init process +[ 46.674507] Run /sbin/init as init process + can't open /dev/null: No such file or directory + can't open /dev/null: No such file or directory + can't open /dev/null: No such file or directory + can't open /dev/null: No such file or directory +Saving 256 bits of non-creditable seed for next boot +Starting syslogd: OK +Starting klogd: OK +Running sysctl: OK +Starting network: OK +Starting crond: OK + +Welcome to Buildroot + buildroot login: \ No newline at end of file diff --git a/examples/dashboard/demo/console_rocket2.txt b/examples/dashboard/demo/console_rocket2.txt new file mode 100644 index 0000000..1af20db --- /dev/null +++ b/examples/dashboard/demo/console_rocket2.txt @@ -0,0 +1,214 @@ + +OpenSBI v1.6 + ____ _____ ____ _____ + / __ \ / ____| _ \_ _| + | | | |_ __ ___ _ __ | (___ | |_) || | + | | | | '_ \ / _ \ '_ \ \___ \| _ < | | + | |__| | |_) | __/ | | |____) | |_) || |_ + \____/| .__/ \___|_| |_|_____/|____/_____| + | | + |_| + +Platform Name : Accemic Rocket64t2 RV64 CTTE Demonstrator, 2 Harts (KV260 PL) +Platform Features : medeleg +Platform HART Count : 2 +Platform IPI Device : aclint-mswi +Platform Timer Device : aclint-mtimer @ 750000Hz +Platform Console Device : uart8250 +Platform HSM Device : --- +Platform PMU Device : --- +Platform Reboot Device : --- +Platform Shutdown Device : --- +Platform Suspend Device : --- +Platform CPPC Device : --- +Firmware Base : 0x80000000 +Firmware Size : 337 KB +Firmware RW Offset : 0x40000 +Firmware RW Size : 81 KB +Firmware Heap Offset : 0x4a000 +Firmware Heap Size : 41 KB (total), 2 KB (reserved), 13 KB (used), 25 KB (free) +Firmware Scratch Size : 4096 B (total), 440 B (used), 3656 B (free) +Runtime SBI Version : 2.0 +Standard SBI Extensions : time,rfnc,ipi,base,hsm,pmu,dbcn,legacy +Experimental SBI Extensions : fwft,dbtr,sse + +Domain0 Name : root +Domain0 Boot HART : 0 +Domain0 HARTs : 0*,1* +Domain0 Region00 : 0x0000000060010000-0x0000000060010fff M: (I,R,W) S/U: (R,W) +Domain0 Region01 : 0x0000000002000000-0x000000000200ffff M: (I,R,W) S/U: () +Domain0 Region02 : 0x0000000080040000-0x000000008005ffff M: (R,W) S/U: () +Domain0 Region03 : 0x0000000080000000-0x000000008003ffff M: (R,X) S/U: () +Domain0 Region04 : 0x000000000c000000-0x000000000fffffff M: (I,R,W) S/U: (R,W) +Domain0 Region05 : 0x0000000000000000-0xffffffffffffffff M: () S/U: (R,W,X) +Domain0 Next Address : 0x0000000080200000 +Domain0 Next Arg1 : 0x0000000082200000 +Domain0 Next Mode : S-mode +Domain0 SysReset : yes +Domain0 SysSuspend : yes + +Boot HART ID : 0 +Boot HART Domain : root +Boot HART Priv Version : v1.12 +Boot HART Base ISA : rv64imacx +Boot HART ISA Extensions : sdtrig +Boot HART PMP Count : 8 +Boot HART PMP Granularity : 2 bits +Boot HART PMP Address Bits : 32 +Boot HART MHPM Info : 0 (0x00000000) +Boot HART Debug Triggers : 8 triggers +Boot HART MIDELEG : 0x0000000000000222 +Boot HART MEDELEG : 0x000000000000b109 +[ 0.000000] Linux version 6.12.19 (aweiss@panama) (riscv64-buildroot-linux-gnu-gcc.br_real (Buildroot 2025.02) 13.3.0, GNU ld (GNU Binutils) 2.43.1) #6 SMP Sun Aug 9 16:15:17 CEST 2026 +[ 0.000000] Machine model: Accemic Rocket64t2 RV64 CTTE Demonstrator, 2 Harts (KV260 PL) +[ 0.000000] SBI specification v2.0 detected +[ 0.000000] SBI implementation ID=0x1 Version=0x10006 +[ 0.000000] SBI TIME extension detected +[ 0.000000] SBI IPI extension detected +[ 0.000000] SBI RFENCE extension detected +[ 0.000000] SBI DBCN extension detected +[ 0.000000] earlycon: uart8250 at MMIO32 0x0000000060010000 (options '') +[ 0.000000] printk: legacy bootconsole [uart8250] enabled +[ 0.000000] printk: debug: skip boot console de-registration. +[ 0.000000] Disabled 4-level and 5-level paging +[ 0.000000] OF: reserved mem: 0x0000000080000000..0x000000008003ffff (256 KiB) nomap non-reusable mmode_resv1@80000000 +[ 0.000000] OF: reserved mem: 0x0000000080040000..0x000000008005ffff (128 KiB) nomap non-reusable mmode_resv0@80040000 +[ 0.000000] Zone ranges: +[ 0.000000] DMA32 [mem 0x0000000080000000-0x000000008bffffff] +[ 0.000000] Normal empty +[ 0.000000] Movable zone start for each node +[ 0.000000] Early memory node ranges +[ 0.000000] node 0: [mem 0x0000000080000000-0x000000008005ffff] +[ 0.000000] node 0: [mem 0x0000000080060000-0x000000008bffffff] +[ 0.000000] Initmem setup node 0 [mem 0x0000000080000000-0x000000008bffffff] +[ 0.000000] On node 0, zone DMA32: 16384 pages in unavailable ranges +[ 0.000000] SBI HSM extension detected +[ 0.000000] riscv: base ISA extensions acim +[ 0.000000] riscv: ELF capabilities acim +[ 0.000000] percpu: Embedded 21 pages/cpu s48872 r8192 d28952 u86016 +[ 0.000000] Kernel command line: earlycon=uart8250,mmio32,0x60010000 keep_bootcon console=ttyS0 no4lvl rdinit=/sbin/init +[ 0.000000] Dentry cache hash table entries: 32768 (order: 6, 262144 bytes, linear) +[ 0.000000] Inode-cache hash table entries: 16384 (order: 5, 131072 bytes, linear) +[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 49152 +[ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off +[ 0.000000] Virtual kernel memory layout: +[ 0.000000] fixmap : 0xffffffc4fea00000 - 0xffffffc4ff000000 (6144 kB) +[ 0.000000] pci io : 0xffffffc4ff000000 - 0xffffffc500000000 ( 16 MB) +[ 0.000000] vmemmap : 0xffffffc500000000 - 0xffffffc600000000 (4096 MB) +[ 0.000000] vmalloc : 0xffffffc600000000 - 0xffffffd600000000 ( 64 GB) +[ 0.000000] modules : 0xffffffff01f8a000 - 0xffffffff80000000 (2016 MB) +[ 0.000000] lowmem : 0xffffffd600000000 - 0xffffffd60c000000 ( 192 MB) +[ 0.000000] kernel : 0xffffffff80000000 - 0xffffffffffffffff (2047 MB) +[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=2, Nodes=1 +[ 0.000000] rcu: Hierarchical RCU implementation. +[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=64 to nr_cpu_ids=2. +[ 0.000000] rcu: RCU debug extended QS entry/exit. +[ 0.000000] Tracing variant of Tasks RCU enabled. +[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies. +[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=2 +[ 0.000000] RCU Tasks Trace: Setting shift to 1 and lim to 1 rcu_task_cb_adjust=1 rcu_task_cpu_ids=2. +[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0 +[ 0.000000] riscv-intc: 64 local interrupts mapped +[ 0.000000] riscv: providing IPIs using SBI IPI extension +[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention. +[ 0.000000] clocksource: riscv_clocksource: mask: 0xffffffffffffffff max_cycles: 0x1623fa770, max_idle_ns: 3526361617904 ns +[ 0.000036] sched_clock: 64 bits at 750kHz, resolution 1333ns, wraps every 4398046510524ns +[ 0.003540] Console: colour dummy device 80x25 +[ 0.004565] Calibrating delay loop (skipped), value calculated using timer frequency.. 1.50 BogoMIPS (lpj=3000) +[ 0.005533] pid_max: default: 32768 minimum: 301 +[ 0.007446] LSM: initializing lsm=capability +[ 0.011305] Mount-cache hash table entries: 512 (order: 0, 4096 bytes, linear) +[ 0.011911] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes, linear) +[ 0.074065] riscv: ELF compat mode unsupported +[ 0.074283] ASID allocator disabled (0 bits) +[ 0.079453] rcu: Hierarchical SRCU implementation. +[ 0.079814] rcu: Max phase no-delay instances is 1000. +[ 0.090133] Timer migration: 1 hierarchy levels; 8 children per group; 1 crossnode level +[ 0.104641] smp: Bringing up secondary CPUs ... +[ 0.127107] smp: Brought up 1 node, 2 CPUs +[ 0.138873] Memory: 140448K/196608K available (9655K kernel code, 5038K rwdata, 4096K rodata, 12443K init, 473K bss, 54228K reserved, 0K cma-reserved) +[ 0.151217] devtmpfs: initialized +[ 0.185029] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns +[ 0.185707] futex hash table entries: 512 (order: 3, 32768 bytes, linear) +[ 0.191543] pinctrl core: initialized pinctrl subsystem +[ 0.220563] NET: Registered PF_NETLINK/PF_ROUTE protocol family +[ 0.228534] DMA: preallocated 128 KiB GFP_KERNEL pool for atomic allocations +[ 0.229467] DMA: preallocated 128 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations +[ 0.230699] audit: initializing netlink subsys (disabled) +[ 0.237589] audit: type=2000 audit(0.216:1): state=initialized audit_enabled=0 res=1 +[ 0.247414] thermal_sys: Registered thermal governor 'step_wise' +[ 0.249385] cpuidle: using governor menu +[ 0.317121] cpu1: Ratio of byte access time to unaligned word access is 0.01, unaligned accesses are slow +[ 0.376757] cpu0: Ratio of byte access time to unaligned word access is 0.01, unaligned accesses are slow +[ 0.419418] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages +[ 0.419861] HugeTLB: 28 KiB vmemmap can be freed for a 2.00 MiB page +[ 0.441305] iommu: Default domain type: Translated +[ 0.441685] iommu: DMA domain TLB invalidation policy: strict mode +[ 0.455238] SCSI subsystem initialized +[ 0.466529] usbcore: registered new interface driver usbfs +[ 0.467709] usbcore: registered new interface driver hub +[ 0.468859] usbcore: registered new device driver usb +[ 0.485465] Advanced Linux Sound Architecture Driver Initialized. +[ 0.503335] vgaarb: loaded +[ 0.511950] clocksource: Switched to clocksource riscv_clocksource +[ 0.858314] NET: Registered PF_INET protocol family +[ 0.863015] IP idents hash table entries: 4096 (order: 3, 32768 bytes, linear) +[ 0.885846] tcp_listen_portaddr_hash hash table entries: 128 (order: 0, 4096 bytes, linear) +[ 0.886646] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear) +[ 0.888079] TCP established hash table entries: 2048 (order: 2, 16384 bytes, linear) +[ 0.889161] TCP bind hash table entries: 2048 (order: 5, 131072 bytes, linear) +[ 0.893490] TCP: Hash tables configured (established 2048 bind 2048) +[ 0.896278] UDP hash table entries: 256 (order: 2, 24576 bytes, linear) +[ 0.897522] UDP-Lite hash table entries: 256 (order: 2, 24576 bytes, linear) +[ 0.902298] NET: Registered PF_UNIX/PF_LOCAL protocol family +[ 0.916911] RPC: Registered named UNIX socket transport module. +[ 0.917335] RPC: Registered udp transport module. +[ 0.917651] RPC: Registered tcp transport module. +[ 0.917935] RPC: Registered tcp-with-tls transport module. +[ 0.918241] RPC: Registered tcp NFSv4.1 backchannel transport module. +[ 0.918677] PCI: CLS 0 bytes, default 64 +[ 0.949462] workingset: timestamp_bits=46 max_order=16 bucket_order=0 +[ 0.972833] NFS: Registering the id_resolver key type +[ 0.973801] Key type id_resolver registered +[ 0.974181] Key type id_legacy registered +[ 0.975662] nfs4filelayout_init: NFSv4 File Layout Driver Registering... +[ 0.976129] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering... +[ 0.982250] 9p: Installing v9fs 9p2000 file system support +[ 0.989103] NET: Registered PF_ALG protocol family +[ 0.991633] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 245) +[ 0.996998] io scheduler mq-deadline registered +[ 0.997419] io scheduler kyber registered +[ 0.998697] io scheduler bfq registered +[ 1.026771] riscv-plic: interrupt-controller@c000000: mapped 8 interrupts with 2 handlers for 4 contexts. +[ 2.862683] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled +[ 2.904909] of_serial 60010000.serial: error -ENXIO: IRQ index 0 not found +[ 2.912625] printk: legacy console [ttyS0] disabled +[ 2.921377] 60010000.serial: ttyS0 at MMIO 0x60010000 (irq = 0, base_baud = 4687500) is a 16550A +[ 2.922170] printk: legacy console [ttyS0] enabled +[ 3.097830] loop: module loaded +[ 3.172707] e1000e: Intel(R) PRO/1000 Network Driver +[ 3.173307] e1000e: Copyright(c) 1999 - 2015 Intel Corporation. +[ 3.189618] usbcore: registered new interface driver uas +[ 3.191583] usbcore: registered new interface driver usb-storage +[ 3.203751] mousedev: PS/2 mouse device common for all mice +[ 3.222103] sdhci: Secure Digital Host Controller Interface driver +[ 3.222739] sdhci: Copyright(c) Pierre Ossman +[ 3.224322] Synopsys Designware Multimedia Card Interface Driver +[ 3.228941] sdhci-pltfm: SDHCI platform and OF driver helper +[ 3.235779] usbcore: registered new interface driver usbhid +[ 3.236445] usbhid: USB HID core driver +[ 3.241717] riscv-pmu-sbi: SBI PMU extension is available +[ 3.242639] riscv-pmu-sbi: 16 firmware and 2 hardware counters +[ 3.243681] riscv-pmu-sbi: Perf sampling/filtering is not supported as sscof extension is not available +[ 3.272751] NET: Registered PF_INET6 protocol family +[ 3.305459] Segment Routing with IPv6 +[ 3.308058] In-situ OAM (IOAM) with IPv6 +[ 3.310109] sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver +[ 3.324462] NET: Registered PF_PACKET protocol family +[ 3.327003] 9pnet: Installing 9P2000 support +[ 3.329450] Key type dns_resolver registered +[ 3.867547] debug_vm_pgtable: [debug_vm_pgtable ]: Validating architecture page table helpers +[ 3.902007] clk: Disabling unused clocks +[ 3.902602] PM: genpd: Disabling unused power domains +[ 3.903999] ALSA device list: +[ 3.904501] No soundcards found. diff --git a/examples/dashboard/demo/console_rocket64.txt b/examples/dashboard/demo/console_rocket64.txt new file mode 100644 index 0000000..a339f66 --- /dev/null +++ b/examples/dashboard/demo/console_rocket64.txt @@ -0,0 +1,180 @@ + +OpenSBI v1.6 + ____ _____ ____ _____ + / __ \ / ____| _ \_ _| + | | | |_ __ ___ _ __ | (___ | |_) || | + | | | | '_ \ / _ \ '_ \ \___ \| _ < | | + | |__| | |_) | __/ | | |____) | |_) || |_ + \____/| .__/ \___|_| |_|_____/|____/_____| + | | + |_| + +Platform Name : Accemic Rocket64t1 RV64 CTTE Demonstrator (KV260 PL) +Platform Features : medeleg +Platform HART Count : 1 +Platform IPI Device : aclint-mswi +Platform Timer Device : aclint-mtimer @ 750000Hz +Platform Console Device : uart8250 +Platform HSM Device : --- +Platform PMU Device : --- +Platform Reboot Device : --- +Platform Shutdown Device : --- +Platform Suspend Device : --- +Platform CPPC Device : --- +Firmware Base : 0x80000000 +Firmware Size : 325 KB +Firmware RW Offset : 0x40000 +Firmware RW Size : 69 KB +Firmware Heap Offset : 0x48000 +Firmware Heap Size : 37 KB (total), 2 KB (reserved), 13 KB (used), 21 KB (free) +Firmware Scratch Size : 4096 B (total), 440 B (used), 3656 B (free) +Runtime SBI Version : 2.0 +Standard SBI Extensions : time,rfnc,ipi,base,hsm,pmu,dbcn,legacy +Experimental SBI Extensions : fwft,dbtr,sse + +Domain0 Name : root +Domain0 Boot HART : 0 +Domain0 HARTs : 0* +Domain0 Region00 : 0x0000000060010000-0x0000000060010fff M: (I,R,W) S/U: (R,W) +Domain0 Region01 : 0x0000000002000000-0x000000000200ffff M: (I,R,W) S/U: () +Domain0 Region02 : 0x0000000080040000-0x000000008005ffff M: (R,W) S/U: () +Domain0 Region03 : 0x0000000080000000-0x000000008003ffff M: (R,X) S/U: () +Domain0 Region04 : 0x000000000c000000-0x000000000fffffff M: (I,R,W) S/U: (R,W) +Domain0 Region05 : 0x0000000000000000-0xffffffffffffffff M: () S/U: (R,W,X) +Domain0 Next Address : 0x0000000080200000 +Domain0 Next Arg1 : 0x0000000082200000 +Domain0 Next Mode : S-mode +Domain0 SysReset : yes +Domain0 SysSuspend : yes + +Boot HART ID : 0 +Boot HART Domain : root +Boot HART Priv Version : v1.12 +Boot HART Base ISA : rv64imacx +Boot HART ISA Extensions : sdtrig +Boot HART PMP Count : 8 +Boot HART PMP Granularity : 2 bits +Boot HART PMP Address Bits : 32 +Boot HART MHPM Info : 0 (0x00000000) +Boot HART Debug Triggers : 8 triggers +Boot HART MIDELEG : 0x0000000000000222 +Boot HART MEDELEG : 0x000000000000b109 +[ 0.000000] Linux version 6.12.19 (aweiss@panama) (riscv64-buildroot-linux-gnu-gcc.br_real (Buildroot 2025.02) 13.3.0, GNU ld (GNU Binutils) 2.43.1) #7 SMP Sun Aug 9 16:21:38 CEST 2026 +[ 0.000000] Machine model: Accemic Rocket64t1 RV64 CTTE Demonstrator (KV260 PL) +[ 0.000000] SBI specification v2.0 detected +[ 0.000000] SBI implementation ID=0x1 Version=0x10006 +[ 0.000000] SBI TIME extension detected +[ 0.000000] SBI IPI extension detected +[ 0.000000] SBI RFENCE extension detected +[ 0.000000] SBI DBCN extension detected +[ 0.000000] earlycon: uart8250 at MMIO32 0x0000000060010000 (options '') +[ 0.000000] printk: legacy bootconsole [uart8250] enabled +[ 0.000000] printk: debug: skip boot console de-registration. +[ 0.000000] Disabled 4-level and 5-level paging +[ 0.000000] OF: reserved mem: 0x0000000080000000..0x000000008003ffff (256 KiB) nomap non-reusable mmode_resv1@80000000 +[ 0.000000] OF: reserved mem: 0x0000000080040000..0x000000008005ffff (128 KiB) nomap non-reusable mmode_resv0@80040000 +[ 0.000000] Zone ranges: +[ 0.000000] DMA32 [mem 0x0000000080000000-0x000000008bffffff] +[ 0.000000] Normal empty +[ 0.000000] Movable zone start for each node +[ 0.000000] Early memory node ranges +[ 0.000000] node 0: [mem 0x0000000080000000-0x000000008005ffff] +[ 0.000000] node 0: [mem 0x0000000080060000-0x000000008bffffff] +[ 0.000000] Initmem setup node 0 [mem 0x0000000080000000-0x000000008bffffff] +[ 0.000000] On node 0, zone DMA32: 16384 pages in unavailable ranges +[ 0.000000] SBI HSM extension detected +[ 0.000000] riscv: base ISA extensions acim +[ 0.000000] riscv: ELF capabilities acim +[ 0.000000] percpu: Embedded 21 pages/cpu s48872 r8192 d28952 u86016 +[ 0.000000] Kernel command line: earlycon=uart8250,mmio32,0x60010000 keep_bootcon console=ttyS0 no4lvl rdinit=/sbin/init +[ 0.000000] Dentry cache hash table entries: 32768 (order: 6, 262144 bytes, linear) +[ 0.000000] Inode-cache hash table entries: 16384 (order: 5, 131072 bytes, linear) +[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 49152 +[ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off +[ 0.000000] Virtual kernel memory layout: +[ 0.000000] fixmap : 0xffffffc4fea00000 - 0xffffffc4ff000000 (6144 kB) +[ 0.000000] pci io : 0xffffffc4ff000000 - 0xffffffc500000000 ( 16 MB) +[ 0.000000] vmemmap : 0xffffffc500000000 - 0xffffffc600000000 (4096 MB) +[ 0.000000] vmalloc : 0xffffffc600000000 - 0xffffffd600000000 ( 64 GB) +[ 0.000000] modules : 0xffffffff01f8a000 - 0xffffffff80000000 (2016 MB) +[ 0.000000] lowmem : 0xffffffd600000000 - 0xffffffd60c000000 ( 192 MB) +[ 0.000000] kernel : 0xffffffff80000000 - 0xffffffffffffffff (2047 MB) +[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1 +[ 0.000000] rcu: Hierarchical RCU implementation. +[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=64 to nr_cpu_ids=1. +[ 0.000000] rcu: RCU debug extended QS entry/exit. +[ 0.000000] Tracing variant of Tasks RCU enabled. +[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies. +[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=1 +[ 0.000000] RCU Tasks Trace: Setting shift to 0 and lim to 1 rcu_task_cb_adjust=1 rcu_task_cpu_ids=1. +[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0 +[ 0.000000] riscv-intc: 64 local interrupts mapped +[ 0.000000] riscv: providing IPIs using SBI IPI extension +[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention. +[ 0.000000] clocksource: riscv_clocksource: mask: 0xffffffffffffffff max_cycles: 0x1623fa770, max_idle_ns: 3526361617904 ns +[ 0.000034] sched_clock: 64 bits at 750kHz, resolution 1333ns, wraps every 4398046510524ns +[ 0.003334] Console: colour dummy device 80x25 +[ 0.004323] Calibrating delay loop (skipped), value calculated using timer frequency.. 1.50 BogoMIPS (lpj=3000) +[ 0.005307] pid_max: default: 32768 minimum: 301 +[ 0.007265] LSM: initializing lsm=capability +[ 0.011227] Mount-cache hash table entries: 512 (order: 0, 4096 bytes, linear) +[ 0.011838] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes, linear) +[ 0.077230] riscv: ELF compat mode unsupported +[ 0.077451] ASID allocator disabled (0 bits) +[ 0.083475] rcu: Hierarchical SRCU implementation. +[ 0.083838] rcu: Max phase no-delay instances is 1000. +[ 0.104582] smp: Bringing up secondary CPUs ... +[ 0.105098] smp: Brought up 1 node, 1 CPU +[ 0.106775] Memory: 140784K/196608K available (9655K kernel code, 5038K rwdata, 4096K rodata, 12443K init, 473K bss, 54140K reserved, 0K cma-reserved) +[ 0.117893] devtmpfs: initialized +[ 0.145762] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns +[ 0.146830] futex hash table entries: 256 (order: 2, 16384 bytes, linear) +[ 0.151665] pinctrl core: initialized pinctrl subsystem +[ 0.181897] NET: Registered PF_NETLINK/PF_ROUTE protocol family +[ 0.197030] DMA: preallocated 128 KiB GFP_KERNEL pool for atomic allocations +[ 0.197970] DMA: preallocated 128 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations +[ 0.199906] audit: initializing netlink subsys (disabled) +[ 0.215093] thermal_sys: Registered thermal governor 'step_wise' +[ 0.216058] audit: type=2000 audit(0.188:1): state=initialized audit_enabled=0 res=1 +[ 0.217655] cpuidle: using governor menu +[ 0.284350] cpu0: Ratio of byte access time to unaligned word access is 0.01, unaligned accesses are slow +[ 0.322494] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages +[ 0.323283] HugeTLB: 28 KiB vmemmap can be freed for a 2.00 MiB page +[ 0.344121] iommu: Default domain type: Translated +[ 0.344869] iommu: DMA domain TLB invalidation policy: strict mode +[ 0.357323] SCSI subsystem initialized +[ 0.368282] usbcore: registered new interface driver usbfs +[ 0.369429] usbcore: registered new interface driver hub +[ 0.370899] usbcore: registered new device driver usb +[ 0.386974] Advanced Linux Sound Architecture Driver Initialized. +[ 0.404923] vgaarb: loaded +[ 0.412397] clocksource: Switched to clocksource riscv_clocksource +[ 0.692473] NET: Registered PF_INET protocol family +[ 0.696949] IP idents hash table entries: 4096 (order: 3, 32768 bytes, linear) +[ 0.718779] tcp_listen_portaddr_hash hash table entries: 128 (order: 0, 4096 bytes, linear) +[ 0.719550] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear) +[ 0.720854] TCP established hash table entries: 2048 (order: 2, 16384 bytes, linear) +[ 0.721927] TCP bind hash table entries: 2048 (order: 5, 131072 bytes, linear) +[ 0.726069] TCP: Hash tables configured (established 2048 bind 2048) +[ 0.728565] UDP hash table entries: 256 (order: 2, 24576 bytes, linear) +[ 0.729781] UDP-Lite hash table entries: 256 (order: 2, 24576 bytes, linear) +[ 0.734102] NET: Registered PF_UNIX/PF_LOCAL protocol family +[ 0.750814] RPC: Registered named UNIX socket transport module. +[ 0.751231] RPC: Registered udp transport module. +[ 0.751538] RPC: Registered tcp transport module. +[ 0.751822] RPC: Registered tcp-with-tls transport module. +[ 0.752621] RPC: Registered tcp NFSv4.1 backchannel transport module. +[ 0.753082] PCI: CLS 0 bytes, default 64 +[ 0.814967] workingset: timestamp_bits=46 max_order=16 bucket_order=0 +[ 0.851591] NFS: Registering the id_resolver key type +[ 0.852994] Key type id_resolver registered +[ 0.853373] Key type id_legacy registered +[ 0.854413] nfs4filelayout_init: NFSv4 File Layout Driver Registering... +[ 0.854858] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering... +[ 0.859507] 9p: Installing v9fs 9p2000 file system support +[ 0.866017] NET: Registered PF_ALG protocol family +[ 0.867798] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 245) +[ 0.889642] io scheduler mq-deadline registered +[ 0.890066] io scheduler kyber registered +[ 0.891330] io scheduler bfq registered +[ 0.918201] riscv-plic: interrupt-controller@c000000: mapped 8 interrupts with 1 handlers for 2 contexts. diff --git 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 \ No newline at end of file diff --git a/examples/dashboard/demo/demo_trace_rocket2.bin b/examples/dashboard/demo/demo_trace_rocket2.bin new file mode 100644 index 0000000..dc16a0c Binary files /dev/null and b/examples/dashboard/demo/demo_trace_rocket2.bin differ diff --git a/examples/dashboard/demo/demo_trace_rocket64.bin b/examples/dashboard/demo/demo_trace_rocket64.bin new file mode 100644 index 0000000..573db93 Binary files /dev/null and b/examples/dashboard/demo/demo_trace_rocket64.bin differ diff --git a/examples/dashboard/demo/demo_trace_trio.bin b/examples/dashboard/demo/demo_trace_trio.bin new file mode 100644 index 0000000..84ff4d2 Binary files /dev/null and b/examples/dashboard/demo/demo_trace_trio.bin differ diff --git a/examples/tgc5b_soc/prog/hello_trace.hex b/examples/dashboard/demo/hello_trace.hex similarity index 100% rename from examples/tgc5b_soc/prog/hello_trace.hex rename to examples/dashboard/demo/hello_trace.hex diff --git a/examples/dashboard/demo/mbv.pcinfo b/examples/dashboard/demo/mbv.pcinfo new file mode 100644 index 0000000..9545714 --- /dev/null +++ b/examples/dashboard/demo/mbv.pcinfo @@ -0,0 +1,82 @@ +0x0,L4 +0x4,L4 +0x8,L4 +0xC,L4 +0x10,BD4,0x20 +0x14,L4 +0x18,L4 +0x1C,JD4,0x10 +0x20,L4 +0x24,L4 +0x28,L4 +0x2C,L4 +0x30,L4 +0x34,CD4,0xF0 +0x38,JD4,0x38 +0x40,L4 +0x44,L4 +0x48,L4 +0x4C,L4 +0x50,L4 +0x54,L4 +0x58,L4 +0x5C,L4 +0x60,L4 +0x64,L4 +0x68,L4 +0x6C,L4 +0x70,L4 +0x74,L4 +0x78,L4 +0x7C,L4 +0x80,L4 +0x84,L4 +0x88,BD4,0x9C +0x8C,L4 +0x90,L4 +0x94,L4 +0x98,JD4,0xA0 +0x9C,CD4,0xE8 +0xA0,L4 +0xA4,L4 +0xA8,L4 +0xAC,L4 +0xB0,L4 +0xB4,L4 +0xB8,L4 +0xBC,L4 +0xC0,L4 +0xC4,L4 +0xC8,L4 +0xCC,L4 +0xD0,L4 +0xD4,L4 +0xD8,L4 +0xDC,L4 +0xE0,L4 +0xE4,JI4 +0xE8,R4 +0xEC,L2 +0xF0,L4 +0xF4,L4 +0xF8,L4 +0xFC,L4 +0x100,L4 +0x104,L4 +0x108,L4 +0x10C,L4 +0x110,L4 +0x114,BD4,0x128 +0x118,L4 +0x11C,L4 +0x120,BD4,0x12C +0x124,JI4 +0x128,L4 +0x12C,L4 +0x130,L4 +0x134,L4 +0x138,L4 +0x13C,L4 +0x140,BD4,0x134 +0x144,L4 +0x148,R4 diff --git a/examples/dashboard/demo/raw/con_cva6_linux.bin b/examples/dashboard/demo/raw/con_cva6_linux.bin new file mode 100644 index 0000000..831598a --- /dev/null +++ b/examples/dashboard/demo/raw/con_cva6_linux.bin @@ -0,0 +1,144 @@ + +OpenSBI 2025.02 + ____ _____ ____ _____ + / __ \ / ____| _ \_ _| + | | | |_ __ ___ _ __ | (___ | |_) || | + | | | | '_ \ / _ \ '_ \ \___ \| _ < | | + | |__| | |_) | __/ | | |____) | |_) || |_ + \____/| .__/ \___|_| |_|_____/|____/_____| + | | + |_| + +Platform Name : Accemic CVA6 C-Trace Demonstrator (KV260 PL) +Platform Features : medeleg +Platform HART Count : 1 +Platform IPI Device : aclint-mswi +Platform Timer Device : aclint-mtimer @ 1000000Hz +Platform Console Device : uart8250 +Platform HSM Device : --- +Platform PMU Device : --- +Platform Reboot Device : --- +Platform Shutdown Device : --- +Platform Suspend Device : --- +Platform CPPC Device : --- +Firmware Base : 0x64000000 +Firmware Size : 321 KB +Firmware RW Offset : 0x40000 +Firmware RW Size : 65 KB +Firmware Heap Offset : 0x47000 +Firmware Heap Size : 37 KB (total), 2 KB (reserved), 10 KB (used), 24 KB (free) +Firmware Scratch Size : 4096 B (total), 252 B (used), 3844 B (free) +Runtime SBI Version : 2.0 +Standard SBI Extensions : time,rfnc,ipi,base,hsm,pmu,dbcn,legacy +Experimental SBI Extensions : fwft,sse + +Domain0 Name : root +Domain0 Boot HART : 0 +Domain0 HARTs : 0* +Domain0 Region00 : 0x10000000-0x10000fff M: (I,R,W) S/U: (R,W) +Domain0 Region01 : 0x02000000-0x0200ffff M: (I,R,W) S/U: () +Domain0 Region02 : 0x64040000-0x6405ffff M: (R,W) S/U: () +Domain0 Region03 : 0x64000000-0x6403ffff M: (R,X) S/U: () +Domain0 Region04 : 0x00000000-0xffffffff M: () S/U: (R,W,X) +Domain0 Next Address : 0x64400000 +Domain0 Next Arg1 : 0x66200000 +Domain0 Next Mode : S-mode +Domain0 SysReset : yes +Domain0 SysSuspend : yes + +Boot HART ID : 0 +Boot HART Domain : root +Boot HART Priv Version : v1.12 +Boot HART Base ISA : rv32ima +Boot HART ISA Extensions : none +Boot HART PMP Count : 0 +Boot HART PMP Granularity : 0 bits +Boot HART PMP Address Bits : 0 +Boot HART MHPM Info : 0 (0x00000000) +Boot HART Debug Triggers : 0 triggers +Boot HART MIDELEG : 0x00000222 +Boot HART MEDELEG : 0x0000b109 +[ 0.000000] Linux version 6.12.19 (aweiss@panama) (riscv32-buildroot-linux-gnu-gcc.br_real (Buildroot 2025.02) 13.3.0, GNU ld (GNU Binutils) 2.43.1) #3 SMP Mon Jul 27 04:10:39 CEST 2026 +[ 0.000000] OF: fdt: Ignoring memory range 0x64000000 - 0x64400000 +[ 0.000000] Machine model: Accemic CVA6 C-Trace Demonstrator (KV260 PL) +[ 0.000000] SBI specification v2.0 detected +[ 0.000000] SBI implementation ID=0x1 Version=0x10006 +[ 0.000000] SBI TIME extension detected +[ 0.000000] SBI IPI extension detected +[ 0.000000] SBI RFENCE extension detected +[ 0.000000] SBI DBCN extension detected +[ 0.000000] earlycon: uart8250 at MMIO32 0x10000000 (options '') +[ 0.000000] printk: legacy bootconsole [uart8250] enabled +[ 0.000000] printk: debug: skip boot console de-registration. +[ 0.000000] OF: reserved mem: 0x64000000..0x6403ffff (256 KiB) nomap non-reusable mmode_resv1@64000000 +[ 0.000000] OF: reserved mem: 0x64040000..0x6405ffff (128 KiB) nomap non-reusable mmode_resv0@64040000 +[ 0.000000] Zone ranges: +[ 0.000000] Normal [mem 0x0000000064400000-0x000000006fffffff] +[ 0.000000] Movable zone start for each node +[ 0.000000] Early memory node ranges +[ 0.000000] node 0: [mem 0x0000000064400000-0x000000006fffffff] +[ 0.000000] Initmem setup node 0 [mem 0x0000000064400000-0x000000006fffffff] +[ 0.000000] On node 0, zone Normal: 17408 pages in unavailable ranges +[ 0.000000] SBI HSM extension detected +[ 0.000000] riscv: base ISA extensions aim +[ 0.000000] riscv: ELF capabilities aim +[ 0.000000] percpu: Embedded 17 pages/cpu s37208 r8192 d24232 u69632 +[ 0.000000] Kernel command line: earlycon=uart8250,mmio32,0x10000000 keep_bootcon console=ttyS0 rdinit=/sbin/init +[ 0.000000] Dentry cache hash table entries: 32768 (order: 5, 131072 bytes, linear) +[ 0.000000] Inode-cache hash table entries: 16384 (order: 4, 65536 bytes, linear) +[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 48128 +[ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off +[ 0.000000] Virtual kernel memory layout: +[ 0.000000] fixmap : 0x9c800000 - 0x9d000000 (8192 kB) +[ 0.000000] pci io : 0x9d000000 - 0x9e000000 ( 16 MB) +[ 0.000000] vmemmap : 0x9e000000 - 0xa0000000 ( 32 MB) +[ 0.000000] vmalloc : 0xa0000000 - 0xc0000000 ( 512 MB) +[ 0.000000] lowmem : 0xc0000000 - 0xcbc00000 ( 188 MB) +[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1 +[ 0.000000] rcu: Hierarchical RCU implementation. +[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=64 to nr_cpu_ids=1. +[ 0.000000] rcu: RCU debug extended QS entry/exit. +[ 0.000000] Tracing variant of Tasks RCU enabled. +[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies. +[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=1 +[ 0.000000] RCU Tasks Trace: Setting shift to 0 and lim to 1 rcu_task_cb_adjust=1 rcu_task_cpu_ids=1. +[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0 +[ 0.000000] riscv-intc: 32 local interrupts mapped +[ 0.000000] riscv: providing IPIs using SBI IPI extension +[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention. +[ 0.000000] clocksource: riscv_clocksource: mask: 0xffffffffffffffff max_cycles: 0x1d854df40, max_idle_ns: 3526361616960 ns +[ 0.000121] sched_clock: 64 bits at 1000kHz, resolution 1000ns, wraps every 2199023255500ns +[ 0.008352] Console: colour dummy device 80x25 +[ 0.011124] Calibrating delay loop (skipped), value calculated using timer frequency.. 2.00 BogoMIPS (lpj=4000) +[ 0.012628] pid_max: default: 32768 minimum: 301 +[ 0.017797] LSM: initializing lsm=capability +[ 0.026487] Mount-cache hash table entries: 1024 (order: 0, 4096 bytes, linear) +[ 0.027893] Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes, linear) +[ 0.182391] ASID allocator disabled (1 bits) +[ 0.198526] rcu: Hierarchical SRCU implementation. +[ 0.199364] rcu: Max phase no-delay instances is 1000. +[ 0.255015] smp: Bringing up secondary CPUs ... +[ 0.256180] smp: Brought up 1 node, 1 CPU +[ 0.261333] Memory: 146920K/192512K available (12835K kernel code, 8940K rwdata, 4096K rodata, 12352K init, 332K bss, 44876K reserved, 0K cma-reserved) +[ 0.285192] devtmpfs: initialized +[ 0.360580] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns +[ 0.363013] futex hash table entries: 256 (order: 2, 16384 bytes, linear) +[ 0.373969] pinctrl core: initialized pinctrl subsystem +[ 0.455811] NET: Registered PF_NETLINK/PF_ROUTE protocol family +[ 0.501108] DMA: preallocated 128 KiB GFP_KERNEL pool for atomic allocations +[ 0.504763] audit: initializing netlink subsys (disabled) +[ 0.548566] thermal_sys: Registered thermal governor 'step_wise' +[ 0.551190] audit: type=2000 audit(0.428:1): state=initialized audit_enabled=0 res=1 +[ 0.555287] cpuidle: using governor menu +[ 0.778415] cpu0: Ratio of byte access time to unaligned word access is 0.01, unaligned accesses are slow +[ 0.870745] HugeTLB: registered 4.00 MiB page size, pre-allocated 0 pages +[ 0.871746] HugeTLB: 0 KiB vmemmap can be freed for a 4.00 MiB page +[ 0.921980] iommu: Default domain type: Translated +[ 0.923751] iommu: DMA domain TLB invalidation policy: strict mode +[ 0.948544] SCSI subsystem initialized +[ 0.974281] usbcore: registered new interface driver usbfs +[ 0.977889] usbcore: registered new interface driver hub +[ 0.980536] usbcore: registered new device driver usb +[ 1.024230] Advanced Linux Sound Architecture Driver Initialized. +[ 1.074681] vgaarb: loaded +[ 1.091248] clocksource: Switched to clocksource riscv_clocksource diff --git a/examples/dashboard/demo/raw/con_cva6_linux64.bin b/examples/dashboard/demo/raw/con_cva6_linux64.bin new file mode 100644 index 0000000..07657c5 --- /dev/null +++ b/examples/dashboard/demo/raw/con_cva6_linux64.bin @@ -0,0 +1,179 @@ + +OpenSBI v1.6 + ____ _____ ____ _____ + / __ \ / ____| _ \_ _| + | | | |_ __ ___ _ __ | (___ | |_) || | + | | | | '_ \ / _ \ '_ \ \___ \| _ < | | + | |__| | |_) | __/ | | |____) | |_) || |_ + \____/| .__/ \___|_| |_|_____/|____/_____| + | | + |_| + +Platform Name : Accemic CVA6 RV64 CTTE Demonstrator (KV260 PL) +Platform Features : medeleg +Platform HART Count : 1 +Platform IPI Device : aclint-mswi +Platform Timer Device : aclint-mtimer @ 1000000Hz +Platform Console Device : uart8250 +Platform HSM Device : --- +Platform PMU Device : --- +Platform Reboot Device : --- +Platform Shutdown Device : --- +Platform Suspend Device : --- +Platform CPPC Device : --- +Firmware Base : 0x64000000 +Firmware Size : 325 KB +Firmware RW Offset : 0x40000 +Firmware RW Size : 69 KB +Firmware Heap Offset : 0x48000 +Firmware Heap Size : 37 KB (total), 2 KB (reserved), 11 KB (used), 23 KB (free) +Firmware Scratch Size : 4096 B (total), 424 B (used), 3672 B (free) +Runtime SBI Version : 2.0 +Standard SBI Extensions : time,rfnc,ipi,base,hsm,pmu,dbcn,legacy +Experimental SBI Extensions : fwft,sse + +Domain0 Name : root +Domain0 Boot HART : 0 +Domain0 HARTs : 0* +Domain0 Region00 : 0x0000000010000000-0x0000000010000fff M: (I,R,W) S/U: (R,W) +Domain0 Region01 : 0x0000000002000000-0x000000000200ffff M: (I,R,W) S/U: () +Domain0 Region02 : 0x0000000064040000-0x000000006405ffff M: (R,W) S/U: () +Domain0 Region03 : 0x0000000064000000-0x000000006403ffff M: (R,X) S/U: () +Domain0 Region04 : 0x0000000000000000-0xffffffffffffffff M: () S/U: (R,W,X) +Domain0 Next Address : 0x0000000064200000 +Domain0 Next Arg1 : 0x0000000066200000 +Domain0 Next Mode : S-mode +Domain0 SysReset : yes +Domain0 SysSuspend : yes + +Boot HART ID : 0 +Boot HART Domain : root +Boot HART Priv Version : v1.12 +Boot HART Base ISA : rv64imac +Boot HART ISA Extensions : zihpm +Boot HART PMP Count : 8 +Boot HART PMP Granularity : 3 bits +Boot HART PMP Address Bits : 54 +Boot HART MHPM Info : 6 (0x000001f8) +Boot HART Debug Triggers : 0 triggers +Boot HART MIDELEG : 0x0000000000000222 +Boot HART MEDELEG : 0x000000000000b109 +[ 0.000000] Linux version 6.12.19 (aweiss@panama) (riscv64-buildroot-linux-gnu-gcc.br_real (Buildroot 2025.02) 13.3.0, GNU ld (GNU Binutils) 2.43.1) #4 SMP Sat Aug 8 08:11:20 CEST 2026 +[ 0.000000] Machine model: Accemic CVA6 RV64 CTTE Demonstrator (KV260 PL) +[ 0.000000] SBI specification v2.0 detected +[ 0.000000] SBI implementation ID=0x1 Version=0x10006 +[ 0.000000] SBI TIME extension detected +[ 0.000000] SBI IPI extension detected +[ 0.000000] SBI RFENCE extension detected +[ 0.000000] SBI DBCN extension detected +[ 0.000000] earlycon: uart8250 at MMIO32 0x0000000010000000 (options '') +[ 0.000000] printk: legacy bootconsole [uart8250] enabled +[ 0.000000] printk: debug: skip boot console de-registration. +[ 0.000000] Disabled 4-level and 5-level paging +[ 0.000000] OF: reserved mem: 0x0000000064000000..0x000000006403ffff (256 KiB) nomap non-reusable mmode_resv1@64000000 +[ 0.000000] OF: reserved mem: 0x0000000064040000..0x000000006405ffff (128 KiB) nomap non-reusable mmode_resv0@64040000 +[ 0.000000] Zone ranges: +[ 0.000000] DMA32 [mem 0x0000000064000000-0x000000006fffffff] +[ 0.000000] Normal empty +[ 0.000000] Movable zone start for each node +[ 0.000000] Early memory node ranges +[ 0.000000] node 0: [mem 0x0000000064000000-0x000000006405ffff] +[ 0.000000] node 0: [mem 0x0000000064060000-0x000000006fffffff] +[ 0.000000] Initmem setup node 0 [mem 0x0000000064000000-0x000000006fffffff] +[ 0.000000] On node 0, zone DMA32: 16384 pages in unavailable ranges +[ 0.000000] SBI HSM extension detected +[ 0.000000] riscv: base ISA extensions acim +[ 0.000000] riscv: ELF capabilities acim +[ 0.000000] percpu: Embedded 21 pages/cpu s48872 r8192 d28952 u86016 +[ 0.000000] Kernel command line: earlycon=uart8250,mmio32,0x10000000 keep_bootcon console=ttyS0 no4lvl rdinit=/sbin/init +[ 0.000000] Dentry cache hash table entries: 32768 (order: 6, 262144 bytes, linear) +[ 0.000000] Inode-cache hash table entries: 16384 (order: 5, 131072 bytes, linear) +[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 49152 +[ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off +[ 0.000000] Virtual kernel memory layout: +[ 0.000000] fixmap : 0xffffffc4fea00000 - 0xffffffc4ff000000 (6144 kB) +[ 0.000000] pci io : 0xffffffc4ff000000 - 0xffffffc500000000 ( 16 MB) +[ 0.000000] vmemmap : 0xffffffc500000000 - 0xffffffc600000000 (4096 MB) +[ 0.000000] vmalloc : 0xffffffc600000000 - 0xffffffd600000000 ( 64 GB) +[ 0.000000] modules : 0xffffffff01d8a000 - 0xffffffff80000000 (2018 MB) +[ 0.000000] lowmem : 0xffffffd600000000 - 0xffffffd60c000000 ( 192 MB) +[ 0.000000] kernel : 0xffffffff80000000 - 0xffffffffffffffff (2047 MB) +[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1 +[ 0.000000] rcu: Hierarchical RCU implementation. +[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=64 to nr_cpu_ids=1. +[ 0.000000] rcu: RCU debug extended QS entry/exit. +[ 0.000000] Tracing variant of Tasks RCU enabled. +[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies. +[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=1 +[ 0.000000] RCU Tasks Trace: Setting shift to 0 and lim to 1 rcu_task_cb_adjust=1 rcu_task_cpu_ids=1. +[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0 +[ 0.000000] riscv-intc: 64 local interrupts mapped +[ 0.000000] riscv: providing IPIs using SBI IPI extension +[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention. +[ 0.000000] clocksource: riscv_clocksource: mask: 0xffffffffffffffff max_cycles: 0x1d854df40, max_idle_ns: 3526361616960 ns +[ 0.000060] sched_clock: 64 bits at 1000kHz, resolution 1000ns, wraps every 2199023255500ns +[ 0.005030] Console: colour dummy device 80x25 +[ 0.007002] Calibrating delay loop (skipped), value calculated using timer frequency.. 2.00 BogoMIPS (lpj=4000) +[ 0.008020] pid_max: default: 32768 minimum: 301 +[ 0.011118] LSM: initializing lsm=capability +[ 0.016967] Mount-cache hash table entries: 512 (order: 0, 4096 bytes, linear) +[ 0.017929] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes, linear) +[ 0.115906] riscv: ELF compat mode unsupported +[ 0.116711] ASID allocator using 16 bits (65536 entries) +[ 0.126912] rcu: Hierarchical SRCU implementation. +[ 0.127507] rcu: Max phase no-delay instances is 1000. +[ 0.161921] smp: Bringing up secondary CPUs ... +[ 0.162806] smp: Brought up 1 node, 1 CPU +[ 0.166481] Memory: 142832K/196608K available (9655K kernel code, 5102K rwdata, 4096K rodata, 10331K init, 473K bss, 52092K reserved, 0K cma-reserved) +[ 0.183627] devtmpfs: initialized +[ 0.229149] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns +[ 0.230369] futex hash table entries: 256 (order: 2, 16384 bytes, linear) +[ 0.238513] pinctrl core: initialized pinctrl subsystem +[ 0.285129] NET: Registered PF_NETLINK/PF_ROUTE protocol family +[ 0.310892] DMA: preallocated 128 KiB GFP_KERNEL pool for atomic allocations +[ 0.312984] DMA: preallocated 128 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations +[ 0.315338] audit: initializing netlink subsys (disabled) +[ 0.340436] thermal_sys: Registered thermal governor 'step_wise' +[ 0.341850] audit: type=2000 audit(0.288:1): state=initialized audit_enabled=0 res=1 +[ 0.344324] cpuidle: using governor menu +[ 0.459776] cpu0: Ratio of byte access time to unaligned word access is 0.00, unaligned accesses are slow +[ 0.516168] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages +[ 0.516870] HugeTLB: 28 KiB vmemmap can be freed for a 2.00 MiB page +[ 0.550216] iommu: Default domain type: Translated +[ 0.550827] iommu: DMA domain TLB invalidation policy: strict mode +[ 0.571540] SCSI subsystem initialized +[ 0.587114] usbcore: registered new interface driver usbfs +[ 0.589416] usbcore: registered new interface driver hub +[ 0.591182] usbcore: registered new device driver usb +[ 0.617130] Advanced Linux Sound Architecture Driver Initialized. +[ 0.649978] vgaarb: loaded +[ 0.661004] clocksource: Switched to clocksource riscv_clocksource +[ 1.106276] NET: Registered PF_INET protocol family +[ 1.113563] IP idents hash table entries: 4096 (order: 3, 32768 bytes, linear) +[ 1.141839] tcp_listen_portaddr_hash hash table entries: 128 (order: 0, 4096 bytes, linear) +[ 1.143039] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear) +[ 1.144095] TCP established hash table entries: 2048 (order: 2, 16384 bytes, linear) +[ 1.146149] TCP bind hash table entries: 2048 (order: 5, 131072 bytes, linear) +[ 1.150891] TCP: Hash tables configured (established 2048 bind 2048) +[ 1.154806] UDP hash table entries: 256 (order: 2, 24576 bytes, linear) +[ 1.157075] UDP-Lite hash table entries: 256 (order: 2, 24576 bytes, linear) +[ 1.162516] NET: Registered PF_UNIX/PF_LOCAL protocol family +[ 1.189956] RPC: Registered named UNIX socket transport module. +[ 1.190640] RPC: Registered udp transport module. +[ 1.191150] RPC: Registered tcp transport module. +[ 1.191641] RPC: Registered tcp-with-tls transport module. +[ 1.192162] RPC: Registered tcp NFSv4.1 backchannel transport module. +[ 1.193557] PCI: CLS 0 bytes, default 64 +[ 1.267008] workingset: timestamp_bits=46 max_order=16 bucket_order=0 +[ 1.312149] NFS: Registering the id_resolver key type +[ 1.314698] Key type id_resolver registered +[ 1.315295] Key type id_legacy registered +[ 1.317421] nfs4filelayout_init: NFSv4 File Layout Driver Registering... +[ 1.318170] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering... +[ 1.345406] 9p: Installing v9fs 9p2000 file system support +[ 1.355028] NET: Registered PF_ALG protocol family +[ 1.358302] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 245) +[ 1.386152] io scheduler mq-deadline registered +[ 1.386843] io scheduler kyber registered +[ 1.389130] io scheduler bfq registered + \ No newline at end of file diff --git a/examples/dashboard/demo/raw/con_rocket2.bin b/examples/dashboard/demo/raw/con_rocket2.bin new file mode 100644 index 0000000..c44d7b4 --- /dev/null +++ b/examples/dashboard/demo/raw/con_rocket2.bin @@ -0,0 +1,243 @@ + +OpenSBI v1.6 + ____ _____ ____ _____ + / __ \ / ____| _ \_ _| + | | | |_ __ ___ _ __ | (___ | |_) || | + | | | | '_ \ / _ \ '_ \ \___ \| _ < | | + | |__| | |_) | __/ | | |____) | |_) || |_ + \____/| .__/ \___|_| |_|_____/|____/_____| + | | + |_| + +Platform Name : Accemic Rocket64t2 RV64 CTTE Demonstrator, 2 Harts (KV260 PL) +Platform Features : medeleg +Platform HART Count : 2 +Platform IPI Device : aclint-mswi +Platform Timer Device : aclint-mtimer @ 750000Hz +Platform Console Device : uart8250 +Platform HSM Device : --- +Platform PMU Device : --- +Platform Reboot Device : --- +Platform Shutdown Device : --- +Platform Suspend Device : --- +Platform CPPC Device : --- +Firmware Base : 0x80000000 +Firmware Size : 337 KB +Firmware RW Offset : 0x40000 +Firmware RW Size : 81 KB +Firmware Heap Offset : 0x4a000 +Firmware Heap Size : 41 KB (total), 2 KB (reserved), 13 KB (used), 25 KB (free) +Firmware Scratch Size : 4096 B (total), 440 B (used), 3656 B (free) +Runtime SBI Version : 2.0 +Standard SBI Extensions : time,rfnc,ipi,base,hsm,pmu,dbcn,legacy +Experimental SBI Extensions : fwft,dbtr,sse + +Domain0 Name : root +Domain0 Boot HART : 0 +Domain0 HARTs : 0*,1* +Domain0 Region00 : 0x0000000060010000-0x0000000060010fff M: (I,R,W) S/U: (R,W) +Domain0 Region01 : 0x0000000002000000-0x000000000200ffff M: (I,R,W) S/U: () +Domain0 Region02 : 0x0000000080040000-0x000000008005ffff M: (R,W) S/U: () +Domain0 Region03 : 0x0000000080000000-0x000000008003ffff M: (R,X) S/U: () +Domain0 Region04 : 0x000000000c000000-0x000000000fffffff M: (I,R,W) S/U: (R,W) +Domain0 Region05 : 0x0000000000000000-0xffffffffffffffff M: () S/U: (R,W,X) +Domain0 Next Address : 0x0000000080200000 +Domain0 Next Arg1 : 0x0000000082200000 +Domain0 Next Mode : S-mode +Domain0 SysReset : yes +Domain0 SysSuspend : yes + +Boot HART ID : 0 +Boot HART Domain : root +Boot HART Priv Version : v1.12 +Boot HART Base ISA : rv64imacx +Boot HART ISA Extensions : sdtrig +Boot HART PMP Count : 8 +Boot HART PMP Granularity : 2 bits +Boot HART PMP Address Bits : 32 +Boot HART MHPM Info : 0 (0x00000000) +Boot HART Debug Triggers : 8 triggers +Boot HART MIDELEG : 0x0000000000000222 +Boot HART MEDELEG : 0x000000000000b109 +[ 0.000000] Linux version 6.12.19 (aweiss@panama) (riscv64-buildroot-linux-gnu-gcc.br_real (Buildroot 2025.02) 13.3.0, GNU ld (GNU Binutils) 2.43.1) #6 SMP Sun Aug 9 16:15:17 CEST 2026 +[ 0.000000] Machine model: Accemic Rocket64t2 RV64 CTTE Demonstrator, 2 Harts (KV260 PL) +[ 0.000000] SBI specification v2.0 detected +[ 0.000000] SBI implementation ID=0x1 Version=0x10006 +[ 0.000000] SBI TIME extension detected +[ 0.000000] SBI IPI extension detected +[ 0.000000] SBI RFENCE extension detected +[ 0.000000] SBI DBCN extension detected +[ 0.000000] earlycon: uart8250 at MMIO32 0x0000000060010000 (options '') +[ 0.000000] printk: legacy bootconsole [uart8250] enabled +[ 0.000000] printk: debug: skip boot console de-registration. +[ 0.000000] Disabled 4-level and 5-level paging +[ 0.000000] OF: reserved mem: 0x0000000080000000..0x000000008003ffff (256 KiB) nomap non-reusable mmode_resv1@80000000 +[ 0.000000] OF: reserved mem: 0x0000000080040000..0x000000008005ffff (128 KiB) nomap non-reusable mmode_resv0@80040000 +[ 0.000000] Zone ranges: +[ 0.000000] DMA32 [mem 0x0000000080000000-0x000000008bffffff] +[ 0.000000] Normal empty +[ 0.000000] Movable zone start for each node +[ 0.000000] Early memory node ranges +[ 0.000000] node 0: [mem 0x0000000080000000-0x000000008005ffff] +[ 0.000000] node 0: [mem 0x0000000080060000-0x000000008bffffff] +[ 0.000000] Initmem setup node 0 [mem 0x0000000080000000-0x000000008bffffff] +[ 0.000000] On node 0, zone DMA32: 16384 pages in unavailable ranges +[ 0.000000] SBI HSM extension detected +[ 0.000000] riscv: base ISA extensions acim +[ 0.000000] riscv: ELF capabilities acim +[ 0.000000] percpu: Embedded 21 pages/cpu s48872 r8192 d28952 u86016 +[ 0.000000] Kernel command line: earlycon=uart8250,mmio32,0x60010000 keep_bootcon console=ttyS0 no4lvl rdinit=/sbin/init +[ 0.000000] Dentry cache hash table entries: 32768 (order: 6, 262144 bytes, linear) +[ 0.000000] Inode-cache hash table entries: 16384 (order: 5, 131072 bytes, linear) +[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 49152 +[ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off +[ 0.000000] Virtual kernel memory layout: +[ 0.000000] fixmap : 0xffffffc4fea00000 - 0xffffffc4ff000000 (6144 kB) +[ 0.000000] pci io : 0xffffffc4ff000000 - 0xffffffc500000000 ( 16 MB) +[ 0.000000] vmemmap : 0xffffffc500000000 - 0xffffffc600000000 (4096 MB) +[ 0.000000] vmalloc : 0xffffffc600000000 - 0xffffffd600000000 ( 64 GB) +[ 0.000000] modules : 0xffffffff01f8a000 - 0xffffffff80000000 (2016 MB) +[ 0.000000] lowmem : 0xffffffd600000000 - 0xffffffd60c000000 ( 192 MB) +[ 0.000000] kernel : 0xffffffff80000000 - 0xffffffffffffffff (2047 MB) +[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=2, Nodes=1 +[ 0.000000] rcu: Hierarchical RCU implementation. +[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=64 to nr_cpu_ids=2. +[ 0.000000] rcu: RCU debug extended QS entry/exit. +[ 0.000000] Tracing variant of Tasks RCU enabled. +[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies. +[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=2 +[ 0.000000] RCU Tasks Trace: Setting shift to 1 and lim to 1 rcu_task_cb_adjust=1 rcu_task_cpu_ids=2. +[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0 +[ 0.000000] riscv-intc: 64 local interrupts mapped +[ 0.000000] riscv: providing IPIs using SBI IPI extension +[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention. +[ 0.000000] clocksource: riscv_clocksource: mask: 0xffffffffffffffff max_cycles: 0x1623fa770, max_idle_ns: 3526361617904 ns +[ 0.000036] sched_clock: 64 bits at 750kHz, resolution 1333ns, wraps every 4398046510524ns +[ 0.003540] Console: colour dummy device 80x25 +[ 0.004565] Calibrating delay loop (skipped), value calculated using timer frequency.. 1.50 BogoMIPS (lpj=3000) +[ 0.005533] pid_max: default: 32768 minimum: 301 +[ 0.007446] LSM: initializing lsm=capability +[ 0.011305] Mount-cache hash table entries: 512 (order: 0, 4096 bytes, linear) +[ 0.011911] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes, linear) +[ 0.074065] riscv: ELF compat mode unsupported +[ 0.074283] ASID allocator disabled (0 bits) +[ 0.079453] rcu: Hierarchical SRCU implementation. +[ 0.079814] rcu: Max phase no-delay instances is 1000. +[ 0.090133] Timer migration: 1 hierarchy levels; 8 children per group; 1 crossnode level +[ 0.104641] smp: Bringing up secondary CPUs ... +[ 0.127107] smp: Brought up 1 node, 2 CPUs +[ 0.138873] Memory: 140448K/196608K available (9655K kernel code, 5038K rwdata, 4096K rodata, 12443K init, 473K bss, 54228K reserved, 0K cma-reserved) +[ 0.151217] devtmpfs: initialized +[ 0.185029] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns +[ 0.185707] futex hash table entries: 512 (order: 3, 32768 bytes, linear) +[ 0.191543] pinctrl core: initialized pinctrl subsystem +[ 0.220563] NET: Registered PF_NETLINK/PF_ROUTE protocol family +[ 0.228534] DMA: preallocated 128 KiB GFP_KERNEL pool for atomic allocations +[ 0.229467] DMA: preallocated 128 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations +[ 0.230699] audit: initializing netlink subsys (disabled) +[ 0.237589] audit: type=2000 audit(0.216:1): state=initialized audit_enabled=0 res=1 +[ 0.247414] thermal_sys: Registered thermal governor 'step_wise' +[ 0.249385] cpuidle: using governor menu +[ 0.317121] cpu1: Ratio of byte access time to unaligned word access is 0.01, unaligned accesses are slow +[ 0.376757] cpu0: Ratio of byte access time to unaligned word access is 0.01, unaligned accesses are slow +[ 0.419418] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages +[ 0.419861] HugeTLB: 28 KiB vmemmap can be freed for a 2.00 MiB page +[ 0.441305] iommu: Default domain type: Translated +[ 0.441685] iommu: DMA domain TLB invalidation policy: strict mode +[ 0.455238] SCSI subsystem initialized +[ 0.466529] usbcore: registered new interface driver usbfs +[ 0.467709] usbcore: registered new interface driver hub +[ 0.468859] usbcore: registered new device driver usb +[ 0.485465] Advanced Linux Sound Architecture Driver Initialized. +[ 0.503335] vgaarb: loaded +[ 0.511950] clocksource: Switched to clocksource riscv_clocksource +[ 0.858314] NET: Registered PF_INET protocol family +[ 0.863015] IP idents hash table entries: 4096 (order: 3, 32768 bytes, linear) +[ 0.885846] tcp_listen_portaddr_hash hash table entries: 128 (order: 0, 4096 bytes, linear) +[ 0.886646] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear) +[ 0.888079] TCP established hash table entries: 2048 (order: 2, 16384 bytes, linear) +[ 0.889161] TCP bind hash table entries: 2048 (order: 5, 131072 bytes, linear) +[ 0.893490] TCP: Hash tables configured (established 2048 bind 2048) +[ 0.896278] UDP hash table entries: 256 (order: 2, 24576 bytes, linear) +[ 0.897522] UDP-Lite hash table entries: 256 (order: 2, 24576 bytes, linear) +[ 0.902298] NET: Registered PF_UNIX/PF_LOCAL protocol family +[ 0.916911] RPC: Registered named UNIX socket transport module. +[ 0.917335] RPC: Registered udp transport module. +[ 0.917651] RPC: Registered tcp transport module. +[ 0.917935] RPC: Registered tcp-with-tls transport module. +[ 0.918241] RPC: Registered tcp NFSv4.1 backchannel transport module. +[ 0.918677] PCI: CLS 0 bytes, default 64 +[ 0.949462] workingset: timestamp_bits=46 max_order=16 bucket_order=0 +[ 0.972833] NFS: Registering the id_resolver key type +[ 0.973801] Key type id_resolver registered +[ 0.974181] Key type id_legacy registered +[ 0.975662] nfs4filelayout_init: NFSv4 File Layout Driver Registering... +[ 0.976129] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering... +[ 0.982250] 9p: Installing v9fs 9p2000 file system support +[ 0.989103] NET: Registered PF_ALG protocol family +[ 0.991633] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 245) +[ 0.996998] io scheduler mq-deadline registered +[ 0.997419] io scheduler kyber registered +[ 0.998697] io scheduler bfq registered +[ 1.026771] riscv-plic: interrupt-controller@c000000: mapped 8 interrupts with 2 handlers for 4 contexts. +[ 2.862683] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled +[ 2.904909] of_serial 60010000.serial: error -ENXIO: IRQ index 0 not found +[ 2.912625] printk: legacy console [ttyS0] disabled +[ 2.921377] 60010000.serial: ttyS0 at MMIO 0x60010000 (irq = 0, base_baud = 4687500) is a 16550A +[ 2.922170] printk: legacy console [ttyS0] enabled +[ 2.922170] printk: legacy console [ttyS0] enabled +[ 3.097830] loop: module loaded +[ 3.097830] loop: module loaded +[ 3.172707] e1000e: Intel(R) PRO/1000 Network Driver +[ 3.172707] e1000e: Intel(R) PRO/1000 Network Driver +[ 3.173307] e1000e: Copyright(c) 1999 - 2015 Intel Corporation. +[ 3.173307] e1000e: Copyright(c) 1999 - 2015 Intel Corporation. +[ 3.189618] usbcore: registered new interface driver uas +[ 3.189618] usbcore: registered new interface driver uas +[ 3.191583] usbcore: registered new interface driver usb-storage +[ 3.191583] usbcore: registered new interface driver usb-storage +[ 3.203751] mousedev: PS/2 mouse device common for all mice +[ 3.203751] mousedev: PS/2 mouse device common for all mice +[ 3.222103] sdhci: Secure Digital Host Controller Interface driver +[ 3.222103] sdhci: Secure Digital Host Controller Interface driver +[ 3.222739] sdhci: Copyright(c) Pierre Ossman +[ 3.222739] sdhci: Copyright(c) Pierre Ossman +[ 3.224322] Synopsys Designware Multimedia Card Interface Driver +[ 3.224322] Synopsys Designware Multimedia Card Interface Driver +[ 3.228941] sdhci-pltfm: SDHCI platform and OF driver helper +[ 3.228941] sdhci-pltfm: SDHCI platform and OF driver helper +[ 3.235779] usbcore: registered new interface driver usbhid +[ 3.235779] usbcore: registered new interface driver usbhid +[ 3.236445] usbhid: USB HID core driver +[ 3.236445] usbhid: USB HID core driver +[ 3.241717] riscv-pmu-sbi: SBI PMU extension is available +[ 3.241717] riscv-pmu-sbi: SBI PMU extension is available +[ 3.242639] riscv-pmu-sbi: 16 firmware and 2 hardware counters +[ 3.242639] riscv-pmu-sbi: 16 firmware and 2 hardware counters +[ 3.243681] riscv-pmu-sbi: Perf sampling/filtering is not supported as sscof extension is not available +[ 3.243681] riscv-pmu-sbi: Perf sampling/filtering is not supported as sscof extension is not available +[ 3.272751] NET: Registered PF_INET6 protocol family +[ 3.272751] NET: Registered PF_INET6 protocol family +[ 3.305459] Segment Routing with IPv6 +[ 3.305459] Segment Routing with IPv6 +[ 3.308058] In-situ OAM (IOAM) with IPv6 +[ 3.308058] In-situ OAM (IOAM) with IPv6 +[ 3.310109] sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver +[ 3.310109] sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver +[ 3.324462] NET: Registered PF_PACKET protocol family +[ 3.324462] NET: Registered PF_PACKET protocol family +[ 3.327003] 9pnet: Installing 9P2000 support +[ 3.327003] 9pnet: Installing 9P2000 support +[ 3.329450] Key type dns_resolver registered +[ 3.329450] Key type dns_resolver registered +[ 3.867547] debug_vm_pgtable: [debug_vm_pgtable ]: Validating architecture page table helpers +[ 3.867547] debug_vm_pgtable: [debug_vm_pgtable ]: Validating architecture page table helpers +[ 3.902007] clk: Disabling unused clocks +[ 3.902007] clk: Disabling unused clocks +[ 3.902602] PM: genpd: Disabling unused power domains +[ 3.902602] PM: genpd: Disabling unused power domains +[ 3.903999] ALSA device list: +[ 3.903999] ALSA device list: +[ 3.904501] No soundcards found. +[ 3.904501] No soundcards found. + \ No newline at end of file diff --git a/examples/dashboard/demo/raw/con_rocket64.bin b/examples/dashboard/demo/raw/con_rocket64.bin new file mode 100644 index 0000000..3511440 --- /dev/null +++ b/examples/dashboard/demo/raw/con_rocket64.bin @@ -0,0 +1,181 @@ + +OpenSBI v1.6 + ____ _____ ____ _____ + / __ \ / ____| _ \_ _| + | | | |_ __ ___ _ __ | (___ | |_) || | + | | | | '_ \ / _ \ '_ \ \___ \| _ < | | + | |__| | |_) | __/ | | |____) | |_) || |_ + \____/| .__/ \___|_| |_|_____/|____/_____| + | | + |_| + +Platform Name : Accemic Rocket64t1 RV64 CTTE Demonstrator (KV260 PL) +Platform Features : medeleg +Platform HART Count : 1 +Platform IPI Device : aclint-mswi +Platform Timer Device : aclint-mtimer @ 750000Hz +Platform Console Device : uart8250 +Platform HSM Device : --- +Platform PMU Device : --- +Platform Reboot Device : --- +Platform Shutdown Device : --- +Platform Suspend Device : --- +Platform CPPC Device : --- +Firmware Base : 0x80000000 +Firmware Size : 325 KB +Firmware RW Offset : 0x40000 +Firmware RW Size : 69 KB +Firmware Heap Offset : 0x48000 +Firmware Heap Size : 37 KB (total), 2 KB (reserved), 13 KB (used), 21 KB (free) +Firmware Scratch Size : 4096 B (total), 440 B (used), 3656 B (free) +Runtime SBI Version : 2.0 +Standard SBI Extensions : time,rfnc,ipi,base,hsm,pmu,dbcn,legacy +Experimental SBI Extensions : fwft,dbtr,sse + +Domain0 Name : root +Domain0 Boot HART : 0 +Domain0 HARTs : 0* +Domain0 Region00 : 0x0000000060010000-0x0000000060010fff M: (I,R,W) S/U: (R,W) +Domain0 Region01 : 0x0000000002000000-0x000000000200ffff M: (I,R,W) S/U: () +Domain0 Region02 : 0x0000000080040000-0x000000008005ffff M: (R,W) S/U: () +Domain0 Region03 : 0x0000000080000000-0x000000008003ffff M: (R,X) S/U: () +Domain0 Region04 : 0x000000000c000000-0x000000000fffffff M: (I,R,W) S/U: (R,W) +Domain0 Region05 : 0x0000000000000000-0xffffffffffffffff M: () S/U: (R,W,X) +Domain0 Next Address : 0x0000000080200000 +Domain0 Next Arg1 : 0x0000000082200000 +Domain0 Next Mode : S-mode +Domain0 SysReset : yes +Domain0 SysSuspend : yes + +Boot HART ID : 0 +Boot HART Domain : root +Boot HART Priv Version : v1.12 +Boot HART Base ISA : rv64imacx +Boot HART ISA Extensions : sdtrig +Boot HART PMP Count : 8 +Boot HART PMP Granularity : 2 bits +Boot HART PMP Address Bits : 32 +Boot HART MHPM Info : 0 (0x00000000) +Boot HART Debug Triggers : 8 triggers +Boot HART MIDELEG : 0x0000000000000222 +Boot HART MEDELEG : 0x000000000000b109 +[ 0.000000] Linux version 6.12.19 (aweiss@panama) (riscv64-buildroot-linux-gnu-gcc.br_real (Buildroot 2025.02) 13.3.0, GNU ld (GNU Binutils) 2.43.1) #7 SMP Sun Aug 9 16:21:38 CEST 2026 +[ 0.000000] Machine model: Accemic Rocket64t1 RV64 CTTE Demonstrator (KV260 PL) +[ 0.000000] SBI specification v2.0 detected +[ 0.000000] SBI implementation ID=0x1 Version=0x10006 +[ 0.000000] SBI TIME extension detected +[ 0.000000] SBI IPI extension detected +[ 0.000000] SBI RFENCE extension detected +[ 0.000000] SBI DBCN extension detected +[ 0.000000] earlycon: uart8250 at MMIO32 0x0000000060010000 (options '') +[ 0.000000] printk: legacy bootconsole [uart8250] enabled +[ 0.000000] printk: debug: skip boot console de-registration. +[ 0.000000] Disabled 4-level and 5-level paging +[ 0.000000] OF: reserved mem: 0x0000000080000000..0x000000008003ffff (256 KiB) nomap non-reusable mmode_resv1@80000000 +[ 0.000000] OF: reserved mem: 0x0000000080040000..0x000000008005ffff (128 KiB) nomap non-reusable mmode_resv0@80040000 +[ 0.000000] Zone ranges: +[ 0.000000] DMA32 [mem 0x0000000080000000-0x000000008bffffff] +[ 0.000000] Normal empty +[ 0.000000] Movable zone start for each node +[ 0.000000] Early memory node ranges +[ 0.000000] node 0: [mem 0x0000000080000000-0x000000008005ffff] +[ 0.000000] node 0: [mem 0x0000000080060000-0x000000008bffffff] +[ 0.000000] Initmem setup node 0 [mem 0x0000000080000000-0x000000008bffffff] +[ 0.000000] On node 0, zone DMA32: 16384 pages in unavailable ranges +[ 0.000000] SBI HSM extension detected +[ 0.000000] riscv: base ISA extensions acim +[ 0.000000] riscv: ELF capabilities acim +[ 0.000000] percpu: Embedded 21 pages/cpu s48872 r8192 d28952 u86016 +[ 0.000000] Kernel command line: earlycon=uart8250,mmio32,0x60010000 keep_bootcon console=ttyS0 no4lvl rdinit=/sbin/init +[ 0.000000] Dentry cache hash table entries: 32768 (order: 6, 262144 bytes, linear) +[ 0.000000] Inode-cache hash table entries: 16384 (order: 5, 131072 bytes, linear) +[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 49152 +[ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off +[ 0.000000] Virtual kernel memory layout: +[ 0.000000] fixmap : 0xffffffc4fea00000 - 0xffffffc4ff000000 (6144 kB) +[ 0.000000] pci io : 0xffffffc4ff000000 - 0xffffffc500000000 ( 16 MB) +[ 0.000000] vmemmap : 0xffffffc500000000 - 0xffffffc600000000 (4096 MB) +[ 0.000000] vmalloc : 0xffffffc600000000 - 0xffffffd600000000 ( 64 GB) +[ 0.000000] modules : 0xffffffff01f8a000 - 0xffffffff80000000 (2016 MB) +[ 0.000000] lowmem : 0xffffffd600000000 - 0xffffffd60c000000 ( 192 MB) +[ 0.000000] kernel : 0xffffffff80000000 - 0xffffffffffffffff (2047 MB) +[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1 +[ 0.000000] rcu: Hierarchical RCU implementation. +[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=64 to nr_cpu_ids=1. +[ 0.000000] rcu: RCU debug extended QS entry/exit. +[ 0.000000] Tracing variant of Tasks RCU enabled. +[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies. +[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=1 +[ 0.000000] RCU Tasks Trace: Setting shift to 0 and lim to 1 rcu_task_cb_adjust=1 rcu_task_cpu_ids=1. +[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0 +[ 0.000000] riscv-intc: 64 local interrupts mapped +[ 0.000000] riscv: providing IPIs using SBI IPI extension +[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention. +[ 0.000000] clocksource: riscv_clocksource: mask: 0xffffffffffffffff max_cycles: 0x1623fa770, max_idle_ns: 3526361617904 ns +[ 0.000034] sched_clock: 64 bits at 750kHz, resolution 1333ns, wraps every 4398046510524ns +[ 0.003334] Console: colour dummy device 80x25 +[ 0.004323] Calibrating delay loop (skipped), value calculated using timer frequency.. 1.50 BogoMIPS (lpj=3000) +[ 0.005307] pid_max: default: 32768 minimum: 301 +[ 0.007265] LSM: initializing lsm=capability +[ 0.011227] Mount-cache hash table entries: 512 (order: 0, 4096 bytes, linear) +[ 0.011838] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes, linear) +[ 0.077230] riscv: ELF compat mode unsupported +[ 0.077451] ASID allocator disabled (0 bits) +[ 0.083475] rcu: Hierarchical SRCU implementation. +[ 0.083838] rcu: Max phase no-delay instances is 1000. +[ 0.104582] smp: Bringing up secondary CPUs ... +[ 0.105098] smp: Brought up 1 node, 1 CPU +[ 0.106775] Memory: 140784K/196608K available (9655K kernel code, 5038K rwdata, 4096K rodata, 12443K init, 473K bss, 54140K reserved, 0K cma-reserved) +[ 0.117893] devtmpfs: initialized +[ 0.145762] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns +[ 0.146830] futex hash table entries: 256 (order: 2, 16384 bytes, linear) +[ 0.151665] pinctrl core: initialized pinctrl subsystem +[ 0.181897] NET: Registered PF_NETLINK/PF_ROUTE protocol family +[ 0.197030] DMA: preallocated 128 KiB GFP_KERNEL pool for atomic allocations +[ 0.197970] DMA: preallocated 128 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations +[ 0.199906] audit: initializing netlink subsys (disabled) +[ 0.215093] thermal_sys: Registered thermal governor 'step_wise' +[ 0.216058] audit: type=2000 audit(0.188:1): state=initialized audit_enabled=0 res=1 +[ 0.217655] cpuidle: using governor menu +[ 0.284350] cpu0: Ratio of byte access time to unaligned word access is 0.01, unaligned accesses are slow +[ 0.322494] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages +[ 0.323283] HugeTLB: 28 KiB vmemmap can be freed for a 2.00 MiB page +[ 0.344121] iommu: Default domain type: Translated +[ 0.344869] iommu: DMA domain TLB invalidation policy: strict mode +[ 0.357323] SCSI subsystem initialized +[ 0.368282] usbcore: registered new interface driver usbfs +[ 0.369429] usbcore: registered new interface driver hub +[ 0.370899] usbcore: registered new device driver usb +[ 0.386974] Advanced Linux Sound Architecture Driver Initialized. +[ 0.404923] vgaarb: loaded +[ 0.412397] clocksource: Switched to clocksource riscv_clocksource +[ 0.692473] NET: Registered PF_INET protocol family +[ 0.696949] IP idents hash table entries: 4096 (order: 3, 32768 bytes, linear) +[ 0.718779] tcp_listen_portaddr_hash hash table entries: 128 (order: 0, 4096 bytes, linear) +[ 0.719550] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear) +[ 0.720854] TCP established hash table entries: 2048 (order: 2, 16384 bytes, linear) +[ 0.721927] TCP bind hash table entries: 2048 (order: 5, 131072 bytes, linear) +[ 0.726069] TCP: Hash tables configured (established 2048 bind 2048) +[ 0.728565] UDP hash table entries: 256 (order: 2, 24576 bytes, linear) +[ 0.729781] UDP-Lite hash table entries: 256 (order: 2, 24576 bytes, linear) +[ 0.734102] NET: Registered PF_UNIX/PF_LOCAL protocol family +[ 0.750814] RPC: Registered named UNIX socket transport module. +[ 0.751231] RPC: Registered udp transport module. +[ 0.751538] RPC: Registered tcp transport module. +[ 0.751822] RPC: Registered tcp-with-tls transport module. +[ 0.752621] RPC: Registered tcp NFSv4.1 backchannel transport module. +[ 0.753082] PCI: CLS 0 bytes, default 64 +[ 0.814967] workingset: timestamp_bits=46 max_order=16 bucket_order=0 +[ 0.851591] NFS: Registering the id_resolver key type +[ 0.852994] Key type id_resolver registered +[ 0.853373] Key type id_legacy registered +[ 0.854413] nfs4filelayout_init: NFSv4 File Layout Driver Registering... +[ 0.854858] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering... +[ 0.859507] 9p: Installing v9fs 9p2000 file system support +[ 0.866017] NET: Registered PF_ALG protocol family +[ 0.867798] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 245) +[ 0.889642] io scheduler mq-deadline registered +[ 0.890066] io scheduler kyber registered +[ 0.891330] io scheduler bfq registered +[ 0.918201] riscv-plic: interrupt-controller@c000000: mapped 8 interrupts with 1 handlers for 2 contexts. + \ No newline at end of file diff --git a/examples/dashboard/demo/rocket2.pcinfo b/examples/dashboard/demo/rocket2.pcinfo new file mode 100644 index 0000000..7b10431 --- /dev/null +++ b/examples/dashboard/demo/rocket2.pcinfo @@ -0,0 +1,52992 @@ +0x10000,L4 +0x10004,L4 +0x10008,L4 +0x1000C,L4 +0x10010,L4 +0x10014,JI2 +0x10016,L2 +0x10018,L4 +0x1001C,L4 +0x10020,L4 +0x10024,L4 +0x10028,CD4,0x116AA +0x1002C,JD4,0x10040 +0x10040,L4 +0x10044,L4 +0x10048,L4 +0x1004C,L4 +0x10050,L4 +0x10054,BD4,0x1005C +0x10058,JD4,0x10000 +0x1005C,L4 +0x10060,L4 +0x10064,L4 +0x10068,L4 +0x1006C,L4 +0x10070,BD4,0x1005C +0x10074,JI4 +0x10078,JD2,0x1005C +0x1007A,L2 +0x1007C,L2 +0x1007E,L2 +0x10080,L2 +0x10082,L2 +0x10084,L2 +0x10086,L4 +0x1008A,L2 +0x1008C,L2 +0x1008E,L2 +0x10090,L2 +0x10092,L2 +0x10094,L2 +0x10096,L2 +0x10098,L2 +0x1009A,L2 +0x1009C,L2 +0x1009E,L2 +0x100A0,L2 +0x100A2,L2 +0x100A4,L2 +0x100A6,L2 +0x100B8,L2 +0x100BA,L2 +0x100BC,L2 +0x100BE,L2 +0x100C0,L2 +0x100C2,L2 +0x100C4,L2 +0x100C6,L2 +0x100C8,L2 +0x100CA,L2 +0x100CC,L2 +0x100CE,L2 +0x100D0,L2 +0x100D2,L2 +0x100D4,L2 +0x100D6,L2 +0x100D8,L2 +0x100DA,L2 +0x100DC,L2 +0x100DE,L2 +0x100E0,L2 +0x100E2,L2 +0x100E4,L2 +0x100E6,L2 +0x100E8,L2 +0x100EA,L2 +0x100EC,L2 +0x100EE,L2 +0x100F0,BD4,0x10800 +0x100F4,L4 +0x100F8,BD4,0x1084E +0x100FC,BD4,0x1080C +0x10100,L2 +0x10102,L2 +0x10104,L2 +0x10106,CD4,0x5275C +0x1010A,L2 +0x1010C,L2 +0x1010E,L2 +0x10110,L2 +0x10112,L2 +0x10114,L2 +0x10116,L2 +0x10118,L2 +0x1011A,L2 +0x1011C,BD4,0x1082C +0x10120,L4 +0x10124,BD4,0x1087A +0x10128,BD4,0x10838 +0x1012C,L2 +0x1012E,L2 +0x10130,L2 +0x10132,JD4,0x10132 +0x10136,L2 +0x10138,BD4,0x10858 +0x1013C,L2 +0x1013E,L2 +0x10140,L2 +0x10142,L2 +0x10144,L2 +0x10146,L2 +0x10148,L2 +0x1014A,L2 +0x1014C,L2 +0x1014E,L2 +0x10150,L2 +0x10152,L2 +0x10154,L2 +0x10156,L2 +0x10158,L2 +0x1015A,L2 +0x1015C,L2 +0x1015E,L2 +0x10160,L2 +0x10162,L2 +0x10164,L2 +0x10166,L2 +0x10168,L2 +0x1016A,L2 +0x1016C,L2 +0x1016E,L2 +0x10170,L2 +0x10172,L2 +0x10174,BD4,0x10574 +0x10178,L2 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1055.0, + 206.0 + ], + [ + 1055.0, + 280.0 + ], + [ + 1072.4, + 280.0 + ] + ], + "head": [ + [ + 1080.1, + 280.0 + ], + [ + 1072.4, + 276.15 + ], + [ + 1072.4, + 283.85 + ] + ] + } + ] + } +} \ No newline at end of file diff --git a/examples/dashboard/devtools/check_congruence.py b/examples/dashboard/devtools/check_congruence.py new file mode 100644 index 0000000..9c0fb51 --- /dev/null +++ b/examples/dashboard/devtools/check_congruence.py @@ -0,0 +1,130 @@ +# SPDX-FileCopyrightText: 2026 Accemic Technologies GmbH +# SPDX-License-Identifier: ISC +"""Check the acceptance criterion: does the rendered view lie congruently +over the drawing? + + py devtools/measure_geometry.py 8142 (measures the rendering) + py devtools/check_congruence.py + +The rendering is uniformly scaled and translated with respect to the drawing +(fit factor, zoom, margin). "Congruent" therefore means: there is ONE +similarity transform (one factor, one translation) under which ALL blocks +coincide. The factor is derived from the overall extents, then the deviation +is measured block by block in drawing units -- not by eye, but as a number per +block. + +Exit 0 = every block within tolerance, otherwise 1. +""" +from __future__ import annotations + +import json +import sys +from pathlib import Path + +# ROOT is this script's own directory (devtools/, the former gui/); see +# export_drawio.py for why the old ROOT/"tools"/"ctrace_dashboard" path +# collapses to ROOT.parent in this repository's layout. +ROOT = Path(__file__).resolve().parent +GUI = ROOT +SCEN = ROOT.parent / "scenarios.json" +TOL = 1.5 # drawing units; below this it is rounding, not an offset + + +def drawing(sid): + """The expected geometry: what the sync read out of the drawing.""" + g = json.loads((GUI / "arch_geometry.json").read_text(encoding="utf-8")) + if sid not in g: + return None, None + d = g[sid] + boxes = {n["id"]: (n["x"], n["y"], n["w"], n["h"]) + for n in d["nodes"] + d["containers"]} + return boxes, d.get("source", "?") + + +def rendered(sid): + f = GUI / "measured" / ("geo_%s.json" % sid) + if not f.exists(): + return None + m = json.loads(f.read_text(encoding="utf-8")) + return {b["id"]: (b["x"], b["y"], b["w"], b["h"]) + for b in m["blocks"] + m["containers"]} + + +def fit(a, b): + """Factor and translation, from the overall extents of both sets.""" + ks = [k for k in a if k in b] + if not ks: + return None + ax0 = min(a[k][0] for k in ks); ax1 = max(a[k][0] + a[k][2] for k in ks) + ay0 = min(a[k][1] for k in ks); ay1 = max(a[k][1] + a[k][3] for k in ks) + bx0 = min(b[k][0] for k in ks); bx1 = max(b[k][0] + b[k][2] for k in ks) + by0 = min(b[k][1] for k in ks); by1 = max(b[k][1] + b[k][3] for k in ks) + sx = (ax1 - ax0) / (bx1 - bx0) if bx1 > bx0 else 1.0 + sy = (ay1 - ay0) / (by1 - by0) if by1 > by0 else 1.0 + s = (sx + sy) / 2 # ONE factor, no distortion + return s, ax0 - bx0 * s, ay0 - by0 * s, ks + + +def main() -> int: + cat = json.loads(SCEN.read_text(encoding="utf-8")) + bad = 0 + for sc in cat["scenarios"]: + sid = sc["id"] + want, src = drawing(sid) + have = rendered(sid) + if not want or not have: + print(" %-11s skipped (no measurement)" % sid) + continue + f = fit(want, have) + if not f: + print(" %-11s no blocks in common" % sid); bad += 1; continue + s, dx, dy, ks = f + worst, wid = 0.0, "" + rows = [] + for k in sorted(ks): + wx, wy, ww, wh = want[k] + hx, hy, hw, hh = have[k] + d = max(abs(hx * s + dx - wx), abs(hy * s + dy - wy), + abs(hw * s - ww), abs(hh * s - wh)) + rows.append((d, k)) + if d > worst: + worst, wid = d, k + # Check the EDGES as well -- the criterion is blocks AND arrows. The + # first version compared blocks only and therefore reported "met" + # while the arrows were visibly in the wrong place (2026-07-29). + emax, eid = 0.0, "" + gw = json.loads((GUI / "arch_geometry.json").read_text(encoding="utf-8")) + want_e = {(e["s"], e["t"]): e.get("path") + for e in gw[sid]["edges"] if e.get("path")} + mm = json.loads((GUI / "measured" / ("geo_%s.json" % sid)) + .read_text(encoding="utf-8")) + for e in mm["edges"]: + wp = want_e.get((e["s"], e["t"])) + if not wp or len(wp) != len(e["pts"]): + continue + # Since the rework the edges are ALREADY in model coordinates + # (the wire SVG uses the model box as its viewBox) -- they must + # NOT be converted back from pixels the way the blocks are. + for (wx, wy), (hx, hy) in zip(wp, e["pts"]): + d = max(abs(hx - wx), abs(hy - wy)) + if d > emax: + emax, eid = d, "%s->%s" % (e["s"], e["t"]) + worst = max(worst, emax) + if emax > TOL: + wid = eid + " (edge)" + ok = worst <= TOL + print(" %-11s %-2s factor %.4f · largest deviation %.2f at %s " + "(%d blocks) <- %s" + % (sid, "OK" if ok else "!!", s, worst, wid, len(ks), src)) + if not ok: + bad += 1 + for d, k in sorted(rows, reverse=True)[:6]: + if d > TOL: + print(" %-12s %.2f" % (k, d)) + print("\n%s" % ("CONGRUENT" if not bad + else "NOT congruent in %d view(s)" % bad)) + return 1 if bad else 0 + + +if __name__ == "__main__": + sys.exit(main()) diff --git a/examples/dashboard/devtools/check_themes.py b/examples/dashboard/devtools/check_themes.py new file mode 100644 index 0000000..54219d0 --- /dev/null +++ b/examples/dashboard/devtools/check_themes.py @@ -0,0 +1,190 @@ +#!/usr/bin/env python3 +# SPDX-FileCopyrightText: 2026 Accemic Technologies GmbH +# SPDX-License-Identifier: ISC +"""Measure colour themes on the RENDERED image, not by reading themes.json. + +Why at all: a theme can sit correctly in the JSON, land on :root -- and still +have no effect, because the CSS rule in question does not use the value (that +is exactly how the wire colour and the flow dots used to sit in the +JavaScript as fixed numbers). This check loads every theme headless and reads +the colours back out of the finished, rendered blocks and wires. + +Checked per theme: + 1. the ground actually changes (otherwise the theme never arrived), + 2. every visible block carries the theme's fill AND its border, + 3. wire and arrowhead follow the token (the old fixed value stands out), + 4. text-on-ground and border-on-ground as a WCAG contrast -- measured, so + that "more contrast" is a number and not a claim. + +Usage: py devtools/check_themes.py [port] +""" +from __future__ import annotations + +import json +import re +import subprocess +import sys +import tempfile +from pathlib import Path + +# ROOT is this script's own directory (devtools/, the former gui/); see +# export_drawio.py for why the old ROOT/"tools"/"ctrace_dashboard" path +# collapses to ROOT.parent in this repository's layout. +ROOT = Path(__file__).resolve().parent +EDGE = Path(r"C:\Program Files (x86)\Microsoft\Edge\Application\msedge.exe") +THEMES = ROOT.parent / "themes.json" + +# A theme has to stand out visibly from the default, otherwise it is not one. +MIN_TEXT_CONTRAST = 4.5 # WCAG AA for normal text +MIN_EDGE_CONTRAST = 3.0 # WCAG "non-text" for borders and wires +MIN_SIDE_CONTRAST = 2.0 # side paths may recede, but not disappear + + +def rgb(s: str): + """Bring a colour from the browser onto the 0..255 scale. + + Careful -- this is where the first attempt went wrong: the browser does + not resolve color-mix() to 'rgb(153, 125, 55)' but to + 'color(srgb 0.6 0.49 0.21)', i.e. 0..1 instead of 0..255. Parsing both + forms the same way measures tinted blocks as nearly black and reports a + contrast failure that does not exist. + """ + s = s or "" + m = re.findall(r"-?[\d.]+(?:e-?\d+)?", s) + if len(m) < 3: + return None + v = [float(x) for x in m[:3]] + if s.lstrip().startswith("color("): + v = [x * 255.0 for x in v] + return tuple(max(0.0, min(255.0, x)) for x in v) + + +def lum(c): + def f(v): + v /= 255.0 + return v / 12.92 if v <= 0.04045 else ((v + 0.055) / 1.055) ** 2.4 + r, g, b = (f(x) for x in c) + return 0.2126 * r + 0.7152 * g + 0.0722 * b + + +def contrast(a, b): + if not a or not b: + return None + la, lb = sorted((lum(a), lum(b)), reverse=True) + return (la + 0.05) / (lb + 0.05) + + +def dump(port, theme, scen, work): + url = ("http://localhost:%s/?scen=%s&theme=%s&themedump=1" + % (port, scen, theme)) + r = subprocess.run([str(EDGE), "--headless=new", "--disable-gpu", + "--user-data-dir=%s" % (work / ("p_" + theme)), + "--window-size=1700,1100", + "--virtual-time-budget=9000", "--dump-dom", url], + capture_output=True, timeout=180) + dom = r.stdout.decode("utf-8", "replace") + m = re.search(r'
]*>(.*?)
', dom, re.S) + if not m: + raise SystemExit("%s: no themedump in the DOM -- is the server " + "running on port %s?" % (theme, port)) + txt = m.group(1) + for a, b in [("&", "&"), ("<", "<"), (">", ">"), (""", '"')]: + txt = txt.replace(a, b) + return json.loads(txt) + + +def main() -> int: + port = sys.argv[1] if len(sys.argv) > 1 else "8142" + scen = sys.argv[2] if len(sys.argv) > 2 else "trio" + doc = json.loads(THEMES.read_text(encoding="utf-8")) + ids = list(doc["themes"]) + + work = Path(tempfile.mkdtemp(prefix="ctte_thm_")) + seen_bg, fails = {}, [] + + for tid in ids: + d = dump(port, tid, scen, work) + bg, txt = rgb(d["bodyBg"]), rgb(d["txt"]) + wire, head = rgb(d["wire"]), rgb(d["head"]) + blocks = d["blocks"] + + print("\n=== %s (%s, %d blocks) ===" % (tid, d["mode"], len(blocks))) + print(" ground %s · text %s · wire %s @ %s" + % (d["bodyBg"], d["txt"], d["wire"], d["wireW"])) + + if d["theme"] != tid: + fails.append("%s: page reports theme %r" % (tid, d["theme"])) + + # 1. Two themes must not look identical -- one of them would not have + # arrived. What is compared is the WHOLE impression, not just the + # ground: 'print' and 'mono' both sit on white and differ only in + # the role colours. + fp = (d["bodyBg"], d["txt"], d["wire"], + tuple(b["bc"] for b in blocks[:12])) + if fp in seen_bg: + fails.append("%s: looks like %s -- the theme has no effect" + % (tid, seen_bg[fp])) + seen_bg[fp] = tid + + # 2. Text on ground + ct = contrast(txt, bg) + ok = ct and ct >= MIN_TEXT_CONTRAST + print(" text/bg %5.2f:1 %s" % (ct or 0, "ok" if ok else "TOO LOW")) + if not ok: + fails.append("%s: text/bg only %.2f:1" % (tid, ct or 0)) + + # 3. Wire against the ground -- the old fixed value #7a8699 would + # come out the same in EVERY scheme and is noticed for that. + cw = contrast(wire, bg) + okw = cw and cw >= MIN_EDGE_CONTRAST + print(" wire/bg %5.2f:1 %s" % (cw or 0, "ok" if okw else "TOO LOW")) + if not okw: + fails.append("%s: wire/bg only %.2f:1" % (tid, cw or 0)) + if head and wire and head != wire: + fails.append("%s: arrow head %s != wire %s" % (tid, head, wire)) + + # 4. Every block carries the theme's fill and border. + # The side paths (k-side) are tracked SEPARATELY: they are meant to + # recede, so a lower value there is intent and not a defect -- their + # identity is carried by the label inside the block. Letting them + # disappear entirely is still not allowed, hence their own, lower + # threshold. + worst, worst_id, flat = 99.0, None, [] + sworst, sworst_id = 99.0, None + for b in blocks: + bc, bbg = rgb(b["bc"]), rgb(b["bg"]) + c = contrast(bc, bg) + side = "k-side" in (b.get("cls") or "") + if c is not None: + if side and c < sworst: + sworst, sworst_id = c, b["id"] + elif not side and c < worst: + worst, worst_id = c, b["id"] + if bbg and bg and bbg == bg: + flat.append(b["id"]) # fill == ground: not tinted + print(" border/bg %5.2f:1 (weakest load-bearing role: %s)" + % (worst, worst_id)) + if sworst_id: + print(" secondary path %5.2f:1 (%s -- meant to recede)" + % (sworst, sworst_id)) + if worst < MIN_EDGE_CONTRAST: + fails.append("%s: block border %s only %.2f:1" % (tid, worst_id, worst)) + if sworst_id and sworst < MIN_SIDE_CONTRAST: + fails.append("%s: secondary path %s practically invisible at %.2f:1" + % (tid, sworst_id, sworst)) + if flat: + fails.append("%s: %d blocks without tint (%s)" + % (tid, len(flat), ", ".join(flat[:4]))) + + print("\n" + "=" * 62) + if fails: + print("ERRORS (%d):" % len(fails)) + for f in fails: + print(" - " + f) + return 1 + print("All %d schemes: applied, tinted, contrast-checked." % len(ids)) + return 0 + + +if __name__ == "__main__": + raise SystemExit(main()) diff --git a/examples/dashboard/devtools/compact_layout.py b/examples/dashboard/devtools/compact_layout.py new file mode 100644 index 0000000..f567821 --- /dev/null +++ b/examples/dashboard/devtools/compact_layout.py @@ -0,0 +1,483 @@ +# SPDX-FileCopyrightText: 2026 Accemic Technologies GmbH +# SPDX-License-Identifier: ISC +r"""Build the geometry source PER SCENARIO -- from the scenario, not from an +earlier measurement. + + py devtools/compact_layout.py -> writes devtools/ctte_view_.drawio.svg + py devtools/sync_arch_view.py -> takes it into the dashboard + +WHY THIS WAS REWRITTEN. The first version derived the set of blocks from +`devtools/measured/geo_.json` -- that is, from a measurement of the already +rendered view. By construction it could therefore produce nothing for a +scenario that had never existed: `cva6_linux64` and `rocket64` stayed without a +drawing, `sync_arch_view.py` bailed out on them with "no geometry source" -- +and because its write step sits BEHIND the loop, it then wrote nothing at all. +In the dashboard `rebuildArch()` silently fell back for those scenarios to the +last geometry that had been set, and that was the TRIO's: three rows, two of +them hidden. That is exactly where the orphaned "Kria PS" boxes, the +unconnected memory blocks and the empty third came from. + +The set of blocks now comes from `scenarios.json` (cores, `features`, `sinks`) +plus one RTL fact per scenario (`ETRACE`, below), not from a measurement. +Adding a scenario therefore gets you its drawing automatically. + +THE GRID (drawing units; 1 unit = 1 rendered pixel at the reference width, see +`--u` in index.html): + + cpu 20 190x138 the observed core + ingress 236 92x 46 TIP adapter / ITI shim / TCI shim / H2E + [ encoder container 352 .. 916 ] + preproc 372 84x 46 + fifo 476 84x 62 + msggen 580 84x 46 \ + nexusfmt 684 92x 46 > N-Trace chain (upper lane) + mseomdo 796 100x 46 / + teinst 580 84x 46 \ E-Trace chain (lower lane), only where + tepktz 684 92x 46 / the build carries it + funnel 940 78x(span) only from two encoders upwards + sinks 1050/960 112x 54 uram/ddr/pib, depending on scenario + +The chain follows the RTL: core -> shim -> ct_L23_preproc -> TIP FIFO -> +{ct_L2_msg_gen -> ct_L2_nexus_formatter -> ct_L2_mseo_mdo_formatter} or +{ct_L2_te_inst_gen -> ct_L2_te_packetizer} -> (ct_L1_funnel) -> sinks. +""" +from __future__ import annotations + +import json +import sys +from pathlib import Path +from xml.sax.saxutils import escape, quoteattr + +# ROOT is this script's own directory (devtools/, the former gui/); see +# export_drawio.py for why the old ROOT/"tools"/"ctrace_dashboard" path +# collapses to ROOT.parent in this repository's layout. +ROOT = Path(__file__).resolve().parent +GUI = ROOT +SCEN = ROOT.parent / "scenarios.json" + +# ---------------------------------------------------------------- Raster ---- +X_CPU, W_CPU, H_CPU = 20, 190, 138 +X_ING, W_ING = 236, 92 +X_CT = 352 +X_PRE, W_PRE = 372, 84 +X_FIFO, W_FIFO, H_FIFO = 476, 84, 62 +X_MSG, W_MSG = 580, 84 +X_NEX, W_NEX = 684, 92 +X_MSEO, W_MSEO = 796, 100 +X_TEI, W_TEI = 580, 84 +X_TEP, W_TEP = 684, 92 +H_SM = 46 +CT_PAD_R = 20 # air between the last block and the container edge +W_CT = (X_MSEO + W_MSEO + CT_PAD_R) - X_CT # 564 + +W_FUNNEL = 78 +W_SINK, H_SINK, GAP_SINK = 112, 54, 20 + +# AXIS sits BELOW THE PREPROCESSOR, not below the FIFO: the ACT-CAP tap comes +# out of ct_L23_preproc (that is where the ACT-CAP/ACT-ST dispatch lives), and +# the edge in the model is preproc->axis. Drawn below the FIFO, the edge +# endpoint sat 62 units away from its target block, and sync_arch_view.py +# dropped the edge silently (tolerance 40) -- the arrow was missing from the +# picture. +X_AXIS, W_AXIS, H_AXIS = 372, 84, 40 +X_PS, W_PS = 236, 92 # Kria PS side, flush left with the shim + +# AXIS-WP chain (feature `axis_wp`): the encoder's 96-bit AXIS port feeds, per +# row, ct_axis_wp_shim -> wp_axi_fifo (axi_fifo_mm_s, 1024 records) -> Kria PS +# (the /dev/mem drain behind /wp.html). Like the ACT-CAP tap the chain hangs +# BELOW the row and starts at the preprocessor (the ACT-ST/WP dispatch sits +# there, edge preproc->wpshim); it reads left to right like the ATB chain above +# it, with the PS consumer at the end. The blocks are taller than the ACT-CAP +# tap (62 instead of 40): the shim carries a fill bar plus a counter line from +# the WPCTRL window. +# Widths of the WP chain, computed rather than guessed: the card font is +# --fs-s = 10 model units in monospace, so ~6 units per character, plus 5+5 +# units of block border and 2 units of .cnt padding. The longest line of the +# shim card is "drop 4,294,967,294" = 18 characters -> 18*6 + 12 = 120 units. +# At 84 it did not fit and wrapped; the second line ("ovf YES") then slid below +# the block's overflow:hidden edge and was gone. 152 leaves room for the +# ten-digit value with separators. +# The space comes out of the arrow runs (124 units between the blocks before, +# 76/74 now) -- not from the right margin: the chain runs in row 0 next to the +# funnel (x 920) and must not touch it. +X_WPS, W_WPS = 372, 152 # ct_axis_wp_shim, below preproc +X_WPF, W_WPF = 600, 116 # wp_axi_fifo, below msggen +X_WPP, W_WPP = 790, 110 # Kria PS (the A53 consumer) +H_AWP = 62 + +# Row heights: two lanes with E-Trace, only one without. +H_ROW_E, H_ROW_N = 158, 96 +LANE_A_E, LANE_B_E = 26, 86 # dy of the lanes when there are two +LANE_A_N = 25 +ROW_GAP = 34 + +# Arrowhead exactly as draw.io draws it: tip 1.9 before the block edge, base +# 7.7 behind it, half-width 3.85. sync_arch_view.rendered_paths() recognises +# the line by fill="none" and the head by having a fill; both are taken over +# (without the head an edge is left as a stub). +A_TIP, A_LEN, A_HALF = 1.9, 9.6, 3.85 + +WIRE = "#5b6b85" + +# Which build carries the E-Trace chain? That is a synthesis parameter +# (EN_ETRACE), not a display detail -- and on the two-hart Rocket it is +# EXPLICITLY 0: the funnel recognises packet boundaries from the Nexus MSEO +# bits, while an E-Trace back end delivers raw bytes and would be merged +# silently wrong (rocket2_soc_top.sv header, item 4; the wrapper aborts +# elaboration at 1). Drawing two lanes here blindly would show blocks that do +# not exist in the bitstream. +ETRACE = { + "mbv": True, "cva6_linux": True, "cva6_linux64": True, + "rocket64": True, "trio": True, "rocket2": False, + # cva6_2: EN_ETRACE=1'b0 (rtl/board_kv260/cva6_2_soc_top.sv:153, header + # item 4 -- the funnel parses Nexus MSEO, the wrapper aborts at 1). + "cva6_2_rv64": False, "cva6_2_rv32": False, + # duo: NO sandbox copy of rtl/pkg as the trio has -- duo's + # examples/kv260/duo/fpga/create_project_kv260.tcl resolves the encoder + # sources unchanged through rtl/ct_encoder.abc, where + # rtl/pkg/ct_pkg.sv:691 `localparam bit CT_EN_ETRACE = 0` applies. The + # build is therefore N-Trace only; te_inst/tePktz blocks would be invented + # in the picture. + "duo": False, + # tgc5b2_axis_wp: CT_EN_ETRACE=0 in BOTH encoder vintages of the scenario + # (rtl/pkg/ct_pkg.sv:691 in either tree): N-Trace only, no te_inst/tePktz + # blocks. + "tgc5b2_axis_wp": False, +} + +LABEL = { + "cpu": "Core", "tip": "Trace ingress", "preproc": "Preproc", "fifo": "FIFO", + "msggen": "MsgGen", "nexusfmt": "Nexus Fmt", "mseomdo": "MSEO/MDO", + "teinst": "te_inst", "tepktz": "te Pktz", "funnel": "Trace Funnel", + "uram": "Mem (URAM)", "ddr": "Mem (DDR4)", "pib": "PIB", + "axis": "AXIS", "kriaps": "Kria PS", + "wpshim": "AXIS WP shim", "wpfifo": "wp_axi_fifo", +} + +NODE = ("rounded=0;whiteSpace=wrap;html=1;verticalAlign=top;align=left;" + "spacing=4;fillColor=%s;strokeColor=%s;fontColor=#e8eef7;fontSize=12;") +CTST = ("rounded=1;dashed=1;whiteSpace=wrap;html=1;fillColor=none;" + "strokeColor=#3c5270;fontColor=#C98500;verticalAlign=top;align=left;" + "spacingLeft=6;fontSize=12;") +EDGE = ("edgeStyle=orthogonalEdgeStyle;rounded=0;html=1;strokeColor=#44536e;" + "strokeWidth=1.7;endArrow=block;endFill=1;") + + +def attr(v): + """Always delimit with double quotes. + + With many inner quotes quoteattr() picks single ones by itself -- but the + sync looks for content="..." and then did not find the file (this really + happened).""" + return '"%s"' % (v.replace("&", "&").replace("<", "<") + .replace(">", ">").replace('"', """)) + + +# -------------------------------------------------------------- geometry ---- +def build(sc): + """Blocks, containers and edges for exactly this scenario.""" + cores = sc.get("cores", []) + feats = sc.get("features", []) + sinks = sc.get("sinks", {}) or {} + etr = ETRACE.get(sc["id"], True) + has_axis = "axis" in feats + has_awp = "axis_wp" in feats + n = len(cores) + + h_row = H_ROW_E if etr else H_ROW_N + # The AXIS tap hangs BELOW the row. Without this allowance it ran into + # the container label of the next row ("…raceEncoder · ENC1 · TGC5B" was + # half covered in the trio) -- the label sits on the container's top edge, + # so it needs the space above. + below = (H_AXIS + 8 + 14) if has_axis else \ + ((H_AWP + 8 + 14) if has_awp else 0) + pitch = max(h_row + below, H_CPU) + ROW_GAP + N = {} # id -> dict + conts = [] + E = [] # (src, dst, kind) -- the route is derived later from the boxes + + def put(nid, x, y, w, h): + N[nid] = {"id": nid, "x": float(x), "y": float(y), + "w": float(w), "h": float(h)} + + for r in range(n): + ry = r * pitch + la = ry + (LANE_A_E if etr else LANE_A_N) + lb = ry + LANE_B_E + conts.append({"id": "ct%d" % r, "x": float(X_CT), "y": float(ry), + "w": float(W_CT), "h": float(h_row)}) + put("cpu%d" % r, X_CPU, ry + (h_row - H_CPU) / 2.0, W_CPU, H_CPU) + # The trio's TGC5B has no ingress block of its own -- its H2E stage + # sits inside the wrapper. That fact lives in the scenario, not here. + # `ingress_block` on the core overrides the rule EXPLICITLY: + # tgc5b2_axis_wp instantiates the H2E->TIP adapter visibly per core in + # tgc5b_wp_synth_wrap, so the diagram shows it in BOTH rows; the trio + # keeps the older rule. + want_tip = cores[r].get("ingress_block") + if want_tip is None: + want_tip = cores[r].get("ingress") not in (None, "", "H2E->TIP") + if want_tip: + put("tip%d" % r, X_ING, ry + (h_row - H_SM) / 2.0, W_ING, H_SM) + put("preproc%d" % r, X_PRE, ry + (h_row - H_SM) / 2.0, W_PRE, H_SM) + put("fifo%d" % r, X_FIFO, ry + (h_row - H_FIFO) / 2.0, W_FIFO, H_FIFO) + put("msggen%d" % r, X_MSG, la, W_MSG, H_SM) + put("nexusfmt%d" % r, X_NEX, la, W_NEX, H_SM) + put("mseomdo%d" % r, X_MSEO, la, W_MSEO, H_SM) + if etr: + put("teinst%d" % r, X_TEI, lb, W_TEI, H_SM) + put("tepktz%d" % r, X_TEP, lb, W_TEP, H_SM) + if has_axis: + ay = ry + h_row + 8 + put("axis%d" % r, X_AXIS, ay, W_AXIS, H_AXIS) + put("kriaps%d" % r, X_PS, ay, W_PS, H_AXIS) + if has_awp: + ay = ry + h_row + 8 + put("wpshim%d" % r, X_WPS, ay, W_WPS, H_AWP) + put("wpfifo%d" % r, X_WPF, ay, W_WPF, H_AWP) + put("kriaps%d" % r, X_WPP, ay, W_WPP, H_AWP) + + ing = "tip%d" % r + if ing in N: + E.append(("cpu%d" % r, ing, "h")) + E.append((ing, "preproc%d" % r, "h")) + else: + E.append(("cpu%d" % r, "preproc%d" % r, "h")) + E.append(("preproc%d" % r, "fifo%d" % r, "h")) + # Middle of the vertical edge to middle of the vertical edge: both + # protocol lanes leave the FIFO at the MIDPOINT of its right edge and + # only fan out halfway along. Before, they started at 27 % and 73 % of + # the block height and met their target at an angle. + E.append(("fifo%d" % r, "msggen%d" % r, "h")) + E.append(("msggen%d" % r, "nexusfmt%d" % r, "h")) + E.append(("nexusfmt%d" % r, "mseomdo%d" % r, "h")) + if etr: + E.append(("fifo%d" % r, "teinst%d" % r, "h")) + E.append(("teinst%d" % r, "tepktz%d" % r, "h")) + if has_axis: + E.append(("preproc%d" % r, "axis%d" % r, "down")) + E.append(("axis%d" % r, "kriaps%d" % r, "left")) + if has_awp: + E.append(("preproc%d" % r, "wpshim%d" % r, "down")) + E.append(("wpshim%d" % r, "wpfifo%d" % r, "h")) + E.append(("wpfifo%d" % r, "kriaps%d" % r, "h")) + + top = 0.0 + bot = (n - 1) * pitch + h_row + + # Merging: only from two encoders upwards. With a single encoder the ATB + # goes straight to the sinks -- a funnel with one channel would be drawn + # hardware that does not exist in the bitstream. + use_funnel = n >= 2 + if use_funnel: + put("funnel", 940, top, W_FUNNEL, bot - top) + x_sink = 940 + W_FUNNEL + 54 + else: + x_sink = X_MSEO + W_MSEO + 64 + + want = [s for s in ("ddr", "uram", "pib") if sinks.get(s)] + if not want: + want = ["uram"] + span = len(want) * H_SINK + (len(want) - 1) * GAP_SINK + y0 = (top + bot) / 2.0 - span / 2.0 + for i, sid in enumerate(want): + put(sid, x_sink, y0 + i * (H_SINK + GAP_SINK), W_SINK, H_SINK) + + for r in range(n): + ends = ["mseomdo%d" % r] + (["tepktz%d" % r] if etr else []) + for e in ends: + if use_funnel: + # Every channel enters the funnel at ITS OWN height. Routing + # them all to the middle looks like one channel and is exactly + # what the drawing is meant to refute: the funnel has one + # input per row (FUNNEL_CTRL b[1:0] / b[5:4] ...). + E.append((e, "funnel", "chan%d" % r)) + else: + for sid in want: + E.append((e, sid, "trunk")) + if use_funnel: + for sid in want: + E.append(("funnel", sid, "h")) + + return N, conts, E + + +# ---------------------------------------------------------------- edges ----- +def route(N, E, n_rows=1): + """Turn (source, target, kind) into an orthogonal route with an + arrowhead. The dashboard draws exclusively what is produced here: + `layoutWires()` skips every edge without a `path` (index.html).""" + out = [] + # A trunk line before the sinks (or before the funnel): all chain ends run + # onto the SAME vertical line and only fan out there. Otherwise, with three + # sinks, six lines cross in open space. + trunk_x = {} + for s, t, kind in E: + if kind == "trunk" or kind.startswith("chan"): + b = N[t] + trunk_x.setdefault(t, b["x"] - 30.0) + trunk_x[t] = min(trunk_x[t], b["x"] - 30.0) + tx_common = min(trunk_x.values()) if trunk_x else 0.0 + + for s, t, kind in E: + a, b = N[s], N[t] + ay, by = a["y"] + a["h"] / 2.0, b["y"] + b["h"] / 2.0 + if kind.startswith("chan"): + # STRAIGHT into the funnel, at the height of the source. The + # entry used to sit at (r+1)/(n+1) of the funnel height, which + # forced a bend. The channels stay separate all the same: every + # row arrives at its own height, because the chain ends already + # sit at different heights. + by = ay + kind = "straight" + if kind == "down": + cx = a["x"] + a["w"] / 2.0 + p = [[cx, a["y"] + a["h"]], [cx, b["y"] - A_LEN]] + head = [[cx, b["y"] - A_TIP], [cx - A_HALF, b["y"] - A_LEN], + [cx + A_HALF, b["y"] - A_LEN]] + elif kind == "left": + xe = b["x"] + b["w"] + p = [[a["x"], ay], [xe + A_LEN, by]] + head = [[xe + A_TIP, by], [xe + A_LEN, by - A_HALF], + [xe + A_LEN, by + A_HALF]] + else: + xs, xe = a["x"] + a["w"], b["x"] + if kind == "trunk": + cx = tx_common + else: + cx = xs + (xe - xs) / 2.0 + if abs(ay - by) < 0.6: + p = [[xs, ay], [xe - A_LEN, ay]] + else: + p = [[xs, ay], [cx, ay], [cx, by], [xe - A_LEN, by]] + head = [[xe - A_TIP, by], [xe - A_LEN, by - A_HALF], + [xe - A_LEN, by + A_HALF]] + out.append({"s": s, "t": t, "path": p, "head": head}) + return out + + +# ------------------------------------------------------------------ SVG ----- +def fill_of(base): + return ("#20293a" if base == "cpu" else + "#18202c" if base in ("uram", "ddr", "pib") else + "#141b26" if base in ("axis", "kriaps", "wpshim", "wpfifo") + else "#1c2532") + + +def stroke_of(base): + return ("#C98500" if base == "cpu" else + "#4a5a72" if base in ("axis", "kriaps", "wpshim", "wpfifo") + else "#33445c") + + +def base_of(nid): + return nid.rstrip("0123456789") or nid + + +def svg(sc, N, conts, edges): + nodes = list(N.values()) + xs = [v["x"] for v in nodes + conts] + [p[0] for e in edges for p in e["path"]] + ys = [v["y"] for v in nodes + conts] + [p[1] for e in edges for p in e["path"]] + xe = [v["x"] + v["w"] for v in nodes + conts] + ye = [v["y"] + v["h"] for v in nodes + conts] + ox, oy = min(xs) - 30, min(ys) - 30 + W = int(max(xe) - ox + 30) + H = int(max(ye) - oy + 30) + + def sh(v): + return {"x": v["x"] - ox, "y": v["y"] - oy, "w": v["w"], "h": v["h"]} + + cells = [] + for c in conts: + i = int(c["id"][2:]) + cap = "CEDARtools.TraceEncoder · ENC%d · %s" % ( + i, sc["cores"][i].get("name", "")) + g = sh(c) + cells.append(' ' + % (quoteattr(c["id"]), quoteattr(cap), CTST, + g["x"], g["y"], g["w"], g["h"])) + for v in nodes: + b = base_of(v["id"]) + g = sh(v) + cells.append(' ' + % (quoteattr(v["id"]), quoteattr(LABEL.get(b, b)), + NODE % (fill_of(b), stroke_of(b)), + g["x"], g["y"], g["w"], g["h"])) + for i, e in enumerate(edges): + cells.append(' ' + % (sc["id"], i, EDGE, quoteattr(e["s"]), quoteattr(e["t"]))) + + model = ('\n \n' + ' \n \n' + ' \n \n' + % (quoteattr("arch-" + sc["id"]), quoteattr(sc["id"]), W, H) + + "\n".join(cells) + + "\n \n \n \n") + + o = ['' % (W, H, W, H, attr(model)), + ''] + for c in conts: + i = int(c["id"][2:]) + g = sh(c) + o.append('' + % (g["x"], g["y"], g["w"], g["h"])) + o.append('%s' + % (g["x"] + 10, g["y"] - 5, + escape("CEDARtools.TraceEncoder · ENC%d · %s" + % (i, sc["cores"][i].get("name", ""))))) + # Edges BEFORE the blocks -- otherwise a line lies on top of the box it + # runs into. The order d= then fill= is mandatory: the sync recognises + # line and head by exactly that pattern. + for e in edges: + d = "M" + " L".join("%g,%g" % (p[0] - ox, p[1] - oy) for p in e["path"]) + o.append('' + % (d, WIRE)) + hd = ("M" + " L".join("%g,%g" % (p[0] - ox, p[1] - oy) for p in e["head"]) + + " Z") + o.append('' % (hd, WIRE)) + for v in nodes: + b = base_of(v["id"]) + g = sh(v) + o.append('' % (g["x"], g["y"], g["w"], g["h"], + fill_of(b), stroke_of(b))) + o.append('%s' + % (g["x"] + 6, g["y"] + 17, escape(LABEL.get(b, b)))) + o.append("") + return "\n".join(o) + + +def main() -> int: + cat = json.loads(SCEN.read_text(encoding="utf-8")) + for sc in cat["scenarios"]: + N, conts, E = build(sc) + edges = route(N, E, max(1, len(sc.get("cores", [])))) + f = GUI / ("ctte_view_%s.drawio.svg" % sc["id"]) + f.write_text(svg(sc, N, conts, edges), encoding="utf-8") + print(" %-13s %2d blocks · %d containers · %2d edges%s -> %s" + % (sc["id"], len(N), len(conts), len(edges), + "" if ETRACE.get(sc["id"], True) else " (without E-Trace)", + f.name)) + stray = sorted(GUI.glob("ctte_view_%s_aw*.drawio.svg" % sc["id"])) + if stray: + print(" ATTENTION: %s takes precedence in the sync and " + "shadows this file" % stray[-1].name) + print("Next: py devtools/sync_arch_view.py") + return 0 + + +if __name__ == "__main__": + sys.exit(main()) diff --git a/examples/dashboard/devtools/ctte_geometry.drawio.svg b/examples/dashboard/devtools/ctte_geometry.drawio.svg new file mode 100644 index 0000000..77930c6 --- /dev/null +++ b/examples/dashboard/devtools/ctte_geometry.drawio.svg @@ -0,0 +1,4 @@ + + + +
C-Trace
C-Trace

MicroBlaze V
RV32IM core · 75 MHz · 128 KiB RAM
MicroBlaze V...
TIP Adapter
TIP Adapter
Preproc
Preproc
FIFO
FIFO
MsgGen
MsgGen
Nexus
Formatter
Nexus...
MSEO/MDO
Formatter
MSEO/MDO...
AXIS
AXIS
Trace
Funnel
Trace...
PIB
PIB
Mem
(URAM)
Mem...
Mem
(DDR4)
Mem...
C-Trace
C-Trace
Minres
Minres
Preproc
Preproc
FIFO
FIFO
MsgGen
MsgGen
Nexus
Formatter
Nexus...
MSEO/MDO
Formatter
MSEO/MDO...
AXIS
AXISText is not SVG - cannot display \ No newline at end of file diff --git a/examples/dashboard/devtools/ctte_view.drawio b/examples/dashboard/devtools/ctte_view.drawio new file mode 100644 index 0000000..3d23dc8 --- /dev/null +++ b/examples/dashboard/devtools/ctte_view.drawio @@ -0,0 +1,692 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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cv32a6 core 0 + +CEDARtools.TraceEncoder · ENC1 · cv32a6 core 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +Core + +Trace ingress + +Preproc + +FIFO + +MsgGen + +Nexus Fmt + +MSEO/MDO + +Core + +Trace ingress + +Preproc + +FIFO + +MsgGen + +Nexus Fmt + +MSEO/MDO + +Trace Funnel + +Mem (DDR4) + +Mem (URAM) + +PIB + \ No newline at end of file diff --git a/examples/dashboard/devtools/ctte_view_cva6_2_rv64.drawio.svg b/examples/dashboard/devtools/ctte_view_cva6_2_rv64.drawio.svg new file mode 100644 index 0000000..21e21fa --- /dev/null +++ b/examples/dashboard/devtools/ctte_view_cva6_2_rv64.drawio.svg @@ -0,0 +1,123 @@ + + + +CEDARtools.TraceEncoder · ENC0 · cv64a6 core 0 + +CEDARtools.TraceEncoder · ENC1 · cv64a6 core 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +Core + +Trace ingress + +Preproc + +FIFO + +MsgGen + +Nexus Fmt + +MSEO/MDO + +Core + +Trace ingress + +Preproc + +FIFO + +MsgGen + +Nexus Fmt + +MSEO/MDO + +Trace Funnel + +Mem (DDR4) + +Mem (URAM) + +PIB + \ No newline at end of file diff --git a/examples/dashboard/devtools/ctte_view_cva6_linux.drawio.svg b/examples/dashboard/devtools/ctte_view_cva6_linux.drawio.svg new file mode 100644 index 0000000..976738b --- /dev/null +++ b/examples/dashboard/devtools/ctte_view_cva6_linux.drawio.svg @@ -0,0 +1,84 @@ + + + +CEDARtools.TraceEncoder · ENC0 · CVA6 + + + + + + + + + + + + + + + + + + + + + + + + + +Core + +Trace ingress + +Preproc + +FIFO + +MsgGen + +Nexus Fmt + +MSEO/MDO + +te_inst + +te Pktz + +Mem (DDR4) + +Mem (URAM) + \ No newline at end of file diff --git a/examples/dashboard/devtools/ctte_view_cva6_linux64.drawio.svg b/examples/dashboard/devtools/ctte_view_cva6_linux64.drawio.svg new file mode 100644 index 0000000..d8cc502 --- /dev/null +++ b/examples/dashboard/devtools/ctte_view_cva6_linux64.drawio.svg @@ -0,0 +1,84 @@ + + + +CEDARtools.TraceEncoder · ENC0 · CVA6 + + + + + + + + + + + + + + + + + + + + + + + + + +Core + +Trace ingress + +Preproc + +FIFO + +MsgGen + +Nexus Fmt + +MSEO/MDO + +te_inst + +te Pktz + +Mem (DDR4) + +Mem (URAM) + \ No newline at end of file diff --git a/examples/dashboard/devtools/ctte_view_duo.drawio.svg b/examples/dashboard/devtools/ctte_view_duo.drawio.svg new file mode 100644 index 0000000..508629a --- /dev/null +++ b/examples/dashboard/devtools/ctte_view_duo.drawio.svg @@ -0,0 +1,141 @@ + + + +CEDARtools.TraceEncoder · ENC0 · MicroBlaze V + +CEDARtools.TraceEncoder · ENC1 · TGC5B + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +Core + +Trace ingress + +Preproc + +FIFO + +MsgGen + +Nexus Fmt + +MSEO/MDO + +AXIS + +Kria PS + +Core + +Preproc + +FIFO + +MsgGen + +Nexus Fmt + +MSEO/MDO + +AXIS + +Kria PS + +Trace Funnel + +Mem (DDR4) + +Mem (URAM) + +PIB + \ No newline at end of file diff --git a/examples/dashboard/devtools/ctte_view_mbv.drawio.svg b/examples/dashboard/devtools/ctte_view_mbv.drawio.svg new file mode 100644 index 0000000..b564a5a --- /dev/null +++ b/examples/dashboard/devtools/ctte_view_mbv.drawio.svg @@ -0,0 +1,105 @@ + + + +CEDARtools.TraceEncoder · ENC0 · MicroBlaze V + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +Core + +Trace ingress + +Preproc + +FIFO + +MsgGen + +Nexus Fmt + +MSEO/MDO + +te_inst + +te Pktz + +AXIS + +Kria PS + +Mem (DDR4) + +Mem (URAM) + +PIB + \ No newline at end of file diff --git a/examples/dashboard/devtools/ctte_view_rocket2.drawio.svg b/examples/dashboard/devtools/ctte_view_rocket2.drawio.svg new file mode 100644 index 0000000..ed3a4ed --- /dev/null +++ b/examples/dashboard/devtools/ctte_view_rocket2.drawio.svg @@ -0,0 +1,123 @@ + + + +CEDARtools.TraceEncoder · ENC0 · Rocket hart 0 + +CEDARtools.TraceEncoder · ENC1 · Rocket hart 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +Core + +Trace ingress + +Preproc + +FIFO + +MsgGen + +Nexus Fmt + +MSEO/MDO + +Core + +Trace ingress + +Preproc + +FIFO + +MsgGen + +Nexus Fmt + +MSEO/MDO + +Trace Funnel + +Mem (DDR4) + +Mem (URAM) + +PIB + \ No newline at end of file diff --git a/examples/dashboard/devtools/ctte_view_rocket64.drawio.svg b/examples/dashboard/devtools/ctte_view_rocket64.drawio.svg new file mode 100644 index 0000000..b6ad13f --- /dev/null +++ b/examples/dashboard/devtools/ctte_view_rocket64.drawio.svg @@ -0,0 +1,93 @@ + + + +CEDARtools.TraceEncoder · ENC0 · Rocket + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +Core + +Trace ingress + +Preproc + +FIFO + +MsgGen + +Nexus Fmt + +MSEO/MDO + +te_inst + +te Pktz + +Mem (DDR4) + +Mem (URAM) + +PIB + \ No newline at end of file diff --git a/examples/dashboard/devtools/ctte_view_tgc5b2_axis_wp.drawio.svg b/examples/dashboard/devtools/ctte_view_tgc5b2_axis_wp.drawio.svg new file mode 100644 index 0000000..7ac4d99 --- /dev/null +++ b/examples/dashboard/devtools/ctte_view_tgc5b2_axis_wp.drawio.svg @@ -0,0 +1,159 @@ + + + +CEDARtools.TraceEncoder · ENC0 · TGC5B core 0 + +CEDARtools.TraceEncoder · ENC1 · TGC5B core 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +Core + +Trace ingress + +Preproc + +FIFO + +MsgGen + +Nexus Fmt + +MSEO/MDO + +AXIS WP shim + +wp_axi_fifo + +Kria PS + +Core + +Trace ingress + +Preproc + +FIFO + +MsgGen + +Nexus Fmt + +MSEO/MDO + +AXIS WP shim + +wp_axi_fifo + +Kria PS + +Trace Funnel + +Mem (DDR4) + +Mem (URAM) + +PIB + \ No newline at end of file diff --git a/examples/dashboard/devtools/ctte_view_trio.drawio.svg b/examples/dashboard/devtools/ctte_view_trio.drawio.svg new file mode 100644 index 0000000..93a60f5 --- /dev/null +++ b/examples/dashboard/devtools/ctte_view_trio.drawio.svg @@ -0,0 +1,243 @@ + + + +CEDARtools.TraceEncoder · ENC0 · MicroBlaze V + +CEDARtools.TraceEncoder · ENC1 · TGC5B + +CEDARtools.TraceEncoder · ENC2 · CVA6 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +Core + +Trace ingress + +Preproc + +FIFO + +MsgGen + +Nexus Fmt + +MSEO/MDO + +te_inst + +te Pktz + +AXIS + +Kria PS + +Core + +Preproc + +FIFO + +MsgGen + +Nexus Fmt + +MSEO/MDO + +te_inst + +te Pktz + +AXIS + +Kria PS + +Core + +Trace ingress + +Preproc + +FIFO + +MsgGen + +Nexus Fmt + +MSEO/MDO + +te_inst + +te Pktz + +AXIS + +Kria PS + +Trace Funnel + +Mem (DDR4) + +Mem (URAM) + +PIB + \ No newline at end of file diff --git a/examples/dashboard/devtools/export_drawio.py b/examples/dashboard/devtools/export_drawio.py new file mode 100644 index 0000000..5966c2d --- /dev/null +++ b/examples/dashboard/devtools/export_drawio.py @@ -0,0 +1,250 @@ +# SPDX-FileCopyrightText: 2026 Accemic Technologies GmbH +# SPDX-License-Identifier: ISC +"""Export the MEASURED dashboard geometry as .drawio -- 1:1, one page per +scenario. + + py server.py --demo --port 8142 (in one shell, from examples/dashboard/) + py devtools/measure_geometry.py 8142 + py devtools/export_drawio.py + ... rearrange in draw.io ... + py devtools/sync_arch_view.py + +WHAT "1:1" MEANS HERE -- and why the previous version was not (found +2026-07-29): + + * COORDINATES: 1 drawio unit = 1 rendered pixel. Before, the raw ARCH + values were in there; but the page scales those at runtime (SCALE 1.78, + not the 2.4 in the source) and CSS padding changes the block size on top + of that. + * FONT SIZES: taken from getComputedStyle (h3 12 px, sub-line 10 px). + Before, everything ran on the drawio default. + * ARROWS: the polylines actually drawn by layoutWires(), as waypoints plus + exact exit/entry points. Before, every edge carried pts:[] -- drawio + routed them itself and therefore drew different paths. + +The edges stay ATTACHED to source and target (exitX/entryX as fractions) so +they follow when a block is moved -- otherwise the file would be worthless +for rearranging. +""" +from __future__ import annotations + +import json +import sys +from pathlib import Path +from xml.sax.saxutils import escape, quoteattr + +# ROOT is this script's own directory (devtools/, the former gui/); the +# dashboard files it reads/writes alongside (scenarios.json etc.) are one +# level up, at ROOT.parent (examples/dashboard/) -- devtools/ moved from +# being a repo-root sibling of tools/ctrace_dashboard/ to living INSIDE the +# dashboard directory it serves (plan AP5), so both halves of the old path +# shifted by one level. +ROOT = Path(__file__).resolve().parent +MEAS = ROOT / "measured" +SCEN = ROOT.parent / "scenarios.json" +OUT = Path(sys.argv[1]) if len(sys.argv) > 1 else ROOT / "ctte_view.drawio" + +BASE = ("rounded=0;whiteSpace=wrap;html=1;verticalAlign=top;align=left;" + "spacing=4;spacingTop=2;spacingLeft=4;") +FILL = {"cpu": "#20293a", "sink": "#18202c", "": "#1c2532"} +STROKE = {"cpu": "#C98500", "sink": "#3b4a63", "": "#33445c"} +CT_STYLE = ("rounded=1;dashed=1;whiteSpace=wrap;html=1;fillColor=none;" + "strokeColor=#3c5270;fontColor=#C98500;verticalAlign=top;" + "align=left;spacingLeft=6;spacingTop=2;fontSize=%d;") + + +def kind(nid): + b = nid[:-1] if nid[-1].isdigit() else nid + if b == "cpu": + return "cpu" + if b in ("uram", "ddr", "pib"): + return "sink" + return "" + + +def label(blk): + """Label as rendered: heading plus sub-lines in their own size + (html=1 carries that).""" + parts = [] + for i, t in enumerate(blk["texts"]): + txt = escape(" ".join(t["text"].split())) + if i == 0: + parts.append("%s" % txt) + else: + parts.append('%s' + % (t["px"], "#8a99ad", txt)) + return "
".join(parts) or escape(blk["id"]) + + +def frac(v, lo, span): + if not span: + return 0.5 + return max(0.0, min(1.0, (v - lo) / span)) + + +def vertex(cid, lbl, style, x, y, w, h): + return (' \n' + ' \n ' + % (quoteattr(cid), quoteattr(lbl), style, x, y, w, h)) + + +def edge_cell(eid, e, byid): + """An edge with exact exit/entry points and the real waypoints.""" + pts = e["pts"] + a, b = byid.get(e["s"]), byid.get(e["t"]) + if not a or not b or len(pts) < 2: + return None + p0, pn = pts[0], pts[-1] + st = ("edgeStyle=orthogonalEdgeStyle;rounded=0;html=1;jettySize=auto;" + "orthogonalLoop=1;strokeColor=%s;strokeWidth=%g;endArrow=block;" + "endFill=1;exitX=%.4f;exitY=%.4f;exitDx=0;exitDy=0;" + "entryX=%.4f;entryY=%.4f;entryDx=0;entryDy=0;" + % (e.get("stroke") or "#44536e", e.get("width") or 1.7, + frac(p0[0], a["x"], a["w"]), frac(p0[1], a["y"], a["h"]), + frac(pn[0], b["x"], b["w"]), frac(pn[1], b["y"], b["h"]))) + mid = pts[1:-1] + arr = ("%s" + % "".join('' % (p[0], p[1]) for p in mid) + ) if mid else "" + return (' \n' + ' %s\n' + ' ' % (quoteattr(eid), st, quoteattr(e["s"]), + quoteattr(e["t"]), arr)) + + +def page(g, name): + cells, byid = [], {} + for c in g["containers"]: + cells.append(vertex(c["id"], escape(c["text"]), + CT_STYLE % round(c["px"] or 12), + c["x"], c["y"], c["w"], c["h"])) + for b in g["blocks"]: + byid[b["id"]] = b + k = kind(b["id"]) + head = b["texts"][0]["px"] if b["texts"] else 12 + st = (BASE + "fillColor=%s;strokeColor=%s;fontColor=#e8eef7;" + "fontSize=%d;fontFamily=%s;" + % (FILL[k], STROKE[k], round(head), + (b["texts"][0]["family"] if b["texts"] else "Segoe UI"))) + cells.append(vertex(b["id"], label(b), st, b["x"], b["y"], b["w"], b["h"])) + for i, e in enumerate(g["edges"]): + c = edge_cell("%s_e%d" % (name, i), e, byid) + if c: + cells.append(c) + w, h = g["stage"]["w"] + 60, g["stage"]["h"] + 60 + return (' \n' + ' \n \n' + ' \n \n' + + "\n".join(cells) + "\n \n \n" + ' \n') % (quoteattr("arch-" + name), quoteattr(name), w, h) + + +# ---------------------------------------------------------------- SVG ------ +def svg_page(g, name, model_xml): + """A .drawio.svg: viewable in a browser AND editable in draw.io. + + The image is drawn from the SAME measured values as the embedded model -- + so what the browser shows is exactly what the dashboard renders. The + mxfile hangs uncompressed in the content attribute; + sync_arch_view.py reads exactly this format. + """ + W, H = g["stage"]["w"] + 40, g["stage"]["h"] + 40 + o = ['' + % (W, H, W, H, quoteattr(model_xml))] + o.append('' + '') + o.append('') + o.append('') + for c in g["containers"]: + o.append('' + % (c["x"], c["y"], c["w"], c["h"])) + o.append('%s' + % (c["x"] + 8, c["y"] + (c["px"] or 12) + 3, c["px"] or 12, + escape(c["text"]))) + for e in g["edges"]: + pts = " ".join("%g,%g" % (p[0], p[1]) for p in e["pts"]) + o.append('' + % (pts, e.get("stroke") or "#44536e", e.get("width") or 1.7)) + for b in g["blocks"]: + k = kind(b["id"]) + o.append('' + % (b["x"], b["y"], b["w"], b["h"], FILL[k], STROKE[k])) + ty = b["y"] + for i, t in enumerate(b["texts"]): + ty += t["px"] + (3 if i == 0 else 2) + o.append('%s' + % (b["x"] + 5, ty, t["family"], t["px"], t["weight"], + "#e8eef7" if i == 0 else "#8a99ad", + escape(" ".join(t["text"].split()))[:58])) + o.append("") + return "\n".join(o) + + + +def refuse_overwrite(path): + """An EXISTING .drawio.svg is NEVER overwritten -- full stop. + + The first attempt inspected the agent in the mxfile header ("from draw.io + or from us?"). It failed twice and destroyed hand-drawn files: the second + time because the newly saved files did not carry the expected marker at + all. A heuristic that DELETES when it is unsure is the wrong shape -- in + doubt it has to protect, not overwrite. + + So: if the file exists, it is skipped. Only what is missing gets created; + replacing needs --force. Anyone who wants to regenerate deletes the file + deliberately first. + """ + return path.exists() + + +def main() -> int: + cat = json.loads(SCEN.read_text(encoding="utf-8")) + pages = [] + for sc in cat["scenarios"]: + f = MEAS / ("geo_%s.json" % sc["id"]) + if not f.exists(): + raise SystemExit("missing: %s -- first run " + "'py devtools/measure_geometry.py'" % f) + g = json.loads(f.read_text(encoding="utf-8")) + pages.append(page(g, sc["id"])) + print(" %-11s %2d blocks · %d containers · %2d edges" + % (sc["id"], len(g["blocks"]), len(g["containers"]), + len(g["edges"]))) + OUT.write_text('\n' + "".join(pages) + '\n', + encoding="utf-8") + print("exported: %d page(s) -> %s" % (len(pages), OUT)) + + # Additionally one .drawio.svg per scenario -- viewable in a browser AND + # editable in draw.io. The image is drawn from the same measured values as + # the embedded model. + for sc, pg in zip(cat["scenarios"], pages): + g = json.loads((MEAS / ("geo_%s.json" % sc["id"])) + .read_text(encoding="utf-8")) + model = ('\n' + pg + '') + f = OUT.parent / ("ctte_view_%s.drawio.svg" % sc["id"]) + if refuse_overwrite(f) and "--force" not in sys.argv: + print(" svg -- %s KEPT (already there; --force " + "overwrites)" % f.name) + continue + f.write_text(svg_page(g, sc["id"], model), encoding="utf-8") + print(" svg -> %s" % f.name) + return 0 + + +if __name__ == "__main__": + sys.exit(main()) diff --git a/examples/dashboard/devtools/measure_geometry.py b/examples/dashboard/devtools/measure_geometry.py new file mode 100644 index 0000000..d4734ea --- /dev/null +++ b/examples/dashboard/devtools/measure_geometry.py @@ -0,0 +1,80 @@ +# SPDX-FileCopyrightText: 2026 Accemic Technologies GmbH +# SPDX-License-Identifier: ISC +"""Measure the RENDERED geometry of the dashboard, per scenario. + +Why measure instead of compute: the page does not draw the ARCH coordinates, +it scales them (SCALE is determined at runtime from the stage size -- +currently 1.78, not the 2.4 in the source), sets font sizes via CSS and +computes the arrows in layoutWires() itself. An export from ARCH +therefore matches neither the edge routing nor the text sizes (from the +request "give me a genuine 1:1 geometry"). + + py devtools/measure_geometry.py [port] [target directory] + +Requires a running dashboard server (demo mode is enough): + py server.py --demo --port 8142 (from examples/dashboard/) +""" +from __future__ import annotations + +import json +import re +import shutil +import subprocess +import sys +import tempfile +from pathlib import Path + +# ROOT is this script's own directory (devtools/, the former gui/); see +# export_drawio.py for why the old ROOT/"tools"/"ctrace_dashboard" path +# collapses to ROOT.parent in this repository's layout. +ROOT = Path(__file__).resolve().parent +EDGE = Path(r"C:\Program Files (x86)\Microsoft\Edge\Application\msedge.exe") +SCEN = ROOT.parent / "scenarios.json" + + +def measure(port, scen, work): + """Load one scenario view and collect its geodump. + + --dump-dom is the way in: JS return values do not come back out of headless + mode, so the page puts the result into the DOM as a 
.
+    """
+    url = "http://localhost:%s/?scen=%s&geodump=1" % (port, scen)
+    r = subprocess.run([str(EDGE), "--headless=new", "--disable-gpu",
+                        "--user-data-dir=%s" % (work / ("p_" + scen)),
+                        "--window-size=1700,1100",
+                        "--virtual-time-budget=9000", "--dump-dom", url],
+                       capture_output=True, timeout=180)
+    dom = r.stdout.decode("utf-8", "replace")
+    m = re.search(r'
]*>(.*?)
', dom, re.S)
+    if not m:
+        raise SystemExit("%s: no geodump in the DOM -- is the server running on "
+                         "Port %s?" % (scen, port))
+    txt = m.group(1)
+    for a, b in [("&", "&"), ("<", "<"), (">", ">"), (""", '"')]:
+        txt = txt.replace(a, b)
+    return json.loads(txt)
+
+
+def main() -> int:
+    port = sys.argv[1] if len(sys.argv) > 1 else "8142"
+    out = Path(sys.argv[2]) if len(sys.argv) > 2 else ROOT / "measured"
+    out.mkdir(parents=True, exist_ok=True)
+    # browser profiles into scratch, not next to the measurements -- otherwise
+    # hundreds of cache files would land in the repo (happened for real, ab96df0).
+    work = Path(tempfile.mkdtemp(prefix="ctte_geo_"))
+    cat = json.loads(SCEN.read_text(encoding="utf-8"))
+    for sc in cat["scenarios"]:
+        g = measure(port, sc["id"], work)
+        (out / ("geo_%s.json" % sc["id"])).write_text(
+            json.dumps(g, indent=1, ensure_ascii=False), encoding="utf-8")
+        print("  %-11s %2d blocks · %d containers · %2d edges · stage %dx%d "
+              "· SCALE %.3f" % (sc["id"], len(g["blocks"]), len(g["containers"]),
+                                len(g["edges"]), g["stage"]["w"], g["stage"]["h"],
+                                g["scale"]))
+    shutil.rmtree(work, ignore_errors=True)
+    print("measured -> %s" % out)
+    return 0
+
+
+if __name__ == "__main__":
+    sys.exit(main())
diff --git a/examples/dashboard/devtools/measured/geo_cva6_2_rv32.json b/examples/dashboard/devtools/measured/geo_cva6_2_rv32.json
new file mode 100644
index 0000000..838eb8d
--- /dev/null
+++ b/examples/dashboard/devtools/measured/geo_cva6_2_rv32.json
@@ -0,0 +1,810 @@
+{
+ "scenario": "cva6_2_rv32",
+ "scale": 2.4,
+ "blocks": [
+  {
+   "id": "cpu0",
+   "x": 45.22,
+   "y": 45.22,
+   "w": 186.81,
+   "h": 135.69,
+   "cls": "blk k-core cpu",
+   "texts": [
+    {
+     "sel": "h3",
+     "text": "cv32a6 core 0",
+     "px": 10.8161,
+     "weight": "600",
+     "color": "rgb(228, 233, 241)",
+     "family": "Segoe UI"
+    },
+    {
+     "sel": "sub",
+     "text": "RV32IMA Sv32 · 75 MHz design · guest 0x6400_0000 +32 MiB cached -> PS DDR 0x6400_0000 (private); mailbox guest 0x6800_0000 +16 MiB uncached -> PS DDR 0x6800_0000 (shared)",
+     "px": 10.8161,
+     "weight": "400",
+     "color": "rgb(151, 164, 186)",
+     "family": "Segoe UI"
+    },
+    {
+     "sel": "stat",
+     "text": "core_run",
+     "px": 10.8161,
+     "weight": "400",
+     "color": "rgb(228, 233, 241)",
+     "family": "Consolas"
+    }
+   ]
+  },
+  {
+   "id": "tip0",
+   "x": 257.61,
+   "y": 90.45,
+   "w": 90.45,
+   "h": 45.22,
+   "cls": "blk k-ingress",
+   "texts": [
+    {
+     "sel": "h3",
+     "text": "ITI shim",
+     "px": 10.8161,
+     "weight": "600",
+     "color": "rgb(228, 233, 241)",
+     "family": "Segoe UI"
+    }
+   ]
+  },
+  {
+   "id": "preproc0",
+   "x": 391.34,
+   "y": 90.45,
+   "w": 82.59,
+   "h": 45.22,
+   "cls": "blk k-ntrace",
+   "texts": [
+    {
+     "sel": "h3",
+     "text": "Preproc",
+     "px": 10.8161,
+     "weight": "600",
+     "color": "rgb(228, 233, 241)",
+     "family": "Segoe UI"
+    }
+   ]
+  },
+  {
+   "id": "fifo0",
+   "x": 493.59,
+   "y": 82.58,
+   "w": 82.59,
+   "h": 60.95,
+   "cls": "blk k-ntrace",
+   "texts": [
+    {
+     "sel": "h3",
+     "text": "FIFO",
+     "px": 10.8161,
+     "weight": "600",
+     "color": "rgb(228, 233, 241)",
+     "family": "Segoe UI"
+    },
+    {
+     "sel": "cnt",
+     "text": "max 0 ovf 0",
+     "px": 9.8328,
+     "weight": "400",
+     "color": "rgb(151, 164, 186)",
+     "family": "Consolas"
+    }
+   ]
+  },
+  {
+   "id": "msggen0",
+   "x": 595.86,
+   "y": 90.45,
+   "w": 82.59,
+   "h": 45.22,
+   "cls": "blk k-ntrace",
+   "texts": [
+    {
+     "sel": "h3",
+     "text": "MsgGen",
+     "px": 10.8161,
+     "weight": "600",
+     "color": "rgb(228, 233, 241)",
+     "family": "Segoe UI"
+    }
+   ]
+  },
+  {
+   "id": "nexusfmt0",
+   "x": 698.13,
+   "y": 90.45,
+   "w": 90.45,
+   "h": 45.22,
+   "cls": "blk k-ntrace",
+   "texts": [
+    {
+     "sel": "h3",
+     "text": "Nexus Fmt",
+     "px": 10.8161,
+     "weight": "600",
+     "color": "rgb(228, 233, 241)",
+     "family": "Segoe UI"
+    },
+    {
+     "sel": "cnt",
+     "text": "SRC 0",
+     "px": 9.8328,
+     "weight": "400",
+     "color": "rgb(151, 164, 186)",
+     "family": "Consolas"
+    }
+   ]
+  },
+  {
+   "id": "mseomdo0",
+   "x": 808.25,
+   "y": 90.45,
+   "w": 98.31,
+   "h": 45.22,
+   "cls": "blk k-ntrace",
+   "texts": [
+    {
+     "sel": "h3",
+     "text": "MSEO/MDO",
+     "px": 10.8161,
+     "weight": "600",
+     "color": "rgb(228, 233, 241)",
+     "family": "Segoe UI"
+    }
+   ]
+  },
+  {
+   "id": "cpu1",
+   "x": 45.22,
+   "y": 214.34,
+   "w": 186.81,
+   "h": 135.69,
+   "cls": "blk k-core cpu",
+   "texts": [
+    {
+     "sel": "h3",
+     "text": "cv32a6 core 1",
+     "px": 10.8161,
+     "weight": "600",
+     "color": "rgb(228, 233, 241)",
+     "family": "Segoe UI"
+    },
+    {
+     "sel": "sub",
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+   ],
+   "stroke": null,
+   "width": null
+  },
+  {
+   "s": "funnel",
+   "t": "uram",
+   "d": "M1028,363 L1072.4,363",
+   "pts": [
+    [
+     1028,
+     363
+    ],
+    [
+     1072.4,
+     363
+    ]
+   ],
+   "stroke": null,
+   "width": null
+  },
+  {
+   "s": "funnel",
+   "t": "pib",
+   "d": "M1028,363 L1055,363 L1055,437 L1072.4,437",
+   "pts": [
+    [
+     1028,
+     363
+    ],
+    [
+     1055,
+     363
+    ],
+    [
+     1055,
+     437
+    ],
+    [
+     1072.4,
+     437
+    ]
+   ],
+   "stroke": null,
+   "width": null
+  }
+ ],
+ "page": {
+  "innerHeight": 1005,
+  "scrollHeight": 1012,
+  "innerWidth": 1670,
+  "scrollWidth": 1655,
+  "overflowX": -15,
+  "overflow": 7,
+  "bodyH": 1012,
+  "main": {
+   "top": 52,
+   "bottom": 1012,
+   "h": 960
+  },
+  "con": {
+   "top": 0,
+   "bottom": 0,
+   "h": 0
+  },
+  "conwrap": {
+   "top": 0,
+   "bottom": 0,
+   "h": 0
+  },
+  "panel": {
+   "top": 52,
+   "bottom": 1012,
+   "h": 960,
+   "scrollH": 960,
+   "innerOverflow": 0
+  },
+  "pipe": {
+   "top": 152,
+   "bottom": 574,
+   "h": 422
+  },
+  "conStyleH": "221.188px"
+ },
+ "stage": {
+  "w": 658,
+  "h": 422
+ }
+}
\ No newline at end of file
diff --git a/examples/dashboard/devtools/sync_arch_view.py b/examples/dashboard/devtools/sync_arch_view.py
new file mode 100644
index 0000000..6bf0f39
--- /dev/null
+++ b/examples/dashboard/devtools/sync_arch_view.py
@@ -0,0 +1,380 @@
+# SPDX-FileCopyrightText: 2026 Accemic Technologies GmbH
+# SPDX-License-Identifier: ISC
+"""Write the geometry rearranged in draw.io back into the dashboard, PER SCENARIO.
+
+    py devtools/sync_arch_view.py
+
+Sources per scenario, searched in this order:
+    devtools/ctte_view_.drawio.svg   rearranged by hand (preferred)
+    devtools/ctte_view.drawio                  multi-page collection file
+    devtools/measured/geo_.json        the measured actual geometry
+
+WHY PER SCENARIO: until 2026-07-29 all views shared ONE geometry. The
+single-core scenarios thereby inherited the trio layout including its hidden
+rows and their empty space -- precisely what compaction is meant to remove.
+Every view now carries its own layout.
+
+THE CELL ID IS THE KEY, not the label. Renaming a block changes nothing;
+deleting it removes it from the view. A block the dashboard does not know is
+REPORTED instead of silently adopted -- a typo in the drawio should stand out,
+not damage the layout.
+"""
+from __future__ import annotations
+
+import base64
+import html
+import json
+import re
+import sys
+import urllib.parse
+import zlib
+from pathlib import Path
+from xml.etree import ElementTree as ET
+
+# ROOT is this script's own directory (devtools/, the former gui/); see
+# export_drawio.py for why the old ROOT/"tools"/"ctrace_dashboard" path
+# collapses to ROOT.parent in this repository's layout. GUI keeps its name
+# for minimal diff below -- it now means "this devtools/ directory", not a
+# repo-root-level gui/ sibling.
+ROOT = Path(__file__).resolve().parent
+GUI = ROOT
+DASH = ROOT.parent
+INDEX = DASH / "index.html"
+SCEN = DASH / "scenarios.json"
+GEOJSON = GUI / "arch_geometry.json"
+
+BEGIN = "/* ARCH-GEOMETRY-BEGIN"
+END = "/* ARCH-GEOMETRY-END */"
+
+
+def model_of(path: Path) -> str:
+    """Fetch the mxfile XML out of a .drawio or .drawio.svg."""
+    src = path.read_text(encoding="utf-8", errors="replace")
+    if path.suffix.lower() == ".svg":
+        # Allow both delimiters -- draw.io and our own generators
+        # write content="..." or content='...' depending on the content.
+        m = (re.search(r'content="([^"]*)"', src)
+             or re.search(r"content='([^']*)'", src))
+        if not m:
+            raise SystemExit("no embedded mxfile in %s" % path)
+        src = html.unescape(m.group(1))
+    return src
+
+
+def diagrams(mx: str):
+    """(page name, mxGraphModel XML). draw.io stores either
+    uncompressed or deflate+base64+urlencode -- both are accepted."""
+    for m in re.finditer(r"]*)>(.*?)", mx, re.S):
+        attrs, inner = m.group(1), m.group(2).strip()
+        nm = re.search(r'name="([^"]*)"', attrs)
+        if not inner.startswith("<"):
+            inner = urllib.parse.unquote(
+                zlib.decompress(base64.b64decode(inner), -15).decode("utf-8"))
+        yield (nm.group(1) if nm else ""), inner
+
+
+def parse_model(xml: str):
+    root = ET.fromstring(xml)
+    nodes, conts, edges = [], [], []
+    for c in root.iter("mxCell"):
+        cid, g = c.get("id"), c.find("mxGeometry")
+        if not cid or cid in ("0", "1"):
+            continue
+        if c.get("vertex") == "1" and g is not None:
+            st = c.get("style") or ""
+            rr = re.search(r"rounded=(\d)", st)
+            rec = {"id": cid, "label": c.get("value") or "",
+                   "round": int(rr.group(1)) if rr else 0,
+                   "x": float(g.get("x", 0)), "y": float(g.get("y", 0)),
+                   "w": float(g.get("width", 0)), "h": float(g.get("height", 0))}
+            (conts if cid.startswith("ct") else nodes).append(rec)
+        elif c.get("edge") == "1" and c.get("source") and c.get("target"):
+            pts = []
+            arr = g.find("Array") if g is not None else None
+            if arr is not None:
+                for p in arr.findall("mxPoint"):
+                    pts.append([float(p.get("x", 0)), float(p.get("y", 0))])
+            edges.append({"s": c.get("source"), "t": c.get("target"), "pts": pts})
+    return nodes, conts, edges
+
+
+def from_measured(path: Path):
+    g = json.loads(path.read_text(encoding="utf-8"))
+    nodes = [{"id": b["id"], "x": b["x"], "y": b["y"], "w": b["w"], "h": b["h"]}
+             for b in g["blocks"]]
+    conts = [{"id": c["id"], "x": c["x"], "y": c["y"], "w": c["w"], "h": c["h"]}
+             for c in g["containers"]]
+    # The first and last point are the exit and entry at the block, which the
+    # dashboard computes itself -- only the bends in between are waypoints.
+    edges = [{"s": e["s"], "t": e["t"], "pts": e["pts"][1:-1]} for e in g["edges"]]
+    return nodes, conts, edges
+
+
+
+def rendered_paths(svg_text, nodes, conts):
+    """Take the edges from the SVG -- the LINE **AND** the ARROWHEAD.
+
+    Both paths are imported and later drawn VERBATIM -- `` and ``. The head is not a
+    marker definition but the triangle draw.io actually drew.
+
+    The first attempt here THREW THE HEADS AWAY and set a marker-end of its
+    own instead. The result was short stubs with arrows in the wrong places
+    (marked up by hand on 2026-07-29). Hence they now come along.
+
+    draw.io normalises the origin on export; the offset is derived from the
+    SIZE (rendered rectangles against model nodes, majority wins).
+    """
+    body = re.sub(r'\scontent="[^"]*"', " ", svg_text)
+    body = re.sub(r"\scontent='[^']*'", " ", body)
+
+    rects = [(float(a), float(b), float(c), float(d)) for a, b, c, d in
+             re.findall(r']*\sx="([-\d.]+)"[^>]*\sy="([-\d.]+)"'
+                        r'[^>]*\swidth="([\d.]+)"[^>]*\sheight="([\d.]+)"', body)]
+    votes = {}
+    for rx, ry, rw, rh in rects:
+        for b in list(nodes) + list(conts):
+            if abs(b["w"] - rw) < 0.6 and abs(b["h"] - rh) < 0.6:
+                k = (round(b["x"] - rx), round(b["y"] - ry))
+                votes[k] = votes.get(k, 0) + 1
+    dx, dy = max(votes, key=votes.get) if votes else (0, 0)
+
+    def pts_of(d):
+        return [[float(a) + dx, float(b) + dy] for a, b in
+                re.findall(r"[MLQCZ]?\s*(-?[\d.]+)[ ,]+(-?[\d.]+)", d)]
+
+    # fill="none" = line, everything else with a fill = arrowhead
+    raw = re.findall(r' 40:
+            # Do NOT drop silently. An edge whose endpoint sits too far from
+            # any block otherwise vanishes from the picture without a trace --
+            # which really happened for preproc->axis, whose target block was
+            # 62 units off. A missing arrow in a drawing with 38 edges catches
+            # nobody's eye; a message does.
+            dropped.append("%s->%s (%.0f/%.0f units from the block)"
+                           % (s_id, t_id, sd, td))
+            continue
+        out.append({"s": s_id, "t": t_id, "pts": P[1:-1],
+                    "path": P, "head": closest_head(P[-1])})
+    for d in dropped:
+        print("  DISCARDED: edge %s -- endpoint hits no block" % d)
+    return out
+
+
+def norm(v):
+    """Bring a label to a comparison key."""
+    v = re.sub(r"<[^>]+>", " ", v or "")
+    return " ".join(html.unescape(v).split()).lower()
+
+
+def resolve_ids(nodes, conts, edges, meas_path):
+    """Map cell ids onto the dashboard blocks -- by ID, else by LABEL.
+
+    On a redraw (copy/paste instead of move) draw.io hands out NEW ids:
+    cpu0/tip0/preproc0 become 3/4/5. Pure id matching then finds nothing at
+    all. The labels stay, however, and they are unique enough -- the measured
+    block text (h3) is the key.
+
+    Ambiguous names (three times "Preproc" in the trio) are assigned in order
+    of their y position: topmost in the drawing -> row 0.
+    """
+    meas = json.loads(meas_path.read_text(encoding="utf-8"))
+    want = {}
+    for b in meas["blocks"]:
+        head = norm(b["texts"][0]["text"]) if b["texts"] else ""
+        want.setdefault(head, []).append(b["id"])
+    for k in want:
+        want[k].sort(key=lambda i: (i[:-1] if i[-1].isdigit() else i,
+                                    int(i[-1]) if i[-1].isdigit() else 0))
+
+    if all(any(n["id"] == b["id"] for b in meas["blocks"]) for n in nodes):
+        return nodes, conts, edges, 0        # the ids already match
+
+    # Containers are otherwise recognised by the id prefix "ct" -- which no
+    # longer exists after a redraw. They do carry the encoder label, though.
+    moved = [n for n in nodes if norm(n.get("label")).startswith("cedartools")]
+    if moved:
+        nodes = [n for n in nodes if n not in moved]
+        conts = list(conts) + moved
+
+    # The ingress stage has a different name per scenario (TIP adapter / ITI
+    # shim / H2E->TIP). Whoever puts "ITI shim" above the MicroBlaze in the
+    # drawing still means the ingress block -- hence an alias onto tip*.
+    INGRESS = ("tip adapter", "iti shim", "h2e->tip", "h2e -> tip")
+    tips = sorted([b["id"] for b in meas["blocks"] if b["id"].startswith("tip")])
+
+    # Blocks the dashboard does not know YET (someone drew in a "Kria PS")
+    # get a derived id instead of being discarded.
+    NEW = {"kria ps": "kriaps"}
+
+    used, ren, tipn, newn = {k: 0 for k in want}, {}, 0, {}
+    for n in sorted(nodes, key=lambda n: (n["y"], n["x"])):
+        lbl = norm(n.get("label"))
+        hit = next((k for k in want if lbl.startswith(k) and k), None)
+        if hit and used[hit] < len(want[hit]):
+            ren[n["id"]] = want[hit][used[hit]]
+            used[hit] += 1
+            continue
+        if any(lbl.startswith(i) for i in INGRESS) and tipn < len(tips):
+            ren[n["id"]] = tips[tipn]; tipn += 1
+            continue
+        base = next((v for k, v in NEW.items() if lbl.startswith(k)), None)
+        if base:
+            i = newn.get(base, 0); newn[base] = i + 1
+            ren[n["id"]] = "%s%d" % (base, i)
+    for i, c in enumerate(sorted(conts, key=lambda c: (c["y"], c["x"]))):
+        ren[c["id"]] = "ct%d" % i
+
+    for n in nodes + conts:
+        n["id"] = ren.get(n["id"], n["id"])
+    keep = []
+    for e in edges:
+        e["s"], e["t"] = ren.get(e["s"], e["s"]), ren.get(e["t"], e["t"])
+        if not e["s"][:1].isdigit() and not e["t"][:1].isdigit():
+            keep.append(e)
+    unresolved = sum(1 for n in nodes if n["id"][:1].isdigit())
+    return [n for n in nodes if not n["id"][:1].isdigit()], conts, keep, unresolved
+
+
+def geometry_for(sid):
+    # Hand-drawn variants carry their own name suffix and therefore lie
+    # outside every path the exporter writes to -- they cannot be steamrolled.
+    # They take precedence over everything else.
+    aw = sorted(GUI.glob("ctte_view_%s_aw*.drawio.svg" % sid))
+    svg = aw[-1] if aw else GUI / ("ctte_view_%s.drawio.svg" % sid)
+    if svg.exists():
+        txt = svg.read_text(encoding="utf-8", errors="replace")
+        mx_src = model_of(svg)
+        for name, xml in diagrams(mx_src):
+            if name in ("", sid):
+                nodes, conts, edges = parse_model(xml)
+                meas = GUI / "measured" / ("geo_%s.json" % sid)
+                # Drawings from compact_layout.py ALREADY carry the canonical
+                # ids -- sending them through resolve_ids() would mean guessing
+                # correct ids afresh from labels. That is genuinely dangerous:
+                # a block the older measurement did not know yet (axis0 in the
+                # MBV build) makes the all() shortcut fail, and after that the
+                # label matching reassigns ids by y position. The generator
+                # states in the mxfile that it was the author -- and BOTH marks
+                # are recognised: "devtools/..." is the current one (this
+                # repo), "gui/..." the one from the predecessor repository that
+                # every already-committed .drawio.svg still carries (they were
+                # copied, not regenerated -- a blind rename would have
+                # misclassified them here as hand-edited).
+                if ('agent="devtools/compact_layout.py"' in mx_src
+                        or 'agent="gui/compact_layout.py"' in mx_src):
+                    meas = None
+                if meas is not None and meas.exists():
+                    nodes, conts, edges, un = resolve_ids(nodes, conts, edges, meas)
+                    if un:
+                        print("  NOTE %s: %d cell(s) without a mapping "
+                              "(the label matches no block)" % (sid, un))
+                drawn = rendered_paths(txt, nodes, conts)
+                if drawn:
+                    # Drawn routes beat the ones derived from the model --
+                    # they ARE what was visible in the drawio.
+                    by = {(e["s"], e["t"]): e for e in drawn}
+                    for e in edges:
+                        d = by.get((e["s"], e["t"]))
+                        if d:
+                            # Take the head ALONG -- without the arrowhead an
+                            # edge is left as a stub (really measured: 1 of 10
+                            # heads made it through).
+                            e["pts"], e["path"] = d["pts"], d["path"]
+                            e["head"] = d.get("head")
+                    have = {(e["s"], e["t"]) for e in edges}
+                    edges += [d for d in drawn
+                              if (d["s"], d["t"]) not in have]
+                return nodes, conts, edges, svg.name
+    multi = GUI / "ctte_view.drawio"
+    if multi.exists():
+        for name, xml in diagrams(model_of(multi)):
+            if name == sid:
+                return parse_model(xml) + (multi.name,)
+    meas = GUI / "measured" / ("geo_%s.json" % sid)
+    if meas.exists():
+        return from_measured(meas) + (meas.name,)
+    raise SystemExit("no geometry source for scenario %r" % sid)
+
+
+def main() -> int:
+    cat = json.loads(SCEN.read_text(encoding="utf-8"))
+    src = INDEX.read_text(encoding="utf-8")
+    # Known blocks = the keys of NODE_TPL. A regex over the whole file raised
+    # false alarms for perfectly valid ids (34 warnings on correct geometry)
+    # -- a check that shouts at correct content gets ignored instead of read.
+    m = re.search(r"const NODE_TPL\s*=\s*\{(.*?)\n\};", src, re.S)
+    known = set()
+    if m:
+        for k in re.findall(r"(?m)^\s*([a-z][a-z0-9]*)\s*:", m.group(1)):
+            known.add(k[:-1] if k[-1].isdigit() else k)
+
+    out, total, warned = {}, 0, 0
+    for sc in cat["scenarios"]:
+        sid = sc["id"]
+        nodes, conts, edges, origin = geometry_for(sid)
+        for n in nodes:
+            base = n["id"][:-1] if n["id"][-1].isdigit() else n["id"]
+            if known and base not in known:
+                print("  WARNING %s: unknown block id %r -- taken over, "
+                      "but the dashboard has no template for it"
+                      % (sid, n["id"]))
+                warned += 1
+        allv = nodes + conts
+        ox = min([v["x"] for v in allv] or [0])
+        oy = min([v["y"] for v in allv] or [0])
+        # Only the matching here needs the labels, the runtime does not.
+        # Writing them out would carry core names back into the front-end
+        # code -- exactly what the corresponding test prevents.
+        for v in nodes + conts:
+            v.pop("label", None)
+        out[sid] = {"source": origin, "ox": ox, "oy": oy,
+                    "containers": conts, "nodes": nodes, "edges": edges}
+        total += len(nodes)
+        print("  %-11s %2d nodes · %d containers · %2d edges   <- %s"
+              % (sid, len(nodes), len(conts), len(edges), origin))
+
+    blob = "const ARCH_BY_SCEN=" + json.dumps(out, separators=(",", ":")) + ";"
+    i, j = src.index(BEGIN), src.index(END)
+    head = src[:i] + (
+        "/* ARCH-GEOMETRY-BEGIN (generated by devtools/sync_arch_view.py -- ONE "
+        "geometry PER SCENARIO; edit the drawio, then re-run; do not edit "
+        "by hand) */\n" + blob + "\n")
+    INDEX.write_text(head + src[j:], encoding="utf-8")
+    GEOJSON.write_text(json.dumps(out, indent=1), encoding="utf-8")
+    print("written: %d scenarios, %d nodes%s"
+          % (len(out), total, (" (%d warnings)" % warned) if warned else ""))
+    return 0
+
+
+if __name__ == "__main__":
+    sys.exit(main())
diff --git a/examples/dashboard/devtools/trio_dual_protocol_view.html b/examples/dashboard/devtools/trio_dual_protocol_view.html
new file mode 100644
index 0000000..96706e9
--- /dev/null
+++ b/examples/dashboard/devtools/trio_dual_protocol_view.html
@@ -0,0 +1,284 @@
+
+
+
+
+
+
+C-Trace Trio Gold -- N-Trace + E-Trace from one build
+
+
+
+

+  
C-Trace Trio Gold -- three CPUs, one stream, two protocols

+  

+

+
+

+  

+    
Architecture

+    

+      
+      
+      
+    

+    

+      
+        
+          
+        
+        
+      
+    

+    

+      Each core has its own C-Trace instance. Up to and including the eTIP FIFO the
+      path is identical; after that trTeProtocolSel (CSR 0x030, writable only
+      when Enable=0) steers the demux to the N-Trace or the
+      E-Trace backend. The funnel merges the three ATB streams message-atomically into
+      ONE ring -- in E-Trace mode it parses the length framing instead of MSEO and
+      prepends the source tag.
+    

+  

+
+  

+    

+      
Wire format per protocol

+      
N-Trace (Nexus/MSEO) -- 4 bytes per ATB beat,
+        MSEO bits carry the packet boundary, the source sits as an SRC field inside the message.

+      

+        TCODE|SRC ...MDO/MSEO
+        MDO/MSEO... END_IDLE
+        Padding
+      

+      
E-Trace (CTMX container) -- 1 byte per
+        ATB beat; packet length in the header, source as an inserted tag byte.

+      

+        1sssssss
Tag: src
+        0mm lllll
msg_type|len
+        payload[0]...
+        payload[len-1]
+        0mm lllll
next packet
+      

+      

+        Header bytes always have bit 7 set to 0, tag bytes always to 1 -- at
+        a packet boundary the distinction is therefore exact, not heuristic.
+        Payload is consumed only via the length. The split
+        (tools/etrace_trio_demux.py) yields one stream per source that is
+        byte-identical to a single-core capture -- the reference decoder stays
+        unchanged.
+      

+    

+
+    

+      
Verification

+      

+      

+    

+  

+
+  

+    
What each mode costs

+    

+    

+      Two levels, deliberately separated: the OOC rows compare a
+      single encoder in the identical CF-only baseline profile (Vivado 2026.1,
+      dual-clock) -- "what replaces what". The second backend in the SoC row, by
+      contrast, is a post-implementation delta between two trio bitstreams from the same flow (full
+      profile, PKT_MAX=208) -- "what does it cost in addition". Neither is
+      comparable with the historical 2022.1/2025.1 number family.
+      Details: docs/RESOURCE_COSTS_per_element.md section 6.
+    

+  

+
+  

+    
Open items / honest limitations

+    
    
+  
    
+
    
+
+
    
+
+
+
+
diff --git a/examples/dashboard/dis_to_symbols.py b/examples/dashboard/dis_to_symbols.py
new file mode 100644
index 0000000..a033dc6
--- /dev/null
+++ b/examples/dashboard/dis_to_symbols.py
@@ -0,0 +1,101 @@
+#!/usr/bin/env python3
+# SPDX-FileCopyrightText: 2026 Accemic Technologies GmbH
+# SPDX-License-Identifier: ISC
+"""objdump listing (`.dis`) -> symbol table + call/return sites.
+
+    py dis_to_symbols.py merged3.dis [more.dis ...] \\
+        -o symbols_cva6_linux.map --sites sites_cva6_linux.map
+
+Why from the LISTING and not from `nm vmlinux`: the listings the decoder needs
+anyway already carry the RIGHT addresses. A Linux boot runs through three
+address spaces (OpenSBI 0x6400_0000, kernel physical 0x6440_0000, kernel
+virtual 0xC000_0000, see sw/cva6_linux/make_listing.sh), and
+`make_listing.sh` relocates the physical copy with `objcopy
+--change-addresses`. An `nm vmlinux` only knows the virtual addresses -- the
+physical phase of the boot would stay unsymbolised.
+
+**Why the sites file exists (a measured defect, not caution):** deriving call
+depth from "a jump target is the start of a symbol" is WRONG. OpenSBI
+assembler names local labels (`_try_lottery`, `_relocate_done`), so an
+ordinary forward jump to one of them looked like a call that never returns --
+over a single boot the depth ran away to 2972 frames (measured on lb3.pcout,
+3,993,361 PCs). From the listing the question can be answered exactly, because
+objdump makes rd=ra visible through the mnemonic:
+
+    jal    rd=ra    -> call        j     rd=zero -> jump
+    jalr      rd=ra    -> call        jr       rd=zero -> jump
+    ret                     -> return
+
+Output:
+    symbols  `64000000 T _fw_start`          (System.map format)
+    sites    `C 6400000c` / `R 640003fc`     (call and return site)
+"""
+import argparse
+import re
+import sys
+from pathlib import Path
+
+LABEL = re.compile(r"^([0-9a-fA-F]{8,16})\s+<([^>]+)>:\s*$")
+INSN = re.compile(r"^\s*([0-9a-fA-F]+):\s+[0-9a-fA-F]+\s+(\S+)")
+CALL_MN = {"jal", "jalr"}      # rd=ra -- objdump shows this via the mnemonic
+RET_MN = {"ret"}               # objdump already renders 'jr ra' as 'ret'
+
+
+def extract(paths):
+    syms, calls, rets = {}, set(), set()
+    for p in paths:
+        ns = nc = nr = 0
+        with open(p, "r", encoding="utf-8", errors="replace") as f:
+            for line in f:
+                m = LABEL.match(line)
+                if m:
+                    a = int(m.group(1), 16)
+                    if a not in syms:
+                        syms[a] = m.group(2)
+                        ns += 1
+                    continue
+                m = INSN.match(line)
+                if not m:
+                    continue
+                mn = m.group(2)
+                if mn in CALL_MN:
+                    calls.add(int(m.group(1), 16))
+                    nc += 1
+                elif mn in RET_MN:
+                    rets.add(int(m.group(1), 16))
+                    nr += 1
+        print("%-24s %7d symbols  %7d call sites  %7d return sites"
+              % (Path(p).name, ns, nc, nr), file=sys.stderr)
+    return syms, calls, rets
+
+
+def main():
+    ap = argparse.ArgumentParser()
+    ap.add_argument("dis", nargs="+", help="objdump -d listing(s)")
+    ap.add_argument("-o", "--out", default="-", help="symbol table (default: stdout)")
+    ap.add_argument("--sites", default=None,
+                    help="call/return sites; WITHOUT this file the call depth in "
+                         "the dashboard stays deliberately empty")
+    a = ap.parse_args()
+    syms, calls, rets = extract(a.dis)
+    if not syms:
+        print("### NO symbol found -- is this really an 'objdump -d' listing?",
+              file=sys.stderr)
+        return 1
+    body = "\n".join("%08x T %s" % (addr, syms[addr]) for addr in sorted(syms)) + "\n"
+    if a.out == "-":
+        sys.stdout.write(body)
+    else:
+        Path(a.out).write_text(body, encoding="utf-8")
+    print("%d symbols -> %s" % (len(syms), a.out), file=sys.stderr)
+    if a.sites:
+        s = "".join("C %08x\n" % x for x in sorted(calls))
+        s += "".join("R %08x\n" % x for x in sorted(rets))
+        Path(a.sites).write_text(s, encoding="utf-8")
+        print("%d call sites + %d return sites -> %s"
+              % (len(calls), len(rets), a.sites), file=sys.stderr)
+    return 0
+
+
+if __name__ == "__main__":
+    sys.exit(main())
diff --git a/examples/dashboard/gen_regmap.py b/examples/dashboard/gen_regmap.py
new file mode 100644
index 0000000..885cd32
--- /dev/null
+++ b/examples/dashboard/gen_regmap.py
@@ -0,0 +1,475 @@
+# SPDX-FileCopyrightText: 2026 Accemic Technologies GmbH
+# SPDX-License-Identifier: ISC
+"""Generate regmap.json for the CEDARtools.TraceEncoder KV260 dashboard.
+
+Compiles the full-profile RDL (rdl/ct_cs_cpuif.rdl, no CT_PROFILE_NO_*
+defines = Vollausstattung) with systemrdl-compiler and walks the elaborated
+tree into a flat JSON register list. The SoC CTRL region registers
+(mbv_soc_top.sv, not RDL-described) are appended by hand here so the
+dashboard has ONE machine-readable source for everything it shows.
+
+Output: examples/dashboard/regmap.json
+Regenerate after every RDL change: py gen_regmap.py   (from examples/dashboard/)
+"""
+import json
+import sys
+from pathlib import Path
+
+from systemrdl import RDLCompiler, RDLCompileError
+from systemrdl.node import RegNode, MemNode
+
+# REPO is the repository root: examples/dashboard/gen_regmap.py -> examples
+# -> repo root (two levels up). In this repository the RDL source lives at
+# the repo-root rdl/ directly -- unlike the predecessor repository, which vendored a CTTE
+# fork under third_party/CTTE/rdl/, this repository's rdl/ IS the source.
+REPO = Path(__file__).resolve().parents[2]
+RDL = REPO / "rdl" / "ct_cs_cpuif.rdl"
+OUT = Path(__file__).resolve().parent / "regmap.json"
+
+# KV260 aperture (trio_soc_top.sv seg_of decode; Trio seit 2026-07-24, Gate C4)
+REGIONS = {
+    "ctrl":  {"base": 0xA0000000, "size": 0x10000,  "name": "SoC CTRL (trio_soc_top)"},
+    "enc":   {"base": 0xA0010000, "size": 0x10000,  "name": "CTTE Encoder 0 CSRs (MBV)"},
+    "enc1":  {"base": 0xA0020000, "size": 0x10000,  "name": "CTTE Encoder 1 CSRs (TGC5B)"},
+    "enc2":  {"base": 0xA0030000, "size": 0x10000,  "name": "CTTE Encoder 2 CSRs (CVA6)"},
+    "ram1":  {"base": 0xA0080000, "size": 0x10000,  "name": "TGC5B Program/Data RAM (64 KiB)"},
+    "ram":   {"base": 0xA0100000, "size": 0x20000,  "name": "MBV Program/Data RAM (128 KiB)"},
+    "trace": {"base": 0xA0200000, "size": 0x100000, "name": "ATB Trace Ring (gemergt, URAM)"},
+    "axis":  {"base": 0xA0300000, "size": 0x100000, "name": "AXIS Capture BRAM"},
+}
+
+
+def access_rule(d):
+    """One English sentence per field: what a write/read REALLY does.
+
+    Written after the question "are the accesses the dashboard offers really
+    read/write?" turned out to have no good answer.
+    `sw = rw` is only half the truth -- the RDL carries
+    four further properties that decide whether a write arrives at all, and
+    the dashboard used to show none of them:
+      swwel        write is silently dropped while trTeControl.Enable=1
+                   (ct_cs_cpuif.sv:1239; cpuif_wr_err is tied to 0, so the
+                   bus cycle ends with OKAY either way)
+      onwrite=woclr  write-1-clears -- a read-modify-write of the whole word
+                   wipes the bit (that is the overflow evidence)
+      singlepulse  self-clearing strobe: reads back 0, never holds the value
+      swacc        the READ has a side effect (moves a pointer)
+    Text, not code, because the consumer is the operator: the badge in the
+    UI is derived from the same machine-readable flags right next to it.
+    """
+    parts = []
+    if d.get("pulse"):
+        parts.append("write-1 pulse: self-clearing, always reads back 0")
+    elif d.get("w1c"):
+        parts.append("write-1-to-clear: a read-modify-write of the whole "
+                     "register clears this bit unintentionally")
+    if d.get("gated"):
+        parts.append("writable only while trTeControl.Enable=0 -- a write "
+                     "while enabled is discarded WITHOUT an error response")
+    if d.get("swacc"):
+        parts.append("reading has a side effect (see the register description)")
+    if not parts:
+        parts.append("read-only" if d["sw"] == "r" else "freely writable")
+    return "; ".join(parts)
+
+
+def field_json(f):
+    d = {
+        "name": f.inst_name,
+        "lsb": f.lsb,
+        "msb": f.msb,
+        "sw": f.get_property("sw").name,
+        "hw": f.get_property("hw").name,
+        "reset": None,
+        "desc": (f.get_property("desc") or "").strip(),
+    }
+    rst = f.get_property("reset")
+    if isinstance(rst, int):
+        d["reset"] = rst
+    enc = f.get_property("encode")
+    if enc is not None:
+        d["enum"] = {
+            str(int(m.value)): {"name": m.name, "desc": (m.rdl_desc or "").strip()}
+            for m in enc
+        }
+    swwel = f.get_property("swwel")
+    if swwel not in (None, False, True):
+        d["gated"] = "trTeControl.Enable=0"
+    ow = f.get_property("onwrite")
+    if ow is not None:
+        d["onwrite"] = ow.name
+        if ow.name == "woclr":
+            d["w1c"] = True
+    if f.get_property("singlepulse"):
+        d["pulse"] = True
+    if f.get_property("swacc"):
+        d["swacc"] = True
+    d["access_rule"] = access_rule(d)
+    return d
+
+
+def reg_json(r, region, group=None):
+    fields = [field_json(f) for f in r.fields()]
+    return {
+        "region": region,
+        "offset": r.absolute_address,
+        "path": r.get_path(array_suffix="[{index:d}]"),
+        "name": r.get_property("name") or r.inst_name,
+        "desc": (r.get_property("desc") or "").strip(),
+        "fields": fields,
+        # Register-level marker: ANY field with a read side effect makes the
+        # whole register unsafe for the panel poller -- a block read across
+        # it moves the pointer just as a targeted read does. The poller and
+        # the cluster builder key on THIS flag, never on a register name
+        # (the name-based filter caught TipFifoHistData and missed
+        # trWpReadHigh -- FINDINGS_u3 §2.2).
+        **({"read_side_effect": True} if any(f.get("swacc") for f in fields) else {}),
+        **({"group": group} if group else {}),
+    }
+
+
+def main():
+    rdlc = RDLCompiler()
+    try:
+        rdlc.compile_file(str(RDL))
+        root = rdlc.elaborate(top_def_name="ct_cs_cpuif")
+    except RDLCompileError as e:
+        sys.exit(f"RDL compile failed: {e}")
+
+    top = root.top
+    regs = []
+    mems = []
+
+    for node in top.descendants(unroll=True):
+        if isinstance(node, MemNode):
+            entry_regs = []
+            for vr in node.children(unroll=False):
+                if isinstance(vr, RegNode):
+                    entry_regs.append({
+                        "entry_offset": vr.raw_address_offset,
+                        "name": vr.get_property("name") or vr.inst_name,
+                        "inst": vr.inst_name,
+                        "desc": (vr.get_property("desc") or "").strip(),
+                        "fields": [field_json(f) for f in vr.fields()],
+                    })
+            mems.append({
+                "region": "enc",
+                "offset": node.absolute_address,
+                "path": node.get_path(),
+                "name": node.get_property("name") or node.inst_name,
+                "desc": (node.get_property("desc") or "").strip(),
+                "entries": node.get_property("mementries"),
+                "stride": node.get_property("memwidth") // 8,
+                "entry_regs": entry_regs,
+            })
+        elif isinstance(node, RegNode):
+            if not node.get_property("ispresent"):
+                continue
+            if isinstance(node.parent, MemNode):
+                continue  # virtual regs are emitted inside their mem
+            regs.append(reg_json(node, "enc"))
+
+    # SoC CTRL region (hand-described; source: rtl/board_kv260/mbv_soc_top.sv)
+    ctrl_regs = [
+        {"region": "ctrl", "offset": 0x00, "path": "soc.CONTROL", "name": "SoC Control Register",
+         "desc": "Board-level control (mbv_soc_top). Core is held in reset while core_run=0; "
+                 "load RAM and configure the encoder first, then set core_run=1.",
+         "fields": [
+             {"name": "core_run", "lsb": 0, "msb": 0, "sw": "rw", "hw": "r", "reset": 0,
+              "desc": "1: release the MicroBlaze V core from reset (run). 0: hold core in reset."},
+             {"name": "trace_clear", "lsb": 1, "msb": 1, "sw": "rw", "hw": "r", "reset": 0,
+              "desc": "1: clear the trace capture buffer and byte/beat counters."},
+             {"name": "trace_flush", "lsb": 2, "msb": 2, "sw": "rw", "hw": "r", "reset": 0,
+              "desc": "1: assert ATB flush (afvalid) so the encoder drains buffered trace."},
+             {"name": "irq_gen_en", "lsb": 3, "msb": 3, "sw": "rw", "hw": "r", "reset": 0,
+              "desc": "1: enable HW IRQ pulse generator (1-cycle pulse every 4096 clks ~ 55 us "
+                      "@75 MHz) into the core's external interrupt (G6 hardening)."},
+             {"name": "cva6_run", "lsb": 5, "msb": 5, "sw": "rw", "hw": "r", "reset": 0,
+              "desc": "1: release the CVA6 core (soc2) from reset. Independent of core_run: "
+                      "set only AFTER the program was loaded into the reserved PS-DDR window "
+                      "at 0x6400_0000 (devmem; examples/kv260/SPEC_board_memory_map.md)."},
+             # U1 (2026-08-14): per-core release bits. Additive -- b0 keeps
+             # meaning "all cores of this SoC", effective is b0 | b(8+i)
+             # (tgc5b2_axis_soc_top.sv:182-183, duo_soc_top.sv:151-152,
+             # trio_soc_top.sv:227-228,234; SPEC_axis_wp_memory_map.md §10).
+             {"name": "core0_run", "lsb": 8, "msb": 8, "sw": "rw", "hw": "r", "reset": 0,
+              "desc": "1: release core 0 alone (tgc5b2: TGC5B-0, duo/trio: MicroBlaze V). "
+                      "Effective run state is core_run | core0_run, so b0 still starts "
+                      "everything. Reads 0 on single-core designs and on pre-U1 bitstreams.",
+              "access_rule": "freely writable; the RAM window of THIS core is only "
+                             "accessible while its effective run bit is 0 -- an access to "
+                             "the RAM of a running core never gets ready and HANGS the AXI "
+                             "transaction (SPEC §10 point 2)"},
+             {"name": "core1_run", "lsb": 9, "msb": 9, "sw": "rw", "hw": "r", "reset": 0,
+              "desc": "1: release core 1 alone (tgc5b2: TGC5B-1, duo/trio: TGC5B). "
+                      "Effective run state is core_run | core1_run. Reads 0 on single-core "
+                      "designs and on pre-U1 bitstreams.",
+              "access_rule": "freely writable; the RAM window of THIS core is only "
+                             "accessible while its effective run bit is 0 (SPEC §10 point 2)"},
+             {"name": "cva6_run2", "lsb": 10, "msb": 10, "sw": "rw", "hw": "r", "reset": 0,
+              "desc": "trio only: second release bit of the CVA6, OR-ed with the historic "
+                      "b5 cva6_run (trio_soc_top.sv:234). Exists so all three cores have a "
+                      "bit in the same b8..b10 field; b5 keeps working unchanged.",
+              "access_rule": "freely writable; alias of b5 (effective cva6_run = b5 | b10)"},
+         ]},
+        {"region": "ctrl", "offset": 0x04, "path": "soc.STATUS", "name": "SoC Status Register",
+         "desc": "Board-level status (read-only).",
+         "fields": [
+             {"name": "trace_wrapped", "lsb": 0, "msb": 0, "sw": "r", "hw": "w", "reset": 0,
+              "desc": "1: the trace capture RING buffer has wrapped at least once -- the "
+                      "oldest beats were overwritten (capture continues; nothing stalls). "
+                      "Clear via CONTROL.trace_clear."},
+             {"name": "axis_overflow", "lsb": 1, "msb": 1, "sw": "r", "hw": "w", "reset": 0,
+              "desc": "1: AXIS capture BRAM overflowed."},
+             # U1: STATUS mirrors the EFFECTIVE run state, so a host learns
+             # with ONE read which core is actually running instead of
+             # keeping shadow bookkeeping (tgc5b2_axis_soc_top.sv:584,
+             # duo_soc_top.sv:546, trio_soc_top.sv:718).
+             {"name": "core0_running", "lsb": 8, "msb": 8, "sw": "r", "hw": "w", "reset": 0,
+              "desc": "1: core 0 is effectively released (CONTROL.core_run | "
+                      "CONTROL.core0_run). Reads 0 on pre-U1 bitstreams."},
+             {"name": "core1_running", "lsb": 9, "msb": 9, "sw": "r", "hw": "w", "reset": 0,
+              "desc": "1: core 1 is effectively released (CONTROL.core_run | "
+                      "CONTROL.core1_run). Reads 0 on pre-U1 bitstreams."},
+             {"name": "cva6_running", "lsb": 10, "msb": 10, "sw": "r", "hw": "w", "reset": 0,
+              "desc": "trio only: 1 = the CVA6 is effectively released "
+                      "(CONTROL.cva6_run | CONTROL.cva6_run2)."},
+         ]},
+        {"region": "ctrl", "offset": 0x08, "path": "soc.TRACE_BEATS", "name": "Trace Beats Counter",
+         "desc": "Total captured ATB beats since last trace_clear (monotonic, does NOT stop "
+                 "at the ring capacity). Ring write position = TRACE_BEATS % (TRACE_BUFSZ/4).",
+         "fields": [{"name": "Value", "lsb": 0, "msb": 31, "sw": "r", "hw": "w", "reset": 0,
+                     "desc": "ATB beats captured since last trace_clear (monotonic)."}]},
+        {"region": "ctrl", "offset": 0x0C, "path": "soc.TRACE_BYTES", "name": "Trace Bytes Counter",
+         "desc": "Total captured ATB bytes since last trace_clear (monotonic). "
+                 "Poll delta = live trace bandwidth.",
+         "fields": [{"name": "Value", "lsb": 0, "msb": 31, "sw": "r", "hw": "w", "reset": 0,
+                     "desc": "ATB bytes captured since last trace_clear (monotonic)."}]},
+        {"region": "ctrl", "offset": 0x10, "path": "soc.AXIS_BEATS", "name": "AXIS Beats Counter",
+         "desc": "Number of captured AXIS beats (read-only).",
+         "fields": [{"name": "Value", "lsb": 0, "msb": 31, "sw": "r", "hw": "w", "reset": 0,
+                     "desc": "AXIS beats captured since last trace_clear."}]},
+        {"region": "ctrl", "offset": 0x14, "path": "soc.TRACE_BUFSZ", "name": "Trace Ring Capacity",
+         "desc": "Capacity of the ATB trace capture ring buffer in bytes (read-only; "
+                 "1 MiB URAM in the G7 build). Reads 0 on pre-ring bitstreams.",
+         "fields": [{"name": "Value", "lsb": 0, "msb": 31, "sw": "r", "hw": "w", "reset": 0,
+                     "desc": "Ring capacity in bytes (TRACE_DEPTH * 4)."}]},
+        {"region": "ctrl", "offset": 0x18, "path": "soc.SINK_CTRL", "name": "Trace Sink Control",
+         "desc": "Enables/config of the additional trace sinks (DDR4 + PIB). Both sinks "
+                 "observe the funnel-merged ATB stream in parallel to the URAM ring and "
+                 "never back-pressure the trace path (own FIFO + drop counters).",
+         "fields": [
+             {"name": "ddr_en", "lsb": 0, "msb": 0, "sw": "rw", "hw": "r", "reset": 0,
+              "desc": "1: DDR4 sink enabled (writes beats to PS DDR at DDR_BASE)."},
+             {"name": "ddr_clear", "lsb": 1, "msb": 1, "sw": "rw", "hw": "r", "reset": 0,
+              "desc": "W1 pulse (only while ddr_en=0): reset DDR_WPTR/full/wrapped/err/"
+                      "drops -- and SINK_STAT.ddr_cfg_rej, the refusal marker of the "
+                      "U6 window interlock.",
+              # ct_trace_sinks.sv:125 masks b1 out of the stored word
+              # (SINK_WR_MASK = 0xFFFF_FFDD) and turns it into a one-cycle
+              # pulse (:142-146) -- it never reads back as 1. The rule "only
+              # while ddr_en=0" is a CONTRACT, not hardware: the pulse fires
+              # regardless, only the button path refuses it (server.py
+              # _ctl ddr_clear). FINDINGS_u3 §2.5 / row 21.
+              "pulse": True,
+              "access_rule": "write-1 pulse: self-clearing, always reads back 0; clear "
+                             "only while ddr_en=0 -- the hardware does NOT enforce that, "
+                             "a pulse during an active capture resets its counters"},
+             {"name": "ddr_circ", "lsb": 2, "msb": 2, "sw": "rw", "hw": "r", "reset": 0,
+              "desc": "DDR capture mode: 0 = one shot (stop when full), 1 = circular "
+                      "(wrap modulo DDR_SIZE, keeps the most recent bytes; write "
+                      "offset = DDR_WPTR % DDR_SIZE). Switch only while cleared."},
+             {"name": "uram_oneshot", "lsb": 3, "msb": 3, "sw": "rw", "hw": "r", "reset": 0,
+              "desc": "URAM trace buffer mode: 0 = circular ring (default, keeps the "
+                      "most recent 1 MiB), 1 = one shot (capture stops when full, "
+                      "keeps the FIRST 1 MiB; SINK_STAT.uram_stopped sets)."},
+             {"name": "pib_en", "lsb": 4, "msb": 4, "sw": "rw", "hw": "r", "reset": 0,
+              "desc": "1: PIB parallel trace port enabled (pib_clk runs, beats serialized)."},
+             {"name": "pib_clear", "lsb": 5, "msb": 5, "sw": "rw", "hw": "r", "reset": 0,
+              "desc": "W1 pulse (only while pib_en=0): reset PIB drop counter.",
+              "pulse": True,
+              "access_rule": "write-1 pulse: self-clearing, always reads back 0; the "
+                             "hardware does NOT enforce the pib_en=0 rule "
+                             "(ct_trace_sinks.sv:125,142-146)"},
+             {"name": "pib_calib", "lsb": 6, "msb": 6, "sw": "rw", "hw": "r", "reset": 0,
+              "desc": "1: PIB emits the calibration pattern instead of trace "
+                      "(reference trPibCalibrate); the trace input is not consumed."},
+             {"name": "pib_div", "lsb": 8, "msb": 10, "sw": "rw", "hw": "r", "reset": 0,
+              "desc": "PIB port clock divider: pib_clk = clk / 2^(div+1); 0 is clamped "
+                      "to 1 (max 18.75 MHz @75 MHz core -> 18.75 MB/s byte rate)."},
+             {"name": "pib_pattern", "lsb": 12, "msb": 13, "sw": "rw", "hw": "r", "reset": 0,
+              "desc": "Calibration pattern (reference trPibCalibPattern): "
+                      "0 = STANDARD (AA 55 00 FF), 1 = MOVING_ONE (walking 1), "
+                      "2 = MOVING_ZERO (walking 0).",
+              "enum": {0: {"name": "STANDARD"}, 1: {"name": "MOVING_ONE"},
+                       2: {"name": "MOVING_ZERO"}}},
+         ]},
+        {"region": "ctrl", "offset": 0x34, "path": "soc.FUNNEL_CTRL", "name": "Trace Funnel Control",
+         "desc": "Per-channel arbitration priority of the message-atomic trace funnel "
+                 "(ct_L1_funnel, MAX_PRIO=3). Higher value wins on message boundaries; "
+                 "equal values arbitrate round-robin. Live-writable (takes effect at "
+                 "the next message boundary). The reference-PIB funnel CSRs "
+                 "(trFunnelArbMode/Shed*) are not part of this build.",
+         "fields": [
+             {"name": "prio_ch0", "lsb": 0, "msb": 1, "sw": "rw", "hw": "r", "reset": 1,
+              "desc": "Priority of channel 0 (Encoder 0, MBV)."},
+             {"name": "prio_ch1", "lsb": 4, "msb": 5, "sw": "rw", "hw": "r", "reset": 1,
+              "desc": "Priority of channel 1 (Encoder 1, TGC5B)."},
+             {"name": "prio_ch2", "lsb": 8, "msb": 9, "sw": "rw", "hw": "r", "reset": 1,
+              "desc": "Priority of channel 2 (Encoder 2, CVA6)."},
+             # The register keeps a fourth bit that the card did not show
+             # (trio_soc_top.sv:253,507,699). Its write mask is 0x0001_0333 --
+             # every other bit reads back 0 no matter what was written, which
+             # is exactly the class of write the readback check now reports.
+             {"name": "te_tag_always", "lsb": 16, "msb": 16, "sw": "rw", "hw": "r", "reset": 0,
+              "desc": "E-Trace mode: emit a source tag in front of EVERY packet instead of "
+                      "only after a channel switch (funnel te_tag_always). No effect in "
+                      "N-Trace mode.",
+              "access_rule": "freely writable; the register write mask is 0x0001_0333 -- "
+                             "bits outside it are dropped silently"},
+         ]},
+        # Address plan v4: the reset default of the ct_trace_sinks designs is
+        # 0x5000_0000 + 256 MiB. It does NOT hold globally -- the tops with
+        # their own sink wiring still sit at 0x6000_0000 + 64 MiB. The number
+        # here is therefore a statement of origin, not a promise: the
+        # dashboard computes everywhere from the register value it READ
+        # (index.html ddr_fill/ddr_wptr), never from this constant.
+        {"region": "ctrl", "offset": 0x1C, "path": "soc.DDR_BASE", "name": "DDR Sink Base Address",
+         "desc": "Byte address of the linear DDR capture buffer in PS DDR (32-byte "
+                 "aligned; low bits are masked). Reset 0x5000_0000 = start of the "
+                 "reserved PL window 0x5000_0000..0x6FFF_FFFF (512 MiB, no-map via "
+                 "ctrace_resmem.dtso; examples/kv260/SPEC_board_memory_map.md address plan v4) "
+                 "for every ct_trace_sinks design (tgc5b2/duo/trio, package U6) and "
+                 "for rocket2. The tops that still wire their own sink (rocket, "
+                 "cva6_2, cva6_linux, cva6_linux64) reset to 0x6000_0000 -- read the "
+                 "register, do not assume it. Keep inside the reserved window when "
+                 "reconfiguring.",
+         "fields": [{"name": "Value", "lsb": 0, "msb": 31, "sw": "rw", "hw": "r",
+                     "reset": 0x50000000,
+                     "desc": "PS DDR byte address (32-byte aligned).",
+                     # The rule is hardware now, no longer just text:
+                     # ct_trace_sinks.sv:203-222 does NOT accept the write
+                     # while ddr_en=1 and reports it in SINK_STAT b4. On the
+                     # tops with their own sink wiring the older behaviour
+                     # still applies (the write goes through).
+                     # The hardware interlock only covers the ARMED sink --
+                     # with ddr_en=0 it accepts any value (proven on the
+                     # board: 0x8000_0000, readback identical). The dashboard
+                     # therefore locks both window registers by POLICY:
+                     # display instead of an input field, /api/write answers
+                     # 403. `sw` stays "rw" -- that is the HARDWARE truth, and
+                     # a register map that falsifies it would be the next
+                     # piece of documentation drift.
+                     "policy_ro": True,
+                     "access_rule": "READ-ONLY BY POLICY in the dashboard (U9): the window "
+                                    "is fixed by the bitstream reset and by the boot "
+                                    "reserved-memory region -- /api/write answers 403 for "
+                                    "this register, and the panel shows it without an input "
+                                    "field. The HARDWARE is weaker: a write while the sink "
+                                    "is armed is REFUSED (U6 interlock, SINK_STAT b4 "
+                                    "ddr_cfg_rej), but at ddr_en=0 it is taken, and on the "
+                                    "older tops with their own sink wiring it is taken even "
+                                    "while the AXI write master is RUNNING"}]},
+        {"region": "ctrl", "offset": 0x20, "path": "soc.DDR_SIZE", "name": "DDR Sink Buffer Size",
+         "desc": "Capture buffer size in bytes (multiple of 4; configurable from the "
+                 "DDR panel). Reset 0x1000_0000 (256 MiB, address plan v4: the trace "
+                 "window 0x5000_0000..0x5FFF_FFFF, 64 MiB clear of the guest code "
+                 "window at 0x6400_0000). The tops with their own sink wiring still "
+                 "reset to 0x0400_0000 (64 MiB). One shot: when full, "
+                 "SINK_STAT.ddr_full sets and further beats are dropped (counted). "
+                 "Circular: write offset wraps modulo this size.",
+         "fields": [{"name": "Value", "lsb": 0, "msb": 31, "sw": "rw", "hw": "r",
+                     "reset": 0x10000000,
+                     "desc": "Buffer size in bytes; 0 disables writes.",
+                     # The same policy as for DDR_BASE -- a size that reaches
+                     # past the reservation is as dangerous as a wrong base
+                     # (the master then writes beyond the reserved window).
+                     "policy_ro": True,
+                     "access_rule": "READ-ONLY BY POLICY in the dashboard (U9): a size that "
+                                    "reaches past the reserved region is as dangerous as a "
+                                    "wrong base -- /api/write answers 403 for this register "
+                                    "and the panel shows it without an input field. The "
+                                    "HARDWARE is weaker: a write while the sink is armed is "
+                                    "REFUSED (U6 interlock, SINK_STAT b4 ddr_cfg_rej, it "
+                                    "would let one burst escape the buffer), but at "
+                                    "ddr_en=0 it is taken, and on the older tops with their "
+                                    "own sink wiring it changes the wrap point of a RUNNING "
+                                    "capture"}]},
+        {"region": "ctrl", "offset": 0x24, "path": "soc.DDR_WPTR", "name": "DDR Sink Write Pointer",
+         "desc": "TOTAL bytes written since last ddr_clear (monotonic, read-only). One "
+                 "shot: host reads [DDR_BASE, DDR_BASE+min(WPTR,SIZE)). Circular: write "
+                 "offset = WPTR % SIZE; chronological order = [off..SIZE) ++ [0..off) "
+                 "once wrapped (same contract as the URAM ring).",
+         "fields": [{"name": "Value", "lsb": 0, "msb": 31, "sw": "r", "hw": "w", "reset": 0,
+                     "desc": "Bytes written (completed AXI bursts only)."}]},
+        {"region": "ctrl", "offset": 0x28, "path": "soc.SINK_STAT", "name": "Trace Sink Status",
+         "desc": "Sink status flags (read-only; DDR bits cleared by ddr_clear).",
+         "fields": [
+             {"name": "ddr_full", "lsb": 0, "msb": 0, "sw": "r", "hw": "w", "reset": 0,
+              "desc": "1: DDR buffer full in one-shot mode; further beats drop."},
+             {"name": "ddr_axi_err", "lsb": 1, "msb": 1, "sw": "r", "hw": "w", "reset": 0,
+              "desc": "1: an AXI write returned BRESP != OKAY (sticky)."},
+             {"name": "ddr_wrapped", "lsb": 2, "msb": 2, "sw": "r", "hw": "w", "reset": 0,
+              "desc": "1: circular DDR buffer wrapped at least once (oldest bytes "
+                      "overwritten)."},
+             {"name": "uram_stopped", "lsb": 3, "msb": 3, "sw": "r", "hw": "w", "reset": 0,
+              "desc": "1: URAM one-shot capture stopped (buffer full, first 1 MiB kept)."},
+             # This bit closed the class "the display keeps a state to
+             # itself": without it the operator only sees that the value did
+             # not arrive, and takes that for masking (WARL) rather than for
+             # a refusal.
+             {"name": "ddr_cfg_rej", "lsb": 4, "msb": 4, "sw": "r", "hw": "w", "reset": 0,
+              "desc": "1: a DDR_BASE/DDR_SIZE write was REFUSED because the sink was "
+                      "armed (ddr_en=1) -- sticky until ddr_clear (U6 window "
+                      "interlock, ct_trace_sinks.sv). Reads 0 on the pre-U6 "
+                      "bitstreams and on the tops that wire their own sink; there "
+                      "the write is taken over while the master runs."},
+         ]},
+        {"region": "ctrl", "offset": 0x2C, "path": "soc.DDR_DROPS", "name": "DDR Sink Dropped Beats",
+         "desc": "Beats dropped by the DDR sink (FIFO overflow or buffer full; "
+                 "saturating; read-only).",
+         "fields": [{"name": "Value", "lsb": 0, "msb": 31, "sw": "r", "hw": "w", "reset": 0,
+                     "desc": "Dropped beats since ddr_clear."}]},
+        {"region": "ctrl", "offset": 0x30, "path": "soc.PIB_DROPS", "name": "PIB Dropped Beats",
+         "desc": "Beats dropped by the PIB sink (FIFO overflow when the port rate is "
+                 "below the trace rate; saturating; read-only).",
+         "fields": [{"name": "Value", "lsb": 0, "msb": 31, "sw": "r", "hw": "w", "reset": 0,
+                     "desc": "Dropped beats since pib_clear."}]},
+        {"region": "ctrl", "offset": 0x38, "path": "soc.DDR_BEATS", "name": "DDR Sink Beat Counter",
+         "desc": "Beats offered to the DDR sink while ddr_en (accepted = BEATS - "
+                 "DDR_DROPS; cleared by ddr_clear; read-only) -- the cheap proof that "
+                 "beats reach the sink at all. NOTE: this counter sat at 0x30 in the "
+                 "tgc5b2 C0B_DDR build; since the shared three-sink subsystem (T2, "
+                 "ct_trace_sinks) it lives at 0x38 for ALL designs and 0x30 is "
+                 "PIB_DROPS (docs/SPEC_axis_wp_memory_map.md §9).",
+         "fields": [{"name": "Value", "lsb": 0, "msb": 31, "sw": "r", "hw": "w", "reset": 0,
+                     "desc": "Beats offered to the DDR sink since ddr_clear."}]},
+    ]
+
+    # Encoder 1 (TGC5B): identical RDL register list, its own region. The
+    # dashboard code picks the region by pipeline row; the register data are
+    # NOT duplicated here (regs apply to enc; enc1 is read and written in the
+    # UI through the region alias).
+
+    # Every field carries an access_rule -- including the hand-written ones
+    # above. The UI must be able to rely on that key; a field without a rule
+    # would be back to the blanket "rw" this work set out to abolish.
+    for r in ctrl_regs:
+        for f in r["fields"]:
+            f.setdefault("access_rule", access_rule(f))
+
+    out = {
+        "generated_from": str(RDL.relative_to(REPO)).replace("\\", "/"),
+        "profile": "FULL (Vollausstattung, no CT_PROFILE_NO_* defines)",
+        "regions": REGIONS,
+        "regs": ctrl_regs + regs,
+        "mems": mems,
+    }
+    OUT.write_text(json.dumps(out, indent=1), encoding="utf-8")
+    n_fields = sum(len(r["fields"]) for r in out["regs"])
+    print(f"regmap.json: {len(out['regs'])} regs / {n_fields} fields / {len(mems)} mems "
+          f"-> {OUT} ({OUT.stat().st_size//1024} KiB)")
+
+
+if __name__ == "__main__":
+    main()
diff --git a/examples/dashboard/index.html b/examples/dashboard/index.html
new file mode 100644
index 0000000..e7b0c04
--- /dev/null
+++ b/examples/dashboard/index.html
@@ -0,0 +1,5005 @@
+
+
+
+
+
+
+CEDARtools.TraceEncoder (CTTE) — Dual-Core Dashboard
+
+
+
+
    
+  
+  
    
+    
    CEDARtools.TraceEncoder
    
+    
    RISC-V Nexus / N-Trace encoder · KV260
    
+  
    
+  
+    
+    
+    
+  
+  connecting…
+  
+  FULL profile
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  
+  trace 0 B/s · captured 0 B
+  
+
    
+
+
+  
    
+    
    Preferences — colour scheme
    
+    
+  
    
+  
    
+    
    
+    
    Tokens of the selected scheme (editable)
    
+    
+    
    
+      Changes apply immediately and stay stored in this browser.
+      A scheme becomes permanent for everyone once it is in
+      examples/dashboard/themes.json —
+      “Save to file” writes the current state exactly there.
+    
    
+  
    
+  
    
+    
+    
+    
+  
    
+    
+
    
+
    
+  
    
+    
    
+      
    instructions reconstructed
    –
    
+      
    Minstr/s (decoder on this host)
    
+    
    
+      
    Trace Bits per Instruction (stream bandwidth: –)
    
+      
    
+        
    – bpi
+          
    
+    
    
+      
    where it is running
    –
    
+      
    no symbol table loaded
    
+    
+    
+  
    
+
+  
    
+  
    
+    traced core
+    trace ingress
+    N-Trace chain
+    E-Trace chain
+    funnel
+    sink
+    side path
+    
+    click a block for its live registers
+  
    
+  
    
+
+  
    
+    
    
+      
+      
+      
+      
+      
+      
+      
+      
+      
+    
    
+    
    
+
+      
    
+        
    
+        
    
+          
    
+            –
+            
+            
+            
+          
    
+          
    
+          
    
+            
+            
+          
    
+        
    
+        
+        
    
+      
    
+
+      
+
+      
+
+      
+
+      
+      
    
+
+      
+
+      
+      
+      
+    
    
+  
    
+
    
+
+
    
+  
    Select a block
    
+  
+  
+  
    
+  
+  
    Click any block in the architecture view to inspect its control/status registers (live values, bitfield decode, enum names). Each pipeline row belongs to the core of the same index in the selected scenario. Hover a block for its relevant live settings.
    
+  
    
+
    
+
    
+
    
+
+
+
+
diff --git a/examples/dashboard/insight.py b/examples/dashboard/insight.py
new file mode 100644
index 0000000..64afcf1
--- /dev/null
+++ b/examples/dashboard/insight.py
@@ -0,0 +1,520 @@
+#!/usr/bin/env python3
+# SPDX-FileCopyrightText: 2026 Accemic Technologies GmbH
+# SPDX-License-Identifier: ISC
+"""Analysis of the decoded PC stream: symbols, live window, hot list.
+
+What happens here, and what does NOT:
+
+* **Symbolisation** from a `System.map`/`nm` file (`addr type name`). Pure
+  lookup work, no estimation.
+* **Window alignment** to Nexus message boundaries. The reference decoder
+  aborts when a byte stream does not start with MSEO='00' (`NexRvDeco.c`:
+  "Message must start from MSEO='00'", return -2). A slice out of a ring
+  buffer practically always starts in the middle of a message -- so before
+  decoding, the stream is advanced to the first byte AFTER an MSEO='11' (end
+  of message) and cut behind the last such byte. The decoder itself
+  deliberately emits no PCs before the first sync message ("Do not emit
+  speculative PCs before the first synchronization message"), so the start of
+  a window yields no wrong addresses.
+* **Call analysis** only where it is exact: with the C extension disabled
+  every instruction is 4 bytes long, so `pc_next != pc + 4` is precisely a
+  control transfer. If the transfer hits the start of a symbol it is a call;
+  if it hits the remembered return address it is a return. On cores WITH the
+  C extension that stride does not hold -- then the depth is NOT computed
+  (`depth = None`) instead of inventing a number.
+* **Coverage** here is function coverage, not instruction coverage, and it
+  refers exclusively to the windows that were actually decoded. That is why
+  the field is called `functions_seen` and carries its frame of reference in
+  its name.
+"""
+import bisect
+import re
+import time
+from pathlib import Path
+
+# Nexus MSEO encoding (the low two bits of every byte):
+#   00 = byte inside a message     01 = end of field
+#   11 = end of message            10 = not allowed
+MSEO_END = 0x3
+
+
+def align_to_messages(raw: bytes):
+    """Trim to whole Nexus messages.
+
+    Returns (payload, dropped_head, dropped_tail). Empty result if the
+    window does not contain two message boundaries.
+    """
+    if not raw:
+        return b"", 0, 0
+    start = -1
+    for i, b in enumerate(raw):
+        if (b & 0x3) == MSEO_END:
+            start = i + 1
+            break
+    if start < 0 or start >= len(raw):
+        return b"", len(raw), 0
+    end = -1
+    for i in range(len(raw) - 1, start - 1, -1):
+        if (raw[i] & 0x3) == MSEO_END:
+            end = i + 1
+            break
+    if end <= start:
+        return b"", start, len(raw) - start
+    return raw[start:end], start, len(raw) - end
+
+
+class SymbolTable:
+    """`System.map`/`nm` symbols, address-ordered, with bisect lookup."""
+
+    LINE = re.compile(r"^\s*([0-9a-fA-F]{4,16})\s+([a-zA-Z])\s+(\S+)")
+    # executable symbols only -- data objects would dilute the coverage
+    TEXT_TYPES = set("tTwW")
+
+    def __init__(self):
+        self.addrs = []          # sorted start addresses
+        self.names = []          # same index
+        self.ends = []           # start address of the following symbol (upper bound)
+        self.source = None
+        self.count = 0
+
+    @classmethod
+    def from_text(cls, text, source=None):
+        st = cls()
+        rows = []
+        for line in text.splitlines():
+            m = cls.LINE.match(line)
+            if not m:
+                continue
+            if m.group(2) not in cls.TEXT_TYPES:
+                continue
+            rows.append((int(m.group(1), 16), m.group(3)))
+        rows.sort()
+        # Duplicate addresses: keep the first name (aliases like _text/_start)
+        for a, n in rows:
+            if st.addrs and st.addrs[-1] == a:
+                continue
+            st.addrs.append(a)
+            st.names.append(n)
+        st.ends = st.addrs[1:] + [st.addrs[-1] + 0x1000 if st.addrs else 0]
+        st.source = source
+        st.count = len(st.addrs)
+        return st
+
+    @classmethod
+    def from_file(cls, path):
+        p = Path(path)
+        return cls.from_text(p.read_text(encoding="utf-8", errors="replace"), str(p))
+
+    def lookup(self, pc):
+        """(name, start, offset) or (None, None, None)."""
+        if not self.addrs:
+            return None, None, None
+        i = bisect.bisect_right(self.addrs, pc) - 1
+        if i < 0 or pc >= self.ends[i]:
+            return None, None, None
+        return self.names[i], self.addrs[i], pc - self.addrs[i]
+
+    def is_entry(self, pc):
+        if not self.addrs:
+            return False
+        i = bisect.bisect_left(self.addrs, pc)
+        return i < len(self.addrs) and self.addrs[i] == pc
+
+    # The distance to the next symbol is the function size ONLY inside one
+    # contiguous text region. At the edge of a region the next symbol points
+    # into a different address space, and the "size" becomes the gap: measured
+    # 1,522,223,620 B for `handshake` (the last symbol before the jump from
+    # the physical to the virtual kernel copy). A treemap with a rectangle
+    # like that is not merely ugly, it is wrong.
+    MAX_FUNC_BYTES = 8192
+
+    def sizes(self):
+        """(name, addr, size, clamped) per symbol.
+
+        `size` is the distance to the next symbol, capped at MAX_FUNC_BYTES;
+        `clamped` says whether it was capped -- that lets the caller show how
+        much of the area is an estimate rather than a measurement.
+        """
+        for i, a in enumerate(self.addrs):
+            raw = max(0, self.ends[i] - a)
+            yield self.names[i], a, min(raw, self.MAX_FUNC_BYTES), raw > self.MAX_FUNC_BYTES
+
+
+class CallSites:
+    """Call and return sites from `dis_to_symbols.py --sites`.
+
+    The point is exactness instead of heuristics: whether a control transfer
+    is a call is decided by the INSTRUCTION at the departure address (`jal`/
+    `jalr` with rd=ra), not by whether the target happens to be the start of a
+    symbol. The latter was measurably wrong -- assembler labels such as
+    `_try_lottery` in OpenSBI are jump targets, not functions.
+    """
+
+    LINE = re.compile(r"^([CR])\s+([0-9a-fA-F]+)\s*$")
+
+    def __init__(self):
+        self.calls = set()
+        self.rets = set()
+        self.source = None
+
+    @property
+    def count(self):
+        return len(self.calls) + len(self.rets)
+
+    @classmethod
+    def from_text(cls, text, source=None):
+        cs = cls()
+        for line in text.splitlines():
+            m = cls.LINE.match(line)
+            if not m:
+                continue
+            (cs.calls if m.group(1) == "C" else cs.rets).add(int(m.group(2), 16))
+        cs.source = source
+        return cs
+
+    @classmethod
+    def from_file(cls, path):
+        p = Path(path)
+        return cls.from_text(p.read_text(encoding="utf-8", errors="replace"), str(p))
+
+
+class PcStreamAnalysis:
+    """One decoded PC window, analysed.
+
+    On call depth: a return target is checked not only against the topmost
+    frame but against the topmost `UNWIND_SEARCH` frames. That is not a
+    softening but the correction of a real defect: trap entries and
+    `mret`/`sret` leave several frames at once, and when switching from the
+    physical into the virtual address space (Linux sets `satp`) the stack
+    carries addresses from the OLD space. Without that search the depth runs
+    away monotonically -- measured 2972 frames over one boot, which is
+    obviously not a stack depth.
+
+    If the stack still stays above `STACK_LIMIT`, the pairing is lost. Then
+    `depth` returns **None** plus a `depth_note` -- an unusable number is not
+    displayed.
+    """
+
+    UNWIND_SEARCH = 64          # search this many frames deep for the return target
+    STACK_LIMIT = 512           # above this the pairing counts as lost
+
+    def __init__(self, pcs, symbols, fixed_width=True, sites=None):
+        self.n = len(pcs)
+        self.first = pcs[0] if pcs else None
+        self.last = pcs[-1] if pcs else None
+        self.per_func = {}          # name -> instructions
+        self.transfers = 0
+        self.calls = 0
+        self.returns = 0
+        self.unwinds = 0            # returns across multiple frames (trap/mret)
+        self.depth = None
+        self.depth_note = None
+        self.trail = []             # function sequence (debounced)
+        self.current = None
+        if not pcs:
+            return
+
+        stack = []
+        # Depth only with EXACT call detection: a fixed instruction width (no
+        # C extension) and the call/return sites from the listing. Without the
+        # sites file it is NOT computed -- the "target is a symbol start"
+        # heuristic used earlier was demonstrably wrong.
+        depth_ok = bool(fixed_width and sites and sites.count)
+        lost = False
+        prev = None
+        cur_name = None
+        for pc in pcs:
+            name, start, _off = symbols.lookup(pc) if symbols else (None, None, None)
+            # Keyed by START ADDRESS, not by name. Reason: the same kernel
+            # symbol exists twice in the listing -- once physical
+            # (0x6440_0000) and once virtual (0xC000_0000). A name as the key
+            # counts the instructions in BOTH regions and therefore claims
+            # twice as much execution as took place (measured: an identical
+            # 17,572 instructions in both regions).
+            key = start if start is not None else (pc & ~0xFFF)
+            self.per_func[key] = self.per_func.get(key, 0) + 1
+            label = name or "0x%08x" % (pc & ~0xFFF)
+            if label != cur_name:
+                cur_name = label
+                if not self.trail or self.trail[-1] != label:
+                    self.trail.append(label)
+            if prev is not None and pc != prev + 4:
+                self.transfers += 1
+                if depth_ok and not lost:
+                    if prev in sites.calls:
+                        stack.append(prev + 4)
+                        self.calls += 1
+                        if len(stack) > self.STACK_LIMIT:
+                            lost = True
+                    elif prev in sites.rets:
+                        # Return: normally the topmost frame. But traps,
+                        # mret/sret and the phys->virt switch leave several
+                        # frames at once -- hence a bounded search downwards
+                        # instead of a check against the top only.
+                        hit = 0
+                        for d in range(1, min(len(stack), self.UNWIND_SEARCH) + 1):
+                            if stack[-d] == pc:
+                                hit = d
+                                break
+                        if hit:
+                            del stack[len(stack) - hit:]
+                            if hit > 1:
+                                self.unwinds += 1
+                        elif stack:
+                            stack.pop()          # target unknown (address space switch)
+                            self.unwinds += 1
+                        self.returns += 1
+            prev = pc
+        self.current = cur_name
+        if not fixed_width:
+            self.depth_note = ("call depth computable only without the C extension "
+                               "(otherwise pc+4 is not a valid stride)")
+        elif not (sites and sites.count):
+            self.depth_note = ("no call/return sites loaded -- "
+                               "dis_to_symbols.py --sites produces them")
+        elif lost:
+            self.depth_note = ("call/return pairing lost (>%d open frames) -- "
+                               "no reliable depth" % self.STACK_LIMIT)
+        else:
+            self.depth = len(stack)
+        self.trail = self.trail[-24:]
+
+    def top(self, k=8):
+        return sorted(self.per_func.items(), key=lambda kv: -kv[1])[:k]
+
+
+class InsightState:
+    """Accumulator over many live windows (hot list, coverage, rate)."""
+
+    MAX_HIST = 120                  # Sparkline-Punkte (~2 min bei 1 s)
+    # Below this instruction count, bits per instruction from a single window
+    # is NOT meaningful and is therefore not reported as a measurement.
+    # Reason: the decoder deliberately emits no PCs before the first sync
+    # message ("Do not emit speculative PCs before the first synchronization
+    # message"). The bytes up to that point still count in the denominator --
+    # so a window that ends shortly before a sync, or breaks off at a stream
+    # boundary, otherwise yields values like 14,560 bit/instr out of 16,380 B
+    # over 9 instructions (really observed on 2026-07-28 in the browser test).
+    # The distortion vanishes as the window grows; below the threshold the
+    # number is omitted rather than dressed up.
+    MIN_INSTR_FOR_RATIO = 1000
+
+    def __init__(self):
+        self.symbols = SymbolTable()
+        self.sites = CallSites()
+        self.func_counts = {}       # name -> instructions (accumulated)
+        self.windows = 0
+        self.total_instr = 0
+        self.total_bytes = 0
+        self.hist = []              # [{t, bytes_per_s, instr_per_s, bits_per_instr}]
+        self.decode_seconds = 0.0
+        self.decode_bytes = 0
+        self.decode_instr = 0
+        self.last = None            # last window evaluation (dict)
+        self._last_beat = None      # (t, trace_bytes) for computing the rate
+
+    # --- Symbols -----------------------------------------------------------
+    def load_symbols(self, path):
+        self.symbols = SymbolTable.from_file(path)
+        return self.symbols
+
+    def set_symbols_text(self, text, source):
+        self.symbols = SymbolTable.from_text(text, source)
+        return self.symbols
+
+    def load_sites(self, path):
+        self.sites = CallSites.from_file(path)
+        return self.sites
+
+    # --- Rate from the monotonic hardware counters ------------------------
+    def note_counters(self, t, trace_bytes, instr_per_s=None):
+        """Byte rate from two samples of the monotonic TRACE_BYTES counter.
+
+        Returns the measured byte rate, or None on the first call and after a
+        counter reset (trace_clear).
+        """
+        prev = self._last_beat
+        self._last_beat = (t, trace_bytes)
+        if prev is None or t <= prev[0] or trace_bytes < prev[1]:
+            return None
+        return (trace_bytes - prev[1]) / (t - prev[0])
+
+    def push_rate(self, t, bytes_per_s, instr_per_s, bits_per_instr):
+        self.hist.append({"t": t, "bps": bytes_per_s, "ips": instr_per_s,
+                          "bpi": bits_per_instr})
+        del self.hist[:-self.MAX_HIST]
+
+    # --- Windows -----------------------------------------------------------
+    def add_window(self, pcs, raw_bytes, decode_seconds, fixed_width=True):
+        a = PcStreamAnalysis(pcs, self.symbols, fixed_width, self.sites)
+        for k, v in a.per_func.items():
+            self.func_counts[k] = self.func_counts.get(k, 0) + v
+        self.windows += 1
+        self.total_instr += a.n
+        self.total_bytes += raw_bytes
+        self.decode_seconds += decode_seconds
+        self.decode_bytes += raw_bytes
+        self.decode_instr += a.n
+        valid = a.n >= self.MIN_INSTR_FOR_RATIO
+        self.last = {
+            "instr": a.n,
+            "bytes": raw_bytes,
+            "bits_per_instr": (raw_bytes * 8.0 / a.n) if (a.n and valid) else None,
+            "bits_per_instr_note": None if valid else (
+                "window yielded only %d instructions (<%d): the bytes before the "
+                "first sync message count in the denominator, so the ratio "
+                "would be skewed" % (a.n, self.MIN_INSTR_FOR_RATIO)),
+            "current": a.current,
+            "trail": a.trail,
+            "depth": a.depth,
+            "depth_note": a.depth_note,
+            "calls": a.calls,
+            "returns": a.returns,
+            "unwinds": a.unwinds,
+            "transfers": a.transfers,
+            "first_pc": a.first,
+            "last_pc": a.last,
+            "top": [{"name": n, "instr": c} for n, c in a.top(10)],
+            "decode_seconds": decode_seconds,
+        }
+        return self.last
+
+    # --- Aggregate -------------------------------------------------------
+    def name_of(self, key):
+        """Display name for a func_counts key (start address)."""
+        if isinstance(key, int):
+            n, s, _ = self.symbols.lookup(key)
+            if n and s == key:
+                return n
+            return "0x%08x" % key
+        return str(key)
+
+    def hot(self, k=15):
+        # `addr` as a HEX STRING: an RV64 kernel address exceeds 2**53 and as
+        # a JSON number would be rounded in the browser before it is displayed
+        # (0xFFFFFFC0_00xxxxxx -> ...00000000). See test_addr64.mjs.
+        tot = sum(self.func_counts.values()) or 1
+        rows = sorted(self.func_counts.items(), key=lambda kv: -kv[1])[:k]
+        return [{"name": self.name_of(a),
+                 "addr": ("0x%x" % a) if isinstance(a, int) else None,
+                 "instr": c, "share": c / tot} for a, c in rows]
+
+    def coverage(self):
+        """Function coverage over ALL windows decoded so far.
+
+        Explicitly: function coverage, not instruction coverage, and only over
+        the windows that were actually decoded -- no claim about a complete
+        run. Without a symbol table there is no reference size and therefore
+        no ratio either.
+        """
+        total = self.symbols.count
+        if not total:
+            return {"total": 0, "seen": 0, "share": None,
+                    "note": "no symbol table loaded -- no reference, so no ratio"}
+        known = set(self.symbols.addrs)
+        seen = len([a for a in self.func_counts if a in known])
+        return {"total": total, "seen": seen, "share": seen / total,
+                "scope": "function-level coverage over %d decoded windows "
+                         "(%d instructions), not over the whole run"
+                         % (self.windows, self.total_instr)}
+
+    def decoder_throughput(self):
+        """The measured decoder throughput of THIS host (MB/s and Minstr/s)."""
+        if self.decode_seconds <= 0 or not self.decode_bytes:
+            return None
+        return {
+            "mb_per_s": self.decode_bytes / self.decode_seconds / 1e6,
+            "minstr_per_s": self.decode_instr / self.decode_seconds / 1e6,
+            "samples": self.windows,
+            "seconds": self.decode_seconds,
+            "bytes": self.decode_bytes,
+            "instr": self.decode_instr,
+        }
+
+    def reset(self):
+        self.func_counts.clear()
+        self.windows = self.total_instr = self.total_bytes = 0
+        self.decode_seconds = 0.0
+        self.decode_bytes = self.decode_instr = 0
+        self.hist.clear()
+        self.last = None
+        self._last_beat = None
+
+    def to_json(self):
+        return {
+            "windows": self.windows,
+            "total_instr": self.total_instr,
+            "total_bytes": self.total_bytes,
+            "symbols": {"count": self.symbols.count, "source": self.symbols.source,
+                        "call_sites": len(self.sites.calls),
+                        "ret_sites": len(self.sites.rets),
+                        "sites_source": self.sites.source},
+            "last": self.last,
+            "hot": self.hot(),
+            "coverage": self.coverage(),
+            "decoder": self.decoder_throughput(),
+            "hist": self.hist[-self.MAX_HIST:],
+            "t": time.time(),
+        }
+
+
+# ---------------------------------------------------------------------------
+# Nexus message statistics straight off the wire bytes
+# ---------------------------------------------------------------------------
+# Deliberately WITHOUT the decoder: the MSEO framing is enough for the
+# distribution of message types. A byte with MSEO='11' ends a message, the
+# next byte with MSEO='00' starts the next one, and its top six bits are the
+# TCODE. That is one pass over the window and costs nothing -- a full decode
+# once per second would be unaffordable on the board (measured: reading the
+# 114 MiB pcinfo alone costs 18 s).
+TCODE_NAMES = {
+    3: "DirectBranch", 4: "IndirectBranch", 8: "Error", 9: "ProgTraceSync",
+    11: "DirectBranchSync", 12: "IndirectBranchSync", 27: "ResourceFull",
+    28: "IndirectBranchHist", 29: "IndirectBranchHistSync",
+    31: "RepeatBranch", 32: "RepeatInstruction", 33: "ProgTraceCorrelation",
+    56: "Vendor-BranchPredict", 57: "Vendor-JumpTargetCache",
+    58: "Vendor-Config",
+}
+
+
+def scan_messages(raw: bytes):
+    """(counts per TCODE, message count, idle bytes) of a wire window.
+
+    The first, partially cut fragment is skipped -- counting starts at the
+    first complete message boundary, otherwise a randomly cut byte would count
+    as a message type.
+    """
+    counts = {}
+    msgs = 0
+    idle = 0
+    started = False
+    prev_end = False
+    for b in raw:
+        mseo = b & 0x3
+        if mseo == 0x3 and (b >> 2) == 0x3F:
+            idle += 1
+            prev_end = True
+            continue
+        if prev_end and mseo == 0x0:
+            started = True
+            t = (b >> 2) & 0x3F
+            counts[t] = counts.get(t, 0) + 1
+            msgs += 1
+        prev_end = (mseo == 0x3)
+    return counts, msgs, idle, started
+
+
+def parse_pcout(data: bytes, limit=None):
+    """`.pcout` (one `0x%08x` line per instruction) -> list of ints."""
+    out = []
+    for line in data.split(b"\n"):
+        line = line.strip()
+        if not line:
+            continue
+        try:
+            out.append(int(line, 16))
+        except ValueError:
+            continue
+        if limit and len(out) >= limit:
+            break
+    return out
diff --git a/examples/dashboard/logo_acctech.svg b/examples/dashboard/logo_acctech.svg
new file mode 100644
index 0000000..2252243
--- /dev/null
+++ b/examples/dashboard/logo_acctech.svg
@@ -0,0 +1,55 @@
+
+
+
+
+
+	
+		
+		
+		
+		
+		
+		
+		
+	
+	
+		
+		
+		
+		
+		
+		
+		
+		
+		
+		
+		
+		
+	
+	
+		
+		
+		
+	
+
+
diff --git a/examples/dashboard/make_demo_console.py b/examples/dashboard/make_demo_console.py
new file mode 100644
index 0000000..3c37a87
--- /dev/null
+++ b/examples/dashboard/make_demo_console.py
@@ -0,0 +1,102 @@
+#!/usr/bin/env python3
+# SPDX-FileCopyrightText: 2026 Accemic Technologies GmbH
+# SPDX-License-Identifier: ISC
+"""Prepare the demo consoles from the board recordings (reproducibly).
+
+    py make_demo_console.py            # writes demo/console_.txt
+
+Sources (real board captures, nothing is invented):
+
+| Target                       | Source                                                      |
+|------------------------------|-------------------------------------------------------------|
+| demo/console_cva6_linux.txt  | demo/raw/con_cva6_linux.bin (RV32 boot, re-recorded 2026-08-19) |
+| demo/console_rocket2.txt     | demo/raw/con_rocket2.bin (RV64 SMP boot, re-recorded 2026-08-19) |
+| demo/console_rocket64.txt    | demo/raw/con_rocket64.bin (RV64 boot, a single hart) |
+| demo/console_cva6_linux64.txt| demo/raw/con_cva6_linux64.bin (cv64a6, Sv39) |
+
+The three raw files are uncut ring contents from the board; they live in
+the repository, so that this script stays reproducible (the earlier sources
+pointed into build directories that do not exist here).
+
+Only CAPTURE artefacts are cleaned up, never content:
+
+1. **Pairwise dedup:** earlycon and console write to the SAME UART, so every
+   kernel line appears twice in the recording. Only IMMEDIATELY consecutive
+   identical lines are collapsed, pairwise -- 2 becomes 1, 4 becomes 2 (the
+   fourfold "can't open /dev/null" message really is
+   four genuine messages from two consoles: two remain).
+2. **Dot artefact (rocket2 only):** the capture path of that run appends a
+   '.' to every line and prefixes some with one (a ring-chunk join).
+   A single trailing dot is removed; '...' and the like remain.
+3. **NUL bytes** at the end (unused ring space) are stripped.
+
+The head of each target file does NOT name source and rules (the file is
+reproduced 1:1) -- this script is the documented provenance.
+"""
+from __future__ import annotations
+
+from pathlib import Path
+
+HERE = Path(__file__).resolve().parent
+ROOT = HERE.parents[1]
+
+JOBS = [
+    (HERE / "demo/raw/con_cva6_linux.bin",
+     HERE / "demo/console_cva6_linux.txt", False),
+    # Recorded 2026-08-19 on kria-kv260 at pl_clk0 = 68.181818 MHz, straight
+    # from the console ring (CON_BYTES words at 0xA030_0000) via the board
+    # runners' `PHASE=con`. The raw ring dumps travel WITH the repository so
+    # this script stays reproducible instead of pointing at a build tree that
+    # no longer exists.
+    (HERE / "demo/raw/con_rocket2.bin",
+     HERE / "demo/console_rocket2.txt", False),
+    (HERE / "demo/raw/con_rocket64.bin",
+     HERE / "demo/console_rocket64.txt", False),
+    (HERE / "demo/raw/con_cva6_linux64.bin",
+     HERE / "demo/console_cva6_linux64.txt", False),
+]
+
+
+def pair_dedup(lines: list[str]) -> list[str]:
+    out: list[str] = []
+    i = 0
+    while i < len(lines):
+        if i + 1 < len(lines) and lines[i] == lines[i + 1] and lines[i].strip():
+            out.append(lines[i])
+            i += 2
+        else:
+            out.append(lines[i])
+            i += 1
+    return out
+
+
+def strip_dot_artifact(line: str) -> str:
+    if line.startswith(".") and not line.startswith(".."):
+        line = line[1:]
+    if line.endswith(".") and not line.endswith(".."):
+        # Kernel lines practically never end on '.' in the original; the
+        # rocket2 capture appends exactly ONE. Doubles stay in place.
+        line = line[:-1]
+    return line
+
+
+def main() -> int:
+    for src, dst, dots in JOBS:
+        if not src.is_file():
+            print("SKIP %s (source missing)" % src.name)
+            continue
+        raw = src.read_bytes().rstrip(bytes(1)).decode("utf-8", errors="replace")
+        raw = raw.replace("\x00", "")
+        lines = raw.replace("\r\n", "\n").replace("\r", "\n").split("\n")
+        if dots:
+            lines = [strip_dot_artifact(l) for l in lines]
+        before = len(lines)
+        lines = pair_dedup(lines)
+        dst.write_text("\n".join(lines).rstrip("\n") + "\n", encoding="utf-8")
+        print("%s -> %s  (%d -> %d lines, source %d B)"
+              % (src.name, dst.name, before, len(lines), src.stat().st_size))
+    return 0
+
+
+if __name__ == "__main__":
+    raise SystemExit(main())
diff --git a/examples/dashboard/plclk.json b/examples/dashboard/plclk.json
new file mode 100644
index 0000000..bf946da
--- /dev/null
+++ b/examples/dashboard/plclk.json
@@ -0,0 +1,72 @@
+{
+  "_comment": [
+    "pl_clk0 label per scenario. The dashboard server reads this in load_app()",
+    "and programs the clock BETWEEN `xmutil unloadapp` and `xmutil loadapp` --",
+    "the only point at which it may be changed: a frequency step underneath a",
+    "loaded design is a clock glitch in the middle of the logic, and",
+    "kv260_plclk.sh refuses the change while a slot is occupied for exactly",
+    "that reason.",
+    "",
+    "The label is NOT a frequency. pl_clk0 = 1500 MHz / DIVISOR0 with an",
+    "integer divider, so only a few values exist: 100 (15), 75 (20),",
+    "71.43 (21), 68.18 (22), 65.22 (23). kv260_plclk.sh accepts the three",
+    "labels 68, 75 and 100 and turns 68 into 1500000000/22 = 68181818 Hz --",
+    "not 68000000. A fourth value is an error, not a compromise, and",
+    "test_demo_assets.py fails on one.",
+    "",
+    "HOW THE VALUES ARE DERIVED. Every KV260 design in this repository is",
+    "constrained to clk_pl_0 = 71.114 MHz (period 14.062 ns) -- that is the",
+    "PS8 PL0 clock the block design asks for, and it is what the routed timing",
+    "report of each design signs off. 68 is the only label AT OR BELOW that",
+    "constraint, so it is the value that needs no further argument. 75 MHz",
+    "(13.333 ns) is 0.729 ns faster than the sign-off period, so a design only",
+    "survives it if its worst negative slack is at least 0.729 ns. Where a",
+    "board runner already programs 75 today, the entry says so and carries",
+    "that design's measured slack; where no runner exists, the entry stays at",
+    "68. A scenario without evidence gets no entry at all -- and then the",
+    "server leaves the clock alone and says so, instead of guessing.",
+    "",
+    "The `evidence` line of every entry names the file the number comes from.",
+    "The slack values below are the clk_pl_0 rows of those routed reports."
+  ],
+  "mbv": {
+    "mhz": 75,
+    "evidence": "examples/kv260/mbv/board/mbv_board_gate.sh:81 programs PL_MHZ=75, and the board gate passed at that clock (PREFIX_PASS 26772/26772). Constraint 71.114 MHz with WNS +2.331 ns (examples/kv260/mbv/fpga/proj_b/mbv_kv260.runs/impl_1/mbv_kv260_top_timing_summary_routed.rpt), i.e. 3.2x the 0.729 ns that 75 MHz costs."
+  },
+  "duo": {
+    "mhz": 75,
+    "evidence": "examples/kv260/duo/board/duo_board_gate.sh:74 programs PLMHZ=75. Constraint 71.114 MHz with WNS +2.188 ns (examples/kv260/duo/fpga/proj/duo_kv260.runs/impl_1/duo_kv260_top_timing_summary_routed.rpt), i.e. 3.0x the 0.729 ns that 75 MHz costs."
+  },
+  "tgc5b2_axis_wp": {
+    "mhz": 75,
+    "evidence": "examples/kv260/tgc5b2_axis_wp/board/wp_board_gate.sh:77 programs PLMHZ=75. Constraint 71.114 MHz with WNS +1.575 ns (examples/kv260/tgc5b2_axis_wp/fpga/reports/tgc5b2_axis_wp_timing_summary.rpt), i.e. 2.2x the 0.729 ns that 75 MHz costs."
+  },
+  "trio": {
+    "mhz": 68,
+    "evidence": "No board runner sets a clock for this design. Constraint 71.114 MHz with WNS +0.215 ns (examples/kv260/trio/fpga/trio_timing_summary.rpt) -- that is LESS than the 0.729 ns 75 MHz would cost, so 75 is not available here. 68 is the only label at or below the constraint."
+  },
+  "cva6_linux": {
+    "mhz": 68,
+    "evidence": "No board runner sets a clock for this design (examples/kv260/cva6_linux/board/cva6_linux_boot_trace.sh has no clock step). Constraint 71.114 MHz with WNS +2.265 ns (examples/kv260/cva6_linux/fpga/cva6_linux_timing_summary.rpt); 68 is the only label at or below the constraint."
+  },
+  "cva6_linux64": {
+    "mhz": 68,
+    "evidence": "Constraint 71.114 MHz with WNS +0.603 ns (examples/kv260/cva6_linux64/fpga/cva6_linux64_x64_timing_summary.rpt) -- LESS than the 0.729 ns 75 MHz would cost, so 75 is not available here. Matches PL_MHZ in this scenario's boot recipe (boot.json)."
+  },
+  "rocket64": {
+    "mhz": 75,
+    "evidence": "Constraint 71.114 MHz with WNS +2.114 ns (examples/kv260/rocket_linux/fpga/rocket_x64_timing_summary.rpt) -- 2.9x the 0.729 ns that 75 MHz costs, the same slack argument by which mbv, duo and tgc5b2_axis_wp already run at 75. Raised 68 -> 75 on 2026-08-21 so the clock matches the guest device tree, which declares clock-frequency = 75000000 (rocket_kv260_rv64.dts:104,118,187); at 68 the guest reckoned time 10 percent fast. Verified on the board that day: boots to buildroot login, WIN_ERR_CNT 0, and the capture decodes to 5,414,841 instructions against the PINNED demo/rocket64.pcinfo -- the same count as the 68 MHz run, i.e. the clock does not touch the decoded trace."
+  },
+  "rocket2": {
+    "mhz": 75,
+    "evidence": "Constraint 71.114 MHz with WNS +3.578 ns (examples/kv260/rocket2/fpga/rocket2_timing_summary.rpt) -- 4.9x the 0.729 ns that 75 MHz costs, the largest margin in the family. Carried PL_MHZ=68 from 2026-08-14 (package R2, finding P0-01) until 2026-08-21, when it was raised to 75 for the same reason as rocket64: the guest device tree declares 75 MHz and the guest reckoned time 10 percent fast. Verified on the board that day: M5_TWOHART_HW PASS with both harts retiring, 0 drops, WIN_ERR_CNT 0, boots to buildroot login, and the DDR sink decodes to 7,770,406 instructions against the PINNED demo/rocket2.pcinfo -- the same count as the 68 MHz run."
+  },
+  "cva6_2_rv32": {
+    "mhz": 68,
+    "evidence": "No board runner sets a clock for this design. Constraint 71.114 MHz with WNS +2.399 ns (examples/kv260/cva6_2/fpga/cva6_2_rv32_timing_summary.rpt); 68 is the only label at or below the constraint."
+  },
+  "cva6_2_rv64": {
+    "mhz": 68,
+    "evidence": "No board runner sets a clock for this design. Constraint 71.114 MHz with WNS +0.125 ns (examples/kv260/cva6_2/fpga/cva6_2_rv64_timing_summary.rpt) -- the smallest margin in the family and far LESS than the 0.729 ns 75 MHz would cost. 75 is not available here."
+  }
+}
diff --git a/examples/dashboard/record_web_demo.py b/examples/dashboard/record_web_demo.py
new file mode 100644
index 0000000..68901f3
--- /dev/null
+++ b/examples/dashboard/record_web_demo.py
@@ -0,0 +1,428 @@
+#!/usr/bin/env python3
+# SPDX-FileCopyrightText: 2026 Accemic Technologies GmbH
+# SPDX-License-Identifier: ISC
+"""Recording helper: a window data set from the demo capture (analysis).
+
+NOTE: the website no longer uses this data set -- it embeds the original
+dashboard as a replay, and `record_web_replay.py` produces that data set. This
+script stays as a measurement and analysis tool: it established the largest
+cleanly decoding prefix (13,436 of 262,144 B), the loop periodicity (53 %
+self-coverage at period 6048) and the prefix stability of the decoder.
+
+From the **recorded** demo artefacts of this directory it builds a
+record-and-replay data set that the website plays back without a board,
+without a server and without network access. The decoder runs here, not in the
+browser.
+
+    py record_web_demo.py -o /site/public/ctte-demo
+
+Method (the reason the numbers hold up)
+---------------------------------------
+A window taken from the middle of the byte stream cannot be decoded on its
+own -- it starts inside a cut message and the decoder rejects it. So decoding
+happens not per window but **per prefix**: for ascending byte bounds
+L0 < L1 < ... < Ln the stream [0, Li) is decoded. Window i is then the
+difference of two real decode runs -- bytes [L(i-1), Li) and the instructions
+that appeared with them.
+
+That is only valid if the decoder is prefix-stable (a longer run yields the
+same first N PCs). The script **checks** that instead of assuming it, and
+aborts on any deviation.
+
+The upper bound is the **largest cleanly decoding prefix** of the capture,
+determined by bisection. Beyond it the decoder aborts (the capture is a slice,
+and `demo/cva6_linux.pcinfo` covers the OpenSBI phase, not the whole boot) --
+a window past that point would no longer be a measurement.
+
+What does NOT travel (on purpose, not forgotten)
+------------------------------------------------
+* **The register map** (`regmap.json`) and every register view -- a release
+  decision.
+* **Scenario internals** (`scenarios.json`) -- likewise.
+* **The FIFO fill histogram** -- in demo mode the server rolls dice for the
+  bins (`DemoBus._tick`). A diced histogram next to real decode numbers is a
+  prop, and synthetic data is not a hardware capture.
+* **Everything except CVA6** -- the MicroBlaze V capture would be a measured
+  number about third-party IP.
+* **Any density statement as a metric.** The slice is a repeating early boot
+  loop (measured: the PC sequence covers itself to 53 % at period 6048). Bits
+  per instruction over such a slice is a loop artefact, not a workload
+  measurement. The script computes the sizes so that they can be followed --
+  the website presents them as the size of THIS slice and not as a metric.
+
+The data set carries its provenance with it: every input file with size and
+SHA-256, the decoder invocation verbatim, and the version of the decoder.
+"""
+from __future__ import annotations
+
+import argparse
+import hashlib
+import json
+import os
+import re
+import shutil
+import subprocess
+import sys
+import tempfile
+import time
+from pathlib import Path
+
+HERE = Path(__file__).resolve().parent
+sys.path.insert(0, str(HERE))
+import insight  # noqa: E402  (lives next to this script)
+
+# ---------------------------------------------------------------------------
+# Inputs -- exclusively the checked-in demo artefacts
+# ---------------------------------------------------------------------------
+TRACE = HERE / "demo" / "demo_trace_cva6_linux.bin"
+PCINFO = HERE / "demo" / "cva6_linux.pcinfo"
+SYMBOLS = HERE / "demo" / "symbols_sbi.map"
+CONSOLE = HERE / "demo" / "console_linux.txt"
+
+# Where the pinned reference decoder lands: bin/, filled by
+# `py scripts/fetch_cttd.py` (scripts/cttd.pin). The two entries that used to
+# stand here pointed into a third_party/ layout of the PREDECESSOR repository,
+# which this tree does not have -- so neither candidate could ever resolve.
+NEXRV_CANDIDATES = [
+    HERE.parents[1] / "bin" / ("cttd-windows-x64.exe" if os.name == "nt"
+                               else "cttd-linux-x86_64"),
+    HERE.parents[1] / "bin" / ("NexRv.exe" if os.name == "nt" else "NexRv"),
+]
+
+WINDOWS = 6          # number of windows; they tile the clean prefix
+CONSOLE_LINES = 220  # excerpt of the boot capture (data budget)
+
+
+def sha256(p: Path) -> str:
+    h = hashlib.sha256()
+    with p.open("rb") as f:
+        for blk in iter(lambda: f.read(1 << 20), b""):
+            h.update(blk)
+    return h.hexdigest()
+
+
+def find_nexrv() -> Path:
+    for c in NEXRV_CANDIDATES:
+        if c.is_file():
+            return c
+    raise SystemExit("NexRv not found: " +
+                     ", ".join(str(c) for c in NEXRV_CANDIDATES))
+
+
+VERSION_LINE = re.compile(r"^NexRv\b.*\bv\d+\.\d+")
+
+
+def nexrv_version(nexrv: Path) -> str:
+    """The version line sits in the usage help.
+
+    The first block of output is an error line ("Unkown option") -- a naive
+    "first line that starts with the tool name" fishes out exactly that one
+    and writes it into the provenance as the decoder version (measured
+    2026-08-11). Hence the match is on the version number.
+    """
+    r = subprocess.run([str(nexrv), "-help"], capture_output=True, text=True)
+    for line in ((r.stdout or "") + (r.stderr or "")).splitlines():
+        if VERSION_LINE.match(line.strip()):
+            return line.strip()
+    return "unknown"
+
+
+class Decoder:
+    """One decoder run over a prefix of the capture."""
+
+    def __init__(self, nexrv: Path, raw: bytes, pcinfo: Path, workdir: Path):
+        self.nexrv, self.raw, self.pcinfo, self.wd = nexrv, raw, pcinfo, workdir
+        self.calls = 0
+
+    def cmdline(self, n: int) -> list[str]:
+        return [str(self.nexrv), "-deco", str(self.wd / "trace.bin"),
+                "-pcinfo", str(self.pcinfo),
+                "-pcout", str(self.wd / "out.pcout"), "-stat"]
+
+    def run(self, n: int):
+        """(ok, pcs) for the prefix [0, n)."""
+        (self.wd / "trace.bin").write_bytes(self.raw[:n])
+        cmd = self.cmdline(n)
+        r = subprocess.run(cmd, capture_output=True, text=True, timeout=600)
+        self.calls += 1
+        out = (r.stdout or "") + (r.stderr or "")
+        ok = r.returncode == 0 and "Decoded OK" in out
+        pcs = insight.parse_pcout((self.wd / "out.pcout").read_bytes())
+        return ok, pcs
+
+
+def message_boundaries(raw: bytes) -> list[int]:
+    """Byte offsets where a new message starts.
+
+    Nexus MSEO: `0b11` ends a message, `0b00` begins the next one. A cut at
+    such a boundary lets the prefix end on whole messages -- exactly what the
+    decoder requires.
+    """
+    out = []
+    prev_end = False
+    for i, b in enumerate(raw):
+        if prev_end and (b & 0x3) == 0x0:
+            out.append(i)
+        prev_end = (b & 0x3) == 0x3
+    return out
+
+
+def largest_clean_prefix(dec: Decoder, hi: int) -> tuple[int, list[int]]:
+    """Largest prefix that NexRv decodes to the end without error (bisection)."""
+    lo = 0
+    ok, pcs = dec.run(hi)
+    if ok:
+        return hi, pcs
+    while hi - lo > 1:
+        mid = (lo + hi) // 2
+        ok, _ = dec.run(mid)
+        if ok:
+            lo = mid
+        else:
+            hi = mid
+    ok, pcs = dec.run(lo)
+    if not ok:
+        raise SystemExit("no cleanly decoding prefix found")
+    return lo, pcs
+
+
+def touched_symbols(pcs, symbols):
+    """[[start, end, name], ...] -- only the symbols that actually occur.
+
+    The lookup happens in the browser by bisection. One symbol name per
+    instruction would be the same name ten thousand times over; the whole
+    OpenSBI table would be 748 entries for the three dozen the slice touches.
+    """
+    hit = {}
+    for pc in pcs:
+        name, start, _off = symbols.lookup(pc)
+        if name is None:
+            continue
+        i = symbols.addrs.index(start)
+        hit[start] = (start, symbols.ends[i], name)
+    return [list(v) for v in sorted(hit.values())]
+
+
+def rle_encode(pcs):
+    """[startPC, [d, n], [d, n], ...] -- a stride and how often it repeats.
+
+    Measured over the slice: 47,892 of 53,039 transitions are exactly +4
+    (RV64, uncompressed instruction). The run-length form therefore costs
+    80 KB instead of 127 KB flat.
+    """
+    if not pcs:
+        return []
+    runs = []
+    cur, n = None, 0
+    for a, b in zip(pcs, pcs[1:]):
+        d = b - a
+        if d == cur:
+            n += 1
+        else:
+            if cur is not None:
+                runs.append([cur, n])
+            cur, n = d, 1
+    if cur is not None:
+        runs.append([cur, n])
+    return [pcs[0]] + runs
+
+
+def console_excerpt(path: Path, lines: int) -> list[str]:
+    text = path.read_text(encoding="utf-8", errors="replace")
+    rows = [ln.rstrip("\r") for ln in text.splitlines()]
+    return rows[:lines]
+
+
+def main() -> int:
+    ap = argparse.ArgumentParser(description=__doc__,
+                                 formatter_class=argparse.RawDescriptionHelpFormatter)
+    ap.add_argument("-o", "--out", required=True,
+                    help="target directory (site/public/ctte-demo of the website)")
+    ap.add_argument("--windows", type=int, default=WINDOWS)
+    args = ap.parse_args()
+
+    for p in (TRACE, PCINFO, SYMBOLS, CONSOLE):
+        if not p.is_file():
+            raise SystemExit("missing: %s" % p)
+
+    nexrv = find_nexrv()
+    raw = TRACE.read_bytes()
+    symbols = insight.SymbolTable.from_file(SYMBOLS)
+    out = Path(args.out)
+    out.mkdir(parents=True, exist_ok=True)
+
+    wd = Path(tempfile.mkdtemp(prefix="ctte_web_"))
+    try:
+        dec = Decoder(nexrv, raw, PCINFO, wd)
+
+        t0 = time.time()
+        clean, full_pcs = largest_clean_prefix(dec, len(raw))
+        print("clean prefix: %d of %d bytes -> %d instructions"
+              % (clean, len(raw), len(full_pcs)))
+
+        bounds = [b for b in message_boundaries(raw[:clean]) if b > 0]
+        if len(bounds) < args.windows:
+            raise SystemExit("too few message boundaries (%d)" % len(bounds))
+
+        # Cuts spread evenly over the prefix, each on a message boundary. The
+        # last cut is the prefix itself.
+        cuts = []
+        for k in range(1, args.windows):
+            target = clean * k // args.windows
+            cuts.append(min(bounds, key=lambda b: abs(b - target)))
+        cuts = sorted(set(cuts)) + [clean]
+
+        # Prefix decodes. Every one of them is a real decoder run.
+        marks = [(0, [])]
+        for c in cuts:
+            ok, pcs = dec.run(c)
+            if not ok:
+                raise SystemExit("prefix %d does not decode cleanly" % c)
+            prev_n = len(marks[-1][1])
+            if pcs[:prev_n] != marks[-1][1]:
+                raise SystemExit(
+                    "prefix stability violated at %d bytes: the first %d "
+                    "PCs differ from the shorter run" % (c, prev_n))
+            marks.append((c, pcs))
+            print("  prefix %6d bytes -> %7d instructions" % (c, len(pcs)))
+
+        if marks[-1][1] != full_pcs:
+            raise SystemExit("final run deviates from the bisection run")
+
+        # Message mix per window as the DIFFERENCE of two prefix scans.
+        # Scanning the byte slice directly would miss its first message:
+        # `scan_messages` recognises a start only by the preceding end marker,
+        # which the slice does not contain. Taken as a difference, the windows
+        # sum exactly to the total.
+        def scan_prefix(n):
+            c, m, idl, _ = insight.scan_messages(raw[:n])
+            return c, m, idl
+
+        windows, total_bytes, total_instr, total_msgs = [], 0, 0, 0
+        for i in range(1, len(marks)):
+            b0, p0 = marks[i - 1]
+            b1, p1 = marks[i]
+            wraw = raw[b0:b1]
+            wpcs = p1[len(p0):]
+            c1, m1, i1 = scan_prefix(b1)
+            c0, m0, i0 = scan_prefix(b0)
+            counts = {t: c1.get(t, 0) - c0.get(t, 0) for t in c1}
+            counts = {t: c for t, c in counts.items() if c}
+            msgs, idle = m1 - m0, i1 - i0
+            # The leading function of the window -- the label in the picker.
+            span = {}
+            for pc in wpcs:
+                name, _s, _o = symbols.lookup(pc)
+                key = name or "\u2014"
+                span[key] = span.get(key, 0) + 1
+            lead = max(span.items(), key=lambda kv: kv[1])[0] if span else "\u2014"
+            windows.append({
+                "index": i - 1,
+                "byte_from": b0, "byte_to": b1, "bytes": len(wraw),
+                "instructions": len(wpcs),
+                "messages": msgs, "idle_bytes": idle,
+                "message_mix": sorted(
+                    ({"tcode": t,
+                      "name": insight.TCODE_NAMES.get(t, "TCODE %d" % t),
+                      "count": c} for t, c in counts.items()),
+                    key=lambda r: -r["count"]),
+                "lead_symbol": lead,
+                "functions": len(span),
+                "hex": wraw.hex(),
+                "pcs": rle_encode(wpcs),
+            })
+            total_bytes += len(wraw)
+            total_instr += len(wpcs)
+            total_msgs += msgs
+
+        # The windows have to tile the prefix without a remainder -- otherwise
+        # the head of the demo claims a total the windows do not add up to.
+        if total_bytes != clean or total_instr != len(full_pcs):
+            raise SystemExit("windows do not tile the prefix (%d/%d B, %d/%d I)"
+                             % (total_bytes, clean, total_instr, len(full_pcs)))
+
+        # Hot list over the whole clean prefix -- a real decode, a real symbol
+        # table, no extrapolation.
+        heat = {}
+        for pc in full_pcs:
+            name, _s, _o = symbols.lookup(pc)
+            heat[name or "\u2014"] = heat.get(name or "\u2014", 0) + 1
+        heat_rows = sorted(heat.items(), key=lambda kv: -kv[1])[:12]
+
+        counts, msgs, idle, _ = insight.scan_messages(raw[:clean])
+        manifest = {
+            "generated": time.strftime("%Y-%m-%d %H:%M %Z"),
+            "generator": "examples/dashboard/record_web_demo.py (CEDARtools.TraceEncoder)",
+            "scenario": {
+                "id": "cva6_linux",
+                "core": "CVA6",
+                "workload": "Linux 6.12 boot, OpenSBI phase",
+                "protocol": "N-Trace",
+            },
+            "capture": {
+                "file_bytes": len(raw),
+                "decoded_bytes": clean,
+                "instructions": len(full_pcs),
+                "messages": msgs,
+                "idle_bytes": idle,
+                "decode_seconds": round(time.time() - t0, 1),
+                "decoder_calls": dec.calls,
+                # Deliberately NO density metric -- see the module header.
+                "density_note": "loop-dominated excerpt; not a workload figure",
+            },
+            "message_mix": sorted(
+                ({"tcode": t, "name": insight.TCODE_NAMES.get(t, "TCODE %d" % t),
+                  "count": c, "share": round(c / msgs, 4) if msgs else 0}
+                 for t, c in counts.items()), key=lambda r: -r["count"]),
+            "heat": [{"symbol": n, "instructions": c,
+                      "share": round(c / len(full_pcs), 4)} for n, c in heat_rows],
+            "windows": [{k: w[k] for k in
+                         ("index", "byte_from", "byte_to", "bytes",
+                          "instructions", "messages", "idle_bytes",
+                          "lead_symbol", "functions")} for w in windows],
+            "console_lines": CONSOLE_LINES,
+            "symbols": {"count": symbols.count, "source": SYMBOLS.name,
+                        "touched": len(touched_symbols(full_pcs, symbols))},
+            "provenance": {
+                "decoder": nexrv_version(nexrv),
+                "decoder_command":
+                    "NexRv -deco .bin -pcinfo %s -pcout  -stat"
+                    % PCINFO.name,
+                "inputs": [
+                    {"file": p.name, "bytes": p.stat().st_size,
+                     "sha256": sha256(p)}
+                    for p in (TRACE, PCINFO, SYMBOLS, CONSOLE)
+                ],
+            },
+        }
+        console = {"lines": console_excerpt(CONSOLE, CONSOLE_LINES),
+                   "source": CONSOLE.name,
+                   "total_lines": len(console_excerpt(CONSOLE, 10 ** 9))}
+
+        # `manifest.json` is the readable summary for a review, `dataset.json`
+        # is what the site build embeds.
+        (out / "manifest.json").write_text(
+            json.dumps(manifest, indent=1, ensure_ascii=False), encoding="utf-8")
+        (out / "dataset.json").write_text(
+            json.dumps({"manifest": manifest, "windows": windows,
+                        "symbols": touched_symbols(full_pcs, symbols),
+                        "console": console},
+                       separators=(",", ":"), ensure_ascii=False),
+            encoding="utf-8")
+
+        sizes = sorted(((f.stat().st_size, f.name) for f in out.iterdir()
+                        if f.is_file()), reverse=True)
+        print("\nwritten to %s" % out)
+        for s, n in sizes:
+            print("  %8d B  %s" % (s, n))
+        ds = (out / "dataset.json").read_bytes()
+        import gzip
+        print("\nembedded payload: %d B (gzip %d B)"
+              % (len(ds), len(gzip.compress(ds, 9))))
+        return 0
+    finally:
+        shutil.rmtree(wd, ignore_errors=True)
+
+
+if __name__ == "__main__":
+    raise SystemExit(main())
diff --git a/examples/dashboard/record_web_replay.py b/examples/dashboard/record_web_replay.py
new file mode 100644
index 0000000..e078495
--- /dev/null
+++ b/examples/dashboard/record_web_replay.py
@@ -0,0 +1,1003 @@
+#!/usr/bin/env python3
+# SPDX-FileCopyrightText: 2026 Accemic Technologies GmbH
+# SPDX-License-Identifier: ISC
+"""Recording v2 for the website replay of the ORIGINAL dashboard.
+
+    py record_web_replay.py -o /assets/ctte-demo/dashboard
+
+v2: two scenarios -- **rocket2 (default)** and **cva6_linux** -- with a RESET
+state (before Run) and a RUN sequence as a time series per scenario, plus a
+**console schedule taken from the kernel timestamps** of the real recording
+(15 s are 15 s -- the flat 2000 characters/s of v1 was too fast) and a
+**livepc series** at the UI poll rate (2.5 s), so that the bpi chart moves
+instead of standing on a single value.
+
+The shim on the website plays that back: Run = series from the start, Stop =
+freeze the state, scenario change = reset. Controlling endpoints are still NOT
+recorded -- this is a read-only replay.
+
+Console schedule -- what is measured and what is presentation:
+
+* Kernel lines carry their timestamp `[ ss.uuuuuu ]` -- the schedule puts them
+  EXACTLY there (measured; the source is the recording itself).
+* Lines BEFORE the first timestamp (the OpenSBI banner) are rolled out from
+  t=0 at UART speed 115200 8N1 (~11,520 characters/s) -- an approximation,
+  and named as one.
+* Lines AFTER the last timestamp (init/services/login) advance by 0.4 s per
+  line; typed input (the login part) at 80 ms per character with a 1.5 s pause
+  for thought before the prompt. That is presentation timing, not a
+  measurement -- and the manifest says so.
+
+Sources per scenario (all real captures; their preparation is documented in
+make_demo_console.py):
+
+| Scenario   | Console                      | Demo stream                         |
+|------------|------------------------------|-------------------------------------|
+| rocket2    | demo/console_rocket2.txt     | demo/demo_trace_rocket2.bin (board capture)      |
+| cva6_linux | demo/console_cva6_linux.txt  | demo/demo_trace_cva6_linux.bin (boot recording)  |
+
+There is additionally a PUBLIC export. The default above stays unchanged --
+full provenance, all comments, a hash per file; that is what developers need.
+For the website there is, alongside it:
+
+    py record_web_replay.py --public --from-bundle  -o 
+    py record_web_replay.py --public -o         # record afresh
+
+The first way is preferred: it converts an EXISTING bundle, deterministically,
+without a board and without a decoder. What happens in the process is
+described further down under "PUBLIC EXPORT"; the interlock is
+check_replay_public.py, which the export applies to its own output.
+"""
+from __future__ import annotations
+
+import argparse
+import fnmatch
+import hashlib
+import json
+import re
+import shutil
+import subprocess
+import sys
+import time
+import urllib.request
+from pathlib import Path
+
+HERE = Path(__file__).resolve().parent
+PORT = 8123
+BASE = "http://127.0.0.1:%d" % PORT
+
+SCENARIOS = ["rocket2", "cva6_linux"]
+DEFAULT = "rocket2"
+SERIES_SECONDS = {"rocket2": 45, "cva6_linux": 75}
+LIVE_EVERY = 2.5            # UI poll rate of the bpi chart
+TRACE_EVERY = 5
+REGION_DUMP_BYTES = 0x1000
+
+UART_CPS = 11520            # 115200 Baud 8N1
+TAIL_LINE_S = 0.4           # lines after the last kernel timestamp
+TYPE_CPS = 12               # typed characters (login part)
+PROMPT_PAUSE_S = 1.5
+
+STAMP = re.compile(r"^\[\s*(\d+)\.(\d{6})\]")
+
+
+def get(path: str, timeout=300):
+    with urllib.request.urlopen(BASE + path, timeout=timeout) as r:
+        return r.read()
+
+
+def get_json(path: str, timeout=300):
+    return json.loads(get(path, timeout))
+
+
+def post_json(path: str, body: dict, timeout=60):
+    req = urllib.request.Request(
+        BASE + path, data=json.dumps(body).encode(),
+        headers={"Content-Type": "application/json"}, method="POST")
+    with urllib.request.urlopen(req, timeout=timeout) as r:
+        return json.loads(r.read())
+
+
+def sha256(p: Path) -> str:
+    h = hashlib.sha256()
+    h.update(p.read_bytes())
+    return h.hexdigest()
+
+
+def console_schedule(text: str):
+    """[[ms, charOffset], ...] - when how much of the console is visible.
+
+    Offsets are CHARACTERS into the text (line breaks included); the shim
+    shows text[:offset]. Monotonically increasing, one mark per line (several
+    per line where input is typed, for the typing effect).
+    """
+    sched: list[list[int]] = [[0, 0]]
+    t = 0.0
+    off = 0
+    last_stamp = None
+    interactive = False
+    for line in text.split("\n"):
+        n = len(line) + 1
+        m = STAMP.match(line)
+        if m:
+            t = max(t, int(m.group(1)) + int(m.group(2)) / 1e6)
+            last_stamp = t
+        elif "login:" in line and last_stamp is not None:
+            interactive = True
+            t += PROMPT_PAUSE_S
+        elif interactive and line.startswith(("#", "$")) is False and line.strip() \
+                and last_stamp is not None and "login:" not in line:
+            t += TAIL_LINE_S
+        elif last_stamp is None:
+            t += n / UART_CPS
+        else:
+            t += TAIL_LINE_S
+        if interactive and ("login: " in line or line.startswith("# ")):
+            # The typed part of the line appears character by character.
+            typed_at = line.find(": ") + 2 if "login: " in line else 2
+            base = off + typed_at
+            for k in range(max(0, len(line) - typed_at)):
+                t += 1.0 / TYPE_CPS
+                sched.append([int(t * 1000), base + k + 1])
+        off += n
+        sched.append([int(t * 1000), min(off, len(text))])
+    return sched
+
+
+class Recorder:
+    def __init__(self, out: Path):
+        self.out = out
+        self.rec = {"meta": {"default": DEFAULT, "scenarios": SCENARIOS,
+                             "version": 2},
+                    "shared": {}, "scenarios": {}, "provenance": {}}
+
+    def record_scenario(self, sc_id: str):
+        srv = subprocess.Popen(
+            [sys.executable, str(HERE / "server.py"), "--demo",
+             "--port", str(PORT), "--scenario", sc_id],
+            cwd=str(HERE), stdout=subprocess.DEVNULL, stderr=subprocess.DEVNULL)
+        try:
+            for _ in range(60):
+                try:
+                    get_json("/api/mode", timeout=2)
+                    break
+                except Exception:
+                    time.sleep(0.5)
+            else:
+                raise SystemExit("demo server (%s) does not answer" % sc_id)
+
+            s: dict = {"state_series": [], "livepc_series": [],
+                       "trace_series": [], "endpoints": {}, "regions": {}}
+
+            # RESET state: the known starting point before every run.
+            s["reset_state"] = get_json("/api/state")
+            for p in ("/api/boot", "/api/symbols"):
+                try:
+                    s["endpoints"][p] = get_json(p)
+                except Exception as e:
+                    print("  MISSING %s (%s)" % (p, e))
+
+            # Start the chain as on the device, then cut the series.
+            # Bring the DDR sink up TOO (found 2026-08-12: the fill bars stood
+            # still -- the sink had simply never been on). Window size as in
+            # the board flow: 256 MiB, set BEFORE enabling.
+            cat0 = get_json("/api/scenarios")
+            act0 = next(x for x in cat0["scenarios"] if x["id"] == sc_id)
+            off_ddr = (act0.get("ctrl") or {}).get("ddr_size")
+            if off_ddr is not None:
+                post_json("/api/write", {"region": "ctrl", "offset": off_ddr,
+                                         "value": 256 * 1024 * 1024})
+            post_json("/api/ctl", {"action": "run"})
+            s["run_response"] = post_json("/api/ctl", {"action": "trace_on"})
+            try:
+                post_json("/api/ctl", {"action": "ddr_on"})
+            except Exception as e:
+                print("  ddr_on not possible: %s" % e)
+            s["stop_response"] = None       # filled in after the series
+
+            secs = SERIES_SECONDS[sc_id]
+            print("  %s: %d s series ..." % (sc_id, secs))
+            t0 = time.time()
+            next_live = 0.0
+            for tick in range(secs):
+                s["state_series"].append(get_json("/api/state"))
+                if time.time() - t0 >= next_live:
+                    try:
+                        s["livepc_series"].append(
+                            {"t": tick, **get_json("/api/livepc?tail=2048")})
+                    except Exception:
+                        pass
+                    next_live += LIVE_EVERY
+                if tick % TRACE_EVERY == 0:
+                    try:
+                        s["trace_series"].append(get_json("/api/trace?tail=384"))
+                    except Exception:
+                        pass
+                time.sleep(max(0.0, (tick + 1) - (time.time() - t0)))
+
+            for p in ("/api/insight", "/api/coverage", "/api/events?n=300",
+                      "/api/packets?tail=65536", "/api/fifohist?region=enc",
+                      "/api/wp/status", "/api/wp/records"):
+                try:
+                    s["endpoints"][p] = get_json(p)
+                except Exception as e:
+                    print("  MISSING %s (%s)" % (p, e))
+            print("  %s: decoding ..." % sc_id)
+            try:
+                s["endpoints"]["/api/decode?src=uram"] = get_json("/api/decode?src=uram")
+                s["endpoints"]["/api/insight"] = get_json("/api/insight")
+                s["endpoints"]["/api/coverage"] = get_json("/api/coverage")
+            except Exception as e:
+                print("  decode not recordable: %s" % e)
+
+            # Run stop once for real, so the response shape is correct.
+            s["stop_response"] = post_json("/api/ctl", {"action": "stop"})
+
+            cat = get_json("/api/scenarios")
+            if "/api/scenarios" not in self.rec["shared"]:
+                cat["scenarios"] = [x for x in cat["scenarios"]
+                                    if x["id"] in SCENARIOS]
+                cat["active"] = DEFAULT
+                self.rec["shared"]["/api/scenarios"] = cat
+            active = next(x for x in self.rec["shared"]["/api/scenarios"]["scenarios"]
+                          if x["id"] == sc_id)
+            for name, reg in (active.get("regions") or {}).items():
+                if name in ("ram", "trace", "axis", "con"):
+                    continue
+                n = min(reg["size"], REGION_DUMP_BYTES) // 4
+                words: list[int] = []
+                off = 0
+                while len(words) < n:
+                    chunk = min(4096, n - len(words))
+                    words += get_json("/api/read?region=%s&off=%d&n=%d"
+                                      % (name, off, chunk))["words"]
+                    off += chunk * 4
+                s["regions"][name] = {"base": reg["base_int"],
+                                      "size": reg["size"], "words": words}
+
+            con = HERE / "demo" / ("console_%s.txt" % sc_id)
+            text = con.read_text(encoding="utf-8")
+            s["console"] = {"text": text, "schedule": console_schedule(text),
+                            "source": con.name,
+                            "timing": "kernel stamps exact; pre-stamp lines "
+                                      "at 115200 baud; post-stamp and typed "
+                                      "lines are presentation pacing"}
+            self.rec["scenarios"][sc_id] = s
+        finally:
+            srv.terminate()
+            try:
+                srv.wait(timeout=5)
+            except Exception:
+                srv.kill()
+
+    def finish(self):
+        self.rec["shared"]["/regmap.json"] = json.loads(
+            (HERE / "regmap.json").read_text(encoding="utf-8"))
+        self.rec["shared"]["/themes.json"] = json.loads(
+            (HERE / "themes.json").read_text(encoding="utf-8"))
+        # Block-to-CSR mapping: the dashboard loads it relatively via
+        # fetch('block_csrs.json'); without recording it, the block panel of
+        # the replay falls back to "No CSRs...".
+        self.rec["shared"]["/block_csrs.json"] = json.loads(
+            (HERE / "block_csrs.json").read_text(encoding="utf-8"))
+        self.rec["shared"]["/api/mode"] = {"mode": "demo",
+                                           "live_available": False,
+                                           "live_error": None}
+        shutil.copyfile(HERE / "index.html", self.out / "index.html")
+        git = subprocess.run(["git", "rev-parse", "HEAD"], cwd=str(HERE),
+                             capture_output=True, text=True).stdout.strip()
+        files = {"index.html": HERE / "index.html",
+                 "regmap.json": HERE / "regmap.json",
+                 "themes.json": HERE / "themes.json",
+                 "block_csrs.json": HERE / "block_csrs.json"}
+        for sc in SCENARIOS:
+            files["console_%s.txt" % sc] = HERE / "demo" / ("console_%s.txt" % sc)
+            p = HERE / "demo" / ("demo_trace_%s.bin" % sc)
+            if p.is_file():
+                files[p.name] = p
+        self.rec["provenance"] = {
+            "generated": time.strftime("%Y-%m-%d %H:%M %z"),
+            "generator": "examples/dashboard/record_web_replay.py (v2)",
+            "source_repo": "TraceEncoder@" + (git[:12] or "unknown"),
+            "default_scenario": DEFAULT,
+            "server_mode": "demo (simulated registers; console and "
+                           "trace stream from real board captures)",
+            "files": {k: sha256(v) for k, v in files.items()},
+        }
+        (self.out / "replay.json").write_text(
+            json.dumps(self.rec, separators=(",", ":"), ensure_ascii=False),
+            encoding="utf-8")
+        import gzip
+        raw = (self.out / "replay.json").read_bytes()
+        print("\nreplay.json: %d B (gzip %d B)" % (len(raw), len(gzip.compress(raw, 9))))
+
+
+# ==========================================================================
+# PUBLIC EXPORT
+# ==========================================================================
+# The bundle above is the INTERNAL state: full provenance, comments, source
+# references, a hash per file. That is exactly what an external review found
+# on the website. The public export below builds a bundle from it that
+# carries ONLY what an outsider needs.
+#
+# The principle is an ALLOW LIST, in three stages -- plus one interlock:
+#   1. STRUCTURE: only the sections, endpoints and scenario keys listed here
+#      travel. Anything in no list drops out and is named in the export log.
+#      A field added later therefore does not leak silently, it disappears
+#      visibly.
+#   2. PROVENANCE: rebuilt, not filtered. Only the five entries in
+#      PUBLIC_PROVENANCE_FIELDS -- capture date, board/cores, trace protocol,
+#      scenarios, and ONE checksum over the bundle.
+#   3. TEXTS: annotation fields survive only if CLEAN. Every string runs
+#      through the same patterns as the scanner (check_replay_public.py);
+#      whatever trips it leaves together with its key. No partial redaction
+#      that leaves half sentences behind.
+#   4. INTERLOCK: at the end the export scans its own result. A single hit
+#      and NOTHING is written (exit 1).
+#
+# The payload (state_series, livepc_series, trace_series, regions, console
+# text and schedule, packet and event lists) stays untouched -- the replay
+# has to behave byte for byte the same.
+
+sys.path.insert(0, str(HERE))
+import check_replay_public as scanner        # noqa: E402
+
+PUBLIC_PROVENANCE_FIELDS = ("captured", "board", "cores", "trace_protocol",
+                            "scenarios", "bundle_sha256")
+
+# Board and protocol entry of the public provenance. Both are statements
+# about the SETUP, not measurements: board = KV260 (every scenario in the
+# catalogue runs in the PL of that board), protocol = N-Trace, evidenced by
+# the fact that both scenarios decode with the N-Trace reference decoder.
+# Cores and clock come from the catalogue, not from hand.
+PUBLIC_BOARD = "AMD Kria KV260 (Zynq UltraScale+ MPSoC), design in the PL"
+PUBLIC_PROTOCOL = "RISC-V N-Trace (Nexus) instruction trace"
+
+PUBLIC_TOP_KEYS = ("meta", "shared", "scenarios", "provenance")
+PUBLIC_META_KEYS = ("default", "scenarios", "version")
+PUBLIC_SHARED_KEYS = ("/api/scenarios", "/regmap.json", "/themes.json",
+                      "/block_csrs.json", "/api/mode")
+PUBLIC_SCENARIO_KEYS = ("reset_state", "state_series", "livepc_series",
+                        "trace_series", "endpoints", "regions",
+                        "run_response", "stop_response", "console")
+PUBLIC_ENDPOINTS = ("/api/boot", "/api/symbols", "/api/insight",
+                    "/api/coverage", "/api/events?n=300",
+                    "/api/packets?tail=65536", "/api/fifohist?region=enc",
+                    "/api/wp/status", "/api/wp/records",
+                    "/api/decode?src=uram")
+
+# Keys that ALWAYS drop -- regardless of content, because by their nature
+# they carry workbench state. A reason per entry.
+PUBLIC_DROP_KEYS = {
+    "ui_build": "md5 over the shipped server files (stale-cache guard of "
+                "the live page); constant in the replay and shaped like "
+                "a short commit id",
+    "generated_from": "RDL source file from which regmap.json was generated",
+    "files": "hash per file -- exactly the table from finding A-05",
+    "source_repo": "repo name plus short commit id",
+    "generator": "path of the generating script in the working tree",
+}
+# Individual locations instead of whole key names -- "path" does not mean
+# the same everywhere (in regmap.json it holds the RDL register path, which
+# the UI displays as the register name).
+PUBLIC_DROP_PATHS = {
+    "$.shared./api/scenarios.nexrv.path":
+        "path of the decoder binary on the workbench. ONLY the path -- the "
+        "sibling field 'available' stays, otherwise the UI reports "
+        "'Decoder MISSING'.",
+}
+# Workbench paths that the UI DISPLAYS. Removing them entirely would put
+# 'undefined' into the text; shortening to the file name says the same thing
+# without naming the drive, the user and the tree of the development
+# machine.
+PUBLIC_BASENAME_KEYS = {
+    "pcinfo": "pcinfo file of the decode",
+    "live_pcinfo": "ditto, live variant",
+    "source": "symbol map",
+    "sites_source": "call-site map",
+}
+# Convention of these JSON trees: a leading underscore marks an INTERNAL
+# annotation (_comment, _src, _ctrl_comment ...). Those go overboard as a
+# group -- that is the "review comments" class.
+PUBLIC_DROP_UNDERSCORE = True
+
+# Renames BEFORE the check. Only documented name equivalences, no
+# whitewashing: "C-Trace" is the informal short name of the product officially
+# called CEDARtools.TraceEncoder (as stated in the header of index.html). A
+# release artefact of the new name should no longer carry the old one.
+PUBLIC_RENAME = [
+    (re.compile(r"\bC-Trace\b"), "CTTE",
+     "short name from before the rename to CEDARtools.TraceEncoder"),
+]
+
+# The same as HTML_REDACTIONS, but for texts INSIDE the recording object: a
+# sentence that says nothing but useful things apart from the internal
+# reference should not disappear entirely. Deliberately kept short -- the rule
+# stays "clean or gone", and this is the named exception for texts the UI
+# shows prominently. Zero hits = the list is stale = the export FAILS.
+JSON_REDACTIONS = [
+    (re.compile(r"\(\+64 MiB, ctrace_resmem\.dtso\)"),
+     "(+64 MiB, reserved via device tree)",
+     "CVA6 core description named the device-tree overlay of the working tree"),
+    (re.compile(r" \(vivado/kv260_app/kv260_plclk\.sh\)"), "",
+     "Rocket clock note named the board script of the working tree"),
+]
+
+# Visible texts in index.html that point at internal sources. The comment
+# strip does not catch them, because they are genuine UI strings. Every
+# replacement says the same thing without the reference; zero hits = the list
+# is stale = the export FAILS (see public_index_html).
+HTML_REDACTIONS = [
+    # The former entry here ("tools/ctrace_dashboard/themes.json" in the help
+    # text of the theme card) went away with the migration into this repo: the
+    # cause was fixed AT THE SOURCE (index.html now says
+    # "examples/dashboard/themes.json" -- a path INSIDE this example, no
+    # longer a reference to the predecessor repository, and therefore no
+    # longer a hit for the "repo_path" pattern of check_replay_public.py). A
+    # redaction is only needed for what cannot be fixed at the source.
+    (re.compile(r"\(RDL ct_cs_cpuif\.rdl:1440-1493, "
+                r"SPEC_axis_wp_memory_map\.md §7\)"),
+     "(see the AXIS watchpoint section of the register reference)",
+     "tooltip pointed at RDL lines and an internal spec document "
+     "(exactly the finding quoted in A-05)"),
+    (re.compile(r"Source: docs/SPEC_axis_wp_memory_map\.md §7\."),
+     "Source: the AXIS watchpoint section of the register reference.",
+     "source reference of a hint text pointed into the docs tree"),
+    (re.compile(r"\(dis_to_symbols\.py --sites\)"),
+     "(disassembly-derived call-site list)",
+     "drop zone named the internal script that produces the file"),
+    (re.compile(r"only the server drain \(wp_view\.py\) reads this window"),
+     "only the server drain reads this window",
+     "block description named the server module in the working tree"),
+    (re.compile(r"\+'from \(md5 over index\.html, wp\.html, regmap\.json, '\s*"
+                r"\n\s*\+'block_csrs\.json, scenarios\.json, server\.py\)\. "
+                r"If the server '"),
+     "+'from. If the server '",
+     "tooltip of the build stamp listed the shipped server files"),
+    (re.compile(r"\(vivado/kv260_app/duo_pib_pmod\.xdc\)\. "), "",
+     "pin assignment named the internal constraints file "
+     "(second finding quoted in A-05)"),
+    (re.compile(r"tools/etrace_trio_demux\.py"), "the stream demultiplexer",
+     "block description named a script of the working tree"),
+]
+
+
+def _verbatim(where: str) -> bool:
+    """A field that stays VERBATIM -- recordings are not rewritten.
+
+    This list is not a second truth: it is exactly the scanner's exemption
+    table. Where the scanner tolerates a marker on purpose (because it comes
+    from a measurement), the rename must not reach in either -- otherwise the
+    export would silently falsify a recording protocol.
+    """
+    return any(fnmatch.fnmatch(where, ex["where"])
+               for ex in scanner.EXEMPTIONS if ex["file"] == "replay.json")
+
+
+_JSON_REDACT_HITS: dict = {}
+
+
+def _rename(s: str) -> str:
+    for rx, repl, _why in PUBLIC_RENAME:
+        s = rx.sub(repl, s)
+    for rx, repl, _why in JSON_REDACTIONS:
+        s, n = rx.subn(repl, s)
+        if n:
+            _JSON_REDACT_HITS[rx.pattern] = _JSON_REDACT_HITS.get(rx.pattern, 0) + n
+    return s
+
+
+def _dirty(s: str, where: str):
+    """Pattern ids this string trips inside the bundle (empty = clean)."""
+    return sorted({f.pid for f in
+                   scanner.string_findings(s, "replay.json", where)})
+
+
+def _basename(v):
+    """Path -> file name; lists element-wise, everything else unchanged."""
+    if isinstance(v, str):
+        return v.replace("\\", "/").rsplit("/", 1)[-1]
+    if isinstance(v, list):
+        return [_basename(x) for x in v]
+    return v
+
+
+class _Dirty:
+    """A mark: this subtree carries an internal marker."""
+
+
+DIRTY = _Dirty()
+
+
+def _sanitize(node, where: str, log: list):
+    if isinstance(node, dict):
+        out = {}
+        for k, v in node.items():
+            sub = "%s.%s" % (where, k)
+            if PUBLIC_DROP_UNDERSCORE and isinstance(k, str) and k.startswith("_"):
+                log.append(("drop-underscore", sub, "internal annotation"))
+                continue
+            if k in PUBLIC_DROP_KEYS:
+                log.append(("drop-key", sub, PUBLIC_DROP_KEYS[k]))
+                continue
+            hit = [g for g in PUBLIC_DROP_PATHS if fnmatch.fnmatch(sub, g)]
+            if hit:
+                log.append(("drop-path", sub, PUBLIC_DROP_PATHS[hit[0]]))
+                continue
+            if k in PUBLIC_BASENAME_KEYS:
+                v = _basename(v)
+                log.append(("basename", sub, PUBLIC_BASENAME_KEYS[k]))
+            v2 = _sanitize(v, sub, log)
+            if v2 is DIRTY:
+                log.append(("drop-dirty", sub, ",".join(_dirty_of(v, sub))))
+                continue
+            out[k] = v2
+        return out
+    if isinstance(node, list):
+        out_l = []
+        for i, v in enumerate(node):
+            v2 = _sanitize(v, "%s[%d]" % (where, i), log)
+            if v2 is DIRTY:
+                # A dirty element invalidates the whole list: a hole in a
+                # text list would leave half sentences, a hole in a data
+                # list would shift indices.
+                return DIRTY
+            out_l.append(v2)
+        return out_l
+    if isinstance(node, str):
+        s = node if _verbatim(where) else _rename(node)
+        return DIRTY if _dirty(s, where) else s
+    return node
+
+
+def _dirty_of(node, where: str) -> list:
+    """Which patterns made the subtree dirty (for the log)."""
+    ids: set = set()
+    if isinstance(node, dict):
+        for k, v in node.items():
+            ids |= set(_dirty_of(v, "%s.%s" % (where, k)))
+    elif isinstance(node, list):
+        for i, v in enumerate(node):
+            ids |= set(_dirty_of(v, "%s[%d]" % (where, i)))
+    elif isinstance(node, str):
+        ids |= set(_dirty(_rename(node), where))
+    return sorted(ids)
+
+
+def _pick(d: dict, keys, where: str, log: list) -> dict:
+    """Apply the allow-list and name every drop."""
+    out = {}
+    for k, v in d.items():
+        if k in keys:
+            out[k] = v
+        else:
+            log.append(("drop-structure", "%s.%s" % (where, k),
+                        "not on any allow-list"))
+    return out
+
+
+def public_replay(rec: dict, log: list) -> dict:
+    """Internal recording object -> public one (without provenance)."""
+    _JSON_REDACT_HITS.clear()       # count afresh per export, otherwise the
+    #                                 second run inherits the first run's hits
+    pub = _pick(rec, PUBLIC_TOP_KEYS, "$", log)
+    pub["meta"] = _pick(pub.get("meta", {}), PUBLIC_META_KEYS, "$.meta", log)
+    pub["meta"]["public"] = True
+    pub["shared"] = _pick(pub.get("shared", {}), PUBLIC_SHARED_KEYS,
+                          "$.shared", log)
+    scen = {}
+    for sid, s in (pub.get("scenarios") or {}).items():
+        s = _pick(s, PUBLIC_SCENARIO_KEYS, "$.scenarios.%s" % sid, log)
+        s["endpoints"] = _pick(s.get("endpoints", {}), PUBLIC_ENDPOINTS,
+                               "$.scenarios.%s.endpoints" % sid, log)
+        scen[sid] = s
+    pub["scenarios"] = scen
+    pub = _sanitize(pub, "$", log)
+    misses = [why for rx, _r, why in JSON_REDACTIONS
+              if not _JSON_REDACT_HITS.get(rx.pattern)]
+    for rx, _r, why in JSON_REDACTIONS:
+        log.append(("json-redact", rx.pattern[:60],
+                    "%dx -- %s" % (_JSON_REDACT_HITS.get(rx.pattern, 0), why)))
+    if misses:
+        raise SystemExit("PUBLIC_EXPORT_FAIL  %d replacement(s) without a hit "
+                         "(the recording has changed):\n  - %s"
+                         % (len(misses), "\n  - ".join(misses)))
+    pub["provenance"] = {}
+    return pub
+
+
+def public_provenance(rec: dict, pub: dict, captured: str) -> dict:
+    """The five permitted entries -- from the data, not from prose."""
+    cores = []
+    cat = (pub.get("shared") or {}).get("/api/scenarios") or {}
+    for s in cat.get("scenarios") or []:
+        names = ", ".join("%s (%s)" % (c.get("name"), c.get("isa"))
+                          for c in s.get("cores") or [])
+        mhz = sorted({c.get("mhz") for c in s.get("cores") or []
+                      if c.get("mhz")})
+        cores.append("%s: %s%s" % (s.get("id"), names,
+                                   " @ %s MHz" % "/".join(str(m) for m in mhz)
+                                   if mhz else ""))
+    prov = {
+        "captured": captured,
+        "board": PUBLIC_BOARD,
+        "cores": cores,
+        "trace_protocol": PUBLIC_PROTOCOL,
+        "scenarios": list((pub.get("meta") or {}).get("scenarios") or []),
+        "bundle_sha256": "",
+    }
+    assert tuple(prov) == PUBLIC_PROVENANCE_FIELDS, "provenance allow-list"
+    return prov
+
+
+# ---- index.html: strip comments, replace references -----------------------
+
+def _html_comment_spans(src: str, start: int, end: int):
+    spans = []
+    i = start
+    while True:
+        a = src.find("", a + 4)
+        b = end if b < 0 else b + 3
+        spans.append((a, b))
+        i = b
+
+
+def _css_comment_spans(src: str, start: int, end: int):
+    spans = []
+    i = start
+    while i < end:
+        c = src[i]
+        if c in "\"'":
+            i = _skip_string(src, i, c)
+            continue
+        if c == "/" and i + 1 < end and src[i + 1] == "*":
+            b = src.find("*/", i + 2)
+            b = end if b < 0 else b + 2
+            spans.append((i, b))
+            i = b
+            continue
+        i += 1
+    return spans
+
+
+def _skip_string(src: str, i: int, q: str) -> int:
+    i += 1
+    while i < len(src):
+        if src[i] == "\\":
+            i += 2
+            continue
+        if src[i] == q:
+            return i + 1
+        i += 1
+    return i
+
+
+# After these characters (and keywords) a "/" starts a regular expression,
+# not a division. The difference matters: mistake a regex literal for a
+# division and the lexer reads a "'" inside it as the start of a string and
+# loses the thread -- which really happened at `.replace(/'/g,"'")` in
+# index.html. The counter-check runs through node --check.
+_RX_OK_PREV = set("(,=:[!&|?{};+-*%~^<>") | {""}
+_RX_OK_WORD = {"return", "typeof", "case", "in", "of", "new", "delete",
+               "void", "do", "else", "yield", "await", "instanceof"}
+
+
+def _prev_word(src: str, i: int) -> str:
+    j = i
+    while j > 0 and src[j - 1].isspace():
+        j -= 1
+    k = j
+    while k > 0 and (src[k - 1].isalnum() or src[k - 1] == "_"):
+        k -= 1
+    return src[k:j]
+
+
+def _skip_regex(src: str, i: int, end: int) -> int:
+    j = i + 1
+    cls = False
+    while j < end:
+        if src[j] == "\\":
+            j += 2
+            continue
+        if src[j] == "[":
+            cls = True
+        elif src[j] == "]":
+            cls = False
+        elif src[j] == "\n":
+            break
+        elif src[j] == "/" and not cls:
+            return j + 1
+        j += 1
+    return j
+
+
+def _js_template(src: str, i: int, end: int, spans: list) -> int:
+    """Skip a template literal; `${...}` is normal code again."""
+    i += 1
+    while i < end:
+        c = src[i]
+        if c == "\\":
+            i += 2
+            continue
+        if c == "`":
+            return i + 1
+        if c == "$" and i + 1 < end and src[i + 1] == "{":
+            i = _js_scan(src, i + 2, end, spans, stop_brace=True)
+            continue
+        i += 1
+    return i
+
+
+def _js_scan(src: str, i: int, end: int, spans: list, stop_brace=False) -> int:
+    """Read JS code, collect comment spans. One pass, one state."""
+    prev = ""
+    depth = 0
+    while i < end:
+        c = src[i]
+        if c == "/" and i + 1 < end:
+            d = src[i + 1]
+            if d == "/":
+                b = src.find("\n", i)
+                b = end if b < 0 or b > end else b
+                spans.append((i, b))
+                i = b
+                continue
+            if d == "*":
+                b = src.find("*/", i + 2)
+                b = end if b < 0 else b + 2
+                spans.append((i, b))
+                i = b
+                continue
+            if prev in _RX_OK_PREV or _prev_word(src, i) in _RX_OK_WORD:
+                i = _skip_regex(src, i, end)
+                prev = "/"
+                continue
+            prev = "/"
+            i += 1
+            continue
+        if c in "\"'":
+            i = _skip_string(src, i, c)
+            prev = c
+            continue
+        if c == "`":
+            i = _js_template(src, i, end, spans)
+            prev = "`"
+            continue
+        if c == "{":
+            depth += 1
+        elif c == "}":
+            if stop_brace and depth == 0:
+                return i + 1
+            depth -= 1
+        if not c.isspace():
+            prev = c
+        i += 1
+    return i
+
+
+def _js_comment_spans(src: str, start: int, end: int):
+    spans: list = []
+    _js_scan(src, start, end, spans)
+    return spans
+
+
+def strip_comments(html: str):
+    """Strip HTML, CSS and JS comments; the line count stays intact.
+
+    A comment is replaced by its line breaks (or by a single space if it sat
+    within one line) -- `a/*x*/b` must not glue into `ab`.
+    """
+    def _body(tag):
+        a = html.find("<%s" % tag)
+        if a < 0:
+            return None
+        a = html.find(">", a) + 1
+        return a, html.find("" % tag, a)
+
+    spans = []
+    style = _body("style")
+    script = _body("script")
+    marks = sorted([m for m in (style, script) if m])
+    plain = []
+    cur = 0
+    for a, b in marks:
+        plain.append((cur, a))
+        cur = b
+    plain.append((cur, len(html)))
+    for a, b in plain:
+        spans += _html_comment_spans(html, a, b)
+    if style:
+        spans += _css_comment_spans(html, *style)
+    if script:
+        spans += _js_comment_spans(html, *script)
+    spans.sort()
+    out = []
+    cur = 0
+    for a, b in spans:
+        assert html[a:a + 2] in ("//", "/*") or html[a:a + 4] == "
+
+"""
+
+
+def t_public_export():
+    rec = _bundle()
+    log = []
+    pub = R.public_replay(json.loads(json.dumps(rec)), log)
+    prov = R.public_provenance(rec, pub, "2026-08-15")
+    check("provenance has EXACTLY the permitted fields",
+          tuple(prov) == R.PUBLIC_PROVENANCE_FIELDS, str(tuple(prov)))
+    check("provenance names no file hashes and no repository",
+          not pids(json.dumps(prov, ensure_ascii=False), "$.provenance"),
+          str(pids(json.dumps(prov, ensure_ascii=False), "$.provenance")))
+    check("provenance names cores taken from the data",
+          any("Rocket hart 0" in c for c in prov["cores"]), str(prov["cores"]))
+
+    flat = json.dumps(pub, ensure_ascii=False)
+    check("ui_build is gone", "ui_build" not in flat)
+    check("underscore keys are gone",
+          "_ctrl_comment" not in flat and "_notiz" not in flat and
+          "_comment" not in flat)
+    check("generated_from is gone", "generated_from" not in flat)
+    check("an endpoint outside the allow list is dropped",
+          "/api/intern" not in flat and "/api/geheim" not in flat)
+    check("the decoder path is gone, its availability stays",
+          "NexRv.exe" not in flat
+          and pub["shared"]["/api/scenarios"]["nexrv"] == {"available": True},
+          str(pub["shared"]["/api/scenarios"].get("nexrv")))
+    check("the workbench path is cut down to the file name",
+          pub["scenarios"]["rocket2"]["endpoints"]["/api/symbols"]["source"]
+          == "symbols.map",
+          str(pub["scenarios"]["rocket2"]["endpoints"]["/api/symbols"]))
+    core0 = pub["shared"]["/api/scenarios"]["scenarios"][0]["cores"][0]
+    check("the replacement keeps the sentence and takes only the reference",
+          core0.get("desc") == "window (+64 MiB, reserved via device tree)"
+          and core0.get("mhz_note") == "75 MHz. WNS +3.466 ns.",
+          json.dumps(core0, ensure_ascii=False))
+    check("C-Trace is renamed in labels",
+          pub["shared"]["/api/scenarios"]["scenarios"][0]["regions"]["ctrl"]
+          ["label"] == "CTTE CSRs")
+    check("Konsolen-Mitschnitt bleibt WOERTLICH",
+          pub["scenarios"]["rocket2"]["console"]["text"]
+          == rec["scenarios"]["rocket2"]["console"]["text"],
+          pub["scenarios"]["rocket2"]["console"]["text"])
+    check("Zeitreihen bleiben vollstaendig",
+          len(pub["scenarios"]["rocket2"]["state_series"]) == 4
+          and pub["scenarios"]["rocket2"]["state_series"][3]["trace_bytes"] == 103)
+    check("Register-Speicherabbild bleibt",
+          pub["scenarios"]["rocket2"]["regions"]["ctrl"]["words"] == [0, 1, 2, 3])
+    check("Konsolen-Zeitplan bleibt",
+          pub["scenarios"]["rocket2"]["console"]["schedule"] == [[0, 0], [10, 33]])
+
+    # For the neutrality check the two DELIBERATELY injected foreign endpoints
+    # are removed first -- they test the allow list (above) and are not
+    # payload that would have to survive.
+    ref = json.loads(json.dumps({k: v for k, v in rec.items()
+                                 if k != "provenance"}))
+    ref["shared"].pop("/api/geheim")
+    ref["scenarios"]["rocket2"]["endpoints"].pop("/api/intern")
+    d = S.compare_payload(ref,
+                          {k: v for k, v in pub.items() if k != "provenance"})
+    check("neutrality: no number changed", not d["numeric"], str(d["numeric"][:3]))
+    check("neutrality: no list length changed", not d["length"],
+          str(d["length"][:3]))
+    check("neutrality: no payload removed",
+          not [x for x in d["removed"] if x[1] == "DATEN"],
+          str([x for x in d["removed"] if x[1] == "DATEN"][:3]))
+
+
+def t_comment_strip():
+    out, spans = R.strip_comments(HTML)
+    check("Kommentare gefunden", len(spans) >= 4, str(len(spans)))
+    check("deutscher Kommentar weg", "AW-Befund" not in out and "Kopfkommentar" not in out)
+    check("HTML-Kommentar weg", "interner Hinweis" not in out)
+    check("a string containing /* stays", "'ein String mit /* Sternchen */ darin'" in out)
+    check("the CSS content string stays", '"/* kein Kommentar */"' in out)
+    check("a regex with quotes is undamaged",
+          "x.replace(/'/g, \"'\")" in out)
+    check("Template bleibt", "${obj.f(1) / 2}" in out and "${'inner'}" in out)
+    check("a regex with a slash stays", "/ab\\/cd/.test('x')" in out)
+    check("Zeilenzahl unveraendert (Diff bleibt lesbar)",
+          out.count("\n") == HTML.count("\n"),
+          "%d/%d" % (out.count("\n"), HTML.count("\n")))
+    msg = R._node_check(R._script_body(out))
+    check("node --check on the de-commented script",
+          msg in ("", "SKIP node not available"), msg)
+
+
+def t_export_refuses():
+    """The interlock: one marker in the result and NOTHING gets written."""
+    keep = R.HTML_REDACTIONS
+    R.HTML_REDACTIONS = []
+    try:
+        with tempfile.TemporaryDirectory() as td:
+            out = Path(td) / "bundle"
+            log = Path(td) / "x.log"
+            bad = "C:\\dev\\ctrace_mbv\\x"
+            rc = R.public_export(_bundle(), bad, out, "2026-08-15", log)
+            check("the export reports FAIL", rc == 1, "rc=%s" % rc)
+            check("the export wrote NOTHING", not out.exists())
+            check("the export log names the reason",
+                  "PUBLIC_SCAN_FAIL" in log.read_text(encoding="utf-8"))
+            # Counter-check: without a marker the same path goes through.
+            rc = R.public_export(_bundle(), "ok",
+                                 out, "2026-08-15", log)
+            check("counter-check: a clean bundle is written",
+                  rc == 0 and (out / "replay.json").is_file(), "rc=%s" % rc)
+            pub = json.loads((out / "replay.json").read_text(encoding="utf-8"))
+            files = {p.name: p.read_bytes() for p in out.iterdir()}
+            got = pub["provenance"]["bundle_sha256"]
+            pub["provenance"]["bundle_sha256"] = ""
+            files["replay.json"] = json.dumps(
+                pub, separators=(",", ":"), ensure_ascii=False).encode("utf-8")
+            check("the bundle checksum can be recomputed",
+                  R.bundle_digest(files) == got,
+                  "%s != %s" % (R.bundle_digest(files)[:16], got[:16]))
+            check("the scan of the generated bundle is green",
+                  not S.scan_bundle(out)[0],
+                  str([f.pid for f in S.scan_bundle(out)[0]][:5]))
+    finally:
+        R.HTML_REDACTIONS = keep
+
+
+def t_mutation():
+    """Counter-check: an injected marker MUST make the scan go red."""
+    with tempfile.TemporaryDirectory() as td:
+        d = Path(td)
+        (d / "replay.json").write_text(json.dumps(
+            {"meta": {"version": 2}, "scenarios": {}}), encoding="utf-8")
+        check("a clean mini bundle is green", not S.scan_bundle(d)[0])
+        for marker in ("ctrace_mbv@660d5b9495e8",
+                       "vivado/kv260_app/duo_pib_pmod.xdc",
+                       "AW-Befund 2026-07-29",
+                       "ct_cs_cpuif.rdl:1440-1493",
+                       "C:\\dev\\ctrace_mbv"):
+            (d / "replay.json").write_text(json.dumps(
+                {"meta": {"version": 2}, "note": marker}), encoding="utf-8")
+            check("Mutation rot: %s" % marker[:34], bool(S.scan_bundle(d)[0]))
+
+
+def main() -> int:
+    for t in (t_patterns_hit, t_no_false_positives, t_exemption_is_narrow,
+              t_public_export, t_comment_strip, t_export_refuses, t_mutation):
+        t()
+    print()
+    if FAILS:
+        print("U12_PUBLIC_FAIL  %d/%d rot:" % (len(FAILS), NCHECK))
+        for f in FAILS:
+            print("  - " + f)
+        return 1
+    print("U12_PUBLIC_ALL_PASS  (%d checks)" % NCHECK)
+    return 0
+
+
+if __name__ == "__main__":
+    sys.exit(main())
diff --git a/examples/dashboard/test_rv64_scenarios.py b/examples/dashboard/test_rv64_scenarios.py
new file mode 100644
index 0000000..bb8c1db
--- /dev/null
+++ b/examples/dashboard/test_rv64_scenarios.py
@@ -0,0 +1,548 @@
+#!/usr/bin/env python3
+# SPDX-FileCopyrightText: 2026 Accemic Technologies GmbH
+# SPDX-License-Identifier: ISC
+"""Gate B1-3: the RV64 scenarios against the RTL and against the server.
+
+The dashboard has exactly one class of defect that nobody notices: a CTRL
+register map that does not match the loaded design. It produces no error
+message but plausible wrong numbers -- which is why scenarios.json exists at
+all. This gate therefore does NOT check the map against itself but against
+the register table in the header of the respective SoC top file, and makes
+the counter-check: a deliberately shifted map MUST colour it red.
+
+What is checkable without a board is checked as well:
+  * app name -> scenario (including the 64-bit bitstream variants),
+  * the tear-free 64-bit PC read including a simulated carry,
+  * the guest->PS translation of the Rocket ELF load,
+  * that all offsets fit into their aperture.
+
+SKIP-clean: sections 1/1b (CTRL map vs. RTL) and 6 (Sv39 through the display
+chain) need source/build files (rtl/board_kv260/*.sv, vivado/kv260_app/*.sv,
+bld/, sw/cva6_char/) that live in the predecessor repository KV260 tree, not in this
+example -- they are skipped, not failed, when that tree is not alongside
+this repo. Section 6 additionally needs a RISC-V toolchain, resolved the
+same way as test_elf_load.py (RISCV_READELF/RISCV_BIN/PATH, no hardcoded
+Windows path). Sections 2-4 and 7 are self-contained (scenarios.json +
+server.py logic only) and always run.
+
+Invocation:  py test_rv64_scenarios.py
+"""
+import re
+import subprocess
+import sys
+from pathlib import Path
+
+HERE = Path(__file__).resolve().parent
+ROOT = HERE.parents[1]
+sys.path.insert(0, str(HERE))
+
+import server                      # noqa: E402
+from scenario import Catalog       # noqa: E402
+
+FAILS = []
+NCHECK = 0
+SKIPS = []
+
+
+def skip(name, reason):
+    """Record a clean skip -- distinct from FAILS, never turns the gate red."""
+    SKIPS.append(name + ((" -- " + reason) if reason else ""))
+    print("  SKIP %s%s" % (name, ("  " + reason) if reason else ""))
+
+
+def find_riscv_tool(*basenames):
+    """Locate a RISC-V toolchain binary without a hardcoded machine path.
+
+    Search order: RISCV_BIN (directory, ct_env.sh convention) > PATH. Tries
+    each name in `basenames` in order (e.g. the rv64 and rv32 variant).
+    Returns None -- a normal outcome on a machine without the toolchain --
+    if nothing is found.
+    """
+    import os
+    import shutil
+    exe = ".exe" if os.name == "nt" else ""
+    riscv_bin = os.environ.get("RISCV_BIN")
+    if riscv_bin:
+        for name in basenames:
+            cand = Path(riscv_bin) / (name + exe)
+            if cand.is_file():
+                return cand
+    for name in basenames:
+        found = shutil.which(name)
+        if found:
+            return Path(found)
+    return None
+
+
+def check(name, ok, info=""):
+    global NCHECK
+    NCHECK += 1
+    print("  %-4s %s%s" % ("OK" if ok else "FAIL", name, ("  " + info) if info else ""))
+    if not ok:
+        FAILS.append(name + ((" -- " + info) if info else ""))
+    return ok
+
+
+def rtl_ctrl_map(path):
+    """Register table from the header comment of a SoC top file.
+
+    Expects lines of the form ` *     0x1C SINK_CTRL   (rw) ...` -- the form
+    in which both designs document their map. Several registers on one line
+    (`0x08 TRACE_BEATS (ro)   0x0C TRACE_BYTES (ro)`) are picked up too.
+    """
+    txt = Path(path).read_text(encoding="utf-8", errors="replace")
+    head = txt.split("*/", 1)[0]
+    out = {}
+    for m in re.finditer(r"0x([0-9A-Fa-f]{2})\s+([A-Z][A-Z0-9_]{2,})\s*\((rw|ro|w)\)", head):
+        out[m.group(2).lower()] = int(m.group(1), 16)
+    return out
+
+
+def cmp_map(sid, sc, rtl, path, skip=()):
+    """The scenarios.json map against the RTL map, in BOTH directions."""
+    ok = True
+    for name, off in sorted(rtl.items()):
+        if name in skip:
+            continue
+        got = sc.co(name)
+        if got is None:
+            ok = check("%s: %s (RTL 0x%02X) missing from scenarios.json" % (sid, name, off),
+                       False) and ok
+        elif got != off:
+            ok = check("%s: %s sits at 0x%02X, the RTL says 0x%02X" % (sid, name, got, off),
+                       False) and ok
+    for name, off in sorted(sc.ctrl.items()):
+        if name in skip:
+            continue
+        if name not in rtl:
+            ok = check("%s: %s@0x%02X is in no RTL table" % (sid, name, off),
+                       False) and ok
+    check("%s: CTRL map congruent with %s (%d registers)"
+          % (sid, Path(path).name, len(rtl)), ok)
+    return ok
+
+
+class FakeBus:
+    """Register bank with controllable behaviour -- for the tear test."""
+
+    demo = False
+
+    def __init__(self, regs, tear_at=None):
+        self.regs = dict(regs)
+        self.tear_at = tear_at          # offset whose read advances the PC
+        self.reads = 0
+
+    def read(self, region, off, n=1):
+        self.reads += 1
+        v = self.regs.get(off, 0)
+        if self.tear_at is not None and off == self.tear_at:
+            # A carry exactly between the two halves: LO jumps to 0, HI counts
+            # up by one -- the classic tear.
+            self.regs[0x4C] = 0x00000000
+            self.regs[0x50] = (self.regs.get(0x50, 0) + 1) & 0xFFFFFFFF
+            self.tear_at = None
+        return [v] * n
+
+
+def main():
+    print("== 1. CTRL maps against the RTL ==")
+    cat = Catalog()
+    rtl_root = ROOT / "rtl" / "board_kv260"
+    vivado_root = ROOT / "vivado" / "kv260_app"
+    rtl_sources = {
+        "rocket64": vivado_root / "rocket_soc_top.sv",
+        "cva6": rtl_root / "cva6_linux_soc_top.sv",
+        "cva6_2": rtl_root / "cva6_2_soc_top.sv",
+        "tgc5b2": rtl_root / "tgc5b2_axis_soc_top.sv",
+        "trio": rtl_root / "trio_soc_top.sv",
+    }
+    have_rtl = all(p.is_file() for p in rtl_sources.values())
+    if not have_rtl:
+        skip("sections 1 + 1b (CTRL map vs. RTL)",
+             "%s is not part of this example (KV260 SoC tops migrate "
+             "under AP4, plan section 3); the RTL-vs-scenarios.json "
+             "cross-check runs in the KV260 examples package once that "
+             "lands" % rtl_root.parent)
+    else:
+        rocket_rtl = rtl_ctrl_map(vivado_root / "rocket_soc_top.sv")
+        cva6_rtl = rtl_ctrl_map(rtl_root / "cva6_linux_soc_top.sv")
+        check("RTL table rocket_soc_top.sv read (>=20 registers)",
+              len(rocket_rtl) >= 20, "%d found" % len(rocket_rtl))
+        check("RTL table cva6_linux_soc_top.sv read (>=14 registers)",
+              len(cva6_rtl) >= 14, "%d found" % len(cva6_rtl))
+        cmp_map("rocket64", cat.by_id["rocket64"], rocket_rtl,
+                vivado_root / "rocket_soc_top.sv")
+        # According to its own file header, cva6_linux64 carries "word for word
+        # the same map" as the RV32 version -- exactly that is verified here,
+        # instead of taking it on faith.
+        cmp_map("cva6_linux64", cat.by_id["cva6_linux64"], cva6_rtl,
+                rtl_root / "cva6_linux_soc_top.sv")
+        cmp_map("cva6_linux", cat.by_id["cva6_linux"], cva6_rtl,
+                rtl_root / "cva6_linux_soc_top.sv")
+
+        # The dual CVA6 SoC (D3): both register widths share ONE SoC file, the
+        # scenarios differ only in values. That is exactly why both belong in
+        # here -- otherwise a shift would hit only one of them, unnoticed.
+        cva6_2_rtl = rtl_ctrl_map(rtl_root / "cva6_2_soc_top.sv")
+        for sid in ("cva6_2_rv64", "cva6_2_rv32"):
+            cmp_map(sid, cat.by_id[sid], cva6_2_rtl,
+                    rtl_root / "cva6_2_soc_top.sv")
+
+        # The shared sink window (ct_trace_sinks) sits in
+        # THREE designs with identical offsets -- and it was exactly during that
+        # unification that a register MOVED: DDR_BEATS from 0x30 to 0x38,
+        # because 0x30 is now PIB_DROPS. A move without a check is the most
+        # expensive kind of drift: both offsets answer, only with the wrong
+        # counter.
+        tgc5b2_top = rtl_root / "tgc5b2_axis_soc_top.sv"
+        tgc5b2_rtl = rtl_ctrl_map(tgc5b2_top)
+        check("RTL table tgc5b2_axis_soc_top.sv read (>=13 registers)",
+              len(tgc5b2_rtl) >= 13, "%d found" % len(tgc5b2_rtl))
+        cmp_map("tgc5b2_axis_wp", cat.by_id["tgc5b2_axis_wp"], tgc5b2_rtl, tgc5b2_top)
+        # In their file headers duo/trio document ONLY the sink window in this
+        # form (the base registers are prose there) -- hence one direction
+        # here: every register of the RTL table has to be present in the
+        # map.
+        trio_top = rtl_root / "trio_soc_top.sv"
+        trio_rtl = rtl_ctrl_map(trio_top)
+        trio_bad = {n: (off, cat.by_id["trio"].co(n))
+                    for n, off in trio_rtl.items() if cat.by_id["trio"].co(n) != off}
+        check("trio: sink window congruent with trio_soc_top.sv (%d registers)"
+              % len(trio_rtl), not trio_bad, repr(trio_bad))
+        for sid in ("tgc5b2_axis_wp", "trio"):
+            sc = cat.by_id[sid]
+            check("%s: 0x30 = PIB_DROPS, DDR_BEATS = 0x38 (T2 move)" % sid,
+                  sc.co("pib_drops") == 0x30 and sc.co("ddr_beats") == 0x38,
+                  "pib_drops=%r ddr_beats=%r" % (sc.co("pib_drops"), sc.co("ddr_beats")))
+        # Counter-check for the move: the OLD map (DDR_BEATS at 0x30) MUST
+        # show up.
+        old = dict(cat.by_id["tgc5b2_axis_wp"].ctrl)
+        old["ddr_beats"] = 0x30
+        check("counter-check -- the old C0B_DDR map (DDR_BEATS@0x30) shows up",
+              [n for n, o in tgc5b2_rtl.items() if old.get(n) != o] == ["ddr_beats"],
+              repr([n for n, o in tgc5b2_rtl.items() if old.get(n) != o]))
+
+        # Sinks per bitstream variant: a scenario may have several builds, and
+        # they do not all carry the same sinks (tgc5b2: the AXIS-only build
+        # first, the C0B_SINK3 build adds DDR and PIB). A variant may
+        # therefore have FEWER sinks than the scenario, never more --
+        # otherwise the view claims a sink for which the scenario has no CTRL
+        # offsets at all.
+        for sc in cat.by_id.values():
+            for v in sc.app_variants:
+                if "sinks" not in v:
+                    continue
+                extra = [k for k, on in (v["sinks"] or {}).items()
+                         if on and not (sc.sinks or {}).get(k)]
+                check("%s/%s: the variant sinks are a subset of the scenario"
+                      % (sc.id, v.get("app")), not extra, repr(extra))
+
+        print("== 1b. counter-check: a shifted map MUST show up ==")
+        bad = dict(cat.by_id["rocket64"].ctrl)
+        bad["pc_hi"] = bad["pc_hi"] + 4          # one single shift
+        shifted = type("S", (), {"co": lambda self, n: bad.get(n), "ctrl": bad})()
+        before = len(FAILS)
+        quiet = []
+        for name, off in rocket_rtl.items():
+            if shifted.co(name) != off:
+                quiet.append(name)
+        check("a shifted PC_HI is detected", quiet == ["pc_hi"],
+              "flagged: %r" % quiet)
+        check("the counter-check did not distort the counter", len(FAILS) == before)
+
+    print("== 2. app name -> scenario ==")
+    for app, want in [("cva6_linux64_x64_ctrace_kv260", "cva6_linux64"),
+                      ("cva6_linux64_ctrace_kv260", "cva6_linux64"),
+                      ("rocket_x64_ctrace_kv260", "rocket64"),
+                      ("rocket_ctrace_kv260", "rocket64"),
+                      ("mbv_ctrace_kv260", "mbv"),
+                      ("cva6_linux_ctrace_kv260", "cva6_linux"),
+                      ("trio_ctrace_kv260", "trio")]:
+        s = cat.by_app(app)
+        check("%s -> %s" % (app, want), s is not None and s.id == want,
+              "got: %s" % (s.id if s else None))
+    check("a foreign app is not mapped", cat.by_app("k26-starter-kits") is None)
+    check("64-bit variants are present in by_id_apps (PL protection)",
+          {"cva6_linux64_x64_ctrace_kv260", "rocket_x64_ctrace_kv260"}
+          <= cat.by_id_apps())
+    for sid in ("cva6_linux64", "rocket64"):
+        check("%s: core width 64 bit" % sid, cat.by_id[sid].xlen == 64)
+
+    print("== 3. offsets fit into the aperture ==")
+    for sid in cat.order:
+        sc = cat.by_id[sid]
+        size = sc.regions["ctrl"][1]
+        bad = {n: o for n, o in sc.ctrl.items() if not (0 <= o < size - 3)}
+        check("%s: all CTRL offsets inside the 0x%X aperture" % (sid, size), not bad, repr(bad))
+        dup = [o for o in set(sc.ctrl.values())
+               if list(sc.ctrl.values()).count(o) > 1]
+        check("%s: no offset used twice" % sid, not dup, repr(dup))
+
+    print("== 4. the 64-bit PC, tear-free and as a hex string ==")
+    sc = cat.by_id["rocket64"]
+    regs = {0x04: (1 << 12) | (0b101 << 8),      # STATUS: priv=1 (S), obs=101
+            0x3C: 0, 0x40: 0, 0x44: 0,
+            0x4C: 0x80200ABC, 0x50: 0xFFFFFFFF, 0x54: 4711}
+    r = server.read_core_pc(FakeBus(regs), sc)
+    check("the PC is a hex string", isinstance(r["pc"], str), repr(r["pc"]))
+    check("PC = 0xffffffff80200abc", r["pc"] == "0xffffffff80200abc", r["pc"])
+    check("the PC does NOT survive Python->JSON->float as a number (hence a string)",
+          float(int(r["pc"], 16)) != int(r["pc"], 16))
+    check("the retire counter is passed through", r.get("retires") == 4711, repr(r.get("retires")))
+    check("privilege level from STATUS[14:12]", r.get("priv") == 1, repr(r.get("priv")))
+    check("observation sticky named", r.get("obs") == ["retire_seen", "rvalid_seen"],
+          repr(r.get("obs")))
+    check("no tear reported when there was none", r.get("torn") is False)
+    torn = server.read_core_pc(FakeBus(regs, tear_at=0x4C), sc)
+    check("a tear between LO and HI is detected and retried",
+          torn.get("torn") is True, repr(torn))
+    check("after the tear it was read again", torn.get("retries", 0) >= 1,
+          repr(torn.get("retries")))
+    check("after the tear the pair is consistent (HI came from the second try)",
+          torn.get("stable") is True and int(torn["pc"], 16) == 0x0_00000000,
+          torn["pc"])
+    check("a torn PC stays representable at 64 bit",
+          int(torn["pc"], 16) < (1 << 64))
+    # Counter-check: a design without an observation channel returns None, not 0.
+    check("a design without core_pc returns None instead of 0x0",
+          server.read_core_pc(FakeBus({}), cat.by_id["cva6_linux64"]) is None)
+
+    print("== 5. ELF64 load: guest->PS translation ==")
+    payload = ROOT / "bld" / "l2_rocket_linux" / "fw_payload.elf"
+    if not payload.is_file():
+        skip("ELF64 load: guest->PS translation",
+             "%s is the predecessor repository build artifact, not part of this example"
+             % payload)
+    else:
+        data = payload.read_bytes()
+        segs = list(server.parse_elf(data))
+        check("ELF64 recognised", server.elf_class(data) == "ELF64")
+        guest, ps, win = 0x80000000, 0x64000000, 0x0C000000
+        core = cat.by_id["rocket64"].cores[0]
+        check("the scenario names guest 0x8000_0000",
+              int(core["load_guest_base"], 0) == guest, core["load_guest_base"])
+        check("the scenario names PS 0x6400_0000", int(core["load_base"], 0) == ps)
+        check("the scenario names a 192 MiB window", int(core["load_size"], 0) == win)
+        inwin = all(guest <= a and a + len(s) <= guest + win for a, s in segs)
+        check("all segments lie inside the guest window", inwin,
+              "first: 0x%x" % segs[0][0])
+        xlat = [(a - guest + ps) for a, _s in segs]
+        check("translated PS addresses inside the reserved window",
+              all(server.HwBus.PL_WIN_LO <= a < server.HwBus.PL_WIN_HI for a in xlat),
+              ", ".join("0x%x" % a for a in xlat))
+        # Counter-check: the UNtranslated guest address would break the bound.
+        check("counter-check -- untranslated it would be outside (the bound bites)",
+              not (server.HwBus.PL_WIN_LO <= segs[0][0] < server.HwBus.PL_WIN_HI),
+              "0x%x" % segs[0][0])
+
+    print("== 6. an Sv39 address through the WHOLE display chain ==")
+    # Do not read the regexes, push a real 64-bit address through them:
+    # objdump listing -> dis_to_symbols -> SymbolTable -> func_counts ->
+    # coverage_tree -> JSON. Exactly the path the coverage map takes.
+    dis = ROOT / "bld" / "b1_dashboard_rv64" / "hi64.dis"
+    elf = ROOT / "sw" / "cva6_char" / "char_test_hi64.elf"
+    symmap = ROOT / "bld" / "b1_dashboard_rv64" / "hi64_symbols.map"
+    if not (dis.is_file() and symmap.is_file()):
+        # Generate it instead of skipping the section: a gate that silently
+        # checks less on a fresh tree is not a gate -- but that only holds if
+        # the raw materials (toolchain + fixture ELF) are THERE. If they are
+        # not (no RISC-V toolchain, or the ELF fixture is a
+        # predecessor-repository characterisation artefact that is not part of
+        # this example), SKIP is the honest answer, not FAIL.
+        objdump = find_riscv_tool("riscv64-unknown-elf-objdump",
+                                   "riscv32-unknown-elf-objdump")
+        if objdump is not None and elf.is_file():
+            # (no local `import subprocess` any more -- it made the name local to
+            # the WHOLE function and let every later use die with an
+            # UnboundLocalError whenever this branch did not run)
+            dis.parent.mkdir(parents=True, exist_ok=True)
+            dis.write_text(subprocess.run([str(objdump), "-d", str(elf)],
+                                          capture_output=True, text=True,
+                                          check=True).stdout, encoding="utf-8")
+            subprocess.run([sys.executable, str(HERE / "dis_to_symbols.py"), str(dis),
+                            "-o", str(symmap),
+                            "--sites", str(symmap.with_name("hi64_sites.map"))],
+                           capture_output=True, check=True)
+    if not dis.is_file():
+        if not elf.is_file():
+            skip("an Sv39 address through the WHOLE display chain",
+                 "%s is the predecessor repository characterization artifact, not part "
+                 "of this example" % elf)
+        else:
+            skip("an Sv39 address through the WHOLE display chain",
+                 "no RISC-V objdump found (set RISCV_BIN or put "
+                 "riscv64-unknown-elf-objdump on PATH) to generate %s "
+                 "from %s" % (dis, elf))
+    else:
+        import json as _json
+        import insight
+        st = insight.SymbolTable.from_file(symmap)
+        check("symbol table read", st.count >= 10, "%d symbols" % st.count)
+        hi = [a for a in st.addrs if a > 0xFFFFFFFF]
+        check("addresses above 2**32 survive the parsing",
+              len(hi) == st.count, "%d of %d" % (len(hi), st.count))
+        check("the lookup hits the Sv39 address",
+              st.lookup(0xFFFFFFC064000000)[0] == "_start",
+              repr(st.lookup(0xFFFFFFC064000000)[0]))
+        # Coverage tree with exactly those symbols, in a scenario whose
+        # code_regions cover the Sv39 range.
+        sc64 = cat.by_id["cva6_linux64"]
+        old_sym, old_cnt = server.INS.symbols, dict(server.INS.func_counts)
+        server.INS.symbols = st
+        server.INS.func_counts = {0xFFFFFFC064000000: 17}
+        region = {"name": "hi64", "base": "0xFFFFFFC064000000", "size": "0x00010000"}
+        sc64.raw.setdefault("_gate_regions", None)
+        saved = sc64.raw.get("code_regions")
+        sc64.raw["code_regions"] = [region]
+        tree = server.coverage_tree(sc64)
+        sc64.raw["code_regions"] = saved
+        server.INS.symbols, server.INS.func_counts = old_sym, old_cnt
+        funcs = [f for r in tree["regions"] for g in r["groups"] for f in g["funcs"]]
+        check("the coverage tree contains the Sv39 symbols", len(funcs) >= 10,
+              "%d functions" % len(funcs))
+        start = next((f for f in funcs if f["name"] == "_start"), None)
+        check("_start is in the tree", start is not None)
+        if start:
+            check("addr is a hex string", isinstance(start["addr"], str),
+                  repr(start["addr"]))
+            check("addr is exactly 0xffffffc064000000",
+                  int(start["addr"], 16) == 0xFFFFFFC064000000, start["addr"])
+            check("the execution count hangs on the right address",
+                  start["instr"] == 17, repr(start["instr"]))
+            # Counter-check: as a JSON NUMBER the same value would be rounded in
+            # the browser -- here with the address that has low bits.
+            probe = 0xFFFFFFC06400002C          # 'outer'
+            check("counter-check -- the same address as a float loses bits",
+                  int(float(probe)) != probe, hex(int(float(probe))))
+        # And the silent drop there used to be: with a 32-bit region ALL Sv39
+        # symbols MUST fall out -- and that has to be reported.
+        server.INS.symbols = st
+        server.INS.func_counts = {}
+        saved = sc64.raw.get("code_regions")
+        sc64.raw["code_regions"] = [{"name": "4 GiB only", "base": "0x0",
+                                     "size": "0xFFFFFFFF"}]
+        tree32 = server.coverage_tree(sc64)
+        sc64.raw["code_regions"] = saved
+        server.INS.symbols, server.INS.func_counts = old_sym, old_cnt
+        check("a 32-bit region lets the Sv39 symbols fall out",
+              not tree32["regions"], repr([r["name"] for r in tree32["regions"]]))
+        check("...and that is counted instead of concealed",
+              tree32.get("outside_regions") == st.count,
+              "outside_regions=%r of %d" % (tree32.get("outside_regions"), st.count))
+        _json.dumps(tree)      # must stay serializable
+
+    print("== 7. a scenario change inherits no foreign symbol table ==")
+    # Measured on the running server (2026-08-08): after cva6_linux ->
+    # cva6_linux64 the RV32 table with 83,074 symbols was still hanging in the
+    # process and the coverage map showed 41,911 RV32 functions under the RV64
+    # region names. Plausible and wrong -- hence a guard.
+    import insight
+    keep = server.INS.symbols
+    fake = insight.SymbolTable.from_text(
+        "64000000 T sbi_init\n64000100 T fdt_next_tag\n", "gate")
+    server.INS.symbols = fake
+    check("precondition: table loaded", server.INS.symbols.count == 2)
+    got = server.load_symbol_files(cat.by_id["cva6_linux64"])
+    check("a scenario without its own symbols reports 0", got["symbols"] == 0, repr(got))
+    check("...and the old table is GONE (not inherited)",
+          server.INS.symbols.count == 0, "%d symbols left" % server.INS.symbols.count)
+    check("...the call sites too", server.INS.sites.count == 0)
+    # Counter-check: a scenario WITH a file still loads.
+    server.INS.symbols = fake
+    demo_map = HERE / "demo" / "symbols_sbi.map"
+    if demo_map.is_file():
+        got2 = server.load_symbol_files(cat.by_id["cva6_linux"])
+        check("counter-check -- a scenario with a file still loads",
+              got2["symbols"] > 100, "%d symbols" % got2["symbols"])
+    else:
+        check("counter-check -- demo/symbols_sbi.map present", False, str(demo_map))
+    server.INS.symbols = keep
+
+    # --- soc offsets: is the scenario map complete? -------------------------
+    # The soc.* registers in regmap.json are appended BY HAND (gen_regmap.py)
+    # and carry the offsets of mbv_soc_top.sv. For every other SoC they are
+    # wrong: the two-hart Rocket has two more console registers, so everything
+    # from SINK_CTRL on sits one slot higher. On 2026-08-10 the board
+    # therefore showed eight registers under a foreign name -- "SINK_STAT
+    # 0xAC" was the write pointer with 172 bytes. That was found in the field,
+    # not by this gate.
+    #
+    # The user interface corrects this at runtime from the scenario map
+    # (fixSocOffsets/ctrlOff). That only carries as long as the map REALLY has
+    # the entries -- if one is missing, the display falls back silently to the
+    # MBV value and the write path refuses. Exactly that is what this gate
+    # checks.
+    SINK_KEYS = ("sink_ctrl", "ddr_base", "ddr_size",
+                 "ddr_wptr", "sink_stat", "ddr_drops")
+    for sc in cat.by_id.values():
+        sinks = sc.raw.get("sinks") or {}
+        if not (sinks.get("ddr") or sinks.get("pib")):
+            continue                    # without DDR/PIB the UI touches none of this
+        cmap = sc.raw.get("ctrl") or {}
+        cmap = cmap.get("regs", cmap)
+        missing = [k for k in SINK_KEYS if k not in cmap]
+        check("scenario %s -- soc offsets complete" % sc.id,
+              not missing,
+              "missing: " + ", ".join(missing) if missing else
+              "all %d" % len(SINK_KEYS))
+
+    # Counter-check: a deliberately removed entry MUST colour it red.
+    _probe = dict(cat.by_id["rocket2"].raw.get("ctrl") or {})
+    _probe.pop("sink_ctrl", None)
+    check("counter-check -- a missing soc offset is detected",
+          "sink_ctrl" not in _probe and
+          [k for k in SINK_KEYS if k not in _probe] != [],
+          "the probe reports %d missing" % len([k for k in SINK_KEYS if k not in _probe]))
+
+    # --- RDL mirror against the master --------------------------------------
+    # The same class of defect as the CTRL map above, one level deeper: the
+    # mirror under third_party/CTTE/rdl/ reports no error when it goes
+    # stale -- it delivers plausible wrong DESCRIPTIONS. On 2026-08-10 it was
+    # 365 lines old and the dashboard showed "[CTTE]" while the master had
+    # long since moved to CTTE. That was found in the field, not by a check.
+    # Without a reachable master this is SKIPPED, not reported green: a SKIP
+    # is not a PASS (lesson from package V2).
+    #
+    # In THIS repository (TraceEncoder instead of the predecessor repository)
+    # the mirror was dropped by plan anyway (plan AP4 point 5: the RDL mirror
+    # problem together with sync_rdl_mirror.py goes away without replacement
+    # -- regmap.json is generated directly from rdl/). A missing
+    # scripts/sync_rdl_mirror.py is therefore the EXPECTED state here, not a
+    # finding -- SKIP, not
+    # FAIL.
+    sync = HERE.parents[1] / "scripts" / "sync_rdl_mirror.py"
+    if sync.is_file():
+        r = subprocess.run([sys.executable, str(sync), "--check"],
+                           capture_output=True, text=True)
+        if r.returncode == 2:
+            print("  SKIP  RDL mirror -- master not reachable "
+                  "(set CTTE_MASTER)")
+        else:
+            check("RDL mirror + regmap.json agree with the master",
+                  r.returncode == 0,
+                  (r.stdout or r.stderr).strip().splitlines()[0]
+                  if (r.stdout or r.stderr).strip() else "")
+    else:
+        skip("RDL mirror against the master",
+             "scripts/sync_rdl_mirror.py is retired in this repository "
+             "(plan AP4 point 5) -- regmap.json is generated from rdl/ "
+             "directly, there is no separate mirror to drift")
+
+    print()
+    if FAILS:
+        print("GATE B1-3: FAIL (%d of %d checks red)" % (len(FAILS), NCHECK))
+        for f in FAILS:
+            print("  - %s" % f)
+        return 1
+    if SKIPS:
+        print("GATE B1-3: PASS -- %d checks green, %d sections SKIPped "
+              "(no RISC-V toolchain and/or KV260 RTL tree -- neither is "
+              "part of this example, see README.md)"
+              % (NCHECK, len(SKIPS)))
+        return 0
+    print("GATE B1-3: PASS -- %d checks green" % NCHECK)
+    return 0
+
+
+if __name__ == "__main__":
+    sys.exit(main())
diff --git a/examples/dashboard/test_wp_view.py b/examples/dashboard/test_wp_view.py
new file mode 100644
index 0000000..359a440
--- /dev/null
+++ b/examples/dashboard/test_wp_view.py
@@ -0,0 +1,2543 @@
+#!/usr/bin/env python3
+# SPDX-FileCopyrightText: 2026 Accemic Technologies GmbH
+# SPDX-License-Identifier: ISC
+"""Gate H (offline): the AXIS watchpoint view without a board.
+
+Checks what is checkable without /dev/mem:
+  * scenario `tgc5b2_axis_wp` loads, all wp offsets lie inside their
+    aperture, the map matches the SPEC (docs/SPEC_axis_wp_memory_map).
+  * the wp_set symbol table loads from the repository path (PC -> name).
+  * the demo generator is DETERMINISTIC: two fresh states deliver the same
+    (core, pc, slot, ts) sequence.
+  * records_json/status_json have the shape wp.html consumes.
+  * the load_table safety contract: core_run=1 -> CONFLICT (handler: 409);
+    trTeControl.Active=1 -> CONFLICT; otherwise writes to ENCx+0x4100+8i with
+    a slot 0 readback (counter-check: the rejection MUST come, otherwise the
+    protection would be decoration).
+  * regression: DemoBus can be instantiated for EVERY scenario and
+    build_poll only delivers regions that exist (the existing scenarios stay
+    loadable).
+  * U2: indexed register instances sit under ONE collapsed parent node. What
+    is checked is the SHIPPED JS code -- groupRegRows/grpNode/
+    renderRegGroups are cut out of index.html and executed against a DOM
+    stub (needs `node`; without node the guard reports RED instead of
+    skipping).
+
+Invocation:  py tools/ctrace_dashboard/test_wp_view.py
+"""
+import sys
+from pathlib import Path
+
+HERE = Path(__file__).resolve().parent
+sys.path.insert(0, str(HERE))
+
+import server                       # noqa: E402
+import wp_view                      # noqa: E402
+from scenario import Catalog        # noqa: E402
+
+FAILS = []
+NCHECK = 0
+SKIPS = []
+
+
+def check(name, ok, info=""):
+    global NCHECK
+    NCHECK += 1
+    print("  %-4s %s%s" % ("OK" if ok else "FAIL", name,
+                           ("  " + info) if info else ""))
+    if not ok:
+        FAILS.append(name + ((" -- " + info) if info else ""))
+    return ok
+
+
+def skip(name, reason):
+    """Record a clean skip -- distinct from FAILS, never turns the gate red."""
+    SKIPS.append(name + ((" -- " + reason) if reason else ""))
+    print("  SKIP %s%s" % (name, ("  " + reason) if reason else ""))
+
+
+class FakeBus:
+    """read/write mock in the dashboard bus format ({region: {off: val}})."""
+
+    demo = False
+
+    def __init__(self, init=None):
+        self.mem = {}
+        for region, vals in (init or {}).items():
+            self.mem[region] = dict(vals)
+
+    def read(self, region, off, n=1):
+        m = self.mem.setdefault(region, {})
+        return [m.get(off + 4 * i, 0) for i in range(n)]
+
+    def write(self, region, off, value):
+        self.mem.setdefault(region, {})[off] = value & 0xFFFFFFFF
+
+
+# --- the shipped grouping code, against a DOM mock --------------------------
+# Modelled on test_addr64.mjs: what gets checked is what the browser receives
+# -- groupRegRows/grpNode/renderRegGroups are CUT OUT of index.html and
+# executed. A reimplementation in Python would be a lie after the first edit to
+# index.html; the Python mirror in test_block_csrs.py is therefore reconciled
+# against exactly this run below.
+# The mock cannot parse HTML -- and it does not need to: grpNode() fetches its
+# two containers through querySelector('.ghead'/'.gbody'), and those are
+# exactly what the mock returns (stable per selector), together with classList
+# and appendChild. That makes the TREE STRUCTURE checkable (parent node ->
+# instance node -> rows) without a jsdom dependency.
+JS_GROUP_PROBE = r"""
+import {readFileSync} from 'node:fs';
+const [IDX, RMP, EDGEJSON] = process.argv.slice(2);
+const HTML = readFileSync(IDX, 'utf8').replace(/\r\n/g, '\n');
+const RES = [];
+/* Keep the info texts to ASCII: the output goes through a Windows console
+   in cp1252, and a caret glyph out of the innerHTML would abort the test run
+   with a UnicodeEncodeError instead of judging it. */
+const ck = (n, ok, info) => RES.push({name: n, ok: !!ok,
+  info: info === undefined ? '' : String(info).replace(/[^\x20-\x7e]/g, '.')
+                                              .slice(0, 160)});
+function fn(name){
+  const s = HTML.indexOf('function ' + name + '(');
+  if (s < 0) throw new Error('function ' + name + '() is missing from index.html');
+  const e = HTML.indexOf('\n}\n', s);
+  if (e < 0) throw new Error('end of ' + name + '() not found');
+  return HTML.slice(s, e + 2);
+}
+function cst(name){
+  const m = new RegExp('^const ' + name + '=.*$', 'm').exec(HTML);
+  if (!m) throw new Error('const ' + name + ' is missing from index.html');
+  return m[0];
+}
+class El{
+  constructor(tag){this.tag=tag;this._c=new Set();this._h='';this.kids=[];this._q={};}
+  set className(v){this._c=new Set(String(v).split(/\s+/).filter(Boolean));}
+  get className(){return [...this._c].join(' ');}
+  get classList(){const s=this._c;return{
+    add:c=>s.add(c), remove:c=>s.delete(c), contains:c=>s.has(c),
+    toggle:c=>{if(s.has(c)){s.delete(c);return false;} s.add(c);return true;}};}
+  set innerHTML(h){this._h=String(h);} get innerHTML(){return this._h;}
+  appendChild(c){this.kids.push(c);return c;}
+  querySelector(sel){return this._q[sel]||(this._q[sel]=new El(sel));}
+}
+try{
+  const src = [cst('esc'), cst('REGGRP_OPEN'), cst('ARRIDX'),
+               fn('groupRegRows'), fn('grpNode'), fn('renderRegGroups')].join('\n');
+  const api = new Function('document', src +
+    '\nreturn {groupRegRows, grpNode, renderRegGroups, REGGRP_OPEN};')(
+      {createElement: t => new El(t)});
+  const regs = JSON.parse(readFileSync(RMP, 'utf8')).regs;
+  const paths = regs.map(r => r.path);
+  const mk = ls => ls.map(l => ({label: l, el: {row: l}}));
+  const flat = ns => {const o=[]; for(const n of ns){ if(n.leaf){o.push(n.leaf.label);}
+    else{for(const i of n.group.idxs)for(const it of n.group.insts.get(i))o.push(it.label);} } return o;};
+  const nodes = api.groupRegRows(mk(paths));
+  const fil = nodes.filter(n => n.group).map(n => n.group)
+                   .find(g => g.prefix.endsWith('trTeFilter'));
+  ck('JS: parent node ct_cs_cpuif.te.trTeFilter[0..15] built',
+     fil && fil.label === 'ct_cs_cpuif.te.trTeFilter[0..15]', fil ? fil.label : 'none');
+  ck('JS: 16 instances / 112 registers under the node',
+     fil && fil.insts.size === 16 && fil.n === 112,
+     fil ? fil.insts.size + '/' + fil.n : '-');
+  ck('JS: no register lost (expanded content == input)',
+     JSON.stringify(flat(nodes)) === JSON.stringify(paths),
+     flat(nodes).length + ' of ' + paths.length);
+  ck('JS: non-array registers stay flat rows',
+     nodes.filter(n => n.leaf).length === paths.filter(p => !p.includes('[')).length,
+     nodes.filter(n => n.leaf).length + ' leaves');
+
+  const list = new El('div');
+  api.renderRegGroups(list, mk(paths), 'all', false);
+  ck('DOM: the register card shows 56 nodes instead of 258', list.kids.length === 56,
+     String(list.kids.length));
+  const gel = list.kids.find(k => (k.innerHTML||'').includes('trTeFilter[0..15]'));
+  ck('DOM: parent node present and COLLAPSED (default)',
+     gel && !gel.classList.contains('open'), gel ? gel.className : 'missing');
+  const gb = gel.querySelector('.gbody');
+  ck('DOM: expanding shows 16 instance nodes', gb.kids.length === 16, String(gb.kids.length));
+  const nrows = gb.kids.reduce((a, k) => a + k.querySelector('.gbody').kids.length, 0);
+  ck('DOM: the instance nodes together carry 112 register rows', nrows === 112, String(nrows));
+  ck('DOM: the header names the instance and register count',
+     /16 instances/.test(gel.innerHTML) && /112 registers/.test(gel.innerHTML),
+     gel.innerHTML.replace(/\s+/g, ' ').slice(0, 120));
+  ck('DOM: instance node is named ct_cs_cpuif.te.trTeFilter[3]',
+     gb.kids[3].innerHTML.includes('ct_cs_cpuif.te.trTeFilter[3]'),
+     gb.kids[3].innerHTML.replace(/\s+/g, ' ').slice(0, 90));
+
+  const l2 = new El('div');
+  api.renderRegGroups(l2, mk(paths.filter(p => p.includes('trTeFilter'))), 'all', true);
+  ck('DOM: a search expands the group (otherwise the filter counts invisible rows)',
+     l2.kids[0].classList.contains('open'), l2.kids[0].className);
+  ck('DOM: a search expands the instance nodes too',
+     l2.kids[0].querySelector('.gbody').kids.every(k => k.classList.contains('open')));
+
+  const l3 = new El('div');
+  api.renderRegGroups(l3, mk(paths), 'all', false);
+  l3.kids.find(k => (k.innerHTML||'').includes('trTeFilter[0..15]'))
+    .querySelector('.ghead').onclick({stopPropagation(){}});
+  ck('state: a click records the node in the client',
+     api.REGGRP_OPEN['all:ct_cs_cpuif.te.trTeFilter'] === true,
+     JSON.stringify(Object.keys(api.REGGRP_OPEN)));
+  const l4 = new El('div');
+  api.renderRegGroups(l4, mk(paths), 'all', false);
+  ck('state: a redraw keeps the expansion',
+     l4.kids.find(k => (k.innerHTML||'').includes('trTeFilter[0..15]')).classList.contains('open'));
+  const l5 = new El('div');
+  api.renderRegGroups(l5, mk(paths), 'panel:filters', false);
+  ck('state: the panel has a namespace of its OWN (stays closed)',
+     !l5.kids.find(k => (k.innerHTML||'').includes('trTeFilter[0..15]')).classList.contains('open'));
+
+  const gapItems = mk(['f[0].A', 'f[1].A', 'f[5].A', 'f[5].B']);
+  const gp = api.groupRegRows(gapItems);
+  ck('gap: ONE node f[0..5] instead of sub-ranges',
+     gp.length === 1 && gp[0].group.label === 'f[0..5]',
+     gp.map(n => n.leaf ? n.leaf.label : n.group.label).join(','));
+  const l6 = new El('div');
+  api.renderRegGroups(l6, gapItems, 'x', false);
+  ck('gap: the header names the missing indices',
+     /not contiguous \(missing 2, 3, 4\)/.test(l6.kids[0].innerHTML),
+     l6.kids[0].innerHTML.replace(/\s+/g, ' ').slice(0, 130));
+  const one = api.groupRegRows(mk(['x[0].A', 'x[0].B', 'y']));
+  ck('a single instance stays flat (no click without gain)',
+     one.length === 3 && one.every(n => n.leaf));
+  const l7 = new El('div');
+  api.renderRegGroups(l7, mk(['y[0].A', 'y[1].A']), 'x', false);
+  ck('an instance with ONE register skips the second level',
+     l7.kids[0].querySelector('.gbody').kids.length === 2
+     && l7.kids[0].querySelector('.gbody').kids.every(k => k.row));
+
+  /* The mirror comparison runs over the real register list PLUS edge
+     cases: the real card only knows rows with three or more instances, so a
+     two-instance row or a gap would not occur in it at all -- the comparison
+     would be blind to exactly those rules that are easiest to get wrong
+     (measured: the mutation "threshold 2 -> 3" stayed undetected without the
+     edge cases). */
+  const edge = JSON.parse(EDGEJSON || '[]');
+  const summary = api.groupRegRows(mk(paths.concat(edge))).map(n => n.leaf
+    ? {kind: 'leaf', label: n.leaf.label}
+    : {kind: 'group', label: n.group.label, prefix: n.group.prefix,
+       insts: n.group.insts.size, n: n.group.n, gaps: n.group.gaps});
+  console.log('U2SUMMARY ' + JSON.stringify(summary));
+}catch(e){
+  ck('the grouping code from index.html is executable', false, e.message);
+}
+console.log('U2RESULT ' + JSON.stringify(RES));
+"""
+
+
+# --- the SHIPPED display logic, against real fields from regmap.json --------
+# The same construction as the probe above and for the same reason: a
+# reimplementation in Python would be a lie after the first edit to
+# index.html. What gets checked are the four functions the access truth in
+# the browser hangs on -- badge, gate state and the run state per core.
+JS_U4_PROBE = r"""
+import {readFileSync} from 'node:fs';
+const [IDX, RMP] = process.argv.slice(2);
+const HTML = readFileSync(IDX, 'utf8').replace(/\r\n/g, '\n');
+const RES = [];
+const ck = (n, ok, info) => RES.push({name: n, ok: !!ok,
+  info: info === undefined ? '' : String(info).replace(/[^\x20-\x7e]/g, '.')
+                                              .slice(0, 160)});
+function fn(name){
+  const s = HTML.indexOf('function ' + name + '(');
+  if (s < 0) throw new Error('function ' + name + '() is missing from index.html');
+  const e = HTML.indexOf('\n}\n', s);
+  if (e < 0) throw new Error('end of ' + name + '() not found');
+  return HTML.slice(s, e + 2);
+}
+try{
+  const STATE = {control: 0, status: 0, trTeControl: 0, trTeControl1: 0,
+                 trTeControl2: 0};
+  const SCEN = {control_bits: {core_run: 0, core0_run: 8, core1_run: 9},
+                status_bits: {core0_running: 8, core1_running: 9},
+                cores: [{id: 0, run_bit: 'core0_run', run_bits: ['core_run','core0_run']},
+                        {id: 1, run_bit: 'core1_run', run_bits: ['core_run','core1_run']}]};
+  const api = new Function('STATE', 'SCEN',
+    [fn('accBadge'), fn('teEnabledOf'), fn('runningBitName'),
+     fn('coreRunControl'), fn('coreRunStatus'), fn('coreRunning')].join('\n') +
+    '\nreturn {accBadge, teEnabledOf, runningBitName, coreRunControl,' +
+    ' coreRunStatus, coreRunning};')(STATE, SCEN);
+
+  /* --- badge: real fields from regmap.json, no invented example -------- */
+  const RM = JSON.parse(readFileSync(RMP, 'utf8'));
+  const fieldOf = (path, name) => {
+    const r = RM.regs.find(r => r.path.endsWith(path));
+    return r && r.fields.find(f => f.name === name);
+  };
+  const b = (path, name) => api.accBadge(fieldOf(path, name));
+  ck('badge: a locked field says Enable=0 (not "rw")',
+     b('te.trTeControl','InstMode').txt === 'rw (Enable=0)',
+     b('te.trTeControl','InstMode').txt);
+  ck('badge: a W1C bit says w1c (RMW would clear it unnoticed otherwise)',
+     b('te.trTeControl','InstStallOrOverflow').cls === 'w1c' &&
+     b('te.trTeControl','InstStallOrOverflow').txt.indexOf('w1c') >= 0,
+     b('te.trTeControl','InstStallOrOverflow').txt);
+  ck('badge: a pulse bit says w1 pulse (always reads 0)',
+     b('te.trTeControl','InstSyncReq').txt === 'w1 pulse',
+     b('te.trTeControl','InstSyncReq').txt);
+  ck('badge: a read side effect is marked',
+     b('trWpReadHigh','Cmd').txt.indexOf('side-eff') >= 0,
+     b('trWpReadHigh','Cmd').txt);
+  ck('badge: a truly free field stays green rw',
+     b('te.trTeTipFifoStatus','trTeTipFifoMaxFillClear').cls === 'rw',
+     b('te.trTeTipFifoStatus','trTeTipFifoMaxFillClear').txt);
+  ck('badge: a read-only field stays r',
+     b('te.trTeImpl','VerMajor').txt === 'r' &&
+     b('te.trTeImpl','VerMajor').cls === 'r',
+     b('te.trTeImpl','VerMajor').txt);
+  ck('counter-check: locked beats free (the colour is a warning, not green)',
+     b('te.trTeControl','InstMode').cls === 'gated');
+
+  /* --- gate state per region --- */
+  STATE.trTeControl = 0x2; STATE.trTeControl1 = 0x0;
+  ck('teEnabledOf: enc locked, enc1 open (per region, not global)',
+     api.teEnabledOf('enc') === true && api.teEnabledOf('enc1') === false);
+
+  /* --- run state per core (b0 | b(8+i)) --- */
+  const set = (c, s) => {STATE.control = c; STATE.status = s;};
+  set(0x1, 0x300);
+  ck('b0 lets BOTH cores run',
+     api.coreRunning(SCEN.cores[0]) && api.coreRunning(SCEN.cores[1]));
+  set(0x200, 0x200);
+  ck('b9 alone: only core 1 runs',
+     !api.coreRunning(SCEN.cores[0]) && api.coreRunning(SCEN.cores[1]));
+  set(0x0, 0x0);
+  ck('nothing set: both are halted',
+     !api.coreRunning(SCEN.cores[0]) && !api.coreRunning(SCEN.cores[1]));
+  set(0x100, 0x0);          // bitstream without the mirror: it does not follow
+  ck('bitstream without a mirror: CONTROL decides (core 0 runs)',
+     api.coreRunning(SCEN.cores[0]) === true);
+  ck('runningBitName: core1_run -> core1_running',
+     api.runningBitName(SCEN.cores[1]) === 'core1_running');
+  ck('runningBitName: cva6_run -> cva6_running (b5/b10 share the mirror)',
+     api.runningBitName({run_bit: 'cva6_run'}) === 'cva6_running');
+}catch(e){
+  ck('the U4 display logic from index.html is executable', false, e.message);
+}
+console.log('U4RESULT ' + JSON.stringify(RES));
+"""
+
+
+# --- the bpi source and the empty graph, from the SHIPPED code --------------
+# The same construction as the probes above. Two things have to hold here and
+# neither of them can be reimplemented in Python without lying:
+#   * bpiPoint() picks the source -- the hardware retire counter where one
+#     exists, otherwise the decoded window, and there the decode figure
+#     (denominator over ALL sources) rather than the single-target figure
+#     next to it.
+#   * drawSpark() draws into a canvas; what a context mock checks is WHICH
+#     texts it sets. An empty graph without a reason was exactly the
+#     reported finding.
+JS_U5_PROBE = r"""
+import {readFileSync} from 'node:fs';
+const [IDX] = process.argv.slice(2);
+const HTML = readFileSync(IDX, 'utf8').replace(/\r\n/g, '\n');
+const RES = [];
+const ck = (n, ok, info) => RES.push({name: n, ok: !!ok,
+  info: info === undefined ? '' : String(info).replace(/[^\x20-\x7e]/g, '.')
+                                              .slice(0, 160)});
+function fn(name){
+  const s = HTML.indexOf('function ' + name + '(');
+  if (s < 0) throw new Error('function ' + name + '() is missing from index.html');
+  const e = HTML.indexOf('\n}\n', s);
+  if (e < 0) throw new Error('end of ' + name + '() not found');
+  return HTML.slice(s, e + 2);
+}
+try{
+  /* --- source selection: bpiPoint() -------------------------------------- */
+  let SCEN = {ctrl: {control: 0, trace_bytes: 12, retires: 0x44}};
+  const mk = () => new Function('SCEN',
+    [fn('hasRetireCounter'), fn('bpiPoint')].join('\n') +
+    '\nreturn {hasRetireCounter, bpiPoint};')(SCEN);
+  let api = mk();
+  const ON = {trTeControl: 1}, OFF = {trTeControl: 0};
+  ck('a scenario WITH a retire counter is recognised', api.hasRetireCounter() === true);
+  ck('hardware path: 800 bit over 100 instructions = 8.0 bpi',
+     api.bpiPoint(ON, 1100, 1100, {r: 1000, b: 1000}, null) === 8,
+     api.bpiPoint(ON, 1100, 1100, {r: 1000, b: 1000}, null));
+  ck('hardware path: no value without a reference point (not 0)',
+     api.bpiPoint(ON, 1100, 1100, null, null) === null);
+  ck('hardware path: no retires -> null instead of 0 (0 would look like '
+     + 'perfect compression)',
+     api.bpiPoint(ON, 1000, 1100, {r: 1000, b: 1000}, null) === null);
+  ck('the hardware path: encoder OFF -> null (instructions without bytes)',
+     api.bpiPoint(OFF, 1100, 1100, {r: 1000, b: 1000}, null) === null);
+  ck('the hardware path wins: a decoded window is NOT taken when there '
+     + 'are counters',
+     api.bpiPoint(ON, 1000, 1100, {r: 1000, b: 1000},
+                  {ok: true, decode: {ok: true, bits_per_instr: 4.9}}) === null);
+
+  /* --- SoC WITHOUT a retire counter (tgc5b2): the decoded window ------- */
+  SCEN = {ctrl: {control: 0, trace_bytes: 12}};   // no 'retires'
+  api = mk();
+  const LIVE_OK = {ok: true, bits_per_instr: 9.81,
+                   decode: {ok: true, bits_per_instr: 4.907}};
+  ck('a scenario WITHOUT a retire counter is recognised', api.hasRetireCounter() === false);
+  ck('the fallback source delivers the value of the decoded window',
+     api.bpiPoint(ON, 0, 0, null, LIVE_OK) === 4.907,
+     api.bpiPoint(ON, 0, 0, null, LIVE_OK));
+  ck('the fallback source takes the decode number (denominator over ALL '
+     + 'sources), NOT the single-target number beside it',
+     api.bpiPoint(ON, 0, 0, null, LIVE_OK) !== LIVE_OK.bits_per_instr);
+  ck('fallback source: failed decode -> null',
+     api.bpiPoint(ON, 0, 0, null,
+                  {ok: true, decode: {ok: false, bits_per_instr: 4.9}}) === null);
+  ck('fallback source: no window yet -> null',
+     api.bpiPoint(ON, 0, 0, null, null) === null);
+  ck('fallback source: encoder OFF -> null',
+     api.bpiPoint(OFF, 0, 0, null, LIVE_OK) === null);
+
+  /* --- the empty graph names its reason (drawSpark) ---------------------- */
+  const texts = [];
+  const ctx = new Proxy({}, {get: (t, k) => {
+    if (k === 'fillText') return (s) => texts.push(String(s));
+    if (k === 'measureText') return () => ({width: 10});
+    if (k === 'canvas') return {};
+    return (typeof k === 'string' && /^(font|fillStyle|strokeStyle|lineWidth|textAlign|textBaseline)$/.test(k))
+      ? '' : (() => {});
+  }, set: () => true});
+  const canvas = {width: 300, height: 60,
+                  getBoundingClientRect: () => ({width: 300, height: 60}),
+                  getContext: () => ctx};
+  const env = {
+    $: (id) => (id === 'spark' ? canvas : null),
+    getComputedStyle: () => ({getPropertyValue: () => ''}),
+    document: {documentElement: {}},
+    pollMs: 1000, WINS: 30,
+    STATE: {trTeControl: 1, control: 1},
+    SCEN: {ctrl: {control: 0}, cores: [{id: 0, run_bit: 'core0_run',
+                                        run_bits: ['core_run', 'core0_run']}],
+           control_bits: {core_run: 0, core0_run: 8}, status_bits: {}},
+    LIVE: null, BPI: [], BPIMAX: [],
+  };
+  const names = Object.keys(env);
+  const mkSpark = (over) => {
+    const e = Object.assign({}, env, over || {});
+    return new Function(...names,
+      [fn('hasRetireCounter'), fn('runningBitName'), fn('coreRunControl'),
+       fn('coreRunStatus'), fn('coreRunning'), fn('drawSpark')].join('\n') +
+      '\nreturn drawSpark;')(...names.map(k => e[k]));
+  };
+  const run = (over) => {texts.length = 0; mkSpark(over)(); return texts.join(' | ');};
+
+  let t = run({BPI: [null, null], STATE: {trTeControl: 1, control: 0x101}});
+  ck('an empty graph names a REASON instead of nothing',
+     /no decoded window|Trace & Decode|waiting for/.test(t), t);
+  t = run({BPI: [null], STATE: {trTeControl: 0, control: 0x101}});
+  ck('the reason "encoder off" is named as such',
+     /encoder trace is off/.test(t), t);
+  t = run({BPI: [null], STATE: {trTeControl: 1, control: 0}});
+  ck('the reason "no core is running" is named as such',
+     /no core is running/.test(t), t);
+  t = run({BPI: [null], STATE: {trTeControl: 1, control: 0x101},
+           LIVE: {ok: true, decode: {ok: true, bits_per_instr: 4.9}}});
+  ck('with a healthy decode it says "waiting for the first window"',
+     /waiting for the first decode window/.test(t), t);
+  t = run({BPI: [null], STATE: {trTeControl: 1, control: 0x101},
+           LIVE: {ok: true, decode: {ok: false, bits_per_instr: 14342}}});
+  ck('a FAILED decode is named as such (not as "nothing there yet") -- '
+     + 'and its nonsense number is NOT drawn',
+     /decode of the ring window FAILED/.test(t) && !/14342/.test(t), t);
+  t = run({BPI: [4.9, 5.1], STATE: {trTeControl: 1, control: 0x101}});
+  ck('with values there is NO empty hint left',
+     !/no bpi|Trace & Decode|waiting for/.test(t), t);
+  ck('the source is stated at the curve as long as there are no counters',
+     /decoded window/.test(t), t);
+  t = run({BPI: [4.9, 5.1],
+           SCEN: Object.assign({}, env.SCEN,
+                               {ctrl: {control: 0, retires: 0x44}})});
+  ck('counter-check: WITH a retire counter "decoded window" is NOT there',
+     !/decoded window/.test(t), t);
+
+  /* --- build stamp: does the tab notice that it is outdated? ---------- */
+  const badge = {style: {}, textContent: '', title: ''};
+  const logs = [];
+  const chk = new Function('UIBUILD', 'UISTALE', '$', 'log',
+    fn('checkUiBuild') + '\nreturn checkUiBuild;')(
+      null, false, (id) => (id === 'uibuild' ? badge : null),
+      (m, warn) => logs.push(String(m)));
+  chk('aaaaaaaa');
+  ck('the build stamp of the first fetch is visible in the header',
+     badge.textContent === 'ui aaaaaaaa' && badge.style.display === '',
+     badge.textContent);
+  chk('aaaaaaaa');
+  ck('the same stamp -> no message (no permanent noise)',
+     logs.length === 0 && badge.textContent === 'ui aaaaaaaa');
+  chk('bbbbbbbb');
+  ck('a different stamp -> the tab reports itself as STALE',
+     /STALE, press F5/.test(badge.textContent) && logs.length === 1,
+     badge.textContent + ' | ' + logs.join(' '));
+  ck('the message names both states (old -> new)',
+     /aaaaaaaa/.test(logs[0]) && /bbbbbbbb/.test(logs[0]), logs[0]);
+  chk('cccccccc');
+  ck('and it comes exactly ONCE, not on every fetch',
+     logs.length === 1, String(logs.length));
+}catch(e){
+  ck('the U5 bpi logic from index.html is executable', false, e.message);
+}
+console.log('U5RESULT ' + JSON.stringify(RES));
+"""
+
+
+# --- the TE enable switch on the encoder card -------------------------------
+# The same construction as the probes above: the SHIPPED code is executed, not
+# a reimplementation. Three things have to hold, and none of them can be read
+# off the source text:
+#   * teLeds() builds one switch per card carrying the region of ITS OWN card
+#     (a fixed 'enc' switched the wrong encoder in every multi-core scenario --
+#     the same trap as the fixed row masks used to be), and it names the state
+#     as a WORD, not only as a colour.
+#   * setTeEnable() writes trTeControl.Enable through the EXISTING /api/write
+#     path, leaves the remaining bits standing and masks out the W1C bits
+#     (otherwise a whole-word write-back clears the overflow evidence in b12).
+#   * one click triggers EXACTLY ONE write, even after many render passes
+#     (teLeds runs on every poll tick -- with addEventListener instead of
+#     assignment the handler stack grows and with it the number of writes).
+JS_U7_PROBE = r"""
+import {readFileSync} from 'node:fs';
+const [IDX, RMP] = process.argv.slice(2);
+const HTML = readFileSync(IDX, 'utf8').replace(/\r\n/g, '\n');
+const RES = [];
+const ck = (n, ok, info) => RES.push({name: n, ok: !!ok,
+  info: info === undefined ? '' : String(info).replace(/[^\x20-\x7e]/g, '.')
+                                              .slice(0, 160)});
+function fn(name){
+  const s = HTML.indexOf('function ' + name + '(');
+  if (s < 0) throw new Error('function ' + name + '() is missing from index.html');
+  const e = HTML.indexOf('\n}\n', s);
+  if (e < 0) throw new Error('end of ' + name + '() not found');
+  return HTML.slice(s, e + 2);
+}
+function cst(name){
+  const m = new RegExp('^const ' + name + '=.*$', 'm').exec(HTML);
+  if (!m) throw new Error('const ' + name + ' is missing from index.html');
+  return m[0];
+}
+/* async functions need their keyword: fn() starts at 'function' and would
+   leave the 'async ' in front of it behind -- the excerpt then contains an
+   `await` in a non-async function and the build fails. It happened once,
+   which is why it is held here instead of patched at the caller. */
+function afn(name){
+  const s = HTML.indexOf('async function ' + name + '(');
+  if (s < 0) throw new Error('async function ' + name + '() is missing from index.html');
+  const e = HTML.indexOf('\n}\n', s);
+  if (e < 0) throw new Error('end of ' + name + '() not found');
+  return HTML.slice(s, e + 2);
+}
+try{
+  const RM = JSON.parse(readFileSync(RMP, 'utf8'));
+  const writes = [];
+  const logs = [];
+  /* The mock only has to do what the switch touches -- innerHTML (text),
+     classList, closest() and the one fetch substitute. */
+  class El{
+    constructor(){this._c=new Set();this._h='';this.onclick=null;this.onkeydown=null;}
+    set innerHTML(h){this._h=String(h);} get innerHTML(){return this._h;}
+    get classList(){const s=this._c;return{
+      add:c=>s.add(c), remove:c=>s.delete(c), contains:c=>s.has(c),
+      toggle:c=>{if(s.has(c)){s.delete(c);return false;} s.add(c);return true;}};}
+  }
+  const STATE = {trTeControl: 0, trTeControl1: 0, trTeControl2: 0};
+  const swEl = new El();
+  const env = {
+    document: {querySelector: () => swEl},
+    STATE, RM,
+    api: async (p, o) => {const b = JSON.parse(o.body);
+      writes.push(Object.assign({path: p}, b));
+      return {ok: true, readback: b.value};},
+    log: (m) => logs.push(String(m)),
+    logEvent: () => {},
+    render: () => {},
+    paintGateState: () => {},
+  };
+  const names = Object.keys(env);
+  const api = new Function(...names,
+    [cst('esc'), cst('hex'), fn('teSwTitle'), fn('teLeds'),
+     afn('setTeEnable')].join('\n') +
+    '\nreturn {teSwTitle, teLeds, setTeEnable};')(...names.map(k => env[k]));
+
+  /* --- what the card shows --------------------------------------------- */
+  const card = new El();
+  api.teLeds(card, 0x00000007, 'enc');          // Act|Enable|ITrace
+  ck('the card carries a switch with the region of ITS card',
+     /data-tesw="enc"/.test(card.innerHTML), card.innerHTML.slice(-90));
+  ck('the state is a WORD, not just a colour',
+     /TE enabled/.test(card.innerHTML), card.innerHTML.slice(-60));
+  ck('the switch is reachable by keyboard (role+tabindex)',
+     /role="button"/.test(card.innerHTML) && /tabindex="0"/.test(card.innerHTML));
+  const card0 = new El();
+  api.teLeds(card0, 0x00000005, 'enc');          // Enable = 0
+  ck('Enable=0 -> the word changes (not just the class)',
+     /TE disabled/.test(card0.innerHTML), card0.innerHTML.slice(-60));
+  ck('Enable=0 also carries the warning class (colour BESIDE the word)',
+     /class="tesw off"/.test(card0.innerHTML), card0.innerHTML.slice(-90));
+  const card1 = new El();
+  api.teLeds(card1, 0x00000007, 'enc1');
+  ck('the second card carries enc1, not enc (the multi-core trap)',
+     /data-tesw="enc1"/.test(card1.innerHTML), card1.innerHTML.slice(-90));
+
+  /* --- the warning says what it costs ---------------------------------- */
+  const tOn = api.teSwTitle('enc', true), tOff = api.teSwTitle('enc', false);
+  ck('the warning names the price: the sinks run dry',
+     /run dry/.test(tOn), tOn.slice(0, 80));
+  ck('the warning names the gain: the locked CSRs become writable',
+     /only way to unlock/.test(tOn));
+  ck('the warning excludes the core (it keeps running)',
+     /the core keeps running/.test(tOn));
+  ck('the warning excludes the WP records too (not Enable-gated)',
+     /not gated by Enable/.test(tOn));
+  ck('counter-check: the switched-off state says that writing is allowed '
+     + 'now',
+     /writable right now/.test(tOff), tOff.slice(0, 80));
+
+  /* --- what the click writes -------------------------------------------- */
+  const trTe = RM.regs.find(r => r.region === 'enc' && r.offset === 0);
+  const w1c = (trTe.fields || []).filter(f => f.w1c)
+    .reduce((m, f) => (m | (((1 << (f.msb - f.lsb + 1)) - 1) << f.lsb)) >>> 0, 0);
+  ck('regmap: trTeControl has a W1C bit (otherwise the next point checks '
+     + 'nothing)', w1c !== 0, '0x' + w1c.toString(16));
+  STATE.trTeControl = (0x014600EF | w1c) >>> 0;   // board value + overflow evidence
+  writes.length = 0;
+  await api.setTeEnable('enc', false);
+  ck('a click writes EXACTLY ONCE', writes.length === 1, String(writes.length));
+  ck('... and it does so over the existing path /api/write',
+     writes[0] && writes[0].path === '/api/write', writes[0] && writes[0].path);
+  ck('... on trTeControl of the RIGHT region (enc+0x000)',
+     writes[0].region === 'enc' && writes[0].offset === 0,
+     writes[0].region + '+' + writes[0].offset);
+  ck('Enable (b1) falls', ((writes[0].value >>> 1) & 1) === 0,
+     '0x' + (writes[0].value >>> 0).toString(16));
+  ck('all remaining bits stay (no whole-word reset)',
+     (writes[0].value & ~2 & ~w1c) === (STATE.trTeControl & ~2 & ~w1c),
+     '0x' + (writes[0].value >>> 0).toString(16));
+  ck('the W1C bit is MASKED OUT (the overflow evidence survives the switch)',
+     (writes[0].value & w1c) === 0,
+     '0x' + (writes[0].value >>> 0).toString(16));
+  ck('the log names the consequence, not just the value',
+     /Enable-locked CSRs are writable/.test(logs.join(' ')),
+     logs.join(' ').slice(0, 120));
+
+  STATE.trTeControl = 0x014600ED;                 // Enable = 0
+  writes.length = 0;
+  await api.setTeEnable('enc', true);
+  ck('the other direction: Enable (b1) gets set',
+     writes.length === 1 && ((writes[0].value >>> 1) & 1) === 1,
+     '0x' + (writes[0].value >>> 0).toString(16));
+
+  /* Region fidelity of the write path: enc1 must NOT read enc's trTeControl. */
+  STATE.trTeControl = 0x00000002; STATE.trTeControl1 = 0x014600EF;
+  writes.length = 0;
+  await api.setTeEnable('enc1', false);
+  ck('enc1 computes with trTeControl1 (not with the word of enc)',
+     writes[0].region === 'enc1' &&
+     (writes[0].value & ~2 & ~w1c) === (0x014600EF & ~2 & ~w1c),
+     writes[0].region + ' 0x' + (writes[0].value >>> 0).toString(16));
+
+  /* --- one click stays one write, even after 50 render passes ---------- */
+  const card2 = new El();
+  for (let i = 0; i < 50; i++) api.teLeds(card2, 0x00000007, 'enc');
+  STATE.trTeControl = 0x00000007;
+  writes.length = 0;
+  const ev = {target: {closest: () => ({dataset: {tesw: 'enc'}})},
+              stopPropagation: () => {}, preventDefault: () => {}};
+  card2.onclick(ev);
+  await new Promise(r => setImmediate(r));
+  ck('50 render passes, one click -> one write (no handler pile-up)',
+     writes.length === 1, String(writes.length));
+  writes.length = 0;
+  card2.onkeydown(Object.assign({key: 'Enter'}, ev));
+  await new Promise(r => setImmediate(r));
+  ck('the keyboard triggers the same single write', writes.length === 1,
+     String(writes.length));
+  writes.length = 0;
+  card2.onkeydown(Object.assign({key: 'a'}, ev));
+  await new Promise(r => setImmediate(r));
+  ck('counter-check: an arbitrary key does NOT switch', writes.length === 0,
+     String(writes.length));
+  /* A click next to it (on a lamp) must write nothing. */
+  writes.length = 0;
+  card2.onclick({target: {closest: () => null}, stopPropagation: () => {}});
+  await new Promise(r => setImmediate(r));
+  ck('counter-check: a click beside the switch does not write',
+     writes.length === 0, String(writes.length));
+}catch(e){
+  ck('the U7 switch logic from index.html is executable', false, e.message);
+}
+console.log('U7RESULT ' + JSON.stringify(RES));
+"""
+
+# The compact number formatting of the cards. What gets checked is the
+# SHIPPED code, not a Python reimplementation -- a second implementation
+# would be exactly the drift the guard is meant to prevent.
+JS_U9_PROBE = r"""
+import {readFileSync} from 'node:fs';
+const [IDX] = process.argv.slice(2);
+const HTML = readFileSync(IDX, 'utf8').replace(/\r\n/g, '\n');
+const RES = [];
+const ck = (n, ok, info) => RES.push({name: n, ok: !!ok,
+  info: info === undefined ? '' : String(info).replace(/[^\x20-\x7e]/g, '.')
+                                              .slice(0, 160)});
+try{
+  /* One contiguous excerpt of the page instead of individual functions:
+     fmtCnt hangs on fmtN, WP_DROP_SAT and the two constants. Whoever moves
+     one of them shows up here -- and that is the point. */
+  const s = HTML.indexOf('function fmtB(');
+  const e = HTML.indexOf('function renderLive(');
+  if (s < 0 || e < 0 || e <= s) throw new Error('number block not found');
+  const CODE = HTML.slice(s, e);
+  const els = {};
+  const $ = id => els[id] || (els[id] = {textContent: '', title: ''});
+  const STATE = {};
+  const api = new Function('$', 'STATE', CODE +
+    '\nreturn {fmtCnt, setCnt, wpDropTxt, paintDdrWindow, CNT_COMPACT_FROM, '
+    + 'CNT_UNITS};')($, STATE);
+  const F = api.fmtCnt;
+
+  ck('threshold stands as a constant (100 000)',
+     api.CNT_COMPACT_FROM === 100000, String(api.CNT_COMPACT_FROM));
+  const cases = [[0, '0'], [999, '999'], [12345, '12,345'],
+                 [99999, '99,999'],          // last number written out in full
+                 [100000, '100.0 k'],        // first compact one
+                 [216251, '216.3 k'],        // from the screenshot
+                 [1300000000, '1.3 G'],      // example from the requirement
+                 [4294967295, 'saturated'],  // the saturation stop
+                 [1500000, '1.5 M'], [2000000000000, '2.0 T']];
+  for (const [v, want] of cases)
+    ck('fmtCnt(' + v + ') = "' + want + '"', F(v) === want, F(v));
+  ck('fmtCnt(null) stays the dash (no invented 0)', F(null) === '–',
+     F(null));
+  ck('fmtCnt(undefined) likewise', F(undefined) === '–', F(undefined));
+
+  /* The actual promise is a LENGTH, not a format: the column has about ten
+     characters, anything beyond that pushes the label out of the box. */
+  let worst = {v: null, t: '', n: 0};
+  for (let v = 0; v < 4294967296; v = v < 1000 ? v + 1 : Math.floor(v * 1.07) + 1) {
+    const t = F(v);
+    if (t.length > worst.n) worst = {v, t, n: t.length};
+  }
+  ck('no value below 2^32 gets longer than 9 characters (sampled over the '
+     + 'whole range)', worst.n <= 9, 'longest: ' + worst.v + ' -> "'
+     + worst.t + '" (' + worst.n + ')');
+  ck('counter-check: the WRITTEN-OUT form would be longer (the problem that '
+     + 'was reported)',
+     (4294967294).toLocaleString('en-US').length > 9,
+     (4294967294).toLocaleString('en-US'));
+
+  /* setCnt: the number short, the exact value in the tooltip. Without the
+     tooltip the rounding would be a loss of data. */
+  api.setCnt('x1', 216251, 'beats dropped');
+  ck('setCnt writes the compact number into the element',
+     $('x1').textContent === '216.3 k', $('x1').textContent);
+  ck('and the EXACT value into the tooltip',
+     /216,251/.test($('x1').title) && /exact value/.test($('x1').title),
+     $('x1').title);
+  ck('the tooltip names WHAT is counted',
+     /beats dropped/.test($('x1').title), $('x1').title);
+  api.setCnt('x2', 4294967295, 'records dropped');
+  ck('at the limit the word is there, and the tooltip says why',
+     $('x2').textContent === 'saturated'
+     && /SATURATED/.test($('x2').title), $('x2').title.slice(0, 90));
+  api.setCnt('x3', null, 'AXIS beats');
+  ck('a missing register stays the dash (not 0)',
+     $('x3').textContent === '—', $('x3').textContent);
+  api.setCnt('x4', 4096, 'beats');
+  ck('a small number is written out in full on the card',
+     $('x4').textContent === '4,096', $('x4').textContent);
+  ck('wpDropTxt uses THE SAME function (no second rule)',
+     api.wpDropTxt(216251) === F(216251)
+     && api.wpDropTxt(4294967295) === 'saturated');
+
+  /* The window display: the case the headless screenshot found -- control
+     panel built before the first state had arrived. */
+  api.paintDdrWindow();
+  ck('empty state: a dash instead of "0x0 + 0 B"',
+     $('d_win').textContent === '–' && /no value read yet/.test($('d_win').title),
+     $('d_win').textContent + ' | ' + $('d_win').title.slice(0, 60));
+  STATE.ddr_base = 0x50000000; STATE.ddr_size = 0x10000000;
+  api.paintDdrWindow();
+  ck('with state: base and size readable',
+     $('d_win').textContent === '0x50000000 + 256.0 MiB', $('d_win').textContent);
+  ck('and the tooltip names BOTH registers with their hex value',
+     /DDR_BASE 0x50000000 \+ DDR_SIZE 0x10000000/.test($('d_win').title)
+     && /403/.test($('d_win').title), $('d_win').title.slice(0, 120));
+  STATE.ddr_size = 0x4000000;
+  api.paintDdrWindow();
+  ck('the display FOLLOWS a change (64 MiB instead of 256)',
+     $('d_win').textContent === '0x50000000 + 64.0 MiB', $('d_win').textContent);
+}catch(e){
+  ck('the U9 number logic from index.html is executable', false, e.message);
+}
+console.log('U9RESULT ' + JSON.stringify(RES));
+"""
+
+
+def _run_tick_live_tests(sc, cfg):
+    """Drain-Budget + RX-Resync: exercise WpState.tick_live() against a
+    software-mocked FIFO bus.
+
+    These mocks stand in for real hardware registers, but the PARSING they
+    exercise (FifoMmS's PG080 read-packet loop) lives in axis_wp_host --
+    tools/axis_wp_host, consumed not copied (wp_view.py docstring). Without
+    it tick_live() is a documented no-op (see wp_view.AXIS_WP_HOST_AVAILABLE),
+    real hardware or not, so this whole section is a clean SKIP rather than a
+    FAIL when that library has not landed in this repository yet.
+    """
+    if not wp_view.AXIS_WP_HOST_AVAILABLE:
+        skip("Drain-Budget + RX-Resync (tick_live via axis_wp_host)",
+             "axis_wp_host not found -- tools/axis_wp_host is not part of "
+             "this example")
+        return
+
+    print("== drain budget (board freeze class, finding 2) ==")
+    # A FIFO that NEVER runs empty (producer faster than the drain -- about
+    # 21k records/s produced per core against some 12.7k drained in total).
+    # An "until empty" drain then never returns and suffocates the board (it
+    # really happened). tick_live MUST return on its budget and must have
+    # pushed the records it read.
+    class EndlessFifoBus(FakeBus):
+        def __init__(self, magic):
+            super().__init__({"wpctrl": {0: magic}})
+            self.pops = 0
+
+        def read(self, region, off, n=1):
+            if region in ("fifo0", "fifo1"):
+                if off == 0x1C:                 # RDFO: always full
+                    return [4096]
+                if off == 0x24:                 # RLR: 16 B = 1 Record
+                    return [16]
+                if off == 0x20:                 # RDFD: counting pattern
+                    self.pops += 1
+                    k = self.pops - 1
+                    core = 1 if region == "fifo1" else 0
+                    w = (0xA6C, k & 0xFF, 0,
+                         (core << 20) | (0xFFF << 8))[k % 4]
+                    return [w]
+            return super().read(region, off, n)
+
+    w3 = wp_view.WpState()
+    w3.reset(sc)
+    bus3 = EndlessFifoBus(int(cfg["magic"], 0))
+    w3.tick_live(bus3)                          # MUST return
+    budget = int(cfg.get("drain_max", 1024))
+    got = sum(w3.received.values())
+    check("tick_live returns on a full FIFO (budget %d/FIFO)" % budget,
+          got == 2 * budget, "received=%d" % got)
+    check("budget records in the ring (pushed per batch, not only at the end)",
+          len(w3.ring) == min(2 * budget, int(cfg.get("ring", 20000))))
+    # The restart word-salad class (shown live on hardware): the FIRST bind
+    # to a FIFO MUST reset the RX side (RDFR := 0xA5 + ISR W1C) -- otherwise
+    # the drain inherits the half-read packet stream of the previous process
+    # and permanently parses shifted records (core_ids 2..15).
+    for reg in ("fifo0", "fifo1"):
+        check("first bind %s: RX reset (RDFR=0xA5)" % reg,
+              bus3.mem.get(reg, {}).get(0x18) == 0xA5)
+        check("first bind %s: ISR W1C" % reg,
+              bus3.mem.get(reg, {}).get(0x00) == 0xFFFFFFFF)
+
+    print("== RX resync (packet boundary drift after a reset under load, H3) ==")
+    # Shown live on hardware: a reset while the producer is writing can hit
+    # the TLAST count in the middle of a record -- after that EVERY packet is
+    # 4 words with shifted content (valid=False), permanently. The drain MUST
+    # notice that and reset the affected FIFO again until the stream is
+    # aligned; a healthy stream must NEVER be force-reset.
+    class MisalignedFifoBus(FakeBus):
+        """Delivers only shifted records until the SECOND RDFR reset."""
+
+        def __init__(self, magic):
+            super().__init__({"wpctrl": {0: magic}})
+            self.resets = {"fifo0": 0, "fifo1": 0}
+            self.k = 0
+
+        def write(self, region, off, value):
+            if region in self.resets and off == 0x18 and value == 0xA5:
+                self.resets[region] += 1
+            super().write(region, off, value)
+
+        def read(self, region, off, n=1):
+            if region in ("fifo0", "fifo1"):
+                if off == 0x1C:
+                    return [4096]
+                if off == 0x24:
+                    return [16]
+                if off == 0x20:
+                    self.k += 1
+                    core = 1 if region == "fifo1" else 0
+                    good = (0xA6C, 7, 0x1234,
+                            (core << 20) | (0xFFF << 8) | (core + 1))
+                    if self.resets[region] >= 2:
+                        return [good[(self.k - 1) % 4]]
+                    # shifted by one word: the W3 slot gets the PC ->
+                    # tstrb partial -> Record.valid == False
+                    return [good[self.k % 4]]
+            return super().read(region, off, n)
+
+    w4 = wp_view.WpState()
+    w4.reset(sc)
+    bus4 = MisalignedFifoBus(int(cfg["magic"], 0))
+    for _ in range(4):
+        w4.tick_live(bus4)
+    check("resync triggered (2nd RDFR reset per FIFO)",
+          bus4.resets["fifo0"] >= 2 and bus4.resets["fifo1"] >= 2,
+          str(bus4.resets))
+    with w4.lock:
+        got_valid = sum(1 for _, _, r in w4.ring if r.valid)
+    check("valid records flow after the resync", got_valid > 0,
+          "valid=%d invalid=%d" % (got_valid, w4.invalid))
+    check("resync reported in status (last_error)",
+          bool(w4.last_error) and "resync" in (w4.last_error or "").lower())
+
+
+def main():
+    cat = Catalog()
+    print("== scenario map ==")
+    check("scenario present", "tgc5b2_axis_wp" in cat.by_id)
+    sc = cat.by_id["tgc5b2_axis_wp"]
+    cfg = sc.raw.get("wp") or {}
+    check("wp block present", bool(cfg))
+
+    # window layout per SPEC §1
+    spec_regions = {"ctrl": 0xA0000000, "enc": 0xA0010000, "enc1": 0xA0020000,
+                    "ram1": 0xA0080000, "ram": 0xA0100000, "trace": 0xA0200000,
+                    "wpctrl": 0xA0400000, "fifo0": 0xA0410000,
+                    "fifo1": 0xA0420000}
+    for name, base in spec_regions.items():
+        b, s = sc.regions.get(name, (None, 0))
+        check("region %s @0x%08X" % (name, base), b == base,
+              "is 0x%08X" % (b or 0))
+
+    # WPCTRL offsets per SPEC §3 (word positions) -- in the aperture?
+    wsize = sc.regions["wpctrl"][1]
+    offs = {"magic_off": 0x00, "ftime_lo": 0x1C, "ftime_hi": 0x20,
+            "fifo_words": 0x24, "shim_recs": 0x28}
+    for k, want in offs.items():
+        v = int(cfg.get(k, -1))
+        check("wp.%s == 0x%02X" % (k, want), v == want, "is %r" % v)
+        check("wp.%s in aperture" % k, 0 <= v < wsize)
+    fifo_offs = {(0, "drop"): 0x04, (0, "fill"): 0x08, (0, "ovf"): 0x0C,
+                 (1, "drop"): 0x10, (1, "fill"): 0x14, (1, "ovf"): 0x18}
+    for f in cfg.get("fifos", []):
+        for fld in ("drop", "fill", "ovf"):
+            want = fifo_offs[(f["core"], fld)]
+            check("wp.fifos[core %d].%s == 0x%02X" % (f["core"], fld, want),
+                  int(f[fld]) == want)
+        check("wp.fifos[core %d].region exists" % f["core"],
+              f["region"] in sc.regions)
+    check("MAGIC == AWP1", int(cfg.get("magic", "0"), 0) == 0x41575031)
+
+    # --- sink window + ring size of the C0B_SINK3 build (SPEC §9) --------
+    # The breakage this checks against really happened: in the C0B_DDR build
+    # DDR_BEATS sat at 0x30, and since the shared sink window
+    # (ct_trace_sinks) PIB_DROPS lives there. Whoever keeps the old number
+    # reads discarded PIB beats and calls them DDR beats -- a plausible wrong
+    # number, exactly the class scenarios.json exists for. The counter-check
+    # against the RTL file header is done by test_rv64_scenarios; what stands
+    # here is the SPEC position.
+    sink_offs = {"sink_ctrl": 0x18, "ddr_base": 0x1C, "ddr_size": 0x20,
+                 "ddr_wptr": 0x24, "sink_stat": 0x28, "ddr_drops": 0x2C,
+                 "pib_drops": 0x30, "ddr_beats": 0x38}
+    for k, want in sink_offs.items():
+        check("ctrl.%s == 0x%02X (SPEC §9)" % (k, want), sc.co(k) == want,
+              "is %r" % sc.co(k))
+    check("0x30 is PIB_DROPS, NOT DDR_BEATS (the T2 break)",
+          sc.co("ddr_beats") != 0x30 and sc.co("pib_drops") == 0x30)
+    # The window size is no longer a number that stands here: the ring grew
+    # from 256 KiB to 1 MiB, and TRACE_BUFSZ @0x10 reports it itself. The
+    # region has to COVER the larger ring (mmap window), otherwise the dump
+    # breaks off at the top end.
+    check("the TRACE region covers the 1 MiB ring", sc.regions["trace"][1] >= 1 << 20,
+          "%d B" % sc.regions["trace"][1])
+    check("TRACE base unchanged 0xA0200000", sc.regions["trace"][0] == 0xA0200000)
+    check("TRACE_BUFSZ sits at 0x10 (hosts read the size there)",
+          sc.co("trace_bufsz") == 0x10, "is %r" % sc.co("trace_bufsz"))
+
+    # --- app variants -- which build has the sinks? -----------------------
+    vars_by_app = {v["app"]: v for v in sc.app_variants}
+    check("app_variants knows tgc5b2_axis_wp_c0b_sink3 (PL_GUARD)",
+          "tgc5b2_axis_wp_c0b_sink3" in vars_by_app,
+          ", ".join(sorted(vars_by_app)))
+    check("scenario sinks = the C0B_SINK3 build (URAM+DDR+PIB)",
+          all(sc.sinks.get(k) for k in ("uram", "ddr", "pib")), repr(sc.sinks))
+    for app in ("tgc5b2_axis_wp", "tgc5b2_axis_wp_c0b"):
+        v = vars_by_app.get(app) or {}
+        s2 = v.get("sinks") or {}
+        check("%s: own sink declaration without DDR/PIB" % app,
+              bool(s2) and not s2.get("ddr") and not s2.get("pib")
+              and s2.get("uram"), repr(s2))
+    check("the C0B_SINK3 variant inherits the scenario sinks (no override)",
+          "sinks" not in (vars_by_app.get("tgc5b2_axis_wp_c0b_sink3") or {}))
+    # And the user interface has to USE that distinction. A scenario field
+    # nobody reads is decoration: s.sinks would take over again, and under
+    # the old bitstream the tile would claim a DDR4 sink that does not exist
+    # there (mirror check as for REG_HOME).
+    idx = (HERE / "index.html").read_text(encoding="utf-8")
+    check("index.html has scenSinks() (the variant beats the scenario)",
+          "function scenSinks(" in idx)
+    check("index.html reads sinks ONLY through scenSinks()",
+          idx.count("scenSinks(") >= 4 and "SCEN?.sinks?.ddr" not in idx
+          and "s.sinks&&s.sinks[k]" not in idx,
+          "%d calls" % idx.count("scenSinks("))
+
+    print("== wp_set / Demo-Generator ==")
+    w = wp_view.WpState()
+    w.reset(sc)
+    # wp_set.txt lives in sw/axis_wp_demo/ (scenarios.json "wp_set"
+    # candidates), which is the tgc5b2_axis_wp example's own bare-metal
+    # payload -- not part of the dashboard-only migration this file is in
+    # (examples/dashboard/, plan AP5), it lands with the tgc5b2_axis_wp
+    # package under AP4. tick_demo() needs BOTH that symbol set (to build
+    # its deterministic schedule) AND axis_wp_host (for the Record wire
+    # format) -- either being absent makes the whole demo-generator section
+    # a clean SKIP, not a FAIL, exactly like the RTL-tree sections in
+    # test_rv64_scenarios.py.
+    wp_demo_ready = wp_view.AXIS_WP_HOST_AVAILABLE and bool(w.wp_syms)
+    if not wp_demo_ready:
+        reasons = []
+        if not wp_view.AXIS_WP_HOST_AVAILABLE:
+            reasons.append("axis_wp_host not found (tools/axis_wp_host is "
+                            "not part of this example)")
+        if not w.wp_syms:
+            reasons.append("wp_set.txt not found (sw/axis_wp_demo/ is not "
+                            "part of this example)")
+        skip("wp_set / Demo-Generator + records_json/status_json form",
+             "; ".join(reasons))
+    else:
+        check("wp_set loaded", bool(w.wp_syms), "path=%s" % w.wp_syms_path)
+        check("symbol name matches (0x1C8 -> entry:f000)",
+              w.wp_syms.get(0x1C8) == "entry:f000",
+              "is %r" % w.wp_syms.get(0x1C8))
+        # wp_slots carries the C0b build size (1023); the wp_set batch has
+        # fewer distinct addresses -- the schedule is the minimum of the two.
+        check("Demo-Schedule = min(wp_slots, wp_set)",
+              len(w.demo_sched) == min(int(cfg.get("wp_slots", 15)),
+                                       len(set(w.wp_syms))),
+              "sched=%d slots=%s set=%d" % (len(w.demo_sched),
+                                            cfg.get("wp_slots"),
+                                            len(set(w.wp_syms))))
+        check("wp_slots is the C0b build (1023)",
+              int(cfg.get("wp_slots", 0)) == 1023)
+        check("wp_load_slots caps the D1 direct path (15)",
+              int(cfg.get("wp_load_slots", 0)) == 15)
+
+        def demo_seq(ticks):
+            s = wp_view.WpState()
+            s.reset(sc)
+            for _ in range(ticks):
+                s.tick_demo(0.25)
+            return [(r.core_id, r.pc, r.direct, r.ts)
+                    for _, _, r in list(s.ring)]
+
+        a, b = demo_seq(4), demo_seq(4)
+        check("demo deterministic (2 runs identical)", a == b and len(a) > 0,
+              "%d records" % len(a))
+        check("both cores present", {c for c, _, _, _ in a} == {0, 1})
+
+        rj = w.records_json(10)
+        check("records_json empty before any ticks", rj["records"] == [])
+        for _ in range(2):
+            w.tick_demo(0.25)
+        rj = w.records_json(10)
+        r0 = rj["records"][0]
+        check("records_json shape",
+              all(k in r0 for k in ("seq", "t", "core", "pc", "sym", "slot",
+                                    "ts", "tid", "valid")))
+        check("symbol resolved in the record", bool(r0["sym"]))
+        st = w.status_json(FakeBus(), demo=True)
+        check("status_json (demo) shape",
+              all(k in st for k in ("scenario", "mode", "cores", "received",
+                                    "rates", "wp_slots", "note")))
+        check("status_json demo hint", "DEMO" in st["note"])
+        check("the note names the C0b state (finding 5)",
+              "C0b" in st["note"] and "1023" in st["note"], st["note"][:70])
+
+    print("== load_table safety contract ==")
+    w2 = wp_view.WpState()
+    w2.reset(sc)
+    # (0) WITHOUT a direct window the write is rejected instead of going
+    # into the void. The scenario no longer carries `wp_table_off` --
+    # +0x4100 does not exist in the C0b build (SPEC §7), yet the endpoint
+    # used to report ok=true on writes that hit no register at all.
+    check("the scenario carries NO direct window any more (0x4100 is gone)",
+          cfg.get("wp_table_off") is None, str(cfg.get("wp_table_off")))
+    try:
+        w2.load_table(FakeBus({"ctrl": {0: 0}}), sc,
+                      [{"addr": "0xA6C", "cmd": "0x41"}])
+        check("rejected without a direct window", False, "no exception")
+    except ValueError as e:
+        check("rejected without a direct window",
+              "no direct watchpoint window" in str(e), str(e)[:60])
+        check("the rejection names the indirect path (migration instead of a dead end)",
+              "0x400C" in str(e) and "wp_load_indirect" in str(e))
+    # For the remaining cases, mimic the older app: ONE key more, otherwise
+    # the same scenario -- the direct path is meant to live on unchanged for
+    # that app.
+    import copy
+    raw_d1 = copy.deepcopy(sc.raw)
+    raw_d1["wp"]["wp_table_off"] = "0x4100"
+    from scenario import Scenario                                  # noqa: E402
+    sc_d1 = Scenario(raw_d1)
+    w2.reset(sc_d1)
+    # (a) running TARGET CORE -> CONFLICT (the handler turns that into 409)
+    bus = FakeBus({"ctrl": {0: 1}})
+    try:
+        w2.load_table(bus, sc_d1, [{"addr": "0xA6C", "cmd": "0x41"}])
+        check("core_run=1 rejected", False, "no exception")
+    except ValueError as e:
+        check("core_run=1 rejected", str(e).startswith("CONFLICT"), str(e)[:60])
+    # (a2) The core's OWN bit counts just as much -- b0=0, b9=1 means
+    # "core 1 is running", and its table must not be loaded then.
+    bus = FakeBus({"ctrl": {0: 0x200}})
+    try:
+        w2.load_table(bus, sc_d1, [{"addr": "0xA6C", "cmd": "0x41"}],
+                      encs=["enc1"])
+        check("CONTROL b9 (only core 1 runs) rejected", False, "no exception")
+    except ValueError as e:
+        check("CONTROL b9 (only core 1 runs) rejected",
+              str(e).startswith("CONFLICT") and "core 1" in str(e).lower(),
+              str(e)[:70])
+    # (a3) ... and the running NEIGHBOUR no longer blocks: core 1 is
+    # running, and the table being loaded is core 0's. That used to be
+    # forbidden.
+    bus = FakeBus({"ctrl": {0: 0x200}})
+    res = w2.load_table(bus, sc_d1, [{"addr": "0xA6C", "cmd": "0x41"}],
+                        encs=["enc"])
+    check("a running neighbour core does NOT block the other table",
+          res["ok"] and list(res["encoders"]) == ["enc"])
+    # (b) active encoder -> CONFLICT
+    bus = FakeBus({"ctrl": {0: 0}, "enc": {0: 1}})
+    try:
+        w2.load_table(bus, sc_d1, [{"addr": "0xA6C", "cmd": "0x41"}])
+        check("Active=1 rejected", False, "no exception")
+    except ValueError as e:
+        check("Active=1 rejected", str(e).startswith("CONFLICT"), str(e)[:60])
+    # (b2) Enable=1 is the HARDWARE bar (swwel + shim commit gate) and used
+    # to be UNCHECKED -- exactly the case where the hardware discards
+    # silently and the endpoint reported success.
+    bus = FakeBus({"ctrl": {0: 0}, "enc": {0: 2}})
+    try:
+        w2.load_table(bus, sc_d1, [{"addr": "0xA6C", "cmd": "0x41"}])
+        check("Enable=1 rejected (HW bar)", False, "no exception")
+    except ValueError as e:
+        check("Enable=1 rejected (HW bar)",
+              str(e).startswith("CONFLICT") and "Enable" in str(e), str(e)[:70])
+    # (c) good case: writes to 0x4100/0x4104 + readback
+    bus = FakeBus({"ctrl": {0: 0}})
+    res = w2.load_table(bus, sc_d1, [{"addr": "0x00000A6C", "cmd": "0x00000041"},
+                                     ["0x1C8", "0x141"]])
+    check("good case ok", res["ok"] and res["slots"] == 2)
+    check("ENC-Write Slot0 addr", bus.mem["enc"].get(0x4100) == 0xA6C)
+    check("ENC-Write Slot1 cmd", bus.mem["enc"].get(0x410C) == 0x141)
+    check("both encoders described", "enc1" in res["encoders"])
+    check("Readback Slot0", res["encoders"]["enc"]["slot0_addr"] == "0x00000A6C")
+    # (d) slot cap
+    try:
+        w2.load_table(bus, sc_d1, [["0x0", "0x0"]] * 16)
+        check("16 slots rejected (max 15)", False)
+    except ValueError:
+        check("16 slots rejected (max 15)", True)
+    w2.reset(sc)
+
+    # ------------------------------------------------------------------
+    # access truth + per-core start/stop (server side)
+    # ------------------------------------------------------------------
+    print("== U4: gate, read-back comparison, W1C, destructive windows ==")
+    # (1) Enable bar: a locked field with the encoder armed is REJECTED
+    # instead of being discarded silently. The counter-check (Enable=0) has
+    # to pass -- a bar that always locks is not a bar.
+    gb = FakeBus({"enc": {0: 0x2}})            # trTeControl.Enable = 1
+    r_gate = server.write_gate_reason(gb, "enc", 0x400)   # trTeFilter[0].Control
+    check("a locked field while Enable=1 -> CONFLICT",
+          bool(r_gate) and r_gate.startswith("CONFLICT"), (r_gate or "")[:60])
+    check("the reason names the silence (no error code from the hardware)",
+          bool(r_gate) and "WITHOUT an error response" in r_gate)
+    check("counter-check Enable=0 -> no interlock",
+          server.write_gate_reason(FakeBus({"enc": {0: 0}}), "enc", 0x400) is None)
+    check("counter-check, an unlocked field (trTeTipFifoStatus) -> no interlock",
+          server.write_gate_reason(gb, "enc", 0xE04) is None)
+    # Regression (measured in the smoke run): the bar must NOT sit in front
+    # of the register that carries the Enable bit itself -- otherwise it is a
+    # door that only opens from the inside, and "trace off" fails on the very
+    # lock it is meant to lift. The same holds for mixed registers: a 409
+    # would forbid a permitted live change there. The example is trTsControl
+    # (Type/Prescale locked, Active/Enable free) -- NOT trTeInstFeatures any
+    # more, see below.
+    check("trTeControl stays writable (it carries the Enable bit itself)",
+          server.write_gate_reason(gb, "enc", 0x000) is None)
+    check("a mixed register (trTsControl) is not rejected",
+          server.write_gate_reason(gb, "enc", 0x040) is None)
+    # Since the vendored sync to CTTE 8b5e41eeda the eight InstEn* bits
+    # are themselves Enable-locked. That makes trTeInstFeatures NO LONGER a
+    # mixed register -- all ten writable fields are locked, and the bar has
+    # to catch it in front. This very line used to be the counter-check "is
+    # not rejected"; it went red with the sync and is deliberately inverted
+    # here.
+    r_feat = server.write_gate_reason(gb, "enc", 0x008)
+    check("trTeInstFeatures is rejected while Enable=1 (U11: all 10 fields locked)",
+          bool(r_feat) and r_feat.startswith("CONFLICT"), (r_feat or "")[:60])
+    for _f in ("InstEnImplicitReturn", "InstEnBranchPrediction",
+               "InstEnJumpTargetCache", "InstEnRepeatedHistory",
+               "InstEnRepeatBranch", "InstEnWideIcnt", "InstEnIbhs",
+               "InstEnRepeatInstr", "SrcID", "SrcBits"):
+        check("... and names %s explicitly" % _f, _f in (r_feat or ""))
+    check("counter-check Enable=0: trTeInstFeatures passes",
+          server.write_gate_reason(FakeBus({"enc": {0: 0}}), "enc", 0x008) is None)
+    check("... and the read-back comparison reports a fizzled field field by field",
+          any("SrcID" in d for d in server.readback_diff(
+              server.reg_at("enc", 0x008), 0x00010000, 0x0)),
+          "; ".join(server.readback_diff(server.reg_at("enc", 0x008),
+                                         0x00010000, 0x0))[:60])
+    # Count check against regmap.json: eight InstEn* fields carry the gate.
+    _feat = server.reg_at("enc", 0x008)
+    check("regmap.json: 8 InstEn* fields carry gated",
+          sum(1 for f in _feat["fields"]
+              if f["name"].startswith("InstEn") and f.get("gated")) == 8,
+          str(sum(1 for f in _feat["fields"]
+                  if f["name"].startswith("InstEn") and f.get("gated"))))
+    check("counter-check, the SoC window (ctrl) -> no Enable interlock",
+          server.write_gate_reason(gb, "ctrl", 0x00) is None)
+
+    # (2) Read-back: the intended value has to arrive in the fields that CAN
+    # carry it. Pulse/W1C/HW fields are excluded, otherwise the guard cries
+    # wolf constantly and ends up switched off.
+    te = server.reg_at("enc", 0x000)
+    check("readback_mask kennt trTeControl", te is not None and
+          server.readback_mask(te) != 0)
+    check("readback_mask leaves the W1C bit b12 OUT",
+          not (server.readback_mask(te) >> 12) & 1)
+    check("the deviation is named (field name + expected/actual)",
+          any("InstTracing" in d for d in
+              server.readback_diff(te, 0x7, 0x3)),
+          "; ".join(server.readback_diff(te, 0x7, 0x3))[:80])
+    check("counter-check: the same value -> no deviation",
+          server.readback_diff(te, 0x7, 0x7) == [])
+
+    # (3) W1C mask: the overflow evidence survives a whole-word write-back.
+    check("w1c_mask(trTeControl) == b12", server.w1c_mask("enc", 0x000) == 1 << 12,
+          hex(server.w1c_mask("enc", 0x000)))
+    check("w1c_mask(trTeDataControl) == b3|b5",
+          server.w1c_mask("enc", 0x010) == (1 << 3 | 1 << 5),
+          hex(server.w1c_mask("enc", 0x010)))
+    check("rmw_value clears the W1C bit from the write-back value",
+          server.rmw_value("enc", 0x000, 0x1FFF) == 0x1FFF & ~(1 << 12))
+    check("counter-check: a register without W1C stays unchanged",
+          server.rmw_value("enc", 0xE04, 0xFFFF) == 0xFFFF)
+
+    # (4) Read side effects are a DATA PROPERTY in regmap.json -- the poller
+    # filters on that, not on names (the old name filter caught
+    # TipFifoHistData and missed trWpReadHigh).
+    se = [r["path"] for r in server.REGMAP["regs"] if r.get("read_side_effect")]
+    check("regmap marks EXACTLY the two read-side-effect registers",
+          sorted(se) == ["ct_cs_cpuif.te.trTeTipFifoHistData",
+                         "ct_cs_cpuif.trWpReadHigh"], ", ".join(sorted(se)))
+    check("trWpReadHigh.Cmd carries swacc",
+          any(f.get("swacc") for f in server.reg_at("enc", 0x401C)["fields"]))
+
+    print("== U4/U1: per-core start/stop and window gating ==")
+
+    class FakeSocBus(FakeBus):
+        """CTRL window like the SoC top: STATUS mirrors the EFFECTIVE run
+        state (b8/b9 = b0 | b(8+i), tgc5b2_axis_soc_top.sv:584).
+        `mirror=False` reproduces a bitstream BEFORE U1 -- there the mirror
+        bits read a constant 0 although b0 lets the cores run."""
+
+        def __init__(self, scn, ctrl=0, mirror=True):
+            super().__init__({"ctrl": {0: ctrl, 4: 0}})
+            self.scn, self.mirror = scn, mirror
+            self._sync()
+
+        def _sync(self):
+            ctrl = self.mem["ctrl"].get(0, 0)
+            st = 0
+            if self.mirror:
+                for c in self.scn.cores:
+                    b = self.scn.status_bits.get(server._running_bit_name(c))
+                    if b is not None and self.scn.core_running(ctrl, c):
+                        st |= 1 << b
+            self.mem["ctrl"][4] = st
+
+        def write(self, region, off, value):
+            super().write(region, off, value)
+            if region == "ctrl" and off == 0:
+                self._sync()
+
+    check("core 0 carries b8, core 1 carries b9 (SPEC §10)",
+          sc.core_own_bit(sc.cores[0]) == 0x100
+          and sc.core_own_bit(sc.cores[1]) == 0x200)
+    check("effective is b0 OR b(8+i)",
+          sc.core_run_mask(sc.cores[0]) == 0x101
+          and sc.core_run_mask(sc.cores[1]) == 0x201)
+    check("b0 alone lets BOTH cores run (the collective bit stays valid)",
+          sc.core_running(0x1, sc.cores[0]) and sc.core_running(0x1, sc.cores[1]))
+    check("counter-check: b9 alone lets ONLY core 1 run",
+          not sc.core_running(0x200, sc.cores[0])
+          and sc.core_running(0x200, sc.cores[1]))
+
+    # A single-core stop out of the collective state: b0 has to fall and the
+    # other core gets ITS bit -- otherwise the stop takes the neighbour along.
+    b = FakeSocBus(sc, ctrl=0x1)
+    before, after, hint = server.set_core_run(b, sc, 0, False)
+    check("single stop from b0: core 0 stands still", not sc.core_running(after, sc.cores[0]),
+          "CONTROL 0x%X -> 0x%X" % (before, after))
+    check("single stop from b0: core 1 KEEPS running (b9 set)",
+          sc.core_running(after, sc.cores[1]) and (after & 0x200), hex(after))
+    check("single stop from b0: no hint needed", hint is None, str(hint))
+    check("the STATUS mirror follows (b9 set, b8 not)",
+          b.read("ctrl", 4)[0] == 0x200, hex(b.read("ctrl", 4)[0]))
+    _, after2, _ = server.set_core_run(b, sc, 1, True)
+    check("starting core 1 afterwards does not change core 0",
+          not sc.core_running(after2, sc.cores[0]))
+    _, after3, _ = server.set_core_run(b, sc, 0, True)
+    check("both started individually -> b8|b9", after3 & 0x300 == 0x300, hex(after3))
+
+    # A bitstream without the per-core bits: the mirror does not follow ->
+    # undo it and say why. Without this probe a single-core stop would have
+    # halted BOTH cores there and nobody would have learned about it.
+    old = FakeSocBus(sc, ctrl=0x1, mirror=False)
+    b4, a4, hint4 = server.set_core_run(old, sc, 0, False)
+    check("bitstream before U1: CONTROL is reset", a4 == b4 == 0x1, hex(a4))
+    check("bitstream before U1: the hint names the missing mirror",
+          bool(hint4) and "WITHOUT per-core run bits" in hint4, str(hint4)[:70])
+
+    # Window gating PER CORE: the RAM of the running core is locked, that of
+    # the halted one is not -- exactly the capability per-core control adds.
+    g = FakeSocBus(sc, ctrl=0x200)             # only core 1 is running
+    check("RAM1 while core 1 runs -> rejected (a hanging AXI is prevented)",
+          bool(server.region_hold_reason(g, sc, "ram1")))
+    check("the rejection names the hang, not just 'forbidden'",
+          "HANG" in (server.region_hold_reason(g, sc, "ram1") or ""))
+    check("RAM0 while core 0 is stopped -> allowed (reloading during operation)",
+          server.region_hold_reason(g, sc, "ram") is None)
+    g2 = FakeSocBus(sc, ctrl=0x1)              # collective bit: both are running
+    check("b0: BOTH RAM windows locked",
+          bool(server.region_hold_reason(g2, sc, "ram"))
+          and bool(server.region_hold_reason(g2, sc, "ram1")))
+    g3 = FakeSocBus(sc, ctrl=0x0)
+    check("counter-check: stopped cores -> both windows open",
+          server.region_hold_reason(g3, sc, "ram") is None
+          and server.region_hold_reason(g3, sc, "ram1") is None)
+    check("non-RAM regions are never gated (encoders hang on Enable)",
+          server.region_hold_reason(g2, sc, "enc") is None
+          and server.region_hold_reason(g2, sc, "wpctrl") is None)
+    check("destructive read windows are named (fifo0/fifo1)",
+          tuple(server.DESTRUCTIVE_READ_REGIONS) == ("fifo0", "fifo1"))
+
+    # The rule is a DATA FIELD, not a label text -- otherwise the server
+    # could not evaluate it.
+    for sid, want in (("tgc5b2_axis_wp", {"ram": 0, "ram1": 1}),
+                      ("trio", {"ram": 0, "ram1": 1}),
+                      ("mbv", {"ram": 0})):
+        s2 = cat.by_id[sid]
+        for reg, cid in want.items():
+            gc = s2.gate_core(reg)
+            check("%s/%s: gate_core -> core %d" % (sid, reg, cid),
+                  gc is not None and gc.get("id") == cid,
+                  str(gc and gc.get("id")))
+    check("trio: the CVA6 does NOT hang on the collective bit b0",
+          cat.by_id["trio"].core_run_mask(cat.by_id["trio"].cores[2]) == 0x420,
+          hex(cat.by_id["trio"].core_run_mask(cat.by_id["trio"].cores[2])))
+    check("trio: b10 is the alias of the historical b5",
+          cat.by_id["trio"].control_bits.get("cva6_run") == 5
+          and cat.by_id["trio"].control_bits.get("cva6_run2") == 10)
+
+    # Regression (measured in the smoke run): the demo bus has to follow the
+    # STATUS mirror IMMEDIATELY, the way the RTL wires it combinationally. If
+    # it only followed on the 250 ms tick, the capability probe in
+    # set_core_run read the OLD mirror, took the build for an older one and
+    # undid every single-core stop -- the function was completely dead in
+    # DEMO.
+    db = server.DemoBus(sc)
+    db.write("ctrl", 0, 0x200)
+    check("DemoBus: the STATUS mirror follows in the SAME access (b9)",
+          db.read("ctrl", 4)[0] & 0x300 == 0x200, hex(db.read("ctrl", 4)[0]))
+    db.write("ctrl", 0, 0x1)
+    check("DemoBus: the collective bit mirrors both cores",
+          db.read("ctrl", 4)[0] & 0x300 == 0x300, hex(db.read("ctrl", 4)[0]))
+    db.write("ctrl", 0, 0x0)
+    check("DemoBus: the mirror falls back to 0",
+          db.read("ctrl", 4)[0] & 0x300 == 0, hex(db.read("ctrl", 4)[0]))
+    # ... and the W1C evidence survives a whole-word write-back.
+    db.write("enc", 0x000, 0x1000)
+    check("DemoBus: a write cannot SET the W1C bit",
+          not (db.read("enc", 0)[0] >> 12) & 1, hex(db.read("enc", 0)[0]))
+
+    _run_tick_live_tests(sc, cfg)
+
+    # ------------------------------------------------------------------
+    # the protocol interlock: N-Trace and E-Trace must not run together
+    # ------------------------------------------------------------------
+    # The trio carries two N-Trace encoders and one E-Trace encoder in one
+    # netlist. The funnel merges them correctly -- but the frame length of
+    # every beat sits in the ATB signal ATBYTES, and NONE of the three sinks
+    # stores it. A merged ring is therefore undecodable for ALL targets, not
+    # only the third one: the decode aborts at the framing.
+    #
+    # Without the interlock nothing announces that. The ring fills, the
+    # counters look healthy, and the decode fails somewhere else entirely --
+    # the class of defect where every number says "fine".
+    print("== protocol interlock: not two protocols at once ==")
+    tri = cat.by_id.get("trio")
+    check("the trio declares its protocols as DATA (not by name)",
+          tri is not None and tri.protocols() == ["etrace", "ntrace"],
+          repr(tri.protocols()) if tri else "no trio")
+    check("... per core: two speak N-Trace, one E-Trace",
+          [tri.core_protocol(c) for c in tri.cores]
+          == ["ntrace", "ntrace", "etrace"],
+          repr([tri.core_protocol(c) for c in tri.cores]))
+
+    # An N-Trace core is running; the E-Trace core must be refused.
+    g_n = FakeSocBus(tri, ctrl=tri.core_own_bit(tri.cores[0]))
+    lock = server.protocol_lock_reason(g_n, tri, 2)
+    check("N-Trace runs -> starting the E-Trace core is REFUSED",
+          bool(lock) and lock.startswith("CONFLICT"), repr(lock)[:70])
+    check("... and the refusal names the reason (ATBYTES), not just 'no'",
+          bool(lock) and "ATBYTES" in lock, repr(lock)[:70])
+
+    # The counter-check that makes the interlock a bar rather than a wall:
+    # the SECOND N-Trace core may start, because that stream stays uniform.
+    check("counter-check: the second N-Trace core is NOT refused",
+          server.protocol_lock_reason(g_n, tri, 1) is None,
+          repr(server.protocol_lock_reason(g_n, tri, 1))[:60])
+
+    # And the other direction, so the rule is not one-sided.
+    g_e = FakeSocBus(tri, ctrl=tri.core_own_bit(tri.cores[2]))
+    check("E-Trace runs -> starting an N-Trace core is REFUSED",
+          bool(server.protocol_lock_reason(g_e, tri, 0)),
+          repr(server.protocol_lock_reason(g_e, tri, 0))[:70])
+
+    # Nothing running: every core may start.
+    g_0 = FakeSocBus(tri, ctrl=0)
+    check("nothing running -> no core is refused",
+          all(server.protocol_lock_reason(g_0, tri, i) is None
+              for i in range(len(tri.cores))))
+
+    # The collective bit releases EVERY core at once -- in a mixed scenario
+    # that is exactly the merged stream, so it is refused outright.
+    check("the collective start is refused in a mixed scenario",
+          bool(server.protocol_lock_reason(g_0, tri, None)),
+          repr(server.protocol_lock_reason(g_0, tri, None))[:70])
+    check("... and it names the way out (start the cores individually)",
+          "core_run" in (server.protocol_lock_reason(g_0, tri, None) or ""))
+
+    # The interlock must not fire where it must not: a scenario that declares
+    # no protocols keeps behaving exactly as before.
+    for other in ("rocket2", "duo", "cva6_linux"):
+        o = cat.by_id.get(other)
+        if not o:
+            continue
+        ob = FakeSocBus(o, ctrl=o.core_own_bit(o.cores[0]) or 1)
+        check("counter-check %s: uniform scenario, interlock stays silent" % other,
+              o.protocols() == []
+              and all(server.protocol_lock_reason(ob, o, i) is None
+                      for i in range(len(o.cores)))
+              and server.protocol_lock_reason(ob, o, None) is None,
+              repr(o.protocols()))
+
+    # The user interface has to say it BEFORE the click. A button that
+    # answers with an error is worse than one that says why it is closed.
+    check("index.html computes the reason from the scenario data",
+          "function protoLockReason(" in idx and "c.protocol" in idx)
+    check("... and passes it into runStop for every core row",
+          idx.count("protoLockReason(") >= 4)
+    check("... the shown reason names ATBYTES, not just 'blocked'",
+          "do not store ATBYTES" in idx)
+    _srv = (HERE / "server.py").read_text(encoding="utf-8")
+    check("the server refuses the same combination (single core AND collective)",
+          "protocol_lock_reason(bus, SC, idx)" in _srv
+          and "protocol_lock_reason(bus, SC, None)" in _srv)
+
+    print("== regression: the existing scenarios ==")
+    for sid in cat.order:
+        s = cat.by_id[sid]
+        try:
+            server.DemoBus(s)
+            poll = server.build_poll(s)
+            ok = all(rg in s.regions or rg == "ctrl" for _, rg, _ in poll)
+            check("scenario %s: DemoBus + poll" % sid, ok,
+                  "%d poll entries" % len(poll))
+        except Exception as e:                   # noqa: BLE001
+            check("scenario %s: DemoBus + poll" % sid, False, str(e))
+
+    print("== architecture geometry (defect class: trio fallback) ==")
+    # rebuildArch() SILENTLY keeps the last geometry it built when a
+    # scenario has no ARCH_BY_SCEN entry -- that is exactly how
+    # tgc5b2_axis_wp ended up with the trio layout (funnel 78x666,
+    # te_inst/tePktz, TIP only in row 0). The guard: EVERY scenario of the
+    # catalogue carries its OWN geometry.
+    import json as _json
+    import re as _re
+    idx = (HERE / "index.html").read_text(encoding="utf-8")
+    m = _re.search(r"const ARCH_BY_SCEN=(\{.*?\});\n", idx, _re.S)
+    check("ARCH_BY_SCEN blob present", bool(m))
+    geo = _json.loads(m.group(1)) if m else {}
+    for sid in cat.order:
+        check("geometry for %s" % sid, sid in geo)
+    g = geo.get("tgc5b2_axis_wp") or {"nodes": [], "edges": []}
+    ids = {n["id"] for n in g["nodes"]}
+    check("tgc5b2: NO E-Trace blocks (finding 2, CT_EN_ETRACE=0)",
+          not any(i.startswith(("teinst", "tepktz")) for i in ids))
+    check("tgc5b2: H2E->TIP in BOTH rows (finding 3)",
+          {"tip0", "tip1"} <= ids)
+    check("tgc5b2: AXIS-WP chain per row (finding 6)",
+          {"wpshim0", "wpfifo0", "kriaps0",
+           "wpshim1", "wpfifo1", "kriaps1"} <= ids)
+    check("tgc5b2: funnel + URAM (finding 1)", {"funnel", "uram"} <= ids)
+    ed = {(e["s"], e["t"]) for e in g["edges"]}
+    for want in (("preproc0", "wpshim0"), ("wpshim0", "wpfifo0"),
+                 ("wpfifo0", "kriaps0"), ("preproc1", "wpshim1"),
+                 ("wpshim1", "wpfifo1"), ("wpfifo1", "kriaps1"),
+                 ("cpu1", "tip1"), ("funnel", "uram")):
+        check("tgc5b2: edge %s->%s" % want, want in ed)
+
+    # The THREE sinks of the sink subsystem (ct_trace_sinks.sv) hang
+    # ADDITIVELY off the funnel output -- one ATB beat input, three sinks in
+    # parallel. For a while the drawing showed only the URAM ring:
+    # scenarios.json already carried the sinks, the SVG was from the day
+    # before.
+    check("tgc5b2: all three sinks drawn (T4)",
+          {"uram", "ddr", "pib"} <= ids,
+          "missing: %s" % sorted({"uram", "ddr", "pib"} - ids))
+    for sid_sink in ("ddr", "pib"):
+        check("tgc5b2: edge funnel->%s" % sid_sink,
+              ("funnel", sid_sink) in ed)
+    # The sinks hang off the FUNNEL, not off an encoder row: an edge
+    # mseomdo*->sink would be drawn hardware that does not exist (the merge
+    # happens before the sinks, ct_trace_sinks has ONE beat input).
+    check("tgc5b2: no sink directly on an encoder row",
+          not [1 for s, t in ed
+               if t in ("uram", "ddr", "pib") and s != "funnel"])
+
+    # Defect class GENERATED-ARTEFACT DRIFT, for EVERY scenario: the sink
+    # set of the drawing is the one from scenarios.json
+    # (gui/compact_layout.py, line
+    # `want = [s for s in ("ddr","uram","pib") if sinks.get(s)]`). Whoever
+    # changes the sinks in the catalogue and does not run the generator gets
+    # red here instead of a view that keeps quiet about a sink -- exactly the
+    # earlier finding, only visible immediately the next time.
+    for sid in cat.order:
+        gg = geo.get(sid) or {"nodes": []}
+        gids = {n["id"] for n in gg["nodes"]}
+        sk = cat.by_id[sid].raw.get("sinks") or {}
+        want_sink = {k for k in ("uram", "ddr", "pib") if sk.get(k)} or {"uram"}
+        have_sink = gids & {"uram", "ddr", "pib"}
+        check("geometry %s: sinks == scenarios.json" % sid,
+              have_sink == want_sink,
+              "drawing %s vs. catalog %s"
+              % (sorted(have_sink), sorted(want_sink)))
+    # layoutWires() does NOT draw edges without a 'path' (the sync import
+    # from pure image exports loses them silently -- really observed when
+    # export_drawio dumps covered the sync sources).
+    for sid in cat.order:
+        gg = geo.get(sid) or {"edges": []}
+        pathless = [e for e in gg["edges"]
+                    if not e.get("path") or len(e["path"]) < 2]
+        check("geometry %s: all edges with a gradient" % sid,
+              not pathless, "%d without a path" % len(pathless))
+
+    print("== U2: indexed instances under ONE parent node ==")
+    # Requirement: te.trTeFilter[0].Control through
+    # te.trTeFilter[15].Control are to sit under ONE parent row
+    # te.trTeFilter[0..15] that expands and only then shows the individual
+    # instances.
+    # The rule is generic (every indexed row, both register lists, all
+    # scenarios); the data side is checked by test_block_csrs.py, here the
+    # SHIPPED JS code itself runs.
+    import json as _j
+    import subprocess                                   # noqa: S404
+    import tempfile
+    import test_block_csrs as _tbc                      # mirror counterpart
+
+    check("the register tab groups (buildAll, a search expands the hits)",
+          "renderRegGroups(list,items,'all',!!q)" in idx)
+    check("the block panel groups the register rows",
+          "'panel:'+b,false)" in idx)
+    check("the memory rows go through the same folding",
+          "'panel:'+b+':mem',false)" in idx)
+    # Counter-check for completeness: if an ungrouped
+    # list.appendChild(regRow(...)) were left standing anywhere, the folding
+    # would be half done -- exactly the class that only shows up in the panel
+    # on a click.
+    check("no ungrouped register row left over (counter-check)",
+          "list.appendChild(regRow(" not in idx)
+    check("COLLAPSED by default, expanding only through the class (CSS)",
+          ".rgrp>.gbody{display:none" in idx
+          and ".rgrp.open>.gbody{display:block}" in idx)
+    check("fold state lives in the client (REGGRP_OPEN per node)",
+          "const REGGRP_OPEN=" in idx and "REGGRP_OPEN[key]" in idx)
+    # Without ?open= the EXPANDED state can only be produced by hand --
+    # neither a headless screenshot nor a board spot check could show it (the
+    # same reasoning as for ?tab=/?sel= above in the init).
+    check("expanding is checkable without a click (?open=:)",
+          "getAll('open')" in idx and "REGGRP_OPEN[k]=true" in idx)
+
+    try:
+        nv = subprocess.run(["node", "--version"], capture_output=True,
+                            text=True)
+        node_ok = nv.returncode == 0
+        node_ver = (nv.stdout or "").strip()
+    except OSError as e:                                 # noqa: BLE001
+        node_ok, node_ver = False, str(e)
+    # NO skip: without node the grouping is merely claimed, and a skipped
+    # guard that reports green is the most expensive kind.
+    check("node available (the guard executes the shipped code)",
+          node_ok, node_ver)
+    # Edge cases that do NOT occur in the real regmap.json (there every row
+    # has >= 3 instances): a two-instance row, a gap, a single instance, a
+    # row without an index. Without them the mirror comparison below would be
+    # blunt -- measured against the mutation "threshold 2 -> 3", which it
+    # would otherwise not see.
+    EDGE = ["zz.pair[0].A", "zz.pair[1].A",
+            "zz.gap[0].A", "zz.gap[1].A", "zz.gap[5].A", "zz.gap[5].B",
+            "zz.single[7].A", "zz.single[7].B", "zz.plain"]
+    if node_ok:
+        rm_path = HERE / "regmap.json"
+        with tempfile.TemporaryDirectory() as td:
+            probe = Path(td) / "u2_group_probe.mjs"
+            probe.write_text(JS_GROUP_PROBE, encoding="utf-8")
+            p = subprocess.run(["node", str(probe), str(HERE / "index.html"),
+                                str(rm_path), _j.dumps(EDGE)],
+                               capture_output=True, text=True,
+                               encoding="utf-8")
+        res, summ = [], None
+        for ln in (p.stdout or "").splitlines():
+            if ln.startswith("U2RESULT "):
+                res = _j.loads(ln[len("U2RESULT "):])
+            elif ln.startswith("U2SUMMARY "):
+                summ = _j.loads(ln[len("U2SUMMARY "):])
+        check("grouping probe ran (node, rc=0)",
+              p.returncode == 0 and bool(res),
+              "rc=%d %s" % (p.returncode, (p.stderr or "")[:160]))
+        for r in res:
+            check(r["name"], r["ok"], r.get("info", ""))
+        # The Python mirror in test_block_csrs.py carries some 40 checks
+        # there -- it must not drift apart from what is shipped.
+        paths = [r["path"] for r in
+                 _j.loads(rm_path.read_text(encoding="utf-8"))["regs"]] + EDGE
+        mirror = _j.loads(_j.dumps(_tbc.group_summary(paths)))
+        check("python mirror (test_block_csrs.group_rows) == JS result"
+              " (real map + 4 edge cases)",
+              summ == mirror,
+              "" if summ == mirror else "first deviation: %s" % next(
+                  ("%r != %r" % (a, b) for a, b in
+                   zip(summ or [], mirror) if a != b), "length %s/%s"
+                  % (len(summ or []), len(mirror))))
+
+        # --- badge, gate state, run state per core ------------------------
+        with tempfile.TemporaryDirectory() as td:
+            probe4 = Path(td) / "u4_access_probe.mjs"
+            probe4.write_text(JS_U4_PROBE, encoding="utf-8")
+            p4 = subprocess.run(["node", str(probe4), str(HERE / "index.html"),
+                                 str(rm_path)],
+                                capture_output=True, text=True,
+                                encoding="utf-8")
+        res4 = []
+        for ln in (p4.stdout or "").splitlines():
+            if ln.startswith("U4RESULT "):
+                res4 = _j.loads(ln[len("U4RESULT "):])
+        check("U4 display probe ran (node, rc=0)",
+              p4.returncode == 0 and bool(res4),
+              "rc=%d %s" % (p4.returncode, (p4.stderr or "")[:160]))
+        for r in res4:
+            check(r["name"], r["ok"], r.get("info", ""))
+
+        # --- bpi source + the empty graph with a reason --------------------
+        with tempfile.TemporaryDirectory() as td:
+            probe5 = Path(td) / "u5_bpi_probe.mjs"
+            probe5.write_text(JS_U5_PROBE, encoding="utf-8")
+            p5 = subprocess.run(["node", str(probe5), str(HERE / "index.html")],
+                                capture_output=True, text=True,
+                                encoding="utf-8")
+        res5 = []
+        for ln in (p5.stdout or "").splitlines():
+            if ln.startswith("U5RESULT "):
+                res5 = _j.loads(ln[len("U5RESULT "):])
+        check("U5 bpi probe ran (node, rc=0)",
+              p5.returncode == 0 and bool(res5),
+              "rc=%d %s" % (p5.returncode, (p5.stderr or "")[:160]))
+        for r in res5:
+            check(r["name"], r["ok"], r.get("info", ""))
+
+        # --- the TE enable switch on the encoder card ----------------------
+        with tempfile.TemporaryDirectory() as td:
+            probe7 = Path(td) / "u7_te_enable_probe.mjs"
+            probe7.write_text(JS_U7_PROBE, encoding="utf-8")
+            p7 = subprocess.run(["node", str(probe7), str(HERE / "index.html"),
+                                 str(rm_path)],
+                                capture_output=True, text=True,
+                                encoding="utf-8")
+        res7 = []
+        for ln in (p7.stdout or "").splitlines():
+            if ln.startswith("U7RESULT "):
+                res7 = _j.loads(ln[len("U7RESULT "):])
+        check("U7 switch probe ran (node, rc=0)",
+              p7.returncode == 0 and bool(res7),
+              "rc=%d %s" % (p7.returncode, (p7.stderr or "")[:160]))
+        for r in res7:
+            check(r["name"], r["ok"], r.get("info", ""))
+
+    # --- sink defaults of the scenario ------------------------------------
+    # The default is DATA, not a special case in the code: a scenario without
+    # the key must not behave any differently than before.
+    sd = sc.raw.get("sink_defaults") or {}
+    check("tgc5b2_axis_wp carries sink_defaults", bool(sd), str(sd))
+    check("the default switches the DDR sink ON (that was the field finding)",
+          sd.get("ddr_en") is True)
+    check("the default selects the RING, not one shot (otherwise the sink "
+          "sits at FULL after ~1.6 s and only counts drops -- T3 point 7)",
+          sd.get("ddr_circ") is True)
+    check("the default names NO pulse bit (b1/b5 are W1 pulses)",
+          not ({"ddr_clear", "pib_clear"} & set(sd)))
+    check("all keys of the default are known to the server",
+          all(k in server.SINK_BITS for k in sd),
+          "unknown: %s" % [k for k in sd if k not in server.SINK_BITS])
+    for other in ("rocket2", "trio", "cva6_linux", "mbv"):
+        if other in cat.by_id:
+            check("existing scenario %s stays without a default (unchanged)" % other,
+                  not (cat.by_id[other].raw.get("sink_defaults")))
+
+    dbus = server.DemoBus(sc)
+    so = sc.co("sink_ctrl")
+    r1 = server.arm_default_sinks(dbus, sc)
+    check("bind armed: SINK_CTRL 0x0 -> 0x5 (ddr_en | ddr_circ)",
+          r1.get("state") == "armed" and dbus.read("ctrl", so)[0] == 0x5,
+          "%s -> 0x%X" % (r1.get("state"), dbus.read("ctrl", so)[0]))
+    r2 = server.arm_default_sinks(dbus, sc)
+    check("a second bind does NOT write again (idempotent, a running sink "
+          "is not touched)",
+          r2.get("state") == "already armed" and r2.get("wrote") is False,
+          str(r2))
+    # Pulse bits: if they stand in the register (for whatever reason),
+    # arming must not write them along -- a permanent ddr_clear would wipe
+    # the counters on every bind.
+    dbus.write("ctrl", so, 0x22)
+    r3 = server.arm_default_sinks(dbus, sc)
+    check("arming masks out the pulse bits b1/b5",
+          (dbus.read("ctrl", so)[0] & 0x22) == 0
+          and (dbus.read("ctrl", so)[0] & 0x5) == 0x5,
+          "0x%X (%s)" % (dbus.read("ctrl", so)[0], r3.get("state")))
+    for other in ("rocket2", "trio"):
+        if other in cat.by_id:
+            osc = cat.by_id[other]
+            ob = server.DemoBus(osc)
+            before = ob.read("ctrl", osc.co("sink_ctrl"))[0]
+            ores = server.arm_default_sinks(ob, osc)
+            check("the bind of %s does not touch SINK_CTRL" % other,
+                  ob.read("ctrl", osc.co("sink_ctrl"))[0] == before
+                  and "no sink_defaults" in ores.get("state", ""),
+                  str(ores))
+
+    # Target window: a DMA WRITE master is not armed on the off chance.
+    # Without evidence from the device tree it stays off.
+    _real_rr = server.resmem_ranges
+    try:
+        server.resmem_ranges = lambda: [(0x50000000, 0x20000000, "ctrace-pl-ddr")]
+        check("a target window inside the reserved area is accepted",
+              server.ddr_window_ok(0x60000000, 0x04000000)[0] is True)
+        check("a window that reaches past the reserved area is "
+              "rejected",
+              server.ddr_window_ok(0x6F000000, 0x04000000)[0] is False)
+        check("a window outside it (Linux memory!) is rejected",
+              server.ddr_window_ok(0x00100000, 0x00010000)[0] is False)
+        check("DDR_SIZE 0 is rejected",
+              server.ddr_window_ok(0x60000000, 0)[0] is False)
+        server.resmem_ranges = lambda: []
+        check("without device-tree evidence: NO arming (counter-check)",
+              server.ddr_window_ok(0x60000000, 0x04000000)[0] is False)
+
+        class _LiveBus(FakeBus):
+            demo = False
+        lb = _LiveBus({"ctrl": {so: 0, sc.co("ddr_base"): 0x60000000,
+                                sc.co("ddr_size"): 0x04000000}})
+        rl = server.arm_default_sinks(lb, sc)
+        check("a live bus without resmem evidence is NOT armed",
+              rl.get("state", "").startswith("refused")
+              and lb.read("ctrl", so)[0] == 0, str(rl)[:120])
+        server.resmem_ranges = lambda: [(0x50000000, 0x20000000, "ctrace-pl-ddr")]
+        rl2 = server.arm_default_sinks(lb, sc)
+        check("a live bus WITH evidence is armed (counter-check to the rejection)",
+              rl2.get("state") == "armed" and lb.read("ctrl", so)[0] == 0x5,
+              str(rl2)[:120])
+    finally:
+        server.resmem_ranges = _real_rr
+
+    # --- U5: build stamp (finding 3) ----------------------------------------
+    b = server.ui_build_id()
+    check("the build stamp is an 8-digit hex value",
+          len(b) == 8 and all(c in "0123456789abcdef" for c in b), b)
+    check("the build stamp covers the files a tab loads ONCE",
+          {"index.html", "regmap.json", "scenarios.json"} <= set(server.UI_FILES),
+          str(server.UI_FILES))
+    check("the build stamp is stable (two fetches, one value)",
+          server.ui_build_id() == b)
+
+    # --- the places in the shipped HTML that are not a function call
+    # (filter, mask, button set). Text checks, as with scenSinks() -- they
+    # stop exactly the roll-backs that arrive labelled "simplification".
+    check("the poller filters on the DATA PROPERTY read_side_effect",
+          "filter(r=>!r.read_side_effect)" in idx)
+    check("the poller no longer hangs on the register name TipFifoHistData",
+          "path.includes('TipFifoHistData')" not in idx)
+    check("no access to a store 'watchpoints' any more (it does not exist)",
+          "includes('watchpoints')" not in idx)
+    check("a field write masks W1C bits out of the write-back value",
+          "f.w1c" in idx and "cur&~mask&~w1c" in idx)
+    check("the write button carries the gate property (it is locked live)",
+          "data-gated" in idx and "b.disabled=locked" in idx)
+    check("core 1 has start/stop buttons of its own",
+          'id="btn_run1"' in idx and 'id="btn_stop1"' in idx)
+    check("the per-core path sends the CORE INDEX to the server",
+          "action:run?'core_run':'core_stop',core:i" in idx.replace(" ", ""))
+    check("the collective path stays reachable (Run all/Stop all in the panel)",
+          "'Run all','run'" in idx and "'Stop all','stop'" in idx)
+    check("the empty catch in the poller is gone (silent errors were the cause)",
+          "}catch(e){}" not in idx.split("function refreshPanelVals")[1]
+          .split("function paintPanelVals")[0])
+
+    # --- what the cards show and what the click does (text checks) --------
+    check("the DDR card says in plain words when the sink is OFF",
+          "'disabled'" in idx and "DDR4 sink is DISABLED (SINK_CTRL b0 = 0)" in idx)
+    check("the PIB card says so too",
+          "Parallel trace port is DISABLED (SINK_CTRL b4 = 0)" in idx)
+    check("both state words are buttons (keyboard included)",
+          'id="ddr_wrapn" class="sinksw" role="button" tabindex="0"' in idx
+          and 'id="pib_state" class="sinksw" role="button" tabindex="0"' in idx)
+    check("the card switch takes the EXISTING server path (no second "
+          "write path for the same thing)",
+          "sinkSw('ddr_wrapn',0x1,'ddr_on','ddr_off'" in idx
+          and "sinkSw('pib_state',0x10,'pib_on','pib_off'" in idx)
+    check("the card switch stops the click from propagating (otherwise "
+          "the panel opens at the same time)",
+          "e.onclick=ev=>{ev.stopPropagation();go();};" in idx)
+    check("the URAM card explains that a full RING is the normal case",
+          "is the NORMAL full state of a ring" in idx)
+    check("URAM stays without a card switch (one shot stops the recording)",
+          "sinkSw('cap_wrapn'" not in idx)
+    check("the bpi tooltip names the source when there are no counters",
+          "Bits per decoded instruction." in idx
+          and "This SoC has NO hardware retire " in idx
+          and "instructions of " in idx)
+    check("an empty graph carries the hint about Trace & Decode",
+          "run Trace & Decode to populate" in idx)
+    check("the build stamp is compared on EVERY fetch",
+          "checkUiBuild(s.ui_build)" in idx and "STALE, press F5" in idx)
+    check("no automatic reload (that used to tear away a running measurement)",
+          "location.reload" not in idx)
+    # --- WP shim card -- width from the GENERATOR plus the stop -----------
+    # The card is absolutely positioned and clips with overflow:hidden.
+    # Whether text fits cannot be rendered in the test -- but it can be
+    # computed: the card font is --fs-s = 10 model units monospace (~6 per
+    # character), plus 5+5 block padding and 2 of .cnt inner spacing.
+    check("the WP shim card no longer wraps (nowrap)",
+          'id="wp_sdrop0">' in idx
+          and '
    drop  200 -> 409 chain OFFLINE, on the demo bus -------------
+    # The board proof was run by hand over /api/write. Here the guard drives
+    # it: the demo bus mirrors the swwel bar, so it also has to show that the
+    # SWITCH opens it and closes it again.
+    d7 = server.DemoBus(sc)
+    d7.write("enc", 0x000, 0x00000007)                 # Active|Enable|ITrace
+    check("demo: encoder armed, a locked field is rejected (409)",
+          (server.write_gate_reason(d7, "enc", 0x400) or "").startswith(
+              "CONFLICT"))
+    before = d7.read("enc", 0x400)[0]
+    d7.write("enc", 0x400, 0x00000001)
+    check("demo: the rejected write would fizzle out SILENTLY (hence 409)",
+          d7.read("enc", 0x400)[0] == before, hex(d7.read("enc", 0x400)[0]))
+    # ... now the switch: Enable itself is NOT locked (the door).
+    d7.write("enc", 0x000, server.rmw_value("enc", 0, d7.read("enc", 0)[0] & ~2))
+    check("demo: the switch gets Enable to 0 (Enable is not swwel)",
+          not (d7.read("enc", 0)[0] >> 1) & 1, hex(d7.read("enc", 0)[0]))
+    check("demo: interlock open -> no 409 any more",
+          server.write_gate_reason(d7, "enc", 0x400) is None)
+    d7.write("enc", 0x400, 0x00000001)
+    check("demo: and the write ARRIVES (the 200 case)",
+          d7.read("enc", 0x400)[0] & 1 == 1, hex(d7.read("enc", 0x400)[0]))
+    d7.write("enc", 0x000, server.rmw_value("enc", 0, d7.read("enc", 0)[0] | 2))
+    check("demo: switched back -> 409 again (bar closes)",
+          (server.write_gate_reason(d7, "enc", 0x400) or "").startswith(
+              "CONFLICT")
+          and (d7.read("enc", 0)[0] >> 1) & 1 == 1)
+    check("demo: the switch did NOT clear the overflow evidence "
+          "(b12 was 0 and stays 0 -- w1c)",
+          not (d7.read("enc", 0)[0] >> 12) & 1)
+
+    # --- and what the switch does to the STREAM (demo pump, 3 windows) ----
+    # The warning next to the switch claims "the sinks run dry". A claim in a
+    # tooltip is not a measurement -- here it is measured.
+    import time as _t
+    d8 = server.DemoBus(sc)
+    d8.write("enc", 0x000, 0x00000007)
+    for e in ("enc1", "enc2"):
+        if e in d8.mem:
+            d8.write(e, 0x000, 0x00000007)
+    d8.write("ctrl", sc.co("control"), 0x1)            # both cores go
+    _t.sleep(0.8)
+    b1 = d8.read("ctrl", sc.co("trace_bytes"))[0]
+    _t.sleep(0.8)
+    b2 = d8.read("ctrl", sc.co("trace_bytes"))[0]
+    check("demo pump runs at all (reference window)", b2 > b1,
+          "%d -> %d" % (b1, b2))
+    for e in ("enc", "enc1", "enc2"):
+        if e in d8.mem:
+            d8.write(e, 0x000,
+                     server.rmw_value(e, 0, d8.read(e, 0)[0] & ~2))
+    _t.sleep(0.6)
+    b3 = d8.read("ctrl", sc.co("trace_bytes"))[0]
+    _t.sleep(0.8)
+    b4 = d8.read("ctrl", sc.co("trace_bytes"))[0]
+    check("Enable=0 -> the stream dries up while the cores are RUNNING",
+          b4 == b3 and d8.read("ctrl", sc.co("control"))[0] & 1 == 1,
+          "%d -> %d, CONTROL=0x%X"
+          % (b3, b4, d8.read("ctrl", sc.co("control"))[0]))
+    for e in ("enc", "enc1", "enc2"):
+        if e in d8.mem:
+            d8.write(e, 0x000, server.rmw_value(e, 0, d8.read(e, 0)[0] | 2))
+    _t.sleep(0.8)
+    b5 = d8.read("ctrl", sc.co("trace_bytes"))[0]
+    check("Enable=1 -> it comes back (counter-check; otherwise it would be a hang)",
+          b5 > b4, "%d -> %d" % (b4, b5))
+
+    # --- 256 MiB window, rejection display, cap for the raw dump ----------
+    # Three things the bitstream brings to the board and the dashboard has to
+    # carry along. The most expensive mistake here would NOT be a wrong
+    # number but a number that lives in the dashboard instead of in the
+    # register: the window size holds PER BITSTREAM VARIANT (rocket/cva6_*
+    # stay at 64 MiB), and a constant in the code would be wrong there
+    # immediately.
+    print("== U8: DDR window 256 MiB, SINK_STAT b4, dump cap ==")
+    rm = _j.loads((HERE / "regmap.json").read_text(encoding="utf-8"))
+    byp = {r["path"]: r for r in rm["regs"]}
+    f_of = lambda p, n: next(  # noqa: E731
+        (f for f in byp[p]["fields"] if f["name"] == n), None)
+    # A drift guard against the RTL, not against itself: the reset values of
+    # the register map are READ from ct_trace_sinks.sv. Exactly that coupling
+    # was missing before -- the old map value 0x6000_0000 was still in place
+    # long after the RTL had moved to 0x5000_0000.
+    # rtl/board_kv260/ is the KV260 SoC-top tree, migrated under AP4 (this
+    # file only covers the dashboard, AP5) -- without it, the drift GUARD
+    # cannot run, but that is not the same as the guarded FACT being wrong.
+    # SKIP, not FAIL, and do not silently drop the two regmap-only checks
+    # below it either -- reset() below still runs.
+    sinks_sv_path = HERE.parents[1] / "rtl" / "board_kv260" / "ct_trace_sinks.sv"
+    if not sinks_sv_path.is_file():
+        skip("RTL reset drift guard (ct_trace_sinks.sv vs. regmap.json)",
+             "%s is not part of this example (KV260 RTL migrates under AP4)"
+             % sinks_sv_path)
+        rtl_base = f_of("soc.DDR_BASE", "Value")["reset"]
+        rtl_size = f_of("soc.DDR_SIZE", "Value")["reset"]
+    else:
+        sinks_sv = sinks_sv_path.read_text(encoding="utf-8")
+        m_b = _re.search(r"DDR_BASE_RST\s*=\s*32'h([0-9a-fA-F_]+)", sinks_sv)
+        m_s = _re.search(r"DDR_SIZE_RST\s*=\s*32'h([0-9a-fA-F_]+)", sinks_sv)
+        rtl_base = int(m_b.group(1).replace("_", ""), 16) if m_b else None
+        rtl_size = int(m_s.group(1).replace("_", ""), 16) if m_s else None
+        check("RTL reset read from ct_trace_sinks.sv (address plan v4)",
+              (rtl_base, rtl_size) == (0x50000000, 0x10000000),
+              "0x%X + 0x%X" % (rtl_base or 0, rtl_size or 0))
+        check("register tab: DDR_BASE reset == RTL",
+              f_of("soc.DDR_BASE", "Value")["reset"] == rtl_base,
+              "0x%X" % (f_of("soc.DDR_BASE", "Value")["reset"] or 0))
+        check("register tab: DDR_SIZE reset == RTL (256 MiB)",
+              f_of("soc.DDR_SIZE", "Value")["reset"] == rtl_size,
+              "0x%X" % (f_of("soc.DDR_SIZE", "Value")["reset"] or 0))
+    check("the register tab names the variant dependency (the tops with "
+          "their own sink wiring stay at 0x6000_0000)",
+          "0x6000_0000" in byp["soc.DDR_BASE"]["desc"]
+          and "cva6_linux" in byp["soc.DDR_BASE"]["desc"])
+    rej = f_of("soc.SINK_STAT", "ddr_cfg_rej")
+    check("SINK_STAT carries b4 ddr_cfg_rej (U6 bar)",
+          rej is not None and rej["lsb"] == 4 and rej["msb"] == 4
+          and rej["sw"] == "r", str(rej and (rej["lsb"], rej["sw"])))
+    for p in ("soc.DDR_BASE", "soc.DDR_SIZE"):
+        check("%s: access_rule says that a write at ddr_en=1 is REJECTED "
+              "(no longer 'freely writable')" % p,
+              "REFUSED" in f_of(p, "Value")["access_rule"]
+              and "ddr_cfg_rej" in f_of(p, "Value")["access_rule"])
+    check("the ddr_clear description names the new bit as clearable",
+          "ddr_cfg_rej" in f_of("soc.SINK_CTRL", "ddr_clear")["desc"])
+
+    # The server's window check against the NEW window -- the same resmem
+    # proof as before, only with the numbers of the current bitstream.
+    _real_rr2 = server.resmem_ranges
+    try:
+        server.resmem_ranges = lambda: [(0x50000000, 0x20000000,
+                                         "ctrace-pl-ddr")]
+        ok256, note256 = server.ddr_window_ok(0x50000000, 0x10000000)
+        check("resmem evidence carries 0x5000_0000 + 256 MiB (U6 reset)",
+              ok256 is True, note256)
+        check("counter-check: 0x5000_0000 + 768 MiB reaches past and is "
+              "rejected",
+              server.ddr_window_ok(0x50000000, 0x30000000)[0] is False)
+
+        class _LiveBus8(FakeBus):
+            demo = False
+        lb8 = _LiveBus8({"ctrl": {sc.co("sink_ctrl"): 0,
+                                  sc.co("ddr_base"): 0x50000000,
+                                  sc.co("ddr_size"): 0x10000000}})
+        r8 = server.arm_default_sinks(lb8, sc)
+        check("the bind arms with the U6 defaults (0x5 in SINK_CTRL)",
+              r8.get("state") == "armed"
+              and lb8.read("ctrl", sc.co("sink_ctrl"))[0] == 0x5, str(r8)[:120])
+        check("and the evidence in the log names the new window",
+              "0x50000000+0x10000000" in (r8.get("ddr_window") or ""),
+              r8.get("ddr_window"))
+    finally:
+        server.resmem_ranges = _real_rr2
+
+    # Cap: numbers first, then the bytes. `?max=` is the explicit way to a
+    # full dump -- without it the cap would amount to data loss.
+    check("the cap default is 32 MiB, the maximum 256 MiB",
+          server.DUMP_CAP_DEFAULT == 32 << 20
+          and server.DUMP_CAP_MAX == 256 << 20)
+    check("without ?max the default applies",
+          server.dump_cap_arg({}) == server.DUMP_CAP_DEFAULT)
+    check("?max=0 raises the cap to the maximum",
+          server.dump_cap_arg({"max": ["0"]}) == server.DUMP_CAP_MAX)
+    check("?max=1024 is accepted",
+          server.dump_cap_arg({"max": ["1024"]}) == 1024)
+    check("?max beyond the maximum is clamped (no suicide on "
+          "request)",
+          server.dump_cap_arg({"max": ["0x40000000"]}) == server.DUMP_CAP_MAX)
+
+    class _DdrBus(FakeBus):
+        """Live bus stub with physical memory behind the window."""
+        demo = False
+
+        def __init__(self, init, base, blob):
+            super().__init__(init)
+            self.base, self.blob, self.reads = base, blob, []
+
+        def phys_read(self, addr, n):
+            self.reads.append((addr, n))
+            off = addr - self.base
+            assert 0 <= off and off + n <= len(self.blob), \
+                "read access 0x%X+%d leaves the buffer" % (addr, n)
+            return self.blob[off:off + n]
+
+    BASE, SIZE = 0x50000000, 4096
+    blob = bytes((i * 7 + 3) & 0xFF for i in range(SIZE))
+    mk_bus = lambda ctl, stat, wptr: _DdrBus(  # noqa: E731
+        {"ctrl": {sc.co("ddr_base"): BASE, sc.co("ddr_size"): SIZE,
+                  sc.co("ddr_wptr"): wptr, sc.co("sink_ctrl"): ctl,
+                  sc.co("sink_stat"): stat}}, BASE, blob)
+
+    # (a) linear, not yet wrapped: the NEWEST bytes sit at the end. The start
+    # moves FORWARD onto the 32-byte burst edge (al(600) = 608), which makes
+    # the dump at most 31 bytes shorter than the cap -- never longer, and
+    # never at a misaligned address (that was the SIGBUS).
+    inf = {}
+    bus_a = mk_bus(0x1, 0x0, 1000)
+    got = server.dump_bytes(bus_a, "ddr", sc=sc, cap=400, info=inf)
+    check("cap, linear: the newest bytes from the burst edge 608",
+          got == blob[608:1000] and len(got) == 392, "%d B" % len(got))
+    check("and the balance names the truncation",
+          inf == {"available": 1000, "returned": 392, "capped": True},
+          str(inf))
+    inf2 = {}
+    bus_f = mk_bus(0x1, 0x0, 1000)
+    full = server.dump_bytes(bus_f, "ddr", sc=sc, cap=0, info=inf2)
+    check("without a cap the same dump as before (counter-check: nothing "
+          "missing, not even 31 bytes through the alignment)",
+          full == blob[:1000] and inf2["capped"] is False, "%d B" % len(full))
+
+    # (b) circular + wrapped: chronologically it is [off..size) ++ [0..off).
+    WP = SIZE + 300                      # wrapped once, off = 300
+    chrono = blob[300:] + blob[:300]
+    inf3 = {}
+    bus_c = mk_bus(0x5, 0x4, WP)
+    got3 = server.dump_bytes(bus_c, "ddr", sc=sc, cap=0, info=inf3)
+    check("ring uncapped: chronological order unchanged",
+          got3 == chrono and inf3["available"] == SIZE, "%d B" % len(got3))
+    inf4 = {}
+    bus_d = mk_bus(0x5, 0x4, WP)
+    got4 = server.dump_bytes(bus_d, "ddr", sc=sc, cap=500, info=inf4)
+    check("ring capped: the newest bytes end at the write pointer "
+          "(start on the burst edge 3904)",
+          got4 == chrono[-492:] and got4 == blob[3904:4096] + blob[:300],
+          "%d B" % len(got4))
+    check("and the cap does not read past the window "
+          "(two pieces instead of one that is too long)",
+          inf4 == {"available": SIZE, "returned": 492, "capped": True}
+          and bus_d.reads == [(BASE + 3904, 192), (BASE, 300)],
+          "%s %s" % (inf4, bus_d.reads))
+    b5 = mk_bus(0x5, 0x4, WP)
+    server.dump_bytes(b5, "ddr", sc=sc, cap=200, info={})
+    check("ring capped without a seam: ONE read access, directly in front "
+          "of the write pointer", b5.reads == [(BASE + 128, 172)], str(b5.reads))
+    # The guard for the crash class: EVERY physical read address sits on the
+    # 32-byte edge. On the board exactly one misaligned address
+    # (0x5096FA3FC, page offset 0x3FC) ended the service with SIGBUS -- the
+    # reserved window is `no-map`, so the mapping is device memory, and a
+    # memcpy using LDP/NEON walks into an alignment trap there.
+    capreads = bus_a.reads + bus_d.reads + b5.reads
+    check("every CAPPED read address sits on the 32-byte burst edge "
+          "(%d accesses)" % len(capreads),
+          all(a % 32 == 0 for a, _ in capreads),
+          str([hex(a) for a, _ in capreads if a % 32]))
+    # The uncapped ring dump starts at the write offset and is ONLY 4-byte
+    # aligned (0x5000012C in the example) -- that was already the case before
+    # and it is fine, BECAUSE the alignment is now ensured inside phys_read
+    # instead of at the caller. That is exactly what the next guard checks,
+    # and it checks it by executing: a mapping mock that behaves like device
+    # memory and REJECTS a misaligned copy start.
+    class BusFault(Exception):
+        """stands here for the SIGBUS a real kernel would send."""
+
+    class _DevMap:
+        """mmap stub with the strictness of Device-nGnRE memory."""
+
+        def __init__(self, blob):
+            self.blob = blob
+
+        def __getitem__(self, sl):
+            if (sl.start or 0) % 16:
+                raise BusFault("unaligned bulk copy on device memory (SIGBUS)")
+            return self.blob[sl]
+
+        def close(self):
+            pass
+
+    import threading as _thr
+
+    class _Stub:
+        fd = -1
+        lock = _thr.Lock()
+
+    phys = bytes((i * 13 + 5) & 0xFF for i in range(2 * 4096))
+
+    class _FakeMmapMod:
+        """Stand-in for the mmap module: the constants MAP_SHARED/PROT_READ do
+        not exist on Windows at all -- the guard is meant to check the logic,
+        not the host system."""
+        MAP_SHARED, PROT_READ = 1, 1
+
+        @staticmethod
+        def mmap(fd, ln, flags=0, prot=0, offset=0):
+            base = offset - 0x50000000
+            return _DevMap(phys[base:base + ln])
+
+    real_mmap = server.mmap
+    try:
+        server.mmap = _FakeMmapMod
+        def _pr(addr, n):
+            """The stub throws where the kernel would send SIGBUS -- a throw
+            must not abort the guard, it is its RED result."""
+            try:
+                return server.HwBus.phys_read(_Stub(), addr, n)
+            except BusFault as e:                            # noqa: BLE001
+                return e
+
+        got_p = _pr(0x50000000 + 0x3FC, 1024)
+        check("phys_read reads from an ODD address without error "
+              "(the device stub would reject an odd copy start)",
+              got_p == phys[0x3FC:0x3FC + 1024], str(got_p)[:90])
+        got_q = _pr(0x50000000 + 0x1000, 64)
+        check("and the aligned case delivers the same as before",
+              got_q == phys[0x1000:0x1040], str(got_q)[:90])
+    finally:
+        server.mmap = real_mmap
+    check("phys_read copies from the PAGE START (not from the odd "
+          "address) -- the fix of the crash class for ALL callers",
+          "raw = bytes(m[0:span])" in srv and "span = (off + n + 15) & ~15" in srv)
+    inf6 = {}
+    got6 = server.dump_bytes(mk_bus(0x1, 0x0, 0), "ddr", sc=sc, cap=400,
+                             info=inf6)
+    check("an empty buffer stays empty (no truncation claimed)",
+          got6 == b"" and inf6 == {"available": 0, "returned": 0,
+                                   "capped": False}, str(inf6))
+
+    check("server: /api/state names the cap (the user interface does not "
+          "invent it)", 'vals["dump_cap"] = DUMP_CAP_DEFAULT' in srv)
+    check("server: the truncated dump has a different file name (_tail)",
+          '"_tail" if info.get("capped") else ""' in srv)
+    check("server: the answer carries the balance in its header",
+          "X-Dump-Available" in srv and "X-Dump-Capped" in srv)
+    check("server: the decode path uses THE SAME cap (NexRv does not get "
+          "256 MiB)",
+          srv.count("cap=dump_cap_arg(q)") == 2)
+    check("server: the ring window is no longer called `cap` (the old "
+          "double use would have set the cap to 1 MiB)",
+          "ring = bus.read(\"ctrl\", sc.co(\"trace_bufsz\"))" in srv)
+
+    # User interface: display of the rejected window write + the cap hint.
+    check("index.html: b4 has a name in the code (not a bare 0x10)",
+          "const DDR_CFG_REJ=0x10;" in idx)
+    check("the DDR card shows the rejection as a WORD",
+          "drej?'cfg!'" in idx and "classList.toggle('rej',drej)" in idx)
+    # Measured on the board: the DDR card is 112 model units wide and clips
+    # with overflow:hidden -- an appended "cfg refused" was gone. The
+    # rejection therefore REPLACES the mode word. What gets checked is the
+    # only promise this change can make: it does NOT make the line longer
+    # than it already was (the existing line "ring · w8" already barely
+    # fits; shortening it is the business of whoever touches the geometry in
+    # the generator -- gui/ is off limits here).
+    ddrw = next((n["w"] for n in (geo.get("tgc5b2_axis_wp") or {})["nodes"]
+                 if n["id"] == "ddr"), 0)
+    rej_line, old_line = len("cfg! · drops 0"), len("ring · w8 · drops 0")
+    check("the rejection line is SHORTER than the existing line (%d < %d "
+          "characters at %d units of block width)" % (rej_line, old_line, ddrw),
+          rej_line < old_line and ddrw > 0)
+    check("the rejection replaces the mode (no appending that would get "
+          "truncated)",
+          "dw.textContent=drej?'cfg!'" in idx)
+    check("the long form goes where there is room (the log, ONCE per "
+          "rejection)",
+          "let DDRREJ=false;" in idx and "if(drej&&!DDRREJ){" in idx
+          and "DDR window write REFUSED (SINK_STAT b4 ddr_cfg_rej)" in idx)
+    check("the rejection is not marked by colour alone",
+          ".sinksw.rej{" in idx)
+    check("the hover panel of the DDR card carries the state as a row of its own",
+          "['window write'," in idx and "REFUSED while armed" in idx)
+    # This used to prove that `apply` reads back instead of reporting
+    # "applied". The button has since been REMOVED -- the proof therefore
+    # moves into the read-only block below (no input field, no apply, server
+    # 403). The old check stays in its NEGATIVE form: it speaks up if the
+    # path comes back.
+    check("the apply panel of U8 is GONE (U9: the window is display only now)",
+          "#b_dapply" not in idx
+          and "Size and base are REFUSED while the sink is armed" not in idx)
+    check("the dump cap is stated at BOTH buttons (panel + "
+          "Trace & Decode)",
+          "esc(dumpHint(src))" in idx and "$('dl_cap').textContent" in idx)
+    check("the hint takes the number from /api/state, not from the HTML",
+          "(STATE||{}).dump_cap" in idx and "dump_cap=" not in idx)
+    check("the hint names the way to the full dump",
+          "append &max=0 to " in idx)
+
+    # ------------------------------------------------------------------
+    # the DDR window is display only, and the server says no
+    # ------------------------------------------------------------------
+    # Requirement after the click test: Apply went through without a murmur,
+    # so not only the SIZE has to be protected but the OFFSET as well -- both
+    # read-only, because a window that can be shoved around the address space
+    # disturbs the hosting Ubuntu. Found on the board: DDR_BASE = DDR_SIZE =
+    # 0x8000_0000, sink armed, WPTR 0, every beat discarded.
+    print("== U9: DDR window read-only (user interface + server) ==")
+    check("the panel has NO input field for size/base any more",
+          'id="in_dsz"' not in idx and 'id="in_dba"' not in idx)
+    check("and no write path to the two registers (not even a "
+          "hidden one)",
+          "ctrlOff('ddr_size')" not in idx and "ctrlOff('ddr_base')" not in idx)
+    seg9 = idx.split('Mode:\n