From 69b3cfeb64dea38f086e47a02e0de44d5ddac611 Mon Sep 17 00:00:00 2001 From: Ram Sargar Date: Sat, 5 Sep 2026 12:52:26 +0530 Subject: [PATCH 1/7] Revert "QCLINUX: arm64: dts: qcom: lemans: Add RTSS Mailbox device tree overlay" This reverts commit f9e0c595ae6b2cf49eb01626284000621aea0fa7. The original overlay accessed the APSS TCSR mutex/status registers via direct memory-mapped reg ranges and shipped RTSS as a standalone lemans-rtss-mb.dtso overlay. Upstream review feedback on this design requires: - Accessing the TCSR registers via a syscon phandle instead of a direct reg-mapped node. - Folding the RTSS mailbox node into the shared lemans-staging.dtso overlay instead of a separate, RTSS-only DTBO. The following commits reintroduce this support using that syscon-based, staging-overlay design. Signed-off-by: Ram Sargar --- arch/arm64/boot/dts/qcom/Makefile | 1 - arch/arm64/boot/dts/qcom/lemans-rtss-mb.dtso | 65 -------------------- 2 files changed, 66 deletions(-) delete mode 100644 arch/arm64/boot/dts/qcom/lemans-rtss-mb.dtso diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 6577a1c826bc5..7f17dd5c3d6b4 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -488,7 +488,6 @@ dtb-$(CONFIG_ARCH_QCOM) += lemans-camx-el2.dtb dtb-$(CONFIG_ARCH_QCOM) += lemans-evk-staging.dtbo -dtb-$(CONFIG_ARCH_QCOM) += lemans-rtss-mb.dtbo dtb-$(CONFIG_ARCH_QCOM) += lemans-staging.dtbo monaco-evk-camx-dtbs := monaco-evk.dtb monaco-evk-camx.dtbo diff --git a/arch/arm64/boot/dts/qcom/lemans-rtss-mb.dtso b/arch/arm64/boot/dts/qcom/lemans-rtss-mb.dtso deleted file mode 100644 index b1d8996c9ea8b..0000000000000 --- a/arch/arm64/boot/dts/qcom/lemans-rtss-mb.dtso +++ /dev/null @@ -1,65 +0,0 @@ -// SPDX-License-Identifier: BSD-3-Clause -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - */ - -/dts-v1/; -/plugin/; - -#include -#include -#include - -&soc { - ipcc_computeL1: qcom,ipcc@488000 { - compatible = "qcom,ipcc"; - reg = <0x0 0x00488000 0x0 0x1000>; - interrupts = ; - interrupt-controller; - #interrupt-cells = <3>; - #mbox-cells = <2>; - num_mbox_chans = <5>; - }; - - rtss_mailbox: rtss-mailbox@1ffe02c { - compatible = "qcom,rtss-mailbox"; - reg = <0x0 0x01ffe02c 0x0 0x10>, - <0x0 0x01ffd018 0x0 0x10>, - <0x0 0x17c0000c 0x0 0x04>; - mboxes = <&ipcc_computeL1 IPCC_CLIENT_RTSS0 0x2>, - <&ipcc_computeL1 IPCC_CLIENT_RTSS1 0x3>, - <&ipcc_computeL1 IPCC_CLIENT_RTSS0 0x4>, - <&ipcc_computeL1 IPCC_CLIENT_RTSS0 0x5>, - <&ipcc_computeL1 IPCC_CLIENT_RTSS0 0x6>, - <&ipcc_computeL1 IPCC_CLIENT_RTSS0 0x7>, - <&ipcc_computeL1 IPCC_CLIENT_RTSS2 0x8>, - <&ipcc_computeL1 IPCC_CLIENT_RTSS1 0x9>, - <&ipcc_computeL1 IPCC_CLIENT_RTSS2 0xa>, - <&ipcc_computeL1 IPCC_CLIENT_RTSS1 0xb>, - <&ipcc_computeL1 IPCC_CLIENT_RTSS0 0xc>, - <&ipcc_computeL1 IPCC_CLIENT_RTSS0 0xd>, - <&ipcc_computeL1 IPCC_CLIENT_RTSS1 0xe>, - <&ipcc_computeL1 IPCC_CLIENT_RTSS2 0xf>, - <&ipcc_computeL1 IPCC_CLIENT_RTSS3 0x10>; - memory-region = <&sail_mailbox_mem>, - <&sail_ota_mem>; - interrupt-parent = <&ipcc_computeL1>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - rtss-handshake-delay = <50000>; - status = "okay"; - }; -}; From 1c113825f3afca10601e050e5d94848017ea88ec Mon Sep 17 00:00:00 2001 From: Ram Sargar Date: Sat, 5 Sep 2026 12:52:26 +0530 Subject: [PATCH 2/7] Revert "QCLINUX: arm64: dts: qcom: Monaco: Add RTSS Mailbox device tree overlay" This reverts commit 5c6149c05f6ce5a14a7c10fe4bc8d54fdb05ea88. Same as the lemans overlay, the original Monaco overlay accessed the APSS TCSR mutex/status registers via direct memory-mapped reg ranges and shipped RTSS as a standalone monaco-rtss-mb.dtso overlay. Upstream review feedback on this design requires: - Accessing the TCSR registers via a syscon phandle instead of a direct reg-mapped node. - Folding the RTSS mailbox node into the shared monaco-staging.dtso overlay instead of a separate, RTSS-only DTBO. The following commits reintroduce this support using that syscon-based, staging-overlay design. Signed-off-by: Ram Sargar --- arch/arm64/boot/dts/qcom/Makefile | 1 - arch/arm64/boot/dts/qcom/monaco-rtss-mb.dtso | 65 -------------------- 2 files changed, 66 deletions(-) delete mode 100644 arch/arm64/boot/dts/qcom/monaco-rtss-mb.dtso diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 7f17dd5c3d6b4..4704c32b5bfc2 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -500,7 +500,6 @@ monaco-camx-el2-dtbs := monaco-evk-el2.dtb monaco-evk-camx.dtbo monaco-camx-el2. dtb-$(CONFIG_ARCH_QCOM) += monaco-camx-el2.dtb dtb-$(CONFIG_ARCH_QCOM) += monaco-evk-staging.dtbo -dtb-$(CONFIG_ARCH_QCOM) += monaco-rtss-mb.dtbo dtb-$(CONFIG_ARCH_QCOM) += monaco-staging.dtbo diff --git a/arch/arm64/boot/dts/qcom/monaco-rtss-mb.dtso b/arch/arm64/boot/dts/qcom/monaco-rtss-mb.dtso deleted file mode 100644 index b1d8996c9ea8b..0000000000000 --- a/arch/arm64/boot/dts/qcom/monaco-rtss-mb.dtso +++ /dev/null @@ -1,65 +0,0 @@ -// SPDX-License-Identifier: BSD-3-Clause -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - */ - -/dts-v1/; -/plugin/; - -#include -#include -#include - -&soc { - ipcc_computeL1: qcom,ipcc@488000 { - compatible = "qcom,ipcc"; - reg = <0x0 0x00488000 0x0 0x1000>; - interrupts = ; - interrupt-controller; - #interrupt-cells = <3>; - #mbox-cells = <2>; - num_mbox_chans = <5>; - }; - - rtss_mailbox: rtss-mailbox@1ffe02c { - compatible = "qcom,rtss-mailbox"; - reg = <0x0 0x01ffe02c 0x0 0x10>, - <0x0 0x01ffd018 0x0 0x10>, - <0x0 0x17c0000c 0x0 0x04>; - mboxes = <&ipcc_computeL1 IPCC_CLIENT_RTSS0 0x2>, - <&ipcc_computeL1 IPCC_CLIENT_RTSS1 0x3>, - <&ipcc_computeL1 IPCC_CLIENT_RTSS0 0x4>, - <&ipcc_computeL1 IPCC_CLIENT_RTSS0 0x5>, - <&ipcc_computeL1 IPCC_CLIENT_RTSS0 0x6>, - <&ipcc_computeL1 IPCC_CLIENT_RTSS0 0x7>, - <&ipcc_computeL1 IPCC_CLIENT_RTSS2 0x8>, - <&ipcc_computeL1 IPCC_CLIENT_RTSS1 0x9>, - <&ipcc_computeL1 IPCC_CLIENT_RTSS2 0xa>, - <&ipcc_computeL1 IPCC_CLIENT_RTSS1 0xb>, - <&ipcc_computeL1 IPCC_CLIENT_RTSS0 0xc>, - <&ipcc_computeL1 IPCC_CLIENT_RTSS0 0xd>, - <&ipcc_computeL1 IPCC_CLIENT_RTSS1 0xe>, - <&ipcc_computeL1 IPCC_CLIENT_RTSS2 0xf>, - <&ipcc_computeL1 IPCC_CLIENT_RTSS3 0x10>; - memory-region = <&sail_mailbox_mem>, - <&sail_ota_mem>; - interrupt-parent = <&ipcc_computeL1>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - rtss-handshake-delay = <50000>; - status = "okay"; - }; -}; From 85b8978ea03e50577fda850d84ea5c6f72743323 Mon Sep 17 00:00:00 2001 From: Ram Sargar Date: Sat, 5 Sep 2026 11:24:11 +0530 Subject: [PATCH 3/7] QCLINUX: arm64: dts: qcom: lemans: Add IPCC and syscon nodes for RTSS Mailbox Add ipcc1-ipcc4 mailbox controllers and apss_tcsr_req, apss_tcsr_resp, apss_shared_ipc syscon nodes for Lemans platform, required by the RTSS Mailbox device node. Signed-off-by: Ram Sargar --- arch/arm64/boot/dts/qcom/lemans.dtsi | 51 ++++++++++++++++++++++++++++ 1 file changed, 51 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/lemans.dtsi b/arch/arm64/boot/dts/qcom/lemans.dtsi index e59f30ce6dd1d..f3fe10fa66183 100644 --- a/arch/arm64/boot/dts/qcom/lemans.dtsi +++ b/arch/arm64/boot/dts/qcom/lemans.dtsi @@ -1130,6 +1130,57 @@ #mbox-cells = <2>; }; + ipcc1: mailbox@488000 { + compatible = "qcom,sa8775p-ipcc", "qcom,ipcc"; + reg = <0x0 0x00488000 0x0 0x1000>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <3>; + #mbox-cells = <2>; + }; + + ipcc2: mailbox@4a1000 { + compatible = "qcom,sa8775p-ipcc", "qcom,ipcc"; + reg = <0x0 0x004a1000 0x0 0x1000>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <3>; + #mbox-cells = <2>; + }; + + ipcc3: mailbox@4a2000 { + compatible = "qcom,sa8775p-ipcc", "qcom,ipcc"; + reg = <0x0 0x004a2000 0x0 0x1000>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <3>; + #mbox-cells = <2>; + }; + + ipcc4: mailbox@4a3000 { + compatible = "qcom,sa8775p-ipcc", "qcom,ipcc"; + reg = <0x0 0x004a3000 0x0 0x1000>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <3>; + #mbox-cells = <2>; + }; + + apss_tcsr_req: syscon@1ffe02c { + compatible = "qcom,sa8775p-tcsr", "syscon"; + reg = <0x0 0x1ffe02c 0x0 0x10>; + }; + + apss_tcsr_resp: syscon@1ffd018 { + compatible = "qcom,sa8775p-tcsr", "syscon"; + reg = <0x0 0x1ffd018 0x0 0x10>; + }; + + apss_shared_ipc: syscon@17c0000c { + compatible = "qcom,sa8775p-tcsr", "syscon"; + reg = <0x0 0x17c0000c 0x0 0x4>; + }; + qfprom: efuse@784000 { compatible = "qcom,sa8775p-qfprom", "qcom,qfprom"; reg = <0x0 0x00784000 0x0 0x3000>; From 82b77ee79b56773bf3b219c3a0879912fe5f6409 Mon Sep 17 00:00:00 2001 From: Ram Sargar Date: Sat, 5 Sep 2026 11:24:29 +0530 Subject: [PATCH 4/7] QCLINUX: arm64: dts: qcom: lemans: Add RTSS Mailbox device tree node Add rtss_mailbox device node for Lemans platform, syscon-based, using ipcc1-ipcc4 and the apss_tcsr_req/apss_tcsr_resp/apss_shared_ipc syscon nodes. Signed-off-by: Ram Sargar --- arch/arm64/boot/dts/qcom/lemans-staging.dtso | 49 ++++++++++++++++++++ 1 file changed, 49 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/lemans-staging.dtso b/arch/arm64/boot/dts/qcom/lemans-staging.dtso index d09d8dba42a37..d832ea8ab11f9 100644 --- a/arch/arm64/boot/dts/qcom/lemans-staging.dtso +++ b/arch/arm64/boot/dts/qcom/lemans-staging.dtso @@ -8,9 +8,58 @@ /dts-v1/; /plugin/; #include +#include #include +#include &soc { + rtss_mailbox: rtss-mailbox { + compatible = "qcom,rtss-mailbox"; + qcom,syscon-tcsr-req = <&apss_tcsr_req>; + qcom,req-tcsr-offset = <0x0>; + qcom,syscon-tcsr-resp = <&apss_tcsr_resp>; + qcom,resp-tcsr-offset = <0x0>; + qcom,syscon-ipc = <&apss_shared_ipc>; + qcom,ipc-offset = <0x0>; + qcom,handshake-magic = <0xD0000000 0xD0020000 0xD0030000>; + qcom,handshake-delay = <0x0000C350>; + qcom,handle-offset = <0x80000 0x80000>; + qcom,client-lut = <0x488000 0x8>, <0x4a1000 0x21>, <0x4a2000 0x22>, <0x4a3000 0x23>; + mboxes = <&ipcc1 IPCC_CLIENT_RTSS0 0x2>, + <&ipcc1 IPCC_CLIENT_RTSS1 0x3>, + <&ipcc1 IPCC_CLIENT_RTSS0 0x4>, + <&ipcc1 IPCC_CLIENT_RTSS0 0x5>, + <&ipcc1 IPCC_CLIENT_RTSS0 0x6>, + <&ipcc1 IPCC_CLIENT_RTSS0 0x7>, + <&ipcc1 IPCC_CLIENT_RTSS2 0x8>, + <&ipcc1 IPCC_CLIENT_RTSS1 0x9>, + <&ipcc1 IPCC_CLIENT_RTSS2 0xa>, + <&ipcc1 IPCC_CLIENT_RTSS1 0xb>, + <&ipcc1 IPCC_CLIENT_RTSS0 0xc>, + <&ipcc1 IPCC_CLIENT_RTSS0 0xd>, + <&ipcc1 IPCC_CLIENT_RTSS1 0xe>, + <&ipcc1 IPCC_CLIENT_RTSS2 0xf>, + <&ipcc1 IPCC_CLIENT_RTSS3 0x10>; + interrupts-extended = <&ipcc1 IPCC_CLIENT_RTSS0 0x2 IRQ_TYPE_EDGE_RISING>, + <&ipcc1 IPCC_CLIENT_RTSS1 0x3 IRQ_TYPE_EDGE_RISING>, + <&ipcc1 IPCC_CLIENT_RTSS0 0x4 IRQ_TYPE_EDGE_RISING>, + <&ipcc1 IPCC_CLIENT_RTSS0 0x5 IRQ_TYPE_EDGE_RISING>, + <&ipcc1 IPCC_CLIENT_RTSS0 0x6 IRQ_TYPE_EDGE_RISING>, + <&ipcc1 IPCC_CLIENT_RTSS0 0x7 IRQ_TYPE_EDGE_RISING>, + <&ipcc1 IPCC_CLIENT_RTSS2 0x8 IRQ_TYPE_EDGE_RISING>, + <&ipcc1 IPCC_CLIENT_RTSS1 0x9 IRQ_TYPE_EDGE_RISING>, + <&ipcc1 IPCC_CLIENT_RTSS2 0xa IRQ_TYPE_EDGE_RISING>, + <&ipcc1 IPCC_CLIENT_RTSS1 0xb IRQ_TYPE_EDGE_RISING>, + <&ipcc1 IPCC_CLIENT_RTSS0 0xc IRQ_TYPE_EDGE_RISING>, + <&ipcc1 IPCC_CLIENT_RTSS0 0xd IRQ_TYPE_EDGE_RISING>, + <&ipcc1 IPCC_CLIENT_RTSS1 0xe IRQ_TYPE_EDGE_RISING>, + <&ipcc1 IPCC_CLIENT_RTSS2 0xf IRQ_TYPE_EDGE_RISING>, + <&ipcc1 IPCC_CLIENT_RTSS3 0x10 IRQ_TYPE_EDGE_RISING>; + memory-region = <&sail_mailbox_mem>, + <&sail_ota_mem>; + status = "okay"; + }; + tgu@4b0e000 { compatible = "qcom,tgu", "arm,primecell"; reg = <0x0 0x4b0e000 0x0 0x1000>; From 1704c1ec8d8b9fad6f9a36c91940a677466c4f32 Mon Sep 17 00:00:00 2001 From: Ram Sargar Date: Sat, 5 Sep 2026 12:08:36 +0530 Subject: [PATCH 5/7] QCLINUX: arm64: dts: qcom: Monaco: Add SAIL/RTSS mailbox reserved-memory regions Reserve the memory regions used by the SAIL/RTSS subsystem for its TZ mailbox, shared-memory mailbox, and OTA buffer on Monaco. These regions back the memory-region references used by the Monaco RTSS mailbox node (qcom,rtss-mailbox). Signed-off-by: Ram Sargar --- arch/arm64/boot/dts/qcom/monaco.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/monaco.dtsi b/arch/arm64/boot/dts/qcom/monaco.dtsi index a32ee14603e7f..41157ae61b039 100644 --- a/arch/arm64/boot/dts/qcom/monaco.dtsi +++ b/arch/arm64/boot/dts/qcom/monaco.dtsi @@ -812,6 +812,21 @@ hwlocks = <&tcsr_mutex 3>; }; + tz_sail_mailbox_mem: tz-sail-mailbox@90c00000 { + reg = <0x0 0x90c00000 0x0 0x100000>; + no-map; + }; + + sail_mailbox_mem: sail-ss@90d00000 { + reg = <0x0 0x90d00000 0x0 0x100000>; + no-map; + }; + + sail_ota_mem: sail-ss@90e00000 { + reg = <0x0 0x90e00000 0x0 0x300000>; + no-map; + }; + gunyah_md_mem: gunyah-md-region@91a80000 { reg = <0x0 0x91a80000 0x0 0x80000>; no-map; From 4d7b44ab61cca7166891986539cef9cf2317bb09 Mon Sep 17 00:00:00 2001 From: Ram Sargar Date: Sat, 5 Sep 2026 12:08:54 +0530 Subject: [PATCH 6/7] QCLINUX: arm64: dts: qcom: Monaco: Add IPCC and syscon nodes for RTSS Mailbox Add ipcc1-4 mailbox nodes and the apss_tcsr_req/apss_tcsr_resp/ apss_shared_ipc syscon nodes on Monaco. These nodes back the syscon/mbox phandle references used by the Monaco RTSS mailbox node (qcom,rtss-mailbox). Signed-off-by: Ram Sargar --- arch/arm64/boot/dts/qcom/monaco.dtsi | 51 ++++++++++++++++++++++++++++ 1 file changed, 51 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/monaco.dtsi b/arch/arm64/boot/dts/qcom/monaco.dtsi index 41157ae61b039..2b917b829e6b9 100644 --- a/arch/arm64/boot/dts/qcom/monaco.dtsi +++ b/arch/arm64/boot/dts/qcom/monaco.dtsi @@ -998,6 +998,57 @@ #mbox-cells = <2>; }; + ipcc1: mailbox@488000 { + compatible = "qcom,qcs8300-ipcc", "qcom,ipcc"; + reg = <0x0 0x00488000 0x0 0x1000>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <3>; + #mbox-cells = <2>; + }; + + ipcc2: mailbox@4a1000 { + compatible = "qcom,qcs8300-ipcc", "qcom,ipcc"; + reg = <0x0 0x004a1000 0x0 0x1000>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <3>; + #mbox-cells = <2>; + }; + + ipcc3: mailbox@4a2000 { + compatible = "qcom,qcs8300-ipcc", "qcom,ipcc"; + reg = <0x0 0x004a2000 0x0 0x1000>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <3>; + #mbox-cells = <2>; + }; + + ipcc4: mailbox@4a3000 { + compatible = "qcom,qcs8300-ipcc", "qcom,ipcc"; + reg = <0x0 0x004a3000 0x0 0x1000>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <3>; + #mbox-cells = <2>; + }; + + apss_tcsr_req: syscon@1ffe02c { + compatible = "qcom,qcs8300-tcsr", "syscon"; + reg = <0x0 0x1ffe02c 0x0 0x10>; + }; + + apss_tcsr_resp: syscon@1ffd018 { + compatible = "qcom,qcs8300-tcsr", "syscon"; + reg = <0x0 0x1ffd018 0x0 0x10>; + }; + + apss_shared_ipc: syscon@17c0000c { + compatible = "qcom,qcs8300-tcsr", "syscon"; + reg = <0x0 0x17c0000c 0x0 0x4>; + }; + qfprom: efuse@784000 { compatible = "qcom,qcs8300-qfprom", "qcom,qfprom"; reg = <0x0 0x00784000 0x0 0x2410>; From 81fbcfc82776b7c8b20ac702087559e6fab5c817 Mon Sep 17 00:00:00 2001 From: Ram Sargar Date: Sat, 5 Sep 2026 12:09:19 +0530 Subject: [PATCH 7/7] QCLINUX: arm64: dts: qcom: Monaco: Add RTSS Mailbox device tree node Add the rtss_mailbox overlay node on Monaco, mirroring the Lemans RTSS mailbox node added in commit 82b77ee79b567 ("QCLINUX: arm64: dts: qcom: lemans: Add RTSS Mailbox device tree node"). Signed-off-by: Ram Sargar --- arch/arm64/boot/dts/qcom/monaco-staging.dtso | 50 ++++++++++++++++++++ 1 file changed, 50 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/monaco-staging.dtso b/arch/arm64/boot/dts/qcom/monaco-staging.dtso index fc44741b8caab..61df6fb73fbf8 100644 --- a/arch/arm64/boot/dts/qcom/monaco-staging.dtso +++ b/arch/arm64/boot/dts/qcom/monaco-staging.dtso @@ -7,8 +7,58 @@ /dts-v1/; /plugin/; +#include +#include +#include &soc { + rtss_mailbox: rtss-mailbox { + compatible = "qcom,rtss-mailbox"; + qcom,syscon-tcsr-req = <&apss_tcsr_req>; + qcom,req-tcsr-offset = <0x0>; + qcom,syscon-tcsr-resp = <&apss_tcsr_resp>; + qcom,resp-tcsr-offset = <0x0>; + qcom,syscon-ipc = <&apss_shared_ipc>; + qcom,ipc-offset = <0x0>; + qcom,handshake-magic = <0xD0000000 0xD0020000 0xD0030000>; + qcom,handshake-delay = <0x0000C350>; + qcom,handle-offset = <0x80000 0x80000>; + qcom,client-lut = <0x488000 0x8>, <0x4a1000 0x21>, <0x4a2000 0x22>, <0x4a3000 0x23>; + mboxes = <&ipcc1 IPCC_CLIENT_RTSS0 0x2>, + <&ipcc1 IPCC_CLIENT_RTSS1 0x3>, + <&ipcc1 IPCC_CLIENT_RTSS0 0x4>, + <&ipcc1 IPCC_CLIENT_RTSS0 0x5>, + <&ipcc1 IPCC_CLIENT_RTSS0 0x6>, + <&ipcc1 IPCC_CLIENT_RTSS0 0x7>, + <&ipcc1 IPCC_CLIENT_RTSS2 0x8>, + <&ipcc1 IPCC_CLIENT_RTSS1 0x9>, + <&ipcc1 IPCC_CLIENT_RTSS2 0xa>, + <&ipcc1 IPCC_CLIENT_RTSS1 0xb>, + <&ipcc1 IPCC_CLIENT_RTSS0 0xc>, + <&ipcc1 IPCC_CLIENT_RTSS0 0xd>, + <&ipcc1 IPCC_CLIENT_RTSS1 0xe>, + <&ipcc1 IPCC_CLIENT_RTSS2 0xf>, + <&ipcc1 IPCC_CLIENT_RTSS3 0x10>; + interrupts-extended = <&ipcc1 IPCC_CLIENT_RTSS0 0x2 IRQ_TYPE_EDGE_RISING>, + <&ipcc1 IPCC_CLIENT_RTSS1 0x3 IRQ_TYPE_EDGE_RISING>, + <&ipcc1 IPCC_CLIENT_RTSS0 0x4 IRQ_TYPE_EDGE_RISING>, + <&ipcc1 IPCC_CLIENT_RTSS0 0x5 IRQ_TYPE_EDGE_RISING>, + <&ipcc1 IPCC_CLIENT_RTSS0 0x6 IRQ_TYPE_EDGE_RISING>, + <&ipcc1 IPCC_CLIENT_RTSS0 0x7 IRQ_TYPE_EDGE_RISING>, + <&ipcc1 IPCC_CLIENT_RTSS2 0x8 IRQ_TYPE_EDGE_RISING>, + <&ipcc1 IPCC_CLIENT_RTSS1 0x9 IRQ_TYPE_EDGE_RISING>, + <&ipcc1 IPCC_CLIENT_RTSS2 0xa IRQ_TYPE_EDGE_RISING>, + <&ipcc1 IPCC_CLIENT_RTSS1 0xb IRQ_TYPE_EDGE_RISING>, + <&ipcc1 IPCC_CLIENT_RTSS0 0xc IRQ_TYPE_EDGE_RISING>, + <&ipcc1 IPCC_CLIENT_RTSS0 0xd IRQ_TYPE_EDGE_RISING>, + <&ipcc1 IPCC_CLIENT_RTSS1 0xe IRQ_TYPE_EDGE_RISING>, + <&ipcc1 IPCC_CLIENT_RTSS2 0xf IRQ_TYPE_EDGE_RISING>, + <&ipcc1 IPCC_CLIENT_RTSS3 0x10 IRQ_TYPE_EDGE_RISING>; + memory-region = <&sail_mailbox_mem>, + <&sail_ota_mem>; + status = "okay"; + }; + tgu@4b0e000 { compatible = "qcom,tgu", "arm,primecell"; reg = <0x0 0x4b0e000 0x0 0x1000>;