From a67ecaef79ee22b3ab70c5f130eb0d4a39f2dc0f Mon Sep 17 00:00:00 2001 From: Yongxing Mou Date: Mon, 7 Sep 2026 12:30:42 +0800 Subject: [PATCH 1/4] Revert "FROMLIST: drm/msm/dp: Add catalog support for 3rd/4th stream MST" This reverts commit cd58926a62d45b9964f8cb6241e18a95e1067757. This is reverted because a newer version of this patch is being introduced. --- drivers/gpu/drm/msm/dp/dp_ctrl.c | 242 +++++++++++----------------- drivers/gpu/drm/msm/dp/dp_ctrl.h | 4 +- drivers/gpu/drm/msm/dp/dp_display.c | 27 +--- drivers/gpu/drm/msm/dp/dp_panel.c | 135 ++++------------ drivers/gpu/drm/msm/dp/dp_panel.h | 2 - drivers/gpu/drm/msm/dp/dp_reg.h | 17 +- 6 files changed, 132 insertions(+), 295 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_ctrl.c index ee8ec87b1a277..8aced87815787 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.c +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c @@ -133,8 +133,6 @@ struct msm_dp_ctrl_private { struct msm_dp_link *link; void __iomem *ahb_base; void __iomem *link_base; - void __iomem *mst2link_base; - void __iomem *mst3link_base; struct phy *phy; @@ -178,45 +176,19 @@ static inline void msm_dp_write_ahb(struct msm_dp_ctrl_private *ctrl, writel(data, ctrl->ahb_base + offset); } -static inline u32 msm_dp_read_link(struct msm_dp_ctrl_private *ctrl, - enum msm_dp_stream_id stream_id, u32 offset) +static inline u32 msm_dp_read_link(struct msm_dp_ctrl_private *ctrl, u32 offset) { - switch (stream_id) { - case DP_STREAM_0: - case DP_STREAM_1: - return readl_relaxed(ctrl->link_base + offset); - case DP_STREAM_2: - return readl_relaxed(ctrl->mst2link_base + offset); - case DP_STREAM_3: - return readl_relaxed(ctrl->mst3link_base + offset); - default: - DRM_ERROR("error stream_id\n"); - return 0; - } + return readl_relaxed(ctrl->link_base + offset); } static inline void msm_dp_write_link(struct msm_dp_ctrl_private *ctrl, - enum msm_dp_stream_id stream_id, u32 offset, u32 data) + u32 offset, u32 data) { /* * To make sure link reg writes happens before any other operation, * this function uses writel() instread of writel_relaxed() */ - switch (stream_id) { - case DP_STREAM_0: - case DP_STREAM_1: - writel(data, ctrl->link_base + offset); - break; - case DP_STREAM_2: - writel(data, ctrl->mst2link_base + offset); - break; - case DP_STREAM_3: - writel(data, ctrl->mst3link_base + offset); - break; - default: - DRM_ERROR("error stream_id\n"); - break; - } + writel(data, ctrl->link_base + offset); } static int msm_dp_aux_link_configure(struct drm_dp_aux *aux, @@ -256,13 +228,13 @@ int msm_dp_ctrl_mst_send_act(struct msm_dp_ctrl *msm_dp_ctrl) if (!ctrl->mst_active) return 0; - msm_dp_write_link(ctrl, 0, REG_DP_MST_ACT, 0x1); + msm_dp_write_link(ctrl, REG_DP_MST_ACT, 0x1); /* make sure ACT signal is performed */ wmb(); msleep(20); /* needs 1 frame time */ - act_complete = msm_dp_read_link(ctrl, 0, REG_DP_MST_ACT); + act_complete = msm_dp_read_link(ctrl, REG_DP_MST_ACT); if (!act_complete) { drm_dbg_dp(ctrl->drm_dev, "MST ACT trigger complete failed\n"); @@ -276,13 +248,13 @@ static void msm_dp_ctrl_mst_config(struct msm_dp_ctrl_private *ctrl, bool enable { u32 mainlink_ctrl; - mainlink_ctrl = msm_dp_read_link(ctrl, 0, REG_DP_MAINLINK_CTRL); + mainlink_ctrl = msm_dp_read_link(ctrl, REG_DP_MAINLINK_CTRL); if (enable) mainlink_ctrl |= DP_MAINLINK_CTRL_MST_EN; else mainlink_ctrl &= ~DP_MAINLINK_CTRL_MST_EN; - msm_dp_write_link(ctrl, 0, REG_DP_MAINLINK_CTRL, mainlink_ctrl); + msm_dp_write_link(ctrl, REG_DP_MAINLINK_CTRL, mainlink_ctrl); } static void msm_dp_ctrl_mst_channel_alloc(struct msm_dp_ctrl_private *ctrl, @@ -326,10 +298,10 @@ static void msm_dp_ctrl_mst_channel_alloc(struct msm_dp_ctrl_private *ctrl, drm_dbg_dp(ctrl->drm_dev, "stream_id:%d slot_reg_1:%d, slot_reg_2:%d\n", stream_id, slot_reg_1, slot_reg_2); - msm_dp_write_link(ctrl, stream_id, stream_id > DP_STREAM_1 ? + msm_dp_write_link(ctrl, stream_id > DP_STREAM_1 ? REG_DP_MSTLINK_TIMESLOT_1_32 : REG_DP_DP0_TIMESLOT_1_32 + reg_off, slot_reg_1); - msm_dp_write_link(ctrl, stream_id, stream_id > DP_STREAM_1 ? + msm_dp_write_link(ctrl, stream_id > DP_STREAM_1 ? REG_DP_MSTLINK_TIMESLOT_33_63 : REG_DP_DP0_TIMESLOT_33_63 + reg_off, slot_reg_2); } @@ -348,7 +320,7 @@ static void msm_dp_ctrl_update_rg(struct msm_dp_ctrl_private *ctrl, if (stream_id == DP_STREAM_1) reg_off = REG_DP_DP1_RG - REG_DP_DP0_RG; - msm_dp_write_link(ctrl, stream_id, stream_id > 1 ? + msm_dp_write_link(ctrl, stream_id > 1 ? REG_DP_MSTLINK_DP_RG : REG_DP_DP0_RG + reg_off, rg); } @@ -463,18 +435,18 @@ static void msm_dp_ctrl_psr_mainlink_enable(struct msm_dp_ctrl_private *ctrl) { u32 val; - val = msm_dp_read_link(ctrl, 0, REG_DP_MAINLINK_CTRL); + val = msm_dp_read_link(ctrl, REG_DP_MAINLINK_CTRL); val |= DP_MAINLINK_CTRL_ENABLE; - msm_dp_write_link(ctrl, 0, REG_DP_MAINLINK_CTRL, val); + msm_dp_write_link(ctrl, REG_DP_MAINLINK_CTRL, val); } static void msm_dp_ctrl_psr_mainlink_disable(struct msm_dp_ctrl_private *ctrl) { u32 val; - val = msm_dp_read_link(ctrl, 0, REG_DP_MAINLINK_CTRL); + val = msm_dp_read_link(ctrl, REG_DP_MAINLINK_CTRL); val &= ~DP_MAINLINK_CTRL_ENABLE; - msm_dp_write_link(ctrl, 0, REG_DP_MAINLINK_CTRL, val); + msm_dp_write_link(ctrl, REG_DP_MAINLINK_CTRL, val); } static void msm_dp_ctrl_mainlink_enable(struct msm_dp_ctrl_private *ctrl) @@ -483,21 +455,21 @@ static void msm_dp_ctrl_mainlink_enable(struct msm_dp_ctrl_private *ctrl) drm_dbg_dp(ctrl->drm_dev, "enable\n"); - mainlink_ctrl = msm_dp_read_link(ctrl, 0, REG_DP_MAINLINK_CTRL); + mainlink_ctrl = msm_dp_read_link(ctrl, REG_DP_MAINLINK_CTRL); mainlink_ctrl &= ~(DP_MAINLINK_CTRL_RESET | DP_MAINLINK_CTRL_ENABLE); - msm_dp_write_link(ctrl, 0, REG_DP_MAINLINK_CTRL, mainlink_ctrl); + msm_dp_write_link(ctrl, REG_DP_MAINLINK_CTRL, mainlink_ctrl); mainlink_ctrl |= DP_MAINLINK_CTRL_RESET; - msm_dp_write_link(ctrl, 0, REG_DP_MAINLINK_CTRL, mainlink_ctrl); + msm_dp_write_link(ctrl, REG_DP_MAINLINK_CTRL, mainlink_ctrl); mainlink_ctrl &= ~DP_MAINLINK_CTRL_RESET; - msm_dp_write_link(ctrl, 0, REG_DP_MAINLINK_CTRL, mainlink_ctrl); + msm_dp_write_link(ctrl, REG_DP_MAINLINK_CTRL, mainlink_ctrl); mainlink_ctrl |= (DP_MAINLINK_CTRL_ENABLE | DP_MAINLINK_FB_BOUNDARY_SEL); - msm_dp_write_link(ctrl, 0, REG_DP_MAINLINK_CTRL, mainlink_ctrl); + msm_dp_write_link(ctrl, REG_DP_MAINLINK_CTRL, mainlink_ctrl); } static void msm_dp_ctrl_mainlink_disable(struct msm_dp_ctrl_private *ctrl) @@ -506,23 +478,23 @@ static void msm_dp_ctrl_mainlink_disable(struct msm_dp_ctrl_private *ctrl) drm_dbg_dp(ctrl->drm_dev, "disable\n"); - mainlink_ctrl = msm_dp_read_link(ctrl, 0, REG_DP_MAINLINK_CTRL); + mainlink_ctrl = msm_dp_read_link(ctrl, REG_DP_MAINLINK_CTRL); mainlink_ctrl &= ~DP_MAINLINK_CTRL_ENABLE; - msm_dp_write_link(ctrl, 0, REG_DP_MAINLINK_CTRL, mainlink_ctrl); + msm_dp_write_link(ctrl, REG_DP_MAINLINK_CTRL, mainlink_ctrl); } static void msm_dp_setup_peripheral_flush(struct msm_dp_ctrl_private *ctrl) { u32 mainlink_ctrl; - mainlink_ctrl = msm_dp_read_link(ctrl, 0, REG_DP_MAINLINK_CTRL); + mainlink_ctrl = msm_dp_read_link(ctrl, REG_DP_MAINLINK_CTRL); if (ctrl->hw_revision >= DP_HW_VERSION_1_2) mainlink_ctrl |= DP_MAINLINK_FLUSH_MODE_SDE_PERIPH_UPDATE; else mainlink_ctrl |= DP_MAINLINK_FLUSH_MODE_UPDATE_SDP; - msm_dp_write_link(ctrl, 0, REG_DP_MAINLINK_CTRL, mainlink_ctrl); + msm_dp_write_link(ctrl, REG_DP_MAINLINK_CTRL, mainlink_ctrl); } static bool msm_dp_ctrl_mainlink_ready(struct msm_dp_ctrl_private *ctrl) @@ -560,10 +532,7 @@ void msm_dp_ctrl_push_idle(struct msm_dp_ctrl *msm_dp_ctrl, struct msm_dp_panel reinit_completion(&ctrl->idle_comp); - msm_dp_write_link(ctrl, msm_dp_panel->stream_id, - msm_dp_panel->stream_id > 1 ? - REG_DP_MSTLINK_STATE_CTRL : REG_DP_STATE_CTRL, - state); + msm_dp_write_link(ctrl, REG_DP_STATE_CTRL, state); if (!wait_for_completion_timeout(&ctrl->idle_comp, IDLE_PATTERN_COMPLETION_TIMEOUT_JIFFIES)) @@ -578,11 +547,7 @@ static void msm_dp_ctrl_config_ctrl_streams(struct msm_dp_ctrl_private *ctrl, u32 config = 0, tbd; u32 reg_offset = 0; - if (msm_dp_panel->stream_id == DP_STREAM_0) - config = msm_dp_read_link(ctrl, 0, REG_DP_CONFIGURATION_CTRL); - - if (msm_dp_panel->stream_id == DP_STREAM_1) - reg_offset = REG_DP1_CONFIGURATION_CTRL - REG_DP_CONFIGURATION_CTRL; + config = msm_dp_read_link(ctrl, REG_DP_CONFIGURATION_CTRL); if (msm_dp_panel->msm_dp_mode.out_fmt_is_yuv_420) config |= DP_CONFIGURATION_CTRL_RGB_YUV; /* YUV420 */ @@ -597,10 +562,8 @@ static void msm_dp_ctrl_config_ctrl_streams(struct msm_dp_ctrl_private *ctrl, drm_dbg_dp(ctrl->drm_dev, "stream DP_CONFIGURATION_CTRL=0x%x\n", config); - msm_dp_write_link(ctrl, msm_dp_panel->stream_id, msm_dp_panel->stream_id > 1 ? - REG_DP_MSTLINK_CONFIGURATION_CTRL : - REG_DP_CONFIGURATION_CTRL + reg_offset, config); - + if (msm_dp_panel->stream_id == DP_STREAM_1) + reg_offset = REG_DP1_CONFIGURATION_CTRL - REG_DP_CONFIGURATION_CTRL; } static void msm_dp_ctrl_config_ctrl_link(struct msm_dp_ctrl_private *ctrl) @@ -630,7 +593,7 @@ static void msm_dp_ctrl_config_ctrl_link(struct msm_dp_ctrl_private *ctrl) drm_dbg_dp(ctrl->drm_dev, "link DP_CONFIGURATION_CTRL=0x%x\n", config); - msm_dp_write_link(ctrl, 0, REG_DP_CONFIGURATION_CTRL, config); + msm_dp_write_link(ctrl, REG_DP_CONFIGURATION_CTRL, config); } static void msm_dp_ctrl_lane_mapping(struct msm_dp_ctrl_private *ctrl) @@ -643,8 +606,8 @@ static void msm_dp_ctrl_lane_mapping(struct msm_dp_ctrl_private *ctrl) ln_mapping |= lane_map[2] << LANE2_MAPPING_SHIFT; ln_mapping |= lane_map[3] << LANE3_MAPPING_SHIFT; - msm_dp_write_link(ctrl, 0, REG_DP_LOGICAL2PHYSICAL_LANE_MAPPING, - ln_mapping); + msm_dp_write_link(ctrl, REG_DP_LOGICAL2PHYSICAL_LANE_MAPPING, + ln_mapping); } static void msm_dp_ctrl_config_misc1_misc0(struct msm_dp_ctrl_private *ctrl, @@ -660,8 +623,7 @@ static void msm_dp_ctrl_config_misc1_misc0(struct msm_dp_ctrl_private *ctrl, if (msm_dp_panel->stream_id == DP_STREAM_1) reg_offset = REG_DP1_MISC1_MISC0 - REG_DP_MISC1_MISC0; - misc_val = msm_dp_read_link(ctrl, msm_dp_panel->stream_id, msm_dp_panel->stream_id > 1 ? - REG_DP_MSTLINK_MISC1_MISC0 : REG_DP_MISC1_MISC0 + reg_offset); + misc_val = msm_dp_read_link(ctrl, REG_DP_MISC1_MISC0 + reg_offset); /* clear bpp bits */ misc_val &= ~(0x07 << DP_MISC0_TEST_BITS_DEPTH_SHIFT); @@ -671,10 +633,7 @@ static void msm_dp_ctrl_config_misc1_misc0(struct msm_dp_ctrl_private *ctrl, misc_val |= DP_MISC0_SYNCHRONOUS_CLK; drm_dbg_dp(ctrl->drm_dev, "misc settings = 0x%x\n", misc_val); - msm_dp_write_link(ctrl, msm_dp_panel->stream_id, - msm_dp_panel->stream_id > 1 ? - REG_DP_MSTLINK_MISC1_MISC0 : REG_DP_MISC1_MISC0 + reg_offset, - misc_val); + msm_dp_write_link(ctrl, REG_DP_MISC1_MISC0 + reg_offset, misc_val); } static void msm_dp_ctrl_configure_source_params(struct msm_dp_ctrl_private *ctrl, @@ -1502,9 +1461,9 @@ static void msm_dp_ctrl_setup_tr_unit(struct msm_dp_ctrl_private *ctrl) pr_debug("dp_tu=0x%x, valid_boundary=0x%x, valid_boundary2=0x%x\n", msm_dp_tu, valid_boundary, valid_boundary2); - msm_dp_write_link(ctrl, 0, REG_DP_VALID_BOUNDARY, valid_boundary); - msm_dp_write_link(ctrl, 0, REG_DP_TU, msm_dp_tu); - msm_dp_write_link(ctrl, 0, REG_DP_VALID_BOUNDARY_2, valid_boundary2); + msm_dp_write_link(ctrl, REG_DP_VALID_BOUNDARY, valid_boundary); + msm_dp_write_link(ctrl, REG_DP_TU, msm_dp_tu); + msm_dp_write_link(ctrl, REG_DP_VALID_BOUNDARY_2, valid_boundary2); } static int msm_dp_ctrl_wait4video_ready(struct msm_dp_ctrl_private *ctrl) @@ -1621,7 +1580,7 @@ static int msm_dp_ctrl_set_pattern_state_bit(struct msm_dp_ctrl_private *ctrl, bit = BIT(state_bit - 1); drm_dbg_dp(ctrl->drm_dev, "hw: bit=%d train=%d\n", bit, state_bit); - msm_dp_write_link(ctrl, 0, REG_DP_STATE_CTRL, bit); + msm_dp_write_link(ctrl, REG_DP_STATE_CTRL, bit); bit = BIT(state_bit - 1) << DP_MAINLINK_READY_LINK_TRAINING_SHIFT; @@ -1648,7 +1607,7 @@ static int msm_dp_ctrl_link_train_1(struct msm_dp_ctrl_private *ctrl, delay_us = drm_dp_read_clock_recovery_delay(ctrl->aux, ctrl->panel->dpcd, dp_phy, false); - msm_dp_write_link(ctrl, 0, REG_DP_STATE_CTRL, 0); + msm_dp_write_link(ctrl, REG_DP_STATE_CTRL, 0); *training_step = DP_TRAINING_1; @@ -1772,7 +1731,7 @@ static int msm_dp_ctrl_link_train_2(struct msm_dp_ctrl_private *ctrl, delay_us = drm_dp_read_channel_eq_delay(ctrl->aux, ctrl->panel->dpcd, dp_phy, false); - msm_dp_write_link(ctrl, 0, REG_DP_STATE_CTRL, 0); + msm_dp_write_link(ctrl, REG_DP_STATE_CTRL, 0); *training_step = DP_TRAINING_2; @@ -1889,7 +1848,7 @@ static int msm_dp_ctrl_link_train(struct msm_dp_ctrl_private *ctrl, } end: - msm_dp_write_link(ctrl, 0, REG_DP_STATE_CTRL, 0); + msm_dp_write_link(ctrl, REG_DP_STATE_CTRL, 0); return ret; } @@ -2035,34 +1994,34 @@ static int msm_dp_ctrl_enable_mainlink_clocks(struct msm_dp_ctrl_private *ctrl) static void msm_dp_ctrl_enable_sdp(struct msm_dp_ctrl_private *ctrl) { /* trigger sdp */ - msm_dp_write_link(ctrl, 0, MMSS_DP_SDP_CFG3, UPDATE_SDP); - msm_dp_write_link(ctrl, 0, MMSS_DP_SDP_CFG3, 0x0); + msm_dp_write_link(ctrl, MMSS_DP_SDP_CFG3, UPDATE_SDP); + msm_dp_write_link(ctrl, MMSS_DP_SDP_CFG3, 0x0); } static void msm_dp_ctrl_psr_enter(struct msm_dp_ctrl_private *ctrl) { u32 cmd; - cmd = msm_dp_read_link(ctrl, 0, REG_PSR_CMD); + cmd = msm_dp_read_link(ctrl, REG_PSR_CMD); cmd &= ~(PSR_ENTER | PSR_EXIT); cmd |= PSR_ENTER; msm_dp_ctrl_enable_sdp(ctrl); - msm_dp_write_link(ctrl, 0, REG_PSR_CMD, cmd); + msm_dp_write_link(ctrl, REG_PSR_CMD, cmd); } static void msm_dp_ctrl_psr_exit(struct msm_dp_ctrl_private *ctrl) { u32 cmd; - cmd = msm_dp_read_link(ctrl, 0, REG_PSR_CMD); + cmd = msm_dp_read_link(ctrl, REG_PSR_CMD); cmd &= ~(PSR_ENTER | PSR_EXIT); cmd |= PSR_EXIT; msm_dp_ctrl_enable_sdp(ctrl); - msm_dp_write_link(ctrl, 0, REG_PSR_CMD, cmd); + msm_dp_write_link(ctrl, REG_PSR_CMD, cmd); } void msm_dp_ctrl_config_psr(struct msm_dp_ctrl *msm_dp_ctrl) @@ -2075,9 +2034,9 @@ void msm_dp_ctrl_config_psr(struct msm_dp_ctrl *msm_dp_ctrl) return; /* enable PSR1 function */ - cfg = msm_dp_read_link(ctrl, 0, REG_PSR_CONFIG); + cfg = msm_dp_read_link(ctrl, REG_PSR_CONFIG); cfg |= PSR1_SUPPORTED; - msm_dp_write_link(ctrl, 0, REG_PSR_CONFIG, cfg); + msm_dp_write_link(ctrl, REG_PSR_CONFIG, cfg); msm_dp_ctrl_config_psr_interrupt(ctrl); msm_dp_ctrl_enable_sdp(ctrl); @@ -2116,16 +2075,16 @@ void msm_dp_ctrl_set_psr(struct msm_dp_ctrl *msm_dp_ctrl, bool enter) } msm_dp_ctrl_push_idle(msm_dp_ctrl, ctrl->panel); - msm_dp_write_link(ctrl, 0, REG_DP_STATE_CTRL, 0); + msm_dp_write_link(ctrl, REG_DP_STATE_CTRL, 0); msm_dp_ctrl_psr_mainlink_disable(ctrl); } else { msm_dp_ctrl_psr_mainlink_enable(ctrl); msm_dp_ctrl_psr_exit(ctrl); - msm_dp_write_link(ctrl, 0, REG_DP_STATE_CTRL, DP_STATE_CTRL_SEND_VIDEO); + msm_dp_write_link(ctrl, REG_DP_STATE_CTRL, DP_STATE_CTRL_SEND_VIDEO); msm_dp_ctrl_wait4video_ready(ctrl); - msm_dp_write_link(ctrl, 0, REG_DP_STATE_CTRL, 0); + msm_dp_write_link(ctrl, REG_DP_STATE_CTRL, 0); } } @@ -2236,7 +2195,7 @@ static int msm_dp_ctrl_link_maintenance(struct msm_dp_ctrl_private *ctrl) msm_dp_ctrl_clear_training_pattern(ctrl, DP_PHY_DPRX); - msm_dp_write_link(ctrl, 0, REG_DP_STATE_CTRL, DP_STATE_CTRL_SEND_VIDEO); + msm_dp_write_link(ctrl, REG_DP_STATE_CTRL, DP_STATE_CTRL_SEND_VIDEO); ret = msm_dp_ctrl_mst_send_act(&ctrl->msm_dp_ctrl); if (ret) @@ -2255,72 +2214,72 @@ static void msm_dp_ctrl_send_phy_pattern(struct msm_dp_ctrl_private *ctrl, u32 value = 0x0; /* Make sure to clear the current pattern before starting a new one */ - msm_dp_write_link(ctrl, 0, REG_DP_STATE_CTRL, 0x0); + msm_dp_write_link(ctrl, REG_DP_STATE_CTRL, 0x0); drm_dbg_dp(ctrl->drm_dev, "pattern: %#x\n", pattern); switch (pattern) { case DP_PHY_TEST_PATTERN_D10_2: - msm_dp_write_link(ctrl, 0, REG_DP_STATE_CTRL, - DP_STATE_CTRL_LINK_TRAINING_PATTERN1); + msm_dp_write_link(ctrl, REG_DP_STATE_CTRL, + DP_STATE_CTRL_LINK_TRAINING_PATTERN1); break; case DP_PHY_TEST_PATTERN_ERROR_COUNT: value &= ~(1 << 16); - msm_dp_write_link(ctrl, 0, REG_DP_HBR2_COMPLIANCE_SCRAMBLER_RESET, - value); + msm_dp_write_link(ctrl, REG_DP_HBR2_COMPLIANCE_SCRAMBLER_RESET, + value); value |= SCRAMBLER_RESET_COUNT_VALUE; - msm_dp_write_link(ctrl, 0, REG_DP_HBR2_COMPLIANCE_SCRAMBLER_RESET, - value); - msm_dp_write_link(ctrl, 0, REG_DP_MAINLINK_LEVELS, - DP_MAINLINK_SAFE_TO_EXIT_LEVEL_2); - msm_dp_write_link(ctrl, 0, REG_DP_STATE_CTRL, - DP_STATE_CTRL_LINK_SYMBOL_ERR_MEASURE); + msm_dp_write_link(ctrl, REG_DP_HBR2_COMPLIANCE_SCRAMBLER_RESET, + value); + msm_dp_write_link(ctrl, REG_DP_MAINLINK_LEVELS, + DP_MAINLINK_SAFE_TO_EXIT_LEVEL_2); + msm_dp_write_link(ctrl, REG_DP_STATE_CTRL, + DP_STATE_CTRL_LINK_SYMBOL_ERR_MEASURE); break; case DP_PHY_TEST_PATTERN_PRBS7: - msm_dp_write_link(ctrl, 0, REG_DP_STATE_CTRL, - DP_STATE_CTRL_LINK_PRBS7); + msm_dp_write_link(ctrl, REG_DP_STATE_CTRL, + DP_STATE_CTRL_LINK_PRBS7); break; case DP_PHY_TEST_PATTERN_80BIT_CUSTOM: - msm_dp_write_link(ctrl, 0, REG_DP_STATE_CTRL, - DP_STATE_CTRL_LINK_TEST_CUSTOM_PATTERN); + msm_dp_write_link(ctrl, REG_DP_STATE_CTRL, + DP_STATE_CTRL_LINK_TEST_CUSTOM_PATTERN); /* 00111110000011111000001111100000 */ - msm_dp_write_link(ctrl, 0, REG_DP_TEST_80BIT_CUSTOM_PATTERN_REG0, - 0x3E0F83E0); + msm_dp_write_link(ctrl, REG_DP_TEST_80BIT_CUSTOM_PATTERN_REG0, + 0x3E0F83E0); /* 00001111100000111110000011111000 */ - msm_dp_write_link(ctrl, 0, REG_DP_TEST_80BIT_CUSTOM_PATTERN_REG1, - 0x0F83E0F8); + msm_dp_write_link(ctrl, REG_DP_TEST_80BIT_CUSTOM_PATTERN_REG1, + 0x0F83E0F8); /* 1111100000111110 */ - msm_dp_write_link(ctrl, 0, REG_DP_TEST_80BIT_CUSTOM_PATTERN_REG2, - 0x0000F83E); + msm_dp_write_link(ctrl, REG_DP_TEST_80BIT_CUSTOM_PATTERN_REG2, + 0x0000F83E); break; case DP_PHY_TEST_PATTERN_CP2520: - value = msm_dp_read_link(ctrl, 0, REG_DP_MAINLINK_CTRL); + value = msm_dp_read_link(ctrl, REG_DP_MAINLINK_CTRL); value &= ~DP_MAINLINK_CTRL_SW_BYPASS_SCRAMBLER; - msm_dp_write_link(ctrl, 0, REG_DP_MAINLINK_CTRL, value); + msm_dp_write_link(ctrl, REG_DP_MAINLINK_CTRL, value); value = DP_HBR2_ERM_PATTERN; - msm_dp_write_link(ctrl, 0, REG_DP_HBR2_COMPLIANCE_SCRAMBLER_RESET, - value); + msm_dp_write_link(ctrl, REG_DP_HBR2_COMPLIANCE_SCRAMBLER_RESET, + value); value |= SCRAMBLER_RESET_COUNT_VALUE; - msm_dp_write_link(ctrl, 0, REG_DP_HBR2_COMPLIANCE_SCRAMBLER_RESET, - value); - msm_dp_write_link(ctrl, 0, REG_DP_MAINLINK_LEVELS, - DP_MAINLINK_SAFE_TO_EXIT_LEVEL_2); - msm_dp_write_link(ctrl, 0, REG_DP_STATE_CTRL, - DP_STATE_CTRL_LINK_SYMBOL_ERR_MEASURE); - value = msm_dp_read_link(ctrl, 0, REG_DP_MAINLINK_CTRL); + msm_dp_write_link(ctrl, REG_DP_HBR2_COMPLIANCE_SCRAMBLER_RESET, + value); + msm_dp_write_link(ctrl, REG_DP_MAINLINK_LEVELS, + DP_MAINLINK_SAFE_TO_EXIT_LEVEL_2); + msm_dp_write_link(ctrl, REG_DP_STATE_CTRL, + DP_STATE_CTRL_LINK_SYMBOL_ERR_MEASURE); + value = msm_dp_read_link(ctrl, REG_DP_MAINLINK_CTRL); value |= DP_MAINLINK_CTRL_ENABLE; - msm_dp_write_link(ctrl, 0, REG_DP_MAINLINK_CTRL, value); + msm_dp_write_link(ctrl, REG_DP_MAINLINK_CTRL, value); break; case DP_PHY_TEST_PATTERN_SEL_MASK: - msm_dp_write_link(ctrl, 0, REG_DP_MAINLINK_CTRL, - DP_MAINLINK_CTRL_ENABLE); - msm_dp_write_link(ctrl, 0, REG_DP_STATE_CTRL, - DP_STATE_CTRL_LINK_TRAINING_PATTERN4); + msm_dp_write_link(ctrl, REG_DP_MAINLINK_CTRL, + DP_MAINLINK_CTRL_ENABLE); + msm_dp_write_link(ctrl, REG_DP_STATE_CTRL, + DP_STATE_CTRL_LINK_TRAINING_PATTERN4); break; default: @@ -2348,7 +2307,7 @@ static bool msm_dp_ctrl_send_phy_test_pattern(struct msm_dp_ctrl_private *ctrl) msm_dp_ctrl_update_phy_vx_px(ctrl, DP_PHY_DPRX); msm_dp_link_send_test_response(ctrl->link); - pattern_sent = msm_dp_read_link(ctrl, 0, REG_DP_MAINLINK_READY); + pattern_sent = msm_dp_read_link(ctrl, REG_DP_MAINLINK_READY); switch (pattern_sent) { case MR_LINK_TRAINING1: @@ -2722,14 +2681,8 @@ static void msm_dp_ctrl_config_msa(struct msm_dp_ctrl_private *ctrl, nvid *= 3; drm_dbg_dp(ctrl->drm_dev, "mvid=0x%x, nvid=0x%x\n", mvid, nvid); - msm_dp_write_link(ctrl, msm_dp_panel->stream_id, - msm_dp_panel->stream_id > 1 ? - REG_MSTLINK_SOFTWARE_MVID : REG_DP_SOFTWARE_MVID + mvid_reg_off, - mvid); - msm_dp_write_link(ctrl, msm_dp_panel->stream_id, - msm_dp_panel->stream_id > 1 ? - REG_MSTLINK_SOFTWARE_NVID : REG_DP_SOFTWARE_NVID + nvid_reg_off, - nvid); + msm_dp_write_link(ctrl, REG_DP_SOFTWARE_MVID + mvid_reg_off, mvid); + msm_dp_write_link(ctrl, REG_DP_SOFTWARE_NVID + nvid_reg_off, nvid); } /* TODO: comments here. */ @@ -2899,8 +2852,7 @@ int msm_dp_ctrl_on_stream(struct msm_dp_ctrl *msm_dp_ctrl, struct msm_dp_panel * if (ctrl->mst_active) msm_dp_ctrl_mst_config(ctrl, true); - if (msm_dp_panel->stream_id == DP_STREAM_0) - msm_dp_ctrl_config_ctrl_link(ctrl); + msm_dp_ctrl_config_ctrl_link(ctrl); msm_dp_ctrl_configure_source_params(ctrl, msm_dp_panel); @@ -2917,7 +2869,7 @@ int msm_dp_ctrl_on_stream(struct msm_dp_ctrl *msm_dp_ctrl, struct msm_dp_panel * msm_dp_ctrl_mst_stream_setup(ctrl, msm_dp_panel); - msm_dp_write_link(ctrl, 0, REG_DP_STATE_CTRL, DP_STATE_CTRL_SEND_VIDEO); + msm_dp_write_link(ctrl, REG_DP_STATE_CTRL, DP_STATE_CTRL_SEND_VIDEO); ret = msm_dp_ctrl_mst_send_act(msm_dp_ctrl); if (ret) @@ -3144,9 +3096,7 @@ struct msm_dp_ctrl *msm_dp_ctrl_get(struct device *dev, struct msm_dp_link *link struct phy *phy, int max_stream, void __iomem *ahb_base, - void __iomem *link_base, - void __iomem *mst2link_base, - void __iomem *mst3link_base) + void __iomem *link_base) { struct msm_dp_ctrl_private *ctrl; int ret; @@ -3186,8 +3136,6 @@ struct msm_dp_ctrl *msm_dp_ctrl_get(struct device *dev, struct msm_dp_link *link ctrl->phy = phy; ctrl->ahb_base = ahb_base; ctrl->link_base = link_base; - ctrl->mst2link_base = mst2link_base; - ctrl->mst3link_base = mst3link_base; ctrl->mst_active = false; ret = msm_dp_ctrl_clk_init(&ctrl->msm_dp_ctrl, max_stream); diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.h b/drivers/gpu/drm/msm/dp/dp_ctrl.h index cfe7e44969437..17a54d96f954a 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.h +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.h @@ -32,9 +32,7 @@ struct msm_dp_ctrl *msm_dp_ctrl_get(struct device *dev, struct phy *phy, int max_stream, void __iomem *ahb_base, - void __iomem *link_base, - void __iomem *mst2link_base, - void __iomem *mst3link_base); + void __iomem *link_base); void msm_dp_ctrl_reset(struct msm_dp_ctrl *msm_dp_ctrl); void msm_dp_ctrl_phy_init(struct msm_dp_ctrl *msm_dp_ctrl); diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/dp_display.c index 2049545ee37d8..94a7bc5dbbf00 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -87,12 +87,6 @@ struct msm_dp_display_private { void __iomem *link_base; size_t link_len; - void __iomem *mst2link_base; - size_t mst2link_len; - - void __iomem *mst3link_base; - size_t mst3link_len; - void __iomem *pixel_base[DP_STREAM_MAX]; size_t pixel_len; @@ -601,8 +595,7 @@ struct msm_dp_panel *msm_dp_display_get_panel(struct msm_dp *msm_dp_display) dp = container_of(msm_dp_display, struct msm_dp_display_private, msm_dp_display); dp_panel = msm_dp_panel_get(&dp->msm_dp_display.pdev->dev, dp->aux, dp->link, - dp->link_base, dp->mst2link_base, dp->mst3link_base, - dp->pixel_base[0]); + dp->link_base, dp->pixel_base[0]); if (IS_ERR(dp->panel)) { DRM_ERROR("failed to initialize panel\n"); @@ -656,8 +649,7 @@ static int msm_dp_init_sub_modules(struct msm_dp_display_private *dp) goto error_link; } - dp->panel = msm_dp_panel_get(dev, dp->aux, dp->link, dp->link_base, - dp->mst2link_base, dp->mst3link_base, dp->pixel_base[0]); + dp->panel = msm_dp_panel_get(dev, dp->aux, dp->link, dp->link_base, dp->pixel_base[0]); if (IS_ERR(dp->panel)) { rc = PTR_ERR(dp->panel); DRM_ERROR("failed to initialize panel, rc = %d\n", rc); @@ -666,8 +658,7 @@ static int msm_dp_init_sub_modules(struct msm_dp_display_private *dp) } dp->ctrl = msm_dp_ctrl_get(dev, dp->link, dp->panel, dp->aux, - phy, dp->max_stream, dp->ahb_base, - dp->link_base, dp->mst2link_base, dp->mst3link_base); + phy, dp->max_stream, dp->ahb_base, dp->link_base); if (IS_ERR(dp->ctrl)) { rc = PTR_ERR(dp->ctrl); DRM_ERROR("failed to initialize ctrl, rc = %d\n", rc); @@ -977,10 +968,6 @@ void msm_dp_snapshot(struct msm_disp_state *disp_state, struct msm_dp *dp) msm_dp_display->aux_base, "dp_aux"); msm_disp_snapshot_add_block(disp_state, msm_dp_display->link_len, msm_dp_display->link_base, "dp_link"); - msm_disp_snapshot_add_block(disp_state, msm_dp_display->mst2link_len, - msm_dp_display->mst2link_base, "dp_mst2link"); - msm_disp_snapshot_add_block(disp_state, msm_dp_display->mst3link_len, - msm_dp_display->mst3link_base, "dp_mst3link"); msm_disp_snapshot_add_block(disp_state, msm_dp_display->pixel_len, msm_dp_display->pixel_base[0], "dp_p0"); msm_disp_snapshot_add_block(disp_state, msm_dp_display->pixel_len, @@ -1335,14 +1322,6 @@ static int msm_dp_display_get_io(struct msm_dp_display_private *display) } } - display->mst2link_base = msm_dp_ioremap(pdev, 7, &display->mst2link_len); - if (IS_ERR(display->mst2link_base)) - DRM_DEBUG_DP("unable to remap link region: %pe\n", display->mst2link_base); - - display->mst3link_base = msm_dp_ioremap(pdev, 8, &display->mst3link_len); - if (IS_ERR(display->mst3link_base)) - DRM_DEBUG_DP("unable to remap link region: %pe\n", display->mst3link_base); - return 0; } diff --git a/drivers/gpu/drm/msm/dp/dp_panel.c b/drivers/gpu/drm/msm/dp/dp_panel.c index e05d96f33c433..34b9079e27d82 100644 --- a/drivers/gpu/drm/msm/dp/dp_panel.c +++ b/drivers/gpu/drm/msm/dp/dp_panel.c @@ -25,50 +25,23 @@ struct msm_dp_panel_private { struct drm_dp_aux *aux; struct msm_dp_link *link; void __iomem *link_base; - void __iomem *mst2link_base; - void __iomem *mst3link_base; void __iomem *pixel_base; bool panel_on; }; static inline u32 msm_dp_read_link(struct msm_dp_panel_private *panel, u32 offset) { - switch (panel->msm_dp_panel.stream_id) { - case DP_STREAM_0: - case DP_STREAM_1: - return readl_relaxed(panel->link_base + offset); - case DP_STREAM_2: - return readl_relaxed(panel->mst2link_base + offset); - case DP_STREAM_3: - return readl_relaxed(panel->mst3link_base + offset); - default: - DRM_ERROR("error stream_id\n"); - return 0; - } + return readl_relaxed(panel->link_base + offset); } static inline void msm_dp_write_link(struct msm_dp_panel_private *panel, - u32 offset, u32 data) + u32 offset, u32 data) { /* * To make sure link reg writes happens before any other operation, * this function uses writel() instread of writel_relaxed() */ - switch (panel->msm_dp_panel.stream_id) { - case DP_STREAM_0: - case DP_STREAM_1: - writel(data, panel->link_base + offset); - break; - case DP_STREAM_2: - writel(data, panel->mst2link_base + offset); - break; - case DP_STREAM_3: - writel(data, panel->mst3link_base + offset); - break; - default: - DRM_ERROR("error stream_id\n"); - break; - } + writel(data, panel->link_base + offset); } static inline void msm_dp_write_pn(struct msm_dp_panel_private *panel, @@ -471,51 +444,38 @@ void msm_dp_panel_clear_dsc_dto(struct msm_dp_panel *msm_dp_panel) static void msm_dp_panel_send_vsc_sdp(struct msm_dp_panel_private *panel, struct dp_sdp *vsc_sdp) { - u32 id = panel->msm_dp_panel.stream_id; u32 header[2]; u32 val; int i; u32 offset = 0; - if (id == DP_STREAM_1) + if (panel->msm_dp_panel.stream_id == DP_STREAM_1) offset = MMSS_DP1_GENERIC0_0 - MMSS_DP_GENERIC0_0; msm_dp_utils_pack_sdp_header(&vsc_sdp->sdp_header, header); - msm_dp_write_link(panel, id > 1 ? - MMSS_DP_MSTLINK_GENERIC0_0 : MMSS_DP_GENERIC0_0 + offset, - header[0]); - msm_dp_write_link(panel, id > 1 ? - MMSS_DP_MSTLINK_GENERIC0_1 : MMSS_DP_GENERIC0_1 + offset, - header[1]); + msm_dp_write_link(panel, MMSS_DP_GENERIC0_0 + offset, header[0]); + msm_dp_write_link(panel, MMSS_DP_GENERIC0_1 + offset, header[1]); for (i = 0; i < sizeof(vsc_sdp->db); i += 4) { val = ((vsc_sdp->db[i]) | (vsc_sdp->db[i + 1] << 8) | (vsc_sdp->db[i + 2] << 16) | (vsc_sdp->db[i + 3] << 24)); - - msm_dp_write_link(panel, id > 1 ? - MMSS_DP_MSTLINK_GENERIC0_2 + i : MMSS_DP_GENERIC0_2 + i + offset, - val); + msm_dp_write_link(panel, MMSS_DP_GENERIC0_2 + i + offset, val); } } static void msm_dp_panel_update_sdp(struct msm_dp_panel_private *panel) { - u32 id = panel->msm_dp_panel.stream_id; u32 hw_revision = panel->msm_dp_panel.hw_revision; u32 offset = 0; - if (id == DP_STREAM_1) + if (panel->msm_dp_panel.stream_id == DP_STREAM_1) offset = MMSS_DP1_SDP_CFG3 - MMSS_DP_SDP_CFG3; if (hw_revision >= DP_HW_VERSION_1_0 && hw_revision < DP_HW_VERSION_1_2) { - msm_dp_write_link(panel, id > 1 ? - MMSS_DP_MSTLINK_SDP_CFG3 : MMSS_DP_SDP_CFG3 + offset, - UPDATE_SDP); - msm_dp_write_link(panel, id > 1 ? - MMSS_DP_MSTLINK_SDP_CFG3 : MMSS_DP_SDP_CFG3 + offset, - 0x0); + msm_dp_write_link(panel, MMSS_DP_SDP_CFG3 + offset, UPDATE_SDP); + msm_dp_write_link(panel, MMSS_DP_SDP_CFG3 + offset, 0x0); } } @@ -523,34 +483,26 @@ void msm_dp_panel_enable_vsc_sdp(struct msm_dp_panel *msm_dp_panel, struct dp_sd { struct msm_dp_panel_private *panel = container_of(msm_dp_panel, struct msm_dp_panel_private, msm_dp_panel); - u32 id = msm_dp_panel->stream_id; u32 cfg, cfg2, misc; u32 misc_reg_offset = 0; u32 sdp_cfg_offset = 0; u32 sdp_cfg2_offset = 0; - if (id == DP_STREAM_1) { + if (msm_dp_panel->stream_id == DP_STREAM_1) { misc_reg_offset = REG_DP1_MISC1_MISC0 - REG_DP_MISC1_MISC0; sdp_cfg_offset = MMSS_DP1_SDP_CFG - MMSS_DP_SDP_CFG; sdp_cfg2_offset = MMSS_DP1_SDP_CFG2 - MMSS_DP_SDP_CFG2; } - cfg = msm_dp_read_link(panel, id > 1 ? - MMSS_DP_MSTLINK_SDP_CFG : MMSS_DP_SDP_CFG + sdp_cfg_offset); - cfg2 = msm_dp_read_link(panel, id > 1 ? - MMSS_DP_MSTLINK_SDP_CFG2 : MMSS_DP_SDP_CFG2 + sdp_cfg2_offset); - misc = msm_dp_read_link(panel, id > 1 ? - REG_DP_MSTLINK_MISC1_MISC0 : REG_DP_MISC1_MISC0 + misc_reg_offset); + cfg = msm_dp_read_link(panel, MMSS_DP_SDP_CFG + sdp_cfg_offset); + cfg2 = msm_dp_read_link(panel, MMSS_DP_SDP_CFG2 + sdp_cfg2_offset); + misc = msm_dp_read_link(panel, REG_DP_MISC1_MISC0 + misc_reg_offset); cfg |= GEN0_SDP_EN; - cfg2 |= GENERIC0_SDPSIZE_VALID; + msm_dp_write_link(panel, MMSS_DP_SDP_CFG + sdp_cfg_offset, cfg); - msm_dp_write_link(panel, id > 1 ? - MMSS_DP_MSTLINK_SDP_CFG : MMSS_DP_SDP_CFG + sdp_cfg_offset, - cfg); - msm_dp_write_link(panel, id > 1 ? - MMSS_DP_MSTLINK_SDP_CFG2 : MMSS_DP_SDP_CFG2 + sdp_cfg2_offset, - cfg2); + cfg2 |= GENERIC0_SDPSIZE_VALID; + msm_dp_write_link(panel, MMSS_DP_SDP_CFG2 + sdp_cfg2_offset, cfg2); msm_dp_panel_send_vsc_sdp(panel, vsc_sdp); @@ -560,9 +512,7 @@ void msm_dp_panel_enable_vsc_sdp(struct msm_dp_panel *msm_dp_panel, struct dp_sd drm_dbg_dp(panel->drm_dev, "vsc sdp enable=1\n"); pr_debug("misc settings = 0x%x\n", misc); - msm_dp_write_link(panel, id > 1 ? - REG_DP_MSTLINK_MISC1_MISC0 : REG_DP_MISC1_MISC0 + misc_reg_offset, - misc); + msm_dp_write_link(panel, REG_DP_MISC1_MISC0 + misc_reg_offset, misc); msm_dp_panel_update_sdp(panel); } @@ -571,34 +521,26 @@ void msm_dp_panel_disable_vsc_sdp(struct msm_dp_panel *msm_dp_panel) { struct msm_dp_panel_private *panel = container_of(msm_dp_panel, struct msm_dp_panel_private, msm_dp_panel); - u32 id = msm_dp_panel->stream_id; u32 cfg, cfg2, misc; u32 misc_reg_offset = 0; u32 sdp_cfg_offset = 0; u32 sdp_cfg2_offset = 0; - if (id == DP_STREAM_1) { + if (msm_dp_panel->stream_id == DP_STREAM_1) { misc_reg_offset = REG_DP1_MISC1_MISC0 - REG_DP_MISC1_MISC0; sdp_cfg_offset = MMSS_DP1_SDP_CFG - MMSS_DP_SDP_CFG; sdp_cfg2_offset = MMSS_DP1_SDP_CFG2 - MMSS_DP_SDP_CFG2; } - cfg = msm_dp_read_link(panel, id > 1 ? - MMSS_DP_MSTLINK_SDP_CFG : MMSS_DP_SDP_CFG + sdp_cfg_offset); - cfg2 = msm_dp_read_link(panel, id > 1 ? - MMSS_DP_MSTLINK_SDP_CFG2 : MMSS_DP_SDP_CFG2 + sdp_cfg2_offset); - misc = msm_dp_read_link(panel, id > 1 ? - REG_DP_MSTLINK_MISC1_MISC0 : REG_DP_MISC1_MISC0 + misc_reg_offset); + cfg = msm_dp_read_link(panel, MMSS_DP_SDP_CFG + sdp_cfg_offset); + cfg2 = msm_dp_read_link(panel, MMSS_DP_SDP_CFG2 + sdp_cfg2_offset); + misc = msm_dp_read_link(panel, REG_DP_MISC1_MISC0 + misc_reg_offset); cfg &= ~GEN0_SDP_EN; - cfg2 &= ~GENERIC0_SDPSIZE_VALID; + msm_dp_write_link(panel, MMSS_DP_SDP_CFG + sdp_cfg_offset, cfg); - msm_dp_write_link(panel, id > 1 ? - MMSS_DP_MSTLINK_SDP_CFG : MMSS_DP_SDP_CFG + sdp_cfg_offset, - cfg); - msm_dp_write_link(panel, id > 1 ? - MMSS_DP_MSTLINK_SDP_CFG2 : MMSS_DP_SDP_CFG2 + sdp_cfg2_offset, - cfg2); + cfg2 &= ~GENERIC0_SDPSIZE_VALID; + msm_dp_write_link(panel, MMSS_DP_SDP_CFG2 + sdp_cfg2_offset, cfg2); /* switch back to MSA */ misc &= ~DP_MISC1_VSC_SDP; @@ -606,9 +548,7 @@ void msm_dp_panel_disable_vsc_sdp(struct msm_dp_panel *msm_dp_panel) drm_dbg_dp(panel->drm_dev, "vsc sdp enable=0\n"); pr_debug("misc settings = 0x%x\n", misc); - msm_dp_write_link(panel, id > 1 ? - REG_DP_MSTLINK_MISC1_MISC0 : REG_DP_MISC1_MISC0 + misc_reg_offset, - misc); + msm_dp_write_link(panel, REG_DP_MISC1_MISC0 + misc_reg_offset, misc); msm_dp_panel_update_sdp(panel); } @@ -658,7 +598,6 @@ static int msm_dp_panel_setup_vsc_sdp_yuv_420(struct msm_dp_panel *msm_dp_panel) int msm_dp_panel_timing_cfg(struct msm_dp_panel *msm_dp_panel, bool wide_bus_en) { - u32 id = msm_dp_panel->stream_id; u32 data, total_ver, total_hor; struct msm_dp_panel_private *panel; struct drm_display_mode *drm_mode; @@ -682,7 +621,7 @@ int msm_dp_panel_timing_cfg(struct msm_dp_panel *msm_dp_panel, bool wide_bus_en) drm_mode->vsync_start - drm_mode->vdisplay, drm_mode->vsync_end - drm_mode->vsync_start); - if (id == DP_STREAM_1) + if (msm_dp_panel->stream_id == DP_STREAM_1) offset = REG_DP1_TOTAL_HOR_VER - REG_DP_TOTAL_HOR_VER; total_hor = drm_mode->htotal; @@ -715,18 +654,10 @@ int msm_dp_panel_timing_cfg(struct msm_dp_panel *msm_dp_panel, bool wide_bus_en) msm_dp_active = data; - msm_dp_write_link(panel, - id > 1 ? REG_DP_MSTLINK_TOTAL_HOR_VER : - REG_DP_TOTAL_HOR_VER + offset, total); - msm_dp_write_link(panel, - id > 1 ? REG_DP_MSTLINK_START_HOR_VER_FROM_SYNC : - REG_DP_START_HOR_VER_FROM_SYNC + offset, sync_start); - msm_dp_write_link(panel, - id > 1 ? REG_DP_MSTLINK_HSYNC_VSYNC_WIDTH_POLARITY : - REG_DP_HSYNC_VSYNC_WIDTH_POLARITY + offset, width_blanking); - msm_dp_write_link(panel, - id > 1 ? REG_DP_MSTLINK_ACTIVE_HOR_VER : - REG_DP_ACTIVE_HOR_VER + offset, msm_dp_active); + msm_dp_write_link(panel, REG_DP_TOTAL_HOR_VER + offset, total); + msm_dp_write_link(panel, REG_DP_START_HOR_VER_FROM_SYNC + offset, sync_start); + msm_dp_write_link(panel, REG_DP_HSYNC_VSYNC_WIDTH_POLARITY + offset, width_blanking); + msm_dp_write_link(panel, REG_DP_ACTIVE_HOR_VER + offset, msm_dp_active); reg = msm_dp_read_pn(panel, MMSS_DP_INTF_CONFIG); if (wide_bus_en) @@ -807,8 +738,6 @@ int msm_dp_panel_init_panel_info(struct msm_dp_panel *msm_dp_panel) struct msm_dp_panel *msm_dp_panel_get(struct device *dev, struct drm_dp_aux *aux, struct msm_dp_link *link, void __iomem *link_base, - void __iomem *mst2link_base, - void __iomem *mst3link_base, void __iomem *pixel_base) { struct msm_dp_panel_private *panel; @@ -828,8 +757,6 @@ struct msm_dp_panel *msm_dp_panel_get(struct device *dev, struct drm_dp_aux *aux panel->link = link; panel->link_base = link_base; panel->pixel_base = pixel_base; - panel->mst2link_base = mst2link_base; - panel->mst3link_base = mst3link_base; msm_dp_panel = &panel->msm_dp_panel; msm_dp_panel->max_bw_code = DP_LINK_BW_8_1; diff --git a/drivers/gpu/drm/msm/dp/dp_panel.h b/drivers/gpu/drm/msm/dp/dp_panel.h index 8bab27520439c..cd9af2f9c463d 100644 --- a/drivers/gpu/drm/msm/dp/dp_panel.h +++ b/drivers/gpu/drm/msm/dp/dp_panel.h @@ -104,7 +104,5 @@ static inline bool is_lane_count_valid(u32 lane_count) struct msm_dp_panel *msm_dp_panel_get(struct device *dev, struct drm_dp_aux *aux, struct msm_dp_link *link, void __iomem *link_base, - void __iomem *mst2link_base, - void __iomem *mst3link_base, void __iomem *pixel_base); #endif /* _DP_PANEL_H_ */ diff --git a/drivers/gpu/drm/msm/dp/dp_reg.h b/drivers/gpu/drm/msm/dp/dp_reg.h index 65695fcb48d0f..4398108ad8c30 100644 --- a/drivers/gpu/drm/msm/dp/dp_reg.h +++ b/drivers/gpu/drm/msm/dp/dp_reg.h @@ -172,6 +172,7 @@ #define REG_DP_START_HOR_VER_FROM_SYNC (0x00000020) #define REG_DP_HSYNC_VSYNC_WIDTH_POLARITY (0x00000024) #define REG_DP_ACTIVE_HOR_VER (0x00000028) + #define REG_DP_MISC1_MISC0 (0x0000002C) #define DP_MISC0_SYNCHRONOUS_CLK (0x00000001) #define DP_MISC0_COLORIMETRY_CFG_SHIFT (0x00000001) @@ -360,23 +361,9 @@ #define REG_DP_DP0_RG (0x000004F8) #define REG_DP_DP1_RG (0x000004FC) -#define REG_DP_MSTLINK_STATE_CTRL (0x00000000) -#define REG_DP_MSTLINK_CONFIGURATION_CTRL (0x00000034) #define REG_DP_MSTLINK_TIMESLOT_1_32 (0x00000038) #define REG_DP_MSTLINK_TIMESLOT_33_63 (0x0000003C) -#define REG_MSTLINK_SOFTWARE_MVID (0x00000040) -#define REG_MSTLINK_SOFTWARE_NVID (0x00000044) -#define REG_DP_MSTLINK_TOTAL_HOR_VER (0x00000048) -#define REG_DP_MSTLINK_START_HOR_VER_FROM_SYNC (0x0000004C) -#define REG_DP_MSTLINK_HSYNC_VSYNC_WIDTH_POLARITY (0x00000050) -#define REG_DP_MSTLINK_ACTIVE_HOR_VER (0x00000054) -#define REG_DP_MSTLINK_MISC1_MISC0 (0x00000058) -#define MMSS_DP_MSTLINK_GENERIC0_0 (0x000000BC) -#define MMSS_DP_MSTLINK_GENERIC0_1 (0x000000C0) -#define MMSS_DP_MSTLINK_GENERIC0_2 (0x000000C4) -#define MMSS_DP_MSTLINK_SDP_CFG (0x0000010c) -#define MMSS_DP_MSTLINK_SDP_CFG2 (0x0000011c) -#define MMSS_DP_MSTLINK_SDP_CFG3 (0x00000114) + #define MMSS_DP_ASYNC_FIFO_CONFIG (0x00000088) From 1d881cc0889847da74235c40d58f3b4f56b5ad80 Mon Sep 17 00:00:00 2001 From: Yongxing Mou Date: Mon, 7 Sep 2026 12:37:41 +0800 Subject: [PATCH 2/4] Revert "FROMLIST: drm/msm/dp: Add support for programming p1/p2/p3 register blocks" This reverts commit c8a98357d82dfbc75289d200a530b43068ab18e1. This is reverted because a newer version of this patch is being introduced. --- drivers/gpu/drm/msm/dp/dp_display.c | 43 +++++--------- drivers/gpu/drm/msm/dp/dp_panel.c | 88 ++++++++++++++--------------- drivers/gpu/drm/msm/dp/dp_panel.h | 2 +- 3 files changed, 58 insertions(+), 75 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/dp_display.c index 94a7bc5dbbf00..f65be5c51dd2d 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -87,8 +87,8 @@ struct msm_dp_display_private { void __iomem *link_base; size_t link_len; - void __iomem *pixel_base[DP_STREAM_MAX]; - size_t pixel_len; + void __iomem *p0_base; + size_t p0_len; int max_stream; }; @@ -595,7 +595,7 @@ struct msm_dp_panel *msm_dp_display_get_panel(struct msm_dp *msm_dp_display) dp = container_of(msm_dp_display, struct msm_dp_display_private, msm_dp_display); dp_panel = msm_dp_panel_get(&dp->msm_dp_display.pdev->dev, dp->aux, dp->link, - dp->link_base, dp->pixel_base[0]); + dp->link_base, dp->p0_base); if (IS_ERR(dp->panel)) { DRM_ERROR("failed to initialize panel\n"); @@ -649,7 +649,7 @@ static int msm_dp_init_sub_modules(struct msm_dp_display_private *dp) goto error_link; } - dp->panel = msm_dp_panel_get(dev, dp->aux, dp->link, dp->link_base, dp->pixel_base[0]); + dp->panel = msm_dp_panel_get(dev, dp->aux, dp->link, dp->link_base, dp->p0_base); if (IS_ERR(dp->panel)) { rc = PTR_ERR(dp->panel); DRM_ERROR("failed to initialize panel, rc = %d\n", rc); @@ -853,7 +853,7 @@ int msm_dp_display_set_stream_info(struct msm_dp *msm_dp_display, struct msm_dp_ if (panel) { panel->stream_id = stream_id; panel->pbn = pbn; - msm_dp_panel_set_pixel_base(panel, dp->pixel_base[stream_id]); + msm_dp_panel_set_pixel_base(panel, dp->p0_base); } return rc; @@ -968,14 +968,8 @@ void msm_dp_snapshot(struct msm_disp_state *disp_state, struct msm_dp *dp) msm_dp_display->aux_base, "dp_aux"); msm_disp_snapshot_add_block(disp_state, msm_dp_display->link_len, msm_dp_display->link_base, "dp_link"); - msm_disp_snapshot_add_block(disp_state, msm_dp_display->pixel_len, - msm_dp_display->pixel_base[0], "dp_p0"); - msm_disp_snapshot_add_block(disp_state, msm_dp_display->pixel_len, - msm_dp_display->pixel_base[1], "dp_p1"); - msm_disp_snapshot_add_block(disp_state, msm_dp_display->pixel_len, - msm_dp_display->pixel_base[2], "dp_p2"); - msm_disp_snapshot_add_block(disp_state, msm_dp_display->pixel_len, - msm_dp_display->pixel_base[3], "dp_p3"); + msm_disp_snapshot_add_block(disp_state, msm_dp_display->p0_len, + msm_dp_display->p0_base, "dp_p0"); } void msm_dp_display_set_psr(struct msm_dp *msm_dp_display, bool enter) @@ -1264,7 +1258,6 @@ static void __iomem *msm_dp_ioremap(struct platform_device *pdev, int idx, size_ static int msm_dp_display_get_io(struct msm_dp_display_private *display) { struct platform_device *pdev = display->msm_dp_display.pdev; - int i; display->ahb_base = msm_dp_ioremap(pdev, 0, &display->ahb_len); if (IS_ERR(display->ahb_base)) @@ -1294,8 +1287,8 @@ static int msm_dp_display_get_io(struct msm_dp_display_private *display) display->aux_len = DP_DEFAULT_AUX_SIZE; display->link_base = display->ahb_base + DP_DEFAULT_LINK_OFFSET; display->link_len = DP_DEFAULT_LINK_SIZE; - display->pixel_base[0] = display->ahb_base + DP_DEFAULT_P0_OFFSET; - display->pixel_len = DP_DEFAULT_P0_SIZE; + display->p0_base = display->ahb_base + DP_DEFAULT_P0_OFFSET; + display->p0_len = DP_DEFAULT_P0_SIZE; return 0; } @@ -1306,20 +1299,10 @@ static int msm_dp_display_get_io(struct msm_dp_display_private *display) return PTR_ERR(display->link_base); } - display->pixel_base[0] = msm_dp_ioremap(pdev, 3, &display->pixel_len); - if (IS_ERR(display->pixel_base[0])) { - DRM_ERROR("unable to remap p0 region: %pe\n", display->pixel_base[0]); - return PTR_ERR(display->pixel_base[0]); - } - - for (i = DP_STREAM_1; i < display->max_stream; i++) { - /* pixels clk reg index start from 3*/ - display->pixel_base[i] = msm_dp_ioremap(pdev, i + 3, &display->pixel_len); - if (IS_ERR(display->pixel_base[i])) { - DRM_DEBUG_DP("unable to remap p%d region: %pe\n", i, - display->pixel_base[i]); - break; - } + display->p0_base = msm_dp_ioremap(pdev, 3, &display->p0_len); + if (IS_ERR(display->p0_base)) { + DRM_ERROR("unable to remap p0 region: %pe\n", display->p0_base); + return PTR_ERR(display->p0_base); } return 0; diff --git a/drivers/gpu/drm/msm/dp/dp_panel.c b/drivers/gpu/drm/msm/dp/dp_panel.c index 34b9079e27d82..435577eb6d9ac 100644 --- a/drivers/gpu/drm/msm/dp/dp_panel.c +++ b/drivers/gpu/drm/msm/dp/dp_panel.c @@ -25,7 +25,7 @@ struct msm_dp_panel_private { struct drm_dp_aux *aux; struct msm_dp_link *link; void __iomem *link_base; - void __iomem *pixel_base; + void __iomem *p0_base; bool panel_on; }; @@ -44,24 +44,24 @@ static inline void msm_dp_write_link(struct msm_dp_panel_private *panel, writel(data, panel->link_base + offset); } -static inline void msm_dp_write_pn(struct msm_dp_panel_private *panel, - u32 offset, u32 data) +static inline void msm_dp_write_p0(struct msm_dp_panel_private *panel, + u32 offset, u32 data) { /* * To make sure interface reg writes happens before any other operation, * this function uses writel() instread of writel_relaxed() */ - writel(data, panel->pixel_base + offset); + writel(data, panel->p0_base + offset); } -static inline u32 msm_dp_read_pn(struct msm_dp_panel_private *panel, - u32 offset) +static inline u32 msm_dp_read_p0(struct msm_dp_panel_private *panel, + u32 offset) { /* * To make sure interface reg writes happens before any other operation, * this function uses writel() instread of writel_relaxed() */ - return readl_relaxed(panel->pixel_base + offset); + return readl_relaxed(panel->p0_base + offset); } static void msm_dp_panel_read_psr_cap(struct msm_dp_panel_private *panel) @@ -367,34 +367,34 @@ static void msm_dp_panel_tpg_enable(struct msm_dp_panel *msm_dp_panel, display_hctl = (hsync_end_x << 16) | hsync_start_x; - msm_dp_write_pn(panel, MMSS_DP_INTF_HSYNC_CTL, hsync_ctl); - msm_dp_write_pn(panel, MMSS_DP_INTF_VSYNC_PERIOD_F0, vsync_period * + msm_dp_write_p0(panel, MMSS_DP_INTF_HSYNC_CTL, hsync_ctl); + msm_dp_write_p0(panel, MMSS_DP_INTF_VSYNC_PERIOD_F0, vsync_period * hsync_period); - msm_dp_write_pn(panel, MMSS_DP_INTF_VSYNC_PULSE_WIDTH_F0, v_sync_width * + msm_dp_write_p0(panel, MMSS_DP_INTF_VSYNC_PULSE_WIDTH_F0, v_sync_width * hsync_period); - msm_dp_write_pn(panel, MMSS_DP_INTF_VSYNC_PERIOD_F1, 0); - msm_dp_write_pn(panel, MMSS_DP_INTF_VSYNC_PULSE_WIDTH_F1, 0); - msm_dp_write_pn(panel, MMSS_DP_INTF_DISPLAY_HCTL, display_hctl); - msm_dp_write_pn(panel, MMSS_DP_INTF_ACTIVE_HCTL, 0); - msm_dp_write_pn(panel, MMSS_INTF_DISPLAY_V_START_F0, display_v_start); - msm_dp_write_pn(panel, MMSS_DP_INTF_DISPLAY_V_END_F0, display_v_end); - msm_dp_write_pn(panel, MMSS_INTF_DISPLAY_V_START_F1, 0); - msm_dp_write_pn(panel, MMSS_DP_INTF_DISPLAY_V_END_F1, 0); - msm_dp_write_pn(panel, MMSS_DP_INTF_ACTIVE_V_START_F0, 0); - msm_dp_write_pn(panel, MMSS_DP_INTF_ACTIVE_V_END_F0, 0); - msm_dp_write_pn(panel, MMSS_DP_INTF_ACTIVE_V_START_F1, 0); - msm_dp_write_pn(panel, MMSS_DP_INTF_ACTIVE_V_END_F1, 0); - msm_dp_write_pn(panel, MMSS_DP_INTF_POLARITY_CTL, 0); - - msm_dp_write_pn(panel, MMSS_DP_TPG_MAIN_CONTROL, - DP_TPG_CHECKERED_RECT_PATTERN); - msm_dp_write_pn(panel, MMSS_DP_TPG_VIDEO_CONFIG, - DP_TPG_VIDEO_CONFIG_BPP_8BIT | - DP_TPG_VIDEO_CONFIG_RGB); - msm_dp_write_pn(panel, MMSS_DP_BIST_ENABLE, - DP_BIST_ENABLE_DPBIST_EN); - msm_dp_write_pn(panel, MMSS_DP_TIMING_ENGINE_EN, - DP_TIMING_ENGINE_EN_EN); + msm_dp_write_p0(panel, MMSS_DP_INTF_VSYNC_PERIOD_F1, 0); + msm_dp_write_p0(panel, MMSS_DP_INTF_VSYNC_PULSE_WIDTH_F1, 0); + msm_dp_write_p0(panel, MMSS_DP_INTF_DISPLAY_HCTL, display_hctl); + msm_dp_write_p0(panel, MMSS_DP_INTF_ACTIVE_HCTL, 0); + msm_dp_write_p0(panel, MMSS_INTF_DISPLAY_V_START_F0, display_v_start); + msm_dp_write_p0(panel, MMSS_DP_INTF_DISPLAY_V_END_F0, display_v_end); + msm_dp_write_p0(panel, MMSS_INTF_DISPLAY_V_START_F1, 0); + msm_dp_write_p0(panel, MMSS_DP_INTF_DISPLAY_V_END_F1, 0); + msm_dp_write_p0(panel, MMSS_DP_INTF_ACTIVE_V_START_F0, 0); + msm_dp_write_p0(panel, MMSS_DP_INTF_ACTIVE_V_END_F0, 0); + msm_dp_write_p0(panel, MMSS_DP_INTF_ACTIVE_V_START_F1, 0); + msm_dp_write_p0(panel, MMSS_DP_INTF_ACTIVE_V_END_F1, 0); + msm_dp_write_p0(panel, MMSS_DP_INTF_POLARITY_CTL, 0); + + msm_dp_write_p0(panel, MMSS_DP_TPG_MAIN_CONTROL, + DP_TPG_CHECKERED_RECT_PATTERN); + msm_dp_write_p0(panel, MMSS_DP_TPG_VIDEO_CONFIG, + DP_TPG_VIDEO_CONFIG_BPP_8BIT | + DP_TPG_VIDEO_CONFIG_RGB); + msm_dp_write_p0(panel, MMSS_DP_BIST_ENABLE, + DP_BIST_ENABLE_DPBIST_EN); + msm_dp_write_p0(panel, MMSS_DP_TIMING_ENGINE_EN, + DP_TIMING_ENGINE_EN_EN); drm_dbg_dp(panel->drm_dev, "%s: enabled tpg\n", __func__); } @@ -403,9 +403,9 @@ static void msm_dp_panel_tpg_disable(struct msm_dp_panel *msm_dp_panel) struct msm_dp_panel_private *panel = container_of(msm_dp_panel, struct msm_dp_panel_private, msm_dp_panel); - msm_dp_write_pn(panel, MMSS_DP_TPG_MAIN_CONTROL, 0x0); - msm_dp_write_pn(panel, MMSS_DP_BIST_ENABLE, 0x0); - msm_dp_write_pn(panel, MMSS_DP_TIMING_ENGINE_EN, 0x0); + msm_dp_write_p0(panel, MMSS_DP_TPG_MAIN_CONTROL, 0x0); + msm_dp_write_p0(panel, MMSS_DP_BIST_ENABLE, 0x0); + msm_dp_write_p0(panel, MMSS_DP_TIMING_ENGINE_EN, 0x0); } void msm_dp_panel_tpg_config(struct msm_dp_panel *msm_dp_panel, bool enable) @@ -439,7 +439,7 @@ void msm_dp_panel_clear_dsc_dto(struct msm_dp_panel *msm_dp_panel) struct msm_dp_panel_private *panel = container_of(msm_dp_panel, struct msm_dp_panel_private, msm_dp_panel); - msm_dp_write_pn(panel, MMSS_DP_DSC_DTO, 0x0); + msm_dp_write_p0(panel, MMSS_DP_DSC_DTO, 0x0); } static void msm_dp_panel_send_vsc_sdp(struct msm_dp_panel_private *panel, struct dp_sdp *vsc_sdp) @@ -659,7 +659,7 @@ int msm_dp_panel_timing_cfg(struct msm_dp_panel *msm_dp_panel, bool wide_bus_en) msm_dp_write_link(panel, REG_DP_HSYNC_VSYNC_WIDTH_POLARITY + offset, width_blanking); msm_dp_write_link(panel, REG_DP_ACTIVE_HOR_VER + offset, msm_dp_active); - reg = msm_dp_read_pn(panel, MMSS_DP_INTF_CONFIG); + reg = msm_dp_read_p0(panel, MMSS_DP_INTF_CONFIG); if (wide_bus_en) reg |= DP_INTF_CONFIG_DATABUS_WIDEN; else @@ -667,7 +667,7 @@ int msm_dp_panel_timing_cfg(struct msm_dp_panel *msm_dp_panel, bool wide_bus_en) drm_dbg_dp(panel->drm_dev, "wide_bus_en=%d reg=%#x\n", wide_bus_en, reg); - msm_dp_write_pn(panel, MMSS_DP_INTF_CONFIG, reg); + msm_dp_write_p0(panel, MMSS_DP_INTF_CONFIG, reg); if (msm_dp_panel->msm_dp_mode.out_fmt_is_yuv_420) msm_dp_panel_setup_vsc_sdp_yuv_420(msm_dp_panel); @@ -681,7 +681,7 @@ void msm_dp_panel_set_pixel_base(struct msm_dp_panel *msm_dp_panel, void __iomem { struct msm_dp_panel_private *panel = container_of(msm_dp_panel, struct msm_dp_panel_private, msm_dp_panel); - panel->pixel_base = pixel_base; + panel->p0_base = pixel_base; } void msm_dp_panel_mst_async_fifo(struct msm_dp_panel *msm_dp_panel, bool mst_en) @@ -691,9 +691,9 @@ void msm_dp_panel_mst_async_fifo(struct msm_dp_panel *msm_dp_panel, bool mst_en) panel = container_of(msm_dp_panel, struct msm_dp_panel_private, msm_dp_panel); if (mst_en) - msm_dp_write_pn(panel, MMSS_DP_ASYNC_FIFO_CONFIG, 0x01); + msm_dp_write_p0(panel, MMSS_DP_ASYNC_FIFO_CONFIG, 0x01); else - msm_dp_write_pn(panel, MMSS_DP_ASYNC_FIFO_CONFIG, 0x00); + msm_dp_write_p0(panel, MMSS_DP_ASYNC_FIFO_CONFIG, 0x00); } int msm_dp_panel_init_panel_info(struct msm_dp_panel *msm_dp_panel) @@ -738,7 +738,7 @@ int msm_dp_panel_init_panel_info(struct msm_dp_panel *msm_dp_panel) struct msm_dp_panel *msm_dp_panel_get(struct device *dev, struct drm_dp_aux *aux, struct msm_dp_link *link, void __iomem *link_base, - void __iomem *pixel_base) + void __iomem *p0_base) { struct msm_dp_panel_private *panel; struct msm_dp_panel *msm_dp_panel; @@ -756,7 +756,7 @@ struct msm_dp_panel *msm_dp_panel_get(struct device *dev, struct drm_dp_aux *aux panel->aux = aux; panel->link = link; panel->link_base = link_base; - panel->pixel_base = pixel_base; + panel->p0_base = p0_base; msm_dp_panel = &panel->msm_dp_panel; msm_dp_panel->max_bw_code = DP_LINK_BW_8_1; diff --git a/drivers/gpu/drm/msm/dp/dp_panel.h b/drivers/gpu/drm/msm/dp/dp_panel.h index cd9af2f9c463d..371d8b99ab8e4 100644 --- a/drivers/gpu/drm/msm/dp/dp_panel.h +++ b/drivers/gpu/drm/msm/dp/dp_panel.h @@ -104,5 +104,5 @@ static inline bool is_lane_count_valid(u32 lane_count) struct msm_dp_panel *msm_dp_panel_get(struct device *dev, struct drm_dp_aux *aux, struct msm_dp_link *link, void __iomem *link_base, - void __iomem *pixel_base); + void __iomem *p0_base); #endif /* _DP_PANEL_H_ */ From 85c4742c2aad6d9b61c43033935b67c655ccf7e6 Mon Sep 17 00:00:00 2001 From: Yongxing Mou Date: Mon, 7 Sep 2026 13:54:22 +0800 Subject: [PATCH 3/4] FROMLIST: drm/msm/dp: Add support for programming p1/p2/p3 register blocks Add support for additional pixel register blocks (p1, p2, p3) to enable 4-stream MST pixel clocks. Introduce the helper functions msm_dp_read_pn and msm_dp_write_pn for pixel register programming. All pixel clocks share the same register layout but use different base addresses. Signed-off-by: Abhinav Kumar Signed-off-by: Yongxing Mou Link: https://lore.kernel.org/all/20260831-msm-dp-mst-v6-5-c91d35d6fb9e@oss.qualcomm.com/ --- drivers/gpu/drm/msm/dp/dp_ctrl.c | 10 ++++ drivers/gpu/drm/msm/dp/dp_ctrl.h | 2 + drivers/gpu/drm/msm/dp/dp_display.c | 43 ++++++++++----- drivers/gpu/drm/msm/dp/dp_panel.c | 86 ++++++++++++++--------------- drivers/gpu/drm/msm/dp/dp_panel.h | 2 +- 5 files changed, 86 insertions(+), 57 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_ctrl.c index 8aced87815787..b3beb7e3a109e 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.c +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c @@ -3091,6 +3091,16 @@ int msm_dp_ctrl_get_stream_cnt(struct msm_dp_ctrl *msm_dp_ctrl) return ctrl->num_pixel_clks; } +bool msm_dp_ctrl_stream_clks_on(struct msm_dp_ctrl *msm_dp_ctrl, + enum msm_dp_stream_id stream_id) +{ + struct msm_dp_ctrl_private *ctrl; + + ctrl = container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctrl); + + return ctrl->stream_clks_on[stream_id]; +} + struct msm_dp_ctrl *msm_dp_ctrl_get(struct device *dev, struct msm_dp_link *link, struct msm_dp_panel *panel, struct drm_dp_aux *aux, struct phy *phy, diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.h b/drivers/gpu/drm/msm/dp/dp_ctrl.h index 17a54d96f954a..6680f0a67ec08 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.h +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.h @@ -50,6 +50,8 @@ void msm_dp_ctrl_disable_irq(struct msm_dp_ctrl *msm_dp_ctrl); void msm_dp_ctrl_reinit_phy(struct msm_dp_ctrl *msm_dp_ctrl); int msm_dp_ctrl_get_stream_cnt(struct msm_dp_ctrl *dp_ctrl); +bool msm_dp_ctrl_stream_clks_on(struct msm_dp_ctrl *dp_ctrl, + enum msm_dp_stream_id stream_id); int msm_dp_ctrl_mst_send_act(struct msm_dp_ctrl *msm_dp_ctrl); void msm_dp_ctrl_mst_stream_channel_slot_setup(struct msm_dp_ctrl *msm_dp_ctrl); void msm_dp_ctrl_set_mst_channel_info(struct msm_dp_ctrl *msm_dp_ctrl, diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/dp_display.c index f65be5c51dd2d..17538bcafd0f0 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -87,8 +87,8 @@ struct msm_dp_display_private { void __iomem *link_base; size_t link_len; - void __iomem *p0_base; - size_t p0_len; + void __iomem *pixel_base[DP_STREAM_MAX]; + size_t pixel_len; int max_stream; }; @@ -595,7 +595,7 @@ struct msm_dp_panel *msm_dp_display_get_panel(struct msm_dp *msm_dp_display) dp = container_of(msm_dp_display, struct msm_dp_display_private, msm_dp_display); dp_panel = msm_dp_panel_get(&dp->msm_dp_display.pdev->dev, dp->aux, dp->link, - dp->link_base, dp->p0_base); + dp->link_base, dp->pixel_base[0]); if (IS_ERR(dp->panel)) { DRM_ERROR("failed to initialize panel\n"); @@ -649,7 +649,7 @@ static int msm_dp_init_sub_modules(struct msm_dp_display_private *dp) goto error_link; } - dp->panel = msm_dp_panel_get(dev, dp->aux, dp->link, dp->link_base, dp->p0_base); + dp->panel = msm_dp_panel_get(dev, dp->aux, dp->link, dp->link_base, dp->pixel_base[0]); if (IS_ERR(dp->panel)) { rc = PTR_ERR(dp->panel); DRM_ERROR("failed to initialize panel, rc = %d\n", rc); @@ -853,7 +853,7 @@ int msm_dp_display_set_stream_info(struct msm_dp *msm_dp_display, struct msm_dp_ if (panel) { panel->stream_id = stream_id; panel->pbn = pbn; - msm_dp_panel_set_pixel_base(panel, dp->p0_base); + msm_dp_panel_set_pixel_base(panel, dp->pixel_base[stream_id]); } return rc; @@ -968,8 +968,12 @@ void msm_dp_snapshot(struct msm_disp_state *disp_state, struct msm_dp *dp) msm_dp_display->aux_base, "dp_aux"); msm_disp_snapshot_add_block(disp_state, msm_dp_display->link_len, msm_dp_display->link_base, "dp_link"); - msm_disp_snapshot_add_block(disp_state, msm_dp_display->p0_len, - msm_dp_display->p0_base, "dp_p0"); + for (int i = 0; i < DP_STREAM_MAX; i++) { + if (!msm_dp_ctrl_stream_clks_on(msm_dp_display->ctrl, i)) + continue; + msm_disp_snapshot_add_block(disp_state, msm_dp_display->pixel_len, + msm_dp_display->pixel_base[i], "dp_p%d", i); + } } void msm_dp_display_set_psr(struct msm_dp *msm_dp_display, bool enter) @@ -1258,6 +1262,7 @@ static void __iomem *msm_dp_ioremap(struct platform_device *pdev, int idx, size_ static int msm_dp_display_get_io(struct msm_dp_display_private *display) { struct platform_device *pdev = display->msm_dp_display.pdev; + int i; display->ahb_base = msm_dp_ioremap(pdev, 0, &display->ahb_len); if (IS_ERR(display->ahb_base)) @@ -1287,8 +1292,8 @@ static int msm_dp_display_get_io(struct msm_dp_display_private *display) display->aux_len = DP_DEFAULT_AUX_SIZE; display->link_base = display->ahb_base + DP_DEFAULT_LINK_OFFSET; display->link_len = DP_DEFAULT_LINK_SIZE; - display->p0_base = display->ahb_base + DP_DEFAULT_P0_OFFSET; - display->p0_len = DP_DEFAULT_P0_SIZE; + display->pixel_base[0] = display->ahb_base + DP_DEFAULT_P0_OFFSET; + display->pixel_len = DP_DEFAULT_P0_SIZE; return 0; } @@ -1299,10 +1304,22 @@ static int msm_dp_display_get_io(struct msm_dp_display_private *display) return PTR_ERR(display->link_base); } - display->p0_base = msm_dp_ioremap(pdev, 3, &display->p0_len); - if (IS_ERR(display->p0_base)) { - DRM_ERROR("unable to remap p0 region: %pe\n", display->p0_base); - return PTR_ERR(display->p0_base); + display->pixel_base[0] = msm_dp_ioremap(pdev, 3, &display->pixel_len); + if (IS_ERR(display->pixel_base[0])) + return PTR_ERR(display->pixel_base[0]); + + for (i = DP_STREAM_1; i < DP_STREAM_MAX; i++) { + display->pixel_base[i] = msm_dp_ioremap(pdev, i + 3, &display->pixel_len); + if (IS_ERR(display->pixel_base[i])) { + int ret = PTR_ERR(display->pixel_base[i]); + + if (ret == -EINVAL) { + /* optional resource not present in DT */ + display->pixel_base[i] = NULL; + break; + } + return ret; + } } return 0; diff --git a/drivers/gpu/drm/msm/dp/dp_panel.c b/drivers/gpu/drm/msm/dp/dp_panel.c index 435577eb6d9ac..42a1d084b2300 100644 --- a/drivers/gpu/drm/msm/dp/dp_panel.c +++ b/drivers/gpu/drm/msm/dp/dp_panel.c @@ -25,7 +25,7 @@ struct msm_dp_panel_private { struct drm_dp_aux *aux; struct msm_dp_link *link; void __iomem *link_base; - void __iomem *p0_base; + void __iomem *pixel_base; bool panel_on; }; @@ -44,24 +44,24 @@ static inline void msm_dp_write_link(struct msm_dp_panel_private *panel, writel(data, panel->link_base + offset); } -static inline void msm_dp_write_p0(struct msm_dp_panel_private *panel, - u32 offset, u32 data) +static inline void msm_dp_write_pn(struct msm_dp_panel_private *panel, + u32 offset, u32 data) { /* - * To make sure interface reg writes happens before any other operation, - * this function uses writel() instread of writel_relaxed() + * Use writel() instead of writel_relaxed() to ensure the interface + * register write reaches the hardware before subsequent operations. */ - writel(data, panel->p0_base + offset); + writel(data, panel->pixel_base + offset); } -static inline u32 msm_dp_read_p0(struct msm_dp_panel_private *panel, - u32 offset) +static inline u32 msm_dp_read_pn(struct msm_dp_panel_private *panel, + u32 offset) { /* - * To make sure interface reg writes happens before any other operation, - * this function uses writel() instread of writel_relaxed() + * Only reads a configuration register: no DMA or memory ordering is + * required, so readl_relaxed() is sufficient. */ - return readl_relaxed(panel->p0_base + offset); + return readl_relaxed(panel->pixel_base + offset); } static void msm_dp_panel_read_psr_cap(struct msm_dp_panel_private *panel) @@ -367,33 +367,33 @@ static void msm_dp_panel_tpg_enable(struct msm_dp_panel *msm_dp_panel, display_hctl = (hsync_end_x << 16) | hsync_start_x; - msm_dp_write_p0(panel, MMSS_DP_INTF_HSYNC_CTL, hsync_ctl); - msm_dp_write_p0(panel, MMSS_DP_INTF_VSYNC_PERIOD_F0, vsync_period * + msm_dp_write_pn(panel, MMSS_DP_INTF_HSYNC_CTL, hsync_ctl); + msm_dp_write_pn(panel, MMSS_DP_INTF_VSYNC_PERIOD_F0, vsync_period * hsync_period); - msm_dp_write_p0(panel, MMSS_DP_INTF_VSYNC_PULSE_WIDTH_F0, v_sync_width * + msm_dp_write_pn(panel, MMSS_DP_INTF_VSYNC_PULSE_WIDTH_F0, v_sync_width * hsync_period); - msm_dp_write_p0(panel, MMSS_DP_INTF_VSYNC_PERIOD_F1, 0); - msm_dp_write_p0(panel, MMSS_DP_INTF_VSYNC_PULSE_WIDTH_F1, 0); - msm_dp_write_p0(panel, MMSS_DP_INTF_DISPLAY_HCTL, display_hctl); - msm_dp_write_p0(panel, MMSS_DP_INTF_ACTIVE_HCTL, 0); - msm_dp_write_p0(panel, MMSS_INTF_DISPLAY_V_START_F0, display_v_start); - msm_dp_write_p0(panel, MMSS_DP_INTF_DISPLAY_V_END_F0, display_v_end); - msm_dp_write_p0(panel, MMSS_INTF_DISPLAY_V_START_F1, 0); - msm_dp_write_p0(panel, MMSS_DP_INTF_DISPLAY_V_END_F1, 0); - msm_dp_write_p0(panel, MMSS_DP_INTF_ACTIVE_V_START_F0, 0); - msm_dp_write_p0(panel, MMSS_DP_INTF_ACTIVE_V_END_F0, 0); - msm_dp_write_p0(panel, MMSS_DP_INTF_ACTIVE_V_START_F1, 0); - msm_dp_write_p0(panel, MMSS_DP_INTF_ACTIVE_V_END_F1, 0); - msm_dp_write_p0(panel, MMSS_DP_INTF_POLARITY_CTL, 0); - - msm_dp_write_p0(panel, MMSS_DP_TPG_MAIN_CONTROL, + msm_dp_write_pn(panel, MMSS_DP_INTF_VSYNC_PERIOD_F1, 0); + msm_dp_write_pn(panel, MMSS_DP_INTF_VSYNC_PULSE_WIDTH_F1, 0); + msm_dp_write_pn(panel, MMSS_DP_INTF_DISPLAY_HCTL, display_hctl); + msm_dp_write_pn(panel, MMSS_DP_INTF_ACTIVE_HCTL, 0); + msm_dp_write_pn(panel, MMSS_INTF_DISPLAY_V_START_F0, display_v_start); + msm_dp_write_pn(panel, MMSS_DP_INTF_DISPLAY_V_END_F0, display_v_end); + msm_dp_write_pn(panel, MMSS_INTF_DISPLAY_V_START_F1, 0); + msm_dp_write_pn(panel, MMSS_DP_INTF_DISPLAY_V_END_F1, 0); + msm_dp_write_pn(panel, MMSS_DP_INTF_ACTIVE_V_START_F0, 0); + msm_dp_write_pn(panel, MMSS_DP_INTF_ACTIVE_V_END_F0, 0); + msm_dp_write_pn(panel, MMSS_DP_INTF_ACTIVE_V_START_F1, 0); + msm_dp_write_pn(panel, MMSS_DP_INTF_ACTIVE_V_END_F1, 0); + msm_dp_write_pn(panel, MMSS_DP_INTF_POLARITY_CTL, 0); + + msm_dp_write_pn(panel, MMSS_DP_TPG_MAIN_CONTROL, DP_TPG_CHECKERED_RECT_PATTERN); - msm_dp_write_p0(panel, MMSS_DP_TPG_VIDEO_CONFIG, + msm_dp_write_pn(panel, MMSS_DP_TPG_VIDEO_CONFIG, DP_TPG_VIDEO_CONFIG_BPP_8BIT | DP_TPG_VIDEO_CONFIG_RGB); - msm_dp_write_p0(panel, MMSS_DP_BIST_ENABLE, + msm_dp_write_pn(panel, MMSS_DP_BIST_ENABLE, DP_BIST_ENABLE_DPBIST_EN); - msm_dp_write_p0(panel, MMSS_DP_TIMING_ENGINE_EN, + msm_dp_write_pn(panel, MMSS_DP_TIMING_ENGINE_EN, DP_TIMING_ENGINE_EN_EN); drm_dbg_dp(panel->drm_dev, "%s: enabled tpg\n", __func__); } @@ -403,9 +403,9 @@ static void msm_dp_panel_tpg_disable(struct msm_dp_panel *msm_dp_panel) struct msm_dp_panel_private *panel = container_of(msm_dp_panel, struct msm_dp_panel_private, msm_dp_panel); - msm_dp_write_p0(panel, MMSS_DP_TPG_MAIN_CONTROL, 0x0); - msm_dp_write_p0(panel, MMSS_DP_BIST_ENABLE, 0x0); - msm_dp_write_p0(panel, MMSS_DP_TIMING_ENGINE_EN, 0x0); + msm_dp_write_pn(panel, MMSS_DP_TPG_MAIN_CONTROL, 0x0); + msm_dp_write_pn(panel, MMSS_DP_BIST_ENABLE, 0x0); + msm_dp_write_pn(panel, MMSS_DP_TIMING_ENGINE_EN, 0x0); } void msm_dp_panel_tpg_config(struct msm_dp_panel *msm_dp_panel, bool enable) @@ -439,7 +439,7 @@ void msm_dp_panel_clear_dsc_dto(struct msm_dp_panel *msm_dp_panel) struct msm_dp_panel_private *panel = container_of(msm_dp_panel, struct msm_dp_panel_private, msm_dp_panel); - msm_dp_write_p0(panel, MMSS_DP_DSC_DTO, 0x0); + msm_dp_write_pn(panel, MMSS_DP_DSC_DTO, 0x0); } static void msm_dp_panel_send_vsc_sdp(struct msm_dp_panel_private *panel, struct dp_sdp *vsc_sdp) @@ -659,7 +659,7 @@ int msm_dp_panel_timing_cfg(struct msm_dp_panel *msm_dp_panel, bool wide_bus_en) msm_dp_write_link(panel, REG_DP_HSYNC_VSYNC_WIDTH_POLARITY + offset, width_blanking); msm_dp_write_link(panel, REG_DP_ACTIVE_HOR_VER + offset, msm_dp_active); - reg = msm_dp_read_p0(panel, MMSS_DP_INTF_CONFIG); + reg = msm_dp_read_pn(panel, MMSS_DP_INTF_CONFIG); if (wide_bus_en) reg |= DP_INTF_CONFIG_DATABUS_WIDEN; else @@ -667,7 +667,7 @@ int msm_dp_panel_timing_cfg(struct msm_dp_panel *msm_dp_panel, bool wide_bus_en) drm_dbg_dp(panel->drm_dev, "wide_bus_en=%d reg=%#x\n", wide_bus_en, reg); - msm_dp_write_p0(panel, MMSS_DP_INTF_CONFIG, reg); + msm_dp_write_pn(panel, MMSS_DP_INTF_CONFIG, reg); if (msm_dp_panel->msm_dp_mode.out_fmt_is_yuv_420) msm_dp_panel_setup_vsc_sdp_yuv_420(msm_dp_panel); @@ -681,7 +681,7 @@ void msm_dp_panel_set_pixel_base(struct msm_dp_panel *msm_dp_panel, void __iomem { struct msm_dp_panel_private *panel = container_of(msm_dp_panel, struct msm_dp_panel_private, msm_dp_panel); - panel->p0_base = pixel_base; + panel->pixel_base = pixel_base; } void msm_dp_panel_mst_async_fifo(struct msm_dp_panel *msm_dp_panel, bool mst_en) @@ -691,9 +691,9 @@ void msm_dp_panel_mst_async_fifo(struct msm_dp_panel *msm_dp_panel, bool mst_en) panel = container_of(msm_dp_panel, struct msm_dp_panel_private, msm_dp_panel); if (mst_en) - msm_dp_write_p0(panel, MMSS_DP_ASYNC_FIFO_CONFIG, 0x01); + msm_dp_write_pn(panel, MMSS_DP_ASYNC_FIFO_CONFIG, 0x01); else - msm_dp_write_p0(panel, MMSS_DP_ASYNC_FIFO_CONFIG, 0x00); + msm_dp_write_pn(panel, MMSS_DP_ASYNC_FIFO_CONFIG, 0x00); } int msm_dp_panel_init_panel_info(struct msm_dp_panel *msm_dp_panel) @@ -738,7 +738,7 @@ int msm_dp_panel_init_panel_info(struct msm_dp_panel *msm_dp_panel) struct msm_dp_panel *msm_dp_panel_get(struct device *dev, struct drm_dp_aux *aux, struct msm_dp_link *link, void __iomem *link_base, - void __iomem *p0_base) + void __iomem *pixel_base) { struct msm_dp_panel_private *panel; struct msm_dp_panel *msm_dp_panel; @@ -756,7 +756,7 @@ struct msm_dp_panel *msm_dp_panel_get(struct device *dev, struct drm_dp_aux *aux panel->aux = aux; panel->link = link; panel->link_base = link_base; - panel->p0_base = p0_base; + panel->pixel_base = pixel_base; msm_dp_panel = &panel->msm_dp_panel; msm_dp_panel->max_bw_code = DP_LINK_BW_8_1; diff --git a/drivers/gpu/drm/msm/dp/dp_panel.h b/drivers/gpu/drm/msm/dp/dp_panel.h index 371d8b99ab8e4..cd9af2f9c463d 100644 --- a/drivers/gpu/drm/msm/dp/dp_panel.h +++ b/drivers/gpu/drm/msm/dp/dp_panel.h @@ -104,5 +104,5 @@ static inline bool is_lane_count_valid(u32 lane_count) struct msm_dp_panel *msm_dp_panel_get(struct device *dev, struct drm_dp_aux *aux, struct msm_dp_link *link, void __iomem *link_base, - void __iomem *p0_base); + void __iomem *pixel_base); #endif /* _DP_PANEL_H_ */ From da47e701dece78a97da595a79e4b2d1293afb5a2 Mon Sep 17 00:00:00 2001 From: Yongxing Mou Date: Mon, 7 Sep 2026 14:11:42 +0800 Subject: [PATCH 4/4] FROMLIST: drm/msm/dp: Add stream-aware link register accessors DisplayPort MST uses multiple stream-specific register spaces. Streams 0 and 1 share the primary link register block with different register offsets, while streams 2 and 3 use dedicated MST link register blocks. Add stream-aware register access helpers that translate stream-specific register offsets and route accesses to the appropriate register space based on the stream id. Signed-off-by: Abhinav Kumar Signed-off-by: Yongxing Mou Link: https://lore.kernel.org/all/20260831-msm-dp-mst-v6-7-c91d35d6fb9e@oss.qualcomm.com/ --- drivers/gpu/drm/msm/dp/dp_ctrl.c | 242 +++++++++++++++++----------- drivers/gpu/drm/msm/dp/dp_ctrl.h | 4 +- drivers/gpu/drm/msm/dp/dp_display.c | 34 +++- drivers/gpu/drm/msm/dp/dp_panel.c | 135 ++++++++++++---- drivers/gpu/drm/msm/dp/dp_panel.h | 2 + drivers/gpu/drm/msm/dp/dp_reg.h | 17 +- 6 files changed, 302 insertions(+), 132 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_ctrl.c index b3beb7e3a109e..77ac5a4958996 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.c +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c @@ -133,6 +133,8 @@ struct msm_dp_ctrl_private { struct msm_dp_link *link; void __iomem *ahb_base; void __iomem *link_base; + void __iomem *mst2link_base; + void __iomem *mst3link_base; struct phy *phy; @@ -176,19 +178,45 @@ static inline void msm_dp_write_ahb(struct msm_dp_ctrl_private *ctrl, writel(data, ctrl->ahb_base + offset); } -static inline u32 msm_dp_read_link(struct msm_dp_ctrl_private *ctrl, u32 offset) +static inline u32 msm_dp_read_link(struct msm_dp_ctrl_private *ctrl, + enum msm_dp_stream_id stream_id, u32 offset) { - return readl_relaxed(ctrl->link_base + offset); + switch (stream_id) { + case DP_STREAM_0: + case DP_STREAM_1: + return readl_relaxed(ctrl->link_base + offset); + case DP_STREAM_2: + return readl_relaxed(ctrl->mst2link_base + offset); + case DP_STREAM_3: + return readl_relaxed(ctrl->mst3link_base + offset); + default: + DRM_ERROR("error stream_id\n"); + return 0; + } } static inline void msm_dp_write_link(struct msm_dp_ctrl_private *ctrl, - u32 offset, u32 data) + enum msm_dp_stream_id stream_id, u32 offset, u32 data) { /* * To make sure link reg writes happens before any other operation, * this function uses writel() instread of writel_relaxed() */ - writel(data, ctrl->link_base + offset); + switch (stream_id) { + case DP_STREAM_0: + case DP_STREAM_1: + writel(data, ctrl->link_base + offset); + break; + case DP_STREAM_2: + writel(data, ctrl->mst2link_base + offset); + break; + case DP_STREAM_3: + writel(data, ctrl->mst3link_base + offset); + break; + default: + DRM_ERROR("error stream_id\n"); + break; + } } static int msm_dp_aux_link_configure(struct drm_dp_aux *aux, @@ -228,13 +256,13 @@ int msm_dp_ctrl_mst_send_act(struct msm_dp_ctrl *msm_dp_ctrl) if (!ctrl->mst_active) return 0; - msm_dp_write_link(ctrl, REG_DP_MST_ACT, 0x1); + msm_dp_write_link(ctrl, 0, REG_DP_MST_ACT, 0x1); /* make sure ACT signal is performed */ wmb(); msleep(20); /* needs 1 frame time */ - act_complete = msm_dp_read_link(ctrl, REG_DP_MST_ACT); + act_complete = msm_dp_read_link(ctrl, 0, REG_DP_MST_ACT); if (!act_complete) { drm_dbg_dp(ctrl->drm_dev, "MST ACT trigger complete failed\n"); @@ -248,13 +276,13 @@ static void msm_dp_ctrl_mst_config(struct msm_dp_ctrl_private *ctrl, bool enable { u32 mainlink_ctrl; - mainlink_ctrl = msm_dp_read_link(ctrl, REG_DP_MAINLINK_CTRL); + mainlink_ctrl = msm_dp_read_link(ctrl, 0, REG_DP_MAINLINK_CTRL); if (enable) mainlink_ctrl |= DP_MAINLINK_CTRL_MST_EN; else mainlink_ctrl &= ~DP_MAINLINK_CTRL_MST_EN; - msm_dp_write_link(ctrl, REG_DP_MAINLINK_CTRL, mainlink_ctrl); + msm_dp_write_link(ctrl, 0, REG_DP_MAINLINK_CTRL, mainlink_ctrl); } static void msm_dp_ctrl_mst_channel_alloc(struct msm_dp_ctrl_private *ctrl, @@ -298,10 +326,10 @@ static void msm_dp_ctrl_mst_channel_alloc(struct msm_dp_ctrl_private *ctrl, drm_dbg_dp(ctrl->drm_dev, "stream_id:%d slot_reg_1:%d, slot_reg_2:%d\n", stream_id, slot_reg_1, slot_reg_2); - msm_dp_write_link(ctrl, stream_id > DP_STREAM_1 ? + msm_dp_write_link(ctrl, stream_id, stream_id > DP_STREAM_1 ? REG_DP_MSTLINK_TIMESLOT_1_32 : REG_DP_DP0_TIMESLOT_1_32 + reg_off, slot_reg_1); - msm_dp_write_link(ctrl, stream_id > DP_STREAM_1 ? + msm_dp_write_link(ctrl, stream_id, stream_id > DP_STREAM_1 ? REG_DP_MSTLINK_TIMESLOT_33_63 : REG_DP_DP0_TIMESLOT_33_63 + reg_off, slot_reg_2); } @@ -320,7 +348,7 @@ static void msm_dp_ctrl_update_rg(struct msm_dp_ctrl_private *ctrl, if (stream_id == DP_STREAM_1) reg_off = REG_DP_DP1_RG - REG_DP_DP0_RG; - msm_dp_write_link(ctrl, stream_id > 1 ? + msm_dp_write_link(ctrl, stream_id, stream_id > 1 ? REG_DP_MSTLINK_DP_RG : REG_DP_DP0_RG + reg_off, rg); } @@ -435,18 +463,18 @@ static void msm_dp_ctrl_psr_mainlink_enable(struct msm_dp_ctrl_private *ctrl) { u32 val; - val = msm_dp_read_link(ctrl, REG_DP_MAINLINK_CTRL); + val = msm_dp_read_link(ctrl, 0, REG_DP_MAINLINK_CTRL); val |= DP_MAINLINK_CTRL_ENABLE; - msm_dp_write_link(ctrl, REG_DP_MAINLINK_CTRL, val); + msm_dp_write_link(ctrl, 0, REG_DP_MAINLINK_CTRL, val); } static void msm_dp_ctrl_psr_mainlink_disable(struct msm_dp_ctrl_private *ctrl) { u32 val; - val = msm_dp_read_link(ctrl, REG_DP_MAINLINK_CTRL); + val = msm_dp_read_link(ctrl, 0, REG_DP_MAINLINK_CTRL); val &= ~DP_MAINLINK_CTRL_ENABLE; - msm_dp_write_link(ctrl, REG_DP_MAINLINK_CTRL, val); + msm_dp_write_link(ctrl, 0, REG_DP_MAINLINK_CTRL, val); } static void msm_dp_ctrl_mainlink_enable(struct msm_dp_ctrl_private *ctrl) @@ -455,21 +483,21 @@ static void msm_dp_ctrl_mainlink_enable(struct msm_dp_ctrl_private *ctrl) drm_dbg_dp(ctrl->drm_dev, "enable\n"); - mainlink_ctrl = msm_dp_read_link(ctrl, REG_DP_MAINLINK_CTRL); + mainlink_ctrl = msm_dp_read_link(ctrl, 0, REG_DP_MAINLINK_CTRL); mainlink_ctrl &= ~(DP_MAINLINK_CTRL_RESET | DP_MAINLINK_CTRL_ENABLE); - msm_dp_write_link(ctrl, REG_DP_MAINLINK_CTRL, mainlink_ctrl); + msm_dp_write_link(ctrl, 0, REG_DP_MAINLINK_CTRL, mainlink_ctrl); mainlink_ctrl |= DP_MAINLINK_CTRL_RESET; - msm_dp_write_link(ctrl, REG_DP_MAINLINK_CTRL, mainlink_ctrl); + msm_dp_write_link(ctrl, 0, REG_DP_MAINLINK_CTRL, mainlink_ctrl); mainlink_ctrl &= ~DP_MAINLINK_CTRL_RESET; - msm_dp_write_link(ctrl, REG_DP_MAINLINK_CTRL, mainlink_ctrl); + msm_dp_write_link(ctrl, 0, REG_DP_MAINLINK_CTRL, mainlink_ctrl); mainlink_ctrl |= (DP_MAINLINK_CTRL_ENABLE | DP_MAINLINK_FB_BOUNDARY_SEL); - msm_dp_write_link(ctrl, REG_DP_MAINLINK_CTRL, mainlink_ctrl); + msm_dp_write_link(ctrl, 0, REG_DP_MAINLINK_CTRL, mainlink_ctrl); } static void msm_dp_ctrl_mainlink_disable(struct msm_dp_ctrl_private *ctrl) @@ -478,23 +506,23 @@ static void msm_dp_ctrl_mainlink_disable(struct msm_dp_ctrl_private *ctrl) drm_dbg_dp(ctrl->drm_dev, "disable\n"); - mainlink_ctrl = msm_dp_read_link(ctrl, REG_DP_MAINLINK_CTRL); + mainlink_ctrl = msm_dp_read_link(ctrl, 0, REG_DP_MAINLINK_CTRL); mainlink_ctrl &= ~DP_MAINLINK_CTRL_ENABLE; - msm_dp_write_link(ctrl, REG_DP_MAINLINK_CTRL, mainlink_ctrl); + msm_dp_write_link(ctrl, 0, REG_DP_MAINLINK_CTRL, mainlink_ctrl); } static void msm_dp_setup_peripheral_flush(struct msm_dp_ctrl_private *ctrl) { u32 mainlink_ctrl; - mainlink_ctrl = msm_dp_read_link(ctrl, REG_DP_MAINLINK_CTRL); + mainlink_ctrl = msm_dp_read_link(ctrl, 0, REG_DP_MAINLINK_CTRL); if (ctrl->hw_revision >= DP_HW_VERSION_1_2) mainlink_ctrl |= DP_MAINLINK_FLUSH_MODE_SDE_PERIPH_UPDATE; else mainlink_ctrl |= DP_MAINLINK_FLUSH_MODE_UPDATE_SDP; - msm_dp_write_link(ctrl, REG_DP_MAINLINK_CTRL, mainlink_ctrl); + msm_dp_write_link(ctrl, 0, REG_DP_MAINLINK_CTRL, mainlink_ctrl); } static bool msm_dp_ctrl_mainlink_ready(struct msm_dp_ctrl_private *ctrl) @@ -532,7 +560,10 @@ void msm_dp_ctrl_push_idle(struct msm_dp_ctrl *msm_dp_ctrl, struct msm_dp_panel reinit_completion(&ctrl->idle_comp); - msm_dp_write_link(ctrl, REG_DP_STATE_CTRL, state); + msm_dp_write_link(ctrl, msm_dp_panel->stream_id, + msm_dp_panel->stream_id > 1 ? + REG_DP_MSTLINK_STATE_CTRL : REG_DP_STATE_CTRL, + state); if (!wait_for_completion_timeout(&ctrl->idle_comp, IDLE_PATTERN_COMPLETION_TIMEOUT_JIFFIES)) @@ -547,7 +578,11 @@ static void msm_dp_ctrl_config_ctrl_streams(struct msm_dp_ctrl_private *ctrl, u32 config = 0, tbd; u32 reg_offset = 0; - config = msm_dp_read_link(ctrl, REG_DP_CONFIGURATION_CTRL); + if (msm_dp_panel->stream_id == DP_STREAM_0) + config = msm_dp_read_link(ctrl, 0, REG_DP_CONFIGURATION_CTRL); + + if (msm_dp_panel->stream_id == DP_STREAM_1) + reg_offset = REG_DP1_CONFIGURATION_CTRL - REG_DP_CONFIGURATION_CTRL; if (msm_dp_panel->msm_dp_mode.out_fmt_is_yuv_420) config |= DP_CONFIGURATION_CTRL_RGB_YUV; /* YUV420 */ @@ -562,8 +597,10 @@ static void msm_dp_ctrl_config_ctrl_streams(struct msm_dp_ctrl_private *ctrl, drm_dbg_dp(ctrl->drm_dev, "stream DP_CONFIGURATION_CTRL=0x%x\n", config); - if (msm_dp_panel->stream_id == DP_STREAM_1) - reg_offset = REG_DP1_CONFIGURATION_CTRL - REG_DP_CONFIGURATION_CTRL; + msm_dp_write_link(ctrl, msm_dp_panel->stream_id, msm_dp_panel->stream_id > 1 ? + REG_DP_MSTLINK_CONFIGURATION_CTRL : + REG_DP_CONFIGURATION_CTRL + reg_offset, config); + } static void msm_dp_ctrl_config_ctrl_link(struct msm_dp_ctrl_private *ctrl) @@ -593,7 +630,7 @@ static void msm_dp_ctrl_config_ctrl_link(struct msm_dp_ctrl_private *ctrl) drm_dbg_dp(ctrl->drm_dev, "link DP_CONFIGURATION_CTRL=0x%x\n", config); - msm_dp_write_link(ctrl, REG_DP_CONFIGURATION_CTRL, config); + msm_dp_write_link(ctrl, 0, REG_DP_CONFIGURATION_CTRL, config); } static void msm_dp_ctrl_lane_mapping(struct msm_dp_ctrl_private *ctrl) @@ -606,8 +643,8 @@ static void msm_dp_ctrl_lane_mapping(struct msm_dp_ctrl_private *ctrl) ln_mapping |= lane_map[2] << LANE2_MAPPING_SHIFT; ln_mapping |= lane_map[3] << LANE3_MAPPING_SHIFT; - msm_dp_write_link(ctrl, REG_DP_LOGICAL2PHYSICAL_LANE_MAPPING, - ln_mapping); + msm_dp_write_link(ctrl, 0, REG_DP_LOGICAL2PHYSICAL_LANE_MAPPING, + ln_mapping); } static void msm_dp_ctrl_config_misc1_misc0(struct msm_dp_ctrl_private *ctrl, @@ -623,7 +660,8 @@ static void msm_dp_ctrl_config_misc1_misc0(struct msm_dp_ctrl_private *ctrl, if (msm_dp_panel->stream_id == DP_STREAM_1) reg_offset = REG_DP1_MISC1_MISC0 - REG_DP_MISC1_MISC0; - misc_val = msm_dp_read_link(ctrl, REG_DP_MISC1_MISC0 + reg_offset); + misc_val = msm_dp_read_link(ctrl, msm_dp_panel->stream_id, msm_dp_panel->stream_id > 1 ? + REG_DP_MSTLINK_MISC1_MISC0 : REG_DP_MISC1_MISC0 + reg_offset); /* clear bpp bits */ misc_val &= ~(0x07 << DP_MISC0_TEST_BITS_DEPTH_SHIFT); @@ -633,7 +671,10 @@ static void msm_dp_ctrl_config_misc1_misc0(struct msm_dp_ctrl_private *ctrl, misc_val |= DP_MISC0_SYNCHRONOUS_CLK; drm_dbg_dp(ctrl->drm_dev, "misc settings = 0x%x\n", misc_val); - msm_dp_write_link(ctrl, REG_DP_MISC1_MISC0 + reg_offset, misc_val); + msm_dp_write_link(ctrl, msm_dp_panel->stream_id, + msm_dp_panel->stream_id > 1 ? + REG_DP_MSTLINK_MISC1_MISC0 : REG_DP_MISC1_MISC0 + reg_offset, + misc_val); } static void msm_dp_ctrl_configure_source_params(struct msm_dp_ctrl_private *ctrl, @@ -1461,9 +1502,9 @@ static void msm_dp_ctrl_setup_tr_unit(struct msm_dp_ctrl_private *ctrl) pr_debug("dp_tu=0x%x, valid_boundary=0x%x, valid_boundary2=0x%x\n", msm_dp_tu, valid_boundary, valid_boundary2); - msm_dp_write_link(ctrl, REG_DP_VALID_BOUNDARY, valid_boundary); - msm_dp_write_link(ctrl, REG_DP_TU, msm_dp_tu); - msm_dp_write_link(ctrl, REG_DP_VALID_BOUNDARY_2, valid_boundary2); + msm_dp_write_link(ctrl, 0, REG_DP_VALID_BOUNDARY, valid_boundary); + msm_dp_write_link(ctrl, 0, REG_DP_TU, msm_dp_tu); + msm_dp_write_link(ctrl, 0, REG_DP_VALID_BOUNDARY_2, valid_boundary2); } static int msm_dp_ctrl_wait4video_ready(struct msm_dp_ctrl_private *ctrl) @@ -1580,7 +1621,7 @@ static int msm_dp_ctrl_set_pattern_state_bit(struct msm_dp_ctrl_private *ctrl, bit = BIT(state_bit - 1); drm_dbg_dp(ctrl->drm_dev, "hw: bit=%d train=%d\n", bit, state_bit); - msm_dp_write_link(ctrl, REG_DP_STATE_CTRL, bit); + msm_dp_write_link(ctrl, 0, REG_DP_STATE_CTRL, bit); bit = BIT(state_bit - 1) << DP_MAINLINK_READY_LINK_TRAINING_SHIFT; @@ -1607,7 +1648,7 @@ static int msm_dp_ctrl_link_train_1(struct msm_dp_ctrl_private *ctrl, delay_us = drm_dp_read_clock_recovery_delay(ctrl->aux, ctrl->panel->dpcd, dp_phy, false); - msm_dp_write_link(ctrl, REG_DP_STATE_CTRL, 0); + msm_dp_write_link(ctrl, 0, REG_DP_STATE_CTRL, 0); *training_step = DP_TRAINING_1; @@ -1731,7 +1772,7 @@ static int msm_dp_ctrl_link_train_2(struct msm_dp_ctrl_private *ctrl, delay_us = drm_dp_read_channel_eq_delay(ctrl->aux, ctrl->panel->dpcd, dp_phy, false); - msm_dp_write_link(ctrl, REG_DP_STATE_CTRL, 0); + msm_dp_write_link(ctrl, 0, REG_DP_STATE_CTRL, 0); *training_step = DP_TRAINING_2; @@ -1848,7 +1889,7 @@ static int msm_dp_ctrl_link_train(struct msm_dp_ctrl_private *ctrl, } end: - msm_dp_write_link(ctrl, REG_DP_STATE_CTRL, 0); + msm_dp_write_link(ctrl, 0, REG_DP_STATE_CTRL, 0); return ret; } @@ -1994,34 +2035,34 @@ static int msm_dp_ctrl_enable_mainlink_clocks(struct msm_dp_ctrl_private *ctrl) static void msm_dp_ctrl_enable_sdp(struct msm_dp_ctrl_private *ctrl) { /* trigger sdp */ - msm_dp_write_link(ctrl, MMSS_DP_SDP_CFG3, UPDATE_SDP); - msm_dp_write_link(ctrl, MMSS_DP_SDP_CFG3, 0x0); + msm_dp_write_link(ctrl, 0, MMSS_DP_SDP_CFG3, UPDATE_SDP); + msm_dp_write_link(ctrl, 0, MMSS_DP_SDP_CFG3, 0x0); } static void msm_dp_ctrl_psr_enter(struct msm_dp_ctrl_private *ctrl) { u32 cmd; - cmd = msm_dp_read_link(ctrl, REG_PSR_CMD); + cmd = msm_dp_read_link(ctrl, 0, REG_PSR_CMD); cmd &= ~(PSR_ENTER | PSR_EXIT); cmd |= PSR_ENTER; msm_dp_ctrl_enable_sdp(ctrl); - msm_dp_write_link(ctrl, REG_PSR_CMD, cmd); + msm_dp_write_link(ctrl, 0, REG_PSR_CMD, cmd); } static void msm_dp_ctrl_psr_exit(struct msm_dp_ctrl_private *ctrl) { u32 cmd; - cmd = msm_dp_read_link(ctrl, REG_PSR_CMD); + cmd = msm_dp_read_link(ctrl, 0, REG_PSR_CMD); cmd &= ~(PSR_ENTER | PSR_EXIT); cmd |= PSR_EXIT; msm_dp_ctrl_enable_sdp(ctrl); - msm_dp_write_link(ctrl, REG_PSR_CMD, cmd); + msm_dp_write_link(ctrl, 0, REG_PSR_CMD, cmd); } void msm_dp_ctrl_config_psr(struct msm_dp_ctrl *msm_dp_ctrl) @@ -2034,9 +2075,9 @@ void msm_dp_ctrl_config_psr(struct msm_dp_ctrl *msm_dp_ctrl) return; /* enable PSR1 function */ - cfg = msm_dp_read_link(ctrl, REG_PSR_CONFIG); + cfg = msm_dp_read_link(ctrl, 0, REG_PSR_CONFIG); cfg |= PSR1_SUPPORTED; - msm_dp_write_link(ctrl, REG_PSR_CONFIG, cfg); + msm_dp_write_link(ctrl, 0, REG_PSR_CONFIG, cfg); msm_dp_ctrl_config_psr_interrupt(ctrl); msm_dp_ctrl_enable_sdp(ctrl); @@ -2075,16 +2116,16 @@ void msm_dp_ctrl_set_psr(struct msm_dp_ctrl *msm_dp_ctrl, bool enter) } msm_dp_ctrl_push_idle(msm_dp_ctrl, ctrl->panel); - msm_dp_write_link(ctrl, REG_DP_STATE_CTRL, 0); + msm_dp_write_link(ctrl, 0, REG_DP_STATE_CTRL, 0); msm_dp_ctrl_psr_mainlink_disable(ctrl); } else { msm_dp_ctrl_psr_mainlink_enable(ctrl); msm_dp_ctrl_psr_exit(ctrl); - msm_dp_write_link(ctrl, REG_DP_STATE_CTRL, DP_STATE_CTRL_SEND_VIDEO); + msm_dp_write_link(ctrl, 0, REG_DP_STATE_CTRL, DP_STATE_CTRL_SEND_VIDEO); msm_dp_ctrl_wait4video_ready(ctrl); - msm_dp_write_link(ctrl, REG_DP_STATE_CTRL, 0); + msm_dp_write_link(ctrl, 0, REG_DP_STATE_CTRL, 0); } } @@ -2195,7 +2236,7 @@ static int msm_dp_ctrl_link_maintenance(struct msm_dp_ctrl_private *ctrl) msm_dp_ctrl_clear_training_pattern(ctrl, DP_PHY_DPRX); - msm_dp_write_link(ctrl, REG_DP_STATE_CTRL, DP_STATE_CTRL_SEND_VIDEO); + msm_dp_write_link(ctrl, 0, REG_DP_STATE_CTRL, DP_STATE_CTRL_SEND_VIDEO); ret = msm_dp_ctrl_mst_send_act(&ctrl->msm_dp_ctrl); if (ret) @@ -2214,72 +2255,72 @@ static void msm_dp_ctrl_send_phy_pattern(struct msm_dp_ctrl_private *ctrl, u32 value = 0x0; /* Make sure to clear the current pattern before starting a new one */ - msm_dp_write_link(ctrl, REG_DP_STATE_CTRL, 0x0); + msm_dp_write_link(ctrl, 0, REG_DP_STATE_CTRL, 0x0); drm_dbg_dp(ctrl->drm_dev, "pattern: %#x\n", pattern); switch (pattern) { case DP_PHY_TEST_PATTERN_D10_2: - msm_dp_write_link(ctrl, REG_DP_STATE_CTRL, - DP_STATE_CTRL_LINK_TRAINING_PATTERN1); + msm_dp_write_link(ctrl, 0, REG_DP_STATE_CTRL, + DP_STATE_CTRL_LINK_TRAINING_PATTERN1); break; case DP_PHY_TEST_PATTERN_ERROR_COUNT: value &= ~(1 << 16); - msm_dp_write_link(ctrl, REG_DP_HBR2_COMPLIANCE_SCRAMBLER_RESET, - value); + msm_dp_write_link(ctrl, 0, REG_DP_HBR2_COMPLIANCE_SCRAMBLER_RESET, + value); value |= SCRAMBLER_RESET_COUNT_VALUE; - msm_dp_write_link(ctrl, REG_DP_HBR2_COMPLIANCE_SCRAMBLER_RESET, - value); - msm_dp_write_link(ctrl, REG_DP_MAINLINK_LEVELS, - DP_MAINLINK_SAFE_TO_EXIT_LEVEL_2); - msm_dp_write_link(ctrl, REG_DP_STATE_CTRL, - DP_STATE_CTRL_LINK_SYMBOL_ERR_MEASURE); + msm_dp_write_link(ctrl, 0, REG_DP_HBR2_COMPLIANCE_SCRAMBLER_RESET, + value); + msm_dp_write_link(ctrl, 0, REG_DP_MAINLINK_LEVELS, + DP_MAINLINK_SAFE_TO_EXIT_LEVEL_2); + msm_dp_write_link(ctrl, 0, REG_DP_STATE_CTRL, + DP_STATE_CTRL_LINK_SYMBOL_ERR_MEASURE); break; case DP_PHY_TEST_PATTERN_PRBS7: - msm_dp_write_link(ctrl, REG_DP_STATE_CTRL, - DP_STATE_CTRL_LINK_PRBS7); + msm_dp_write_link(ctrl, 0, REG_DP_STATE_CTRL, + DP_STATE_CTRL_LINK_PRBS7); break; case DP_PHY_TEST_PATTERN_80BIT_CUSTOM: - msm_dp_write_link(ctrl, REG_DP_STATE_CTRL, - DP_STATE_CTRL_LINK_TEST_CUSTOM_PATTERN); + msm_dp_write_link(ctrl, 0, REG_DP_STATE_CTRL, + DP_STATE_CTRL_LINK_TEST_CUSTOM_PATTERN); /* 00111110000011111000001111100000 */ - msm_dp_write_link(ctrl, REG_DP_TEST_80BIT_CUSTOM_PATTERN_REG0, - 0x3E0F83E0); + msm_dp_write_link(ctrl, 0, REG_DP_TEST_80BIT_CUSTOM_PATTERN_REG0, + 0x3E0F83E0); /* 00001111100000111110000011111000 */ - msm_dp_write_link(ctrl, REG_DP_TEST_80BIT_CUSTOM_PATTERN_REG1, - 0x0F83E0F8); + msm_dp_write_link(ctrl, 0, REG_DP_TEST_80BIT_CUSTOM_PATTERN_REG1, + 0x0F83E0F8); /* 1111100000111110 */ - msm_dp_write_link(ctrl, REG_DP_TEST_80BIT_CUSTOM_PATTERN_REG2, - 0x0000F83E); + msm_dp_write_link(ctrl, 0, REG_DP_TEST_80BIT_CUSTOM_PATTERN_REG2, + 0x0000F83E); break; case DP_PHY_TEST_PATTERN_CP2520: - value = msm_dp_read_link(ctrl, REG_DP_MAINLINK_CTRL); + value = msm_dp_read_link(ctrl, 0, REG_DP_MAINLINK_CTRL); value &= ~DP_MAINLINK_CTRL_SW_BYPASS_SCRAMBLER; - msm_dp_write_link(ctrl, REG_DP_MAINLINK_CTRL, value); + msm_dp_write_link(ctrl, 0, REG_DP_MAINLINK_CTRL, value); value = DP_HBR2_ERM_PATTERN; - msm_dp_write_link(ctrl, REG_DP_HBR2_COMPLIANCE_SCRAMBLER_RESET, - value); + msm_dp_write_link(ctrl, 0, REG_DP_HBR2_COMPLIANCE_SCRAMBLER_RESET, + value); value |= SCRAMBLER_RESET_COUNT_VALUE; - msm_dp_write_link(ctrl, REG_DP_HBR2_COMPLIANCE_SCRAMBLER_RESET, - value); - msm_dp_write_link(ctrl, REG_DP_MAINLINK_LEVELS, - DP_MAINLINK_SAFE_TO_EXIT_LEVEL_2); - msm_dp_write_link(ctrl, REG_DP_STATE_CTRL, - DP_STATE_CTRL_LINK_SYMBOL_ERR_MEASURE); - value = msm_dp_read_link(ctrl, REG_DP_MAINLINK_CTRL); + msm_dp_write_link(ctrl, 0, REG_DP_HBR2_COMPLIANCE_SCRAMBLER_RESET, + value); + msm_dp_write_link(ctrl, 0, REG_DP_MAINLINK_LEVELS, + DP_MAINLINK_SAFE_TO_EXIT_LEVEL_2); + msm_dp_write_link(ctrl, 0, REG_DP_STATE_CTRL, + DP_STATE_CTRL_LINK_SYMBOL_ERR_MEASURE); + value = msm_dp_read_link(ctrl, 0, REG_DP_MAINLINK_CTRL); value |= DP_MAINLINK_CTRL_ENABLE; - msm_dp_write_link(ctrl, REG_DP_MAINLINK_CTRL, value); + msm_dp_write_link(ctrl, 0, REG_DP_MAINLINK_CTRL, value); break; case DP_PHY_TEST_PATTERN_SEL_MASK: - msm_dp_write_link(ctrl, REG_DP_MAINLINK_CTRL, - DP_MAINLINK_CTRL_ENABLE); - msm_dp_write_link(ctrl, REG_DP_STATE_CTRL, - DP_STATE_CTRL_LINK_TRAINING_PATTERN4); + msm_dp_write_link(ctrl, 0, REG_DP_MAINLINK_CTRL, + DP_MAINLINK_CTRL_ENABLE); + msm_dp_write_link(ctrl, 0, REG_DP_STATE_CTRL, + DP_STATE_CTRL_LINK_TRAINING_PATTERN4); break; default: @@ -2307,7 +2348,7 @@ static bool msm_dp_ctrl_send_phy_test_pattern(struct msm_dp_ctrl_private *ctrl) msm_dp_ctrl_update_phy_vx_px(ctrl, DP_PHY_DPRX); msm_dp_link_send_test_response(ctrl->link); - pattern_sent = msm_dp_read_link(ctrl, REG_DP_MAINLINK_READY); + pattern_sent = msm_dp_read_link(ctrl, 0, REG_DP_MAINLINK_READY); switch (pattern_sent) { case MR_LINK_TRAINING1: @@ -2681,8 +2722,14 @@ static void msm_dp_ctrl_config_msa(struct msm_dp_ctrl_private *ctrl, nvid *= 3; drm_dbg_dp(ctrl->drm_dev, "mvid=0x%x, nvid=0x%x\n", mvid, nvid); - msm_dp_write_link(ctrl, REG_DP_SOFTWARE_MVID + mvid_reg_off, mvid); - msm_dp_write_link(ctrl, REG_DP_SOFTWARE_NVID + nvid_reg_off, nvid); + msm_dp_write_link(ctrl, msm_dp_panel->stream_id, + msm_dp_panel->stream_id > 1 ? + REG_MSTLINK_SOFTWARE_MVID : REG_DP_SOFTWARE_MVID + mvid_reg_off, + mvid); + msm_dp_write_link(ctrl, msm_dp_panel->stream_id, + msm_dp_panel->stream_id > 1 ? + REG_MSTLINK_SOFTWARE_NVID : REG_DP_SOFTWARE_NVID + nvid_reg_off, + nvid); } /* TODO: comments here. */ @@ -2852,7 +2899,8 @@ int msm_dp_ctrl_on_stream(struct msm_dp_ctrl *msm_dp_ctrl, struct msm_dp_panel * if (ctrl->mst_active) msm_dp_ctrl_mst_config(ctrl, true); - msm_dp_ctrl_config_ctrl_link(ctrl); + if (msm_dp_panel->stream_id == DP_STREAM_0) + msm_dp_ctrl_config_ctrl_link(ctrl); msm_dp_ctrl_configure_source_params(ctrl, msm_dp_panel); @@ -2869,7 +2917,7 @@ int msm_dp_ctrl_on_stream(struct msm_dp_ctrl *msm_dp_ctrl, struct msm_dp_panel * msm_dp_ctrl_mst_stream_setup(ctrl, msm_dp_panel); - msm_dp_write_link(ctrl, REG_DP_STATE_CTRL, DP_STATE_CTRL_SEND_VIDEO); + msm_dp_write_link(ctrl, 0, REG_DP_STATE_CTRL, DP_STATE_CTRL_SEND_VIDEO); ret = msm_dp_ctrl_mst_send_act(msm_dp_ctrl); if (ret) @@ -3106,7 +3154,9 @@ struct msm_dp_ctrl *msm_dp_ctrl_get(struct device *dev, struct msm_dp_link *link struct phy *phy, int max_stream, void __iomem *ahb_base, - void __iomem *link_base) + void __iomem *link_base, + void __iomem *mst2link_base, + void __iomem *mst3link_base) { struct msm_dp_ctrl_private *ctrl; int ret; @@ -3146,6 +3196,8 @@ struct msm_dp_ctrl *msm_dp_ctrl_get(struct device *dev, struct msm_dp_link *link ctrl->phy = phy; ctrl->ahb_base = ahb_base; ctrl->link_base = link_base; + ctrl->mst2link_base = mst2link_base; + ctrl->mst3link_base = mst3link_base; ctrl->mst_active = false; ret = msm_dp_ctrl_clk_init(&ctrl->msm_dp_ctrl, max_stream); diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.h b/drivers/gpu/drm/msm/dp/dp_ctrl.h index 6680f0a67ec08..ea7db139cfc6b 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.h +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.h @@ -32,7 +32,9 @@ struct msm_dp_ctrl *msm_dp_ctrl_get(struct device *dev, struct phy *phy, int max_stream, void __iomem *ahb_base, - void __iomem *link_base); + void __iomem *link_base, + void __iomem *mst2link_base, + void __iomem *mst3link_base); void msm_dp_ctrl_reset(struct msm_dp_ctrl *msm_dp_ctrl); void msm_dp_ctrl_phy_init(struct msm_dp_ctrl *msm_dp_ctrl); diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/dp_display.c index 17538bcafd0f0..43fa7cf12ea69 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -87,6 +87,12 @@ struct msm_dp_display_private { void __iomem *link_base; size_t link_len; + void __iomem *mst2link_base; + size_t mst2link_len; + + void __iomem *mst3link_base; + size_t mst3link_len; + void __iomem *pixel_base[DP_STREAM_MAX]; size_t pixel_len; @@ -595,7 +601,8 @@ struct msm_dp_panel *msm_dp_display_get_panel(struct msm_dp *msm_dp_display) dp = container_of(msm_dp_display, struct msm_dp_display_private, msm_dp_display); dp_panel = msm_dp_panel_get(&dp->msm_dp_display.pdev->dev, dp->aux, dp->link, - dp->link_base, dp->pixel_base[0]); + dp->link_base, dp->mst2link_base, dp->mst3link_base, + dp->pixel_base[0]); if (IS_ERR(dp->panel)) { DRM_ERROR("failed to initialize panel\n"); @@ -649,7 +656,8 @@ static int msm_dp_init_sub_modules(struct msm_dp_display_private *dp) goto error_link; } - dp->panel = msm_dp_panel_get(dev, dp->aux, dp->link, dp->link_base, dp->pixel_base[0]); + dp->panel = msm_dp_panel_get(dev, dp->aux, dp->link, dp->link_base, + dp->mst2link_base, dp->mst3link_base, dp->pixel_base[0]); if (IS_ERR(dp->panel)) { rc = PTR_ERR(dp->panel); DRM_ERROR("failed to initialize panel, rc = %d\n", rc); @@ -658,7 +666,8 @@ static int msm_dp_init_sub_modules(struct msm_dp_display_private *dp) } dp->ctrl = msm_dp_ctrl_get(dev, dp->link, dp->panel, dp->aux, - phy, dp->max_stream, dp->ahb_base, dp->link_base); + phy, dp->max_stream, dp->ahb_base, + dp->link_base, dp->mst2link_base, dp->mst3link_base); if (IS_ERR(dp->ctrl)) { rc = PTR_ERR(dp->ctrl); DRM_ERROR("failed to initialize ctrl, rc = %d\n", rc); @@ -968,6 +977,13 @@ void msm_dp_snapshot(struct msm_disp_state *disp_state, struct msm_dp *dp) msm_dp_display->aux_base, "dp_aux"); msm_disp_snapshot_add_block(disp_state, msm_dp_display->link_len, msm_dp_display->link_base, "dp_link"); + if (msm_dp_display->mst2link_base) + msm_disp_snapshot_add_block(disp_state, msm_dp_display->mst2link_len, + msm_dp_display->mst2link_base, "dp_mst2link"); + if (msm_dp_display->mst3link_base) + msm_disp_snapshot_add_block(disp_state, msm_dp_display->mst3link_len, + msm_dp_display->mst3link_base, "dp_mst3link"); + for (int i = 0; i < DP_STREAM_MAX; i++) { if (!msm_dp_ctrl_stream_clks_on(msm_dp_display->ctrl, i)) continue; @@ -1322,6 +1338,18 @@ static int msm_dp_display_get_io(struct msm_dp_display_private *display) } } + display->mst2link_base = msm_dp_ioremap(pdev, 7, &display->mst2link_len); + if (IS_ERR(display->mst2link_base)) { + DRM_DEBUG_DP("unable to remap mst2link region: %pe\n", display->mst2link_base); + display->mst2link_base = NULL; + } + + display->mst3link_base = msm_dp_ioremap(pdev, 8, &display->mst3link_len); + if (IS_ERR(display->mst3link_base)) { + DRM_DEBUG_DP("unable to remap mst3link region: %pe\n", display->mst3link_base); + display->mst3link_base = NULL; + } + return 0; } diff --git a/drivers/gpu/drm/msm/dp/dp_panel.c b/drivers/gpu/drm/msm/dp/dp_panel.c index 42a1d084b2300..f476f38d3d31e 100644 --- a/drivers/gpu/drm/msm/dp/dp_panel.c +++ b/drivers/gpu/drm/msm/dp/dp_panel.c @@ -25,23 +25,50 @@ struct msm_dp_panel_private { struct drm_dp_aux *aux; struct msm_dp_link *link; void __iomem *link_base; + void __iomem *mst2link_base; + void __iomem *mst3link_base; void __iomem *pixel_base; bool panel_on; }; static inline u32 msm_dp_read_link(struct msm_dp_panel_private *panel, u32 offset) { - return readl_relaxed(panel->link_base + offset); + switch (panel->msm_dp_panel.stream_id) { + case DP_STREAM_0: + case DP_STREAM_1: + return readl_relaxed(panel->link_base + offset); + case DP_STREAM_2: + return readl_relaxed(panel->mst2link_base + offset); + case DP_STREAM_3: + return readl_relaxed(panel->mst3link_base + offset); + default: + DRM_ERROR("error stream_id\n"); + return 0; + } } static inline void msm_dp_write_link(struct msm_dp_panel_private *panel, - u32 offset, u32 data) + u32 offset, u32 data) { /* * To make sure link reg writes happens before any other operation, * this function uses writel() instread of writel_relaxed() */ - writel(data, panel->link_base + offset); + switch (panel->msm_dp_panel.stream_id) { + case DP_STREAM_0: + case DP_STREAM_1: + writel(data, panel->link_base + offset); + break; + case DP_STREAM_2: + writel(data, panel->mst2link_base + offset); + break; + case DP_STREAM_3: + writel(data, panel->mst3link_base + offset); + break; + default: + DRM_ERROR("error stream_id\n"); + break; + } } static inline void msm_dp_write_pn(struct msm_dp_panel_private *panel, @@ -444,38 +471,51 @@ void msm_dp_panel_clear_dsc_dto(struct msm_dp_panel *msm_dp_panel) static void msm_dp_panel_send_vsc_sdp(struct msm_dp_panel_private *panel, struct dp_sdp *vsc_sdp) { + u32 id = panel->msm_dp_panel.stream_id; u32 header[2]; u32 val; int i; u32 offset = 0; - if (panel->msm_dp_panel.stream_id == DP_STREAM_1) + if (id == DP_STREAM_1) offset = MMSS_DP1_GENERIC0_0 - MMSS_DP_GENERIC0_0; msm_dp_utils_pack_sdp_header(&vsc_sdp->sdp_header, header); - msm_dp_write_link(panel, MMSS_DP_GENERIC0_0 + offset, header[0]); - msm_dp_write_link(panel, MMSS_DP_GENERIC0_1 + offset, header[1]); + msm_dp_write_link(panel, id > 1 ? + MMSS_DP_MSTLINK_GENERIC0_0 : MMSS_DP_GENERIC0_0 + offset, + header[0]); + msm_dp_write_link(panel, id > 1 ? + MMSS_DP_MSTLINK_GENERIC0_1 : MMSS_DP_GENERIC0_1 + offset, + header[1]); for (i = 0; i < sizeof(vsc_sdp->db); i += 4) { val = ((vsc_sdp->db[i]) | (vsc_sdp->db[i + 1] << 8) | (vsc_sdp->db[i + 2] << 16) | (vsc_sdp->db[i + 3] << 24)); - msm_dp_write_link(panel, MMSS_DP_GENERIC0_2 + i + offset, val); + + msm_dp_write_link(panel, id > 1 ? + MMSS_DP_MSTLINK_GENERIC0_2 + i : MMSS_DP_GENERIC0_2 + i + offset, + val); } } static void msm_dp_panel_update_sdp(struct msm_dp_panel_private *panel) { + u32 id = panel->msm_dp_panel.stream_id; u32 hw_revision = panel->msm_dp_panel.hw_revision; u32 offset = 0; - if (panel->msm_dp_panel.stream_id == DP_STREAM_1) + if (id == DP_STREAM_1) offset = MMSS_DP1_SDP_CFG3 - MMSS_DP_SDP_CFG3; if (hw_revision >= DP_HW_VERSION_1_0 && hw_revision < DP_HW_VERSION_1_2) { - msm_dp_write_link(panel, MMSS_DP_SDP_CFG3 + offset, UPDATE_SDP); - msm_dp_write_link(panel, MMSS_DP_SDP_CFG3 + offset, 0x0); + msm_dp_write_link(panel, id > 1 ? + MMSS_DP_MSTLINK_SDP_CFG3 : MMSS_DP_SDP_CFG3 + offset, + UPDATE_SDP); + msm_dp_write_link(panel, id > 1 ? + MMSS_DP_MSTLINK_SDP_CFG3 : MMSS_DP_SDP_CFG3 + offset, + 0x0); } } @@ -483,26 +523,34 @@ void msm_dp_panel_enable_vsc_sdp(struct msm_dp_panel *msm_dp_panel, struct dp_sd { struct msm_dp_panel_private *panel = container_of(msm_dp_panel, struct msm_dp_panel_private, msm_dp_panel); + u32 id = msm_dp_panel->stream_id; u32 cfg, cfg2, misc; u32 misc_reg_offset = 0; u32 sdp_cfg_offset = 0; u32 sdp_cfg2_offset = 0; - if (msm_dp_panel->stream_id == DP_STREAM_1) { + if (id == DP_STREAM_1) { misc_reg_offset = REG_DP1_MISC1_MISC0 - REG_DP_MISC1_MISC0; sdp_cfg_offset = MMSS_DP1_SDP_CFG - MMSS_DP_SDP_CFG; sdp_cfg2_offset = MMSS_DP1_SDP_CFG2 - MMSS_DP_SDP_CFG2; } - cfg = msm_dp_read_link(panel, MMSS_DP_SDP_CFG + sdp_cfg_offset); - cfg2 = msm_dp_read_link(panel, MMSS_DP_SDP_CFG2 + sdp_cfg2_offset); - misc = msm_dp_read_link(panel, REG_DP_MISC1_MISC0 + misc_reg_offset); + cfg = msm_dp_read_link(panel, id > 1 ? + MMSS_DP_MSTLINK_SDP_CFG : MMSS_DP_SDP_CFG + sdp_cfg_offset); + cfg2 = msm_dp_read_link(panel, id > 1 ? + MMSS_DP_MSTLINK_SDP_CFG2 : MMSS_DP_SDP_CFG2 + sdp_cfg2_offset); + misc = msm_dp_read_link(panel, id > 1 ? + REG_DP_MSTLINK_MISC1_MISC0 : REG_DP_MISC1_MISC0 + misc_reg_offset); cfg |= GEN0_SDP_EN; - msm_dp_write_link(panel, MMSS_DP_SDP_CFG + sdp_cfg_offset, cfg); - cfg2 |= GENERIC0_SDPSIZE_VALID; - msm_dp_write_link(panel, MMSS_DP_SDP_CFG2 + sdp_cfg2_offset, cfg2); + + msm_dp_write_link(panel, id > 1 ? + MMSS_DP_MSTLINK_SDP_CFG : MMSS_DP_SDP_CFG + sdp_cfg_offset, + cfg); + msm_dp_write_link(panel, id > 1 ? + MMSS_DP_MSTLINK_SDP_CFG2 : MMSS_DP_SDP_CFG2 + sdp_cfg2_offset, + cfg2); msm_dp_panel_send_vsc_sdp(panel, vsc_sdp); @@ -512,7 +560,9 @@ void msm_dp_panel_enable_vsc_sdp(struct msm_dp_panel *msm_dp_panel, struct dp_sd drm_dbg_dp(panel->drm_dev, "vsc sdp enable=1\n"); pr_debug("misc settings = 0x%x\n", misc); - msm_dp_write_link(panel, REG_DP_MISC1_MISC0 + misc_reg_offset, misc); + msm_dp_write_link(panel, id > 1 ? + REG_DP_MSTLINK_MISC1_MISC0 : REG_DP_MISC1_MISC0 + misc_reg_offset, + misc); msm_dp_panel_update_sdp(panel); } @@ -521,26 +571,34 @@ void msm_dp_panel_disable_vsc_sdp(struct msm_dp_panel *msm_dp_panel) { struct msm_dp_panel_private *panel = container_of(msm_dp_panel, struct msm_dp_panel_private, msm_dp_panel); + u32 id = msm_dp_panel->stream_id; u32 cfg, cfg2, misc; u32 misc_reg_offset = 0; u32 sdp_cfg_offset = 0; u32 sdp_cfg2_offset = 0; - if (msm_dp_panel->stream_id == DP_STREAM_1) { + if (id == DP_STREAM_1) { misc_reg_offset = REG_DP1_MISC1_MISC0 - REG_DP_MISC1_MISC0; sdp_cfg_offset = MMSS_DP1_SDP_CFG - MMSS_DP_SDP_CFG; sdp_cfg2_offset = MMSS_DP1_SDP_CFG2 - MMSS_DP_SDP_CFG2; } - cfg = msm_dp_read_link(panel, MMSS_DP_SDP_CFG + sdp_cfg_offset); - cfg2 = msm_dp_read_link(panel, MMSS_DP_SDP_CFG2 + sdp_cfg2_offset); - misc = msm_dp_read_link(panel, REG_DP_MISC1_MISC0 + misc_reg_offset); + cfg = msm_dp_read_link(panel, id > 1 ? + MMSS_DP_MSTLINK_SDP_CFG : MMSS_DP_SDP_CFG + sdp_cfg_offset); + cfg2 = msm_dp_read_link(panel, id > 1 ? + MMSS_DP_MSTLINK_SDP_CFG2 : MMSS_DP_SDP_CFG2 + sdp_cfg2_offset); + misc = msm_dp_read_link(panel, id > 1 ? + REG_DP_MSTLINK_MISC1_MISC0 : REG_DP_MISC1_MISC0 + misc_reg_offset); cfg &= ~GEN0_SDP_EN; - msm_dp_write_link(panel, MMSS_DP_SDP_CFG + sdp_cfg_offset, cfg); - cfg2 &= ~GENERIC0_SDPSIZE_VALID; - msm_dp_write_link(panel, MMSS_DP_SDP_CFG2 + sdp_cfg2_offset, cfg2); + + msm_dp_write_link(panel, id > 1 ? + MMSS_DP_MSTLINK_SDP_CFG : MMSS_DP_SDP_CFG + sdp_cfg_offset, + cfg); + msm_dp_write_link(panel, id > 1 ? + MMSS_DP_MSTLINK_SDP_CFG2 : MMSS_DP_SDP_CFG2 + sdp_cfg2_offset, + cfg2); /* switch back to MSA */ misc &= ~DP_MISC1_VSC_SDP; @@ -548,7 +606,9 @@ void msm_dp_panel_disable_vsc_sdp(struct msm_dp_panel *msm_dp_panel) drm_dbg_dp(panel->drm_dev, "vsc sdp enable=0\n"); pr_debug("misc settings = 0x%x\n", misc); - msm_dp_write_link(panel, REG_DP_MISC1_MISC0 + misc_reg_offset, misc); + msm_dp_write_link(panel, id > 1 ? + REG_DP_MSTLINK_MISC1_MISC0 : REG_DP_MISC1_MISC0 + misc_reg_offset, + misc); msm_dp_panel_update_sdp(panel); } @@ -598,6 +658,7 @@ static int msm_dp_panel_setup_vsc_sdp_yuv_420(struct msm_dp_panel *msm_dp_panel) int msm_dp_panel_timing_cfg(struct msm_dp_panel *msm_dp_panel, bool wide_bus_en) { + u32 id = msm_dp_panel->stream_id; u32 data, total_ver, total_hor; struct msm_dp_panel_private *panel; struct drm_display_mode *drm_mode; @@ -621,7 +682,7 @@ int msm_dp_panel_timing_cfg(struct msm_dp_panel *msm_dp_panel, bool wide_bus_en) drm_mode->vsync_start - drm_mode->vdisplay, drm_mode->vsync_end - drm_mode->vsync_start); - if (msm_dp_panel->stream_id == DP_STREAM_1) + if (id == DP_STREAM_1) offset = REG_DP1_TOTAL_HOR_VER - REG_DP_TOTAL_HOR_VER; total_hor = drm_mode->htotal; @@ -654,10 +715,18 @@ int msm_dp_panel_timing_cfg(struct msm_dp_panel *msm_dp_panel, bool wide_bus_en) msm_dp_active = data; - msm_dp_write_link(panel, REG_DP_TOTAL_HOR_VER + offset, total); - msm_dp_write_link(panel, REG_DP_START_HOR_VER_FROM_SYNC + offset, sync_start); - msm_dp_write_link(panel, REG_DP_HSYNC_VSYNC_WIDTH_POLARITY + offset, width_blanking); - msm_dp_write_link(panel, REG_DP_ACTIVE_HOR_VER + offset, msm_dp_active); + msm_dp_write_link(panel, + id > 1 ? REG_DP_MSTLINK_TOTAL_HOR_VER : + REG_DP_TOTAL_HOR_VER + offset, total); + msm_dp_write_link(panel, + id > 1 ? REG_DP_MSTLINK_START_HOR_VER_FROM_SYNC : + REG_DP_START_HOR_VER_FROM_SYNC + offset, sync_start); + msm_dp_write_link(panel, + id > 1 ? REG_DP_MSTLINK_HSYNC_VSYNC_WIDTH_POLARITY : + REG_DP_HSYNC_VSYNC_WIDTH_POLARITY + offset, width_blanking); + msm_dp_write_link(panel, + id > 1 ? REG_DP_MSTLINK_ACTIVE_HOR_VER : + REG_DP_ACTIVE_HOR_VER + offset, msm_dp_active); reg = msm_dp_read_pn(panel, MMSS_DP_INTF_CONFIG); if (wide_bus_en) @@ -738,6 +807,8 @@ int msm_dp_panel_init_panel_info(struct msm_dp_panel *msm_dp_panel) struct msm_dp_panel *msm_dp_panel_get(struct device *dev, struct drm_dp_aux *aux, struct msm_dp_link *link, void __iomem *link_base, + void __iomem *mst2link_base, + void __iomem *mst3link_base, void __iomem *pixel_base) { struct msm_dp_panel_private *panel; @@ -757,6 +828,8 @@ struct msm_dp_panel *msm_dp_panel_get(struct device *dev, struct drm_dp_aux *aux panel->link = link; panel->link_base = link_base; panel->pixel_base = pixel_base; + panel->mst2link_base = mst2link_base; + panel->mst3link_base = mst3link_base; msm_dp_panel = &panel->msm_dp_panel; msm_dp_panel->max_bw_code = DP_LINK_BW_8_1; diff --git a/drivers/gpu/drm/msm/dp/dp_panel.h b/drivers/gpu/drm/msm/dp/dp_panel.h index cd9af2f9c463d..8bab27520439c 100644 --- a/drivers/gpu/drm/msm/dp/dp_panel.h +++ b/drivers/gpu/drm/msm/dp/dp_panel.h @@ -104,5 +104,7 @@ static inline bool is_lane_count_valid(u32 lane_count) struct msm_dp_panel *msm_dp_panel_get(struct device *dev, struct drm_dp_aux *aux, struct msm_dp_link *link, void __iomem *link_base, + void __iomem *mst2link_base, + void __iomem *mst3link_base, void __iomem *pixel_base); #endif /* _DP_PANEL_H_ */ diff --git a/drivers/gpu/drm/msm/dp/dp_reg.h b/drivers/gpu/drm/msm/dp/dp_reg.h index 4398108ad8c30..65695fcb48d0f 100644 --- a/drivers/gpu/drm/msm/dp/dp_reg.h +++ b/drivers/gpu/drm/msm/dp/dp_reg.h @@ -172,7 +172,6 @@ #define REG_DP_START_HOR_VER_FROM_SYNC (0x00000020) #define REG_DP_HSYNC_VSYNC_WIDTH_POLARITY (0x00000024) #define REG_DP_ACTIVE_HOR_VER (0x00000028) - #define REG_DP_MISC1_MISC0 (0x0000002C) #define DP_MISC0_SYNCHRONOUS_CLK (0x00000001) #define DP_MISC0_COLORIMETRY_CFG_SHIFT (0x00000001) @@ -361,9 +360,23 @@ #define REG_DP_DP0_RG (0x000004F8) #define REG_DP_DP1_RG (0x000004FC) +#define REG_DP_MSTLINK_STATE_CTRL (0x00000000) +#define REG_DP_MSTLINK_CONFIGURATION_CTRL (0x00000034) #define REG_DP_MSTLINK_TIMESLOT_1_32 (0x00000038) #define REG_DP_MSTLINK_TIMESLOT_33_63 (0x0000003C) - +#define REG_MSTLINK_SOFTWARE_MVID (0x00000040) +#define REG_MSTLINK_SOFTWARE_NVID (0x00000044) +#define REG_DP_MSTLINK_TOTAL_HOR_VER (0x00000048) +#define REG_DP_MSTLINK_START_HOR_VER_FROM_SYNC (0x0000004C) +#define REG_DP_MSTLINK_HSYNC_VSYNC_WIDTH_POLARITY (0x00000050) +#define REG_DP_MSTLINK_ACTIVE_HOR_VER (0x00000054) +#define REG_DP_MSTLINK_MISC1_MISC0 (0x00000058) +#define MMSS_DP_MSTLINK_GENERIC0_0 (0x000000BC) +#define MMSS_DP_MSTLINK_GENERIC0_1 (0x000000C0) +#define MMSS_DP_MSTLINK_GENERIC0_2 (0x000000C4) +#define MMSS_DP_MSTLINK_SDP_CFG (0x0000010c) +#define MMSS_DP_MSTLINK_SDP_CFG2 (0x0000011c) +#define MMSS_DP_MSTLINK_SDP_CFG3 (0x00000114) #define MMSS_DP_ASYNC_FIFO_CONFIG (0x00000088)