Slice: Orchestrator coordinates a conflicted Memory branch switch #263

Parent

Part of #259. Related: #81 (Assignment Runtime), #261.

What to build

A Human requests a Memory branch switch while the repository has unfinished edits or an Assignment is working on relevant files. The Orchestrator immediately starts the request, inspects the real Git conflict, coordinates the affected Assignment through its existing request/report path, preserves unfinished work, and retries when it can switch safely. The Channel shows meaningful progress and the final branch or blocked state. The UI does not run Git or silently force the switch.

This slice completes a deterministic end-to-end conflict case. If the available facts leave a genuine Human choice, the Orchestrator must preserve the current files and report that choice as pending; the native in-Channel Ask Question flow is delivered by its sibling slice.

Acceptance criteria

• A real dirty-worktree switch refusal preserves modified files, index state, and the old branch; no reset, force checkout, or silent discard occurs.
• For a reproducible in-progress Assignment case, the Orchestrator identifies the affected Assignment, uses its existing addressed coordination path, receives the resulting report, and safely completes or clearly blocks the switch.
• The Channel reports requested, conflict/coordination, and completed or blocked states with the target branch and useful reason; it does not claim success while Git stayed on the old branch.
• A successful retry changes the real current branch and the same Orchestrator Session can read the resulting working tree; an unresolved conflict leaves both Session and files intact.
• Focused real-repository and Assignment integration tests cover refusal, coordination, retry, preservation, and restart visibility. A live LLM-backed DSH Human QA URL and saved screenshots demonstrate one full conflict-to-resolution path.

Blocked by

• Slice: switch an existing Memory branch in a live Orchestrator Session #261 — clean existing-branch switching and branch-aware Memory authority.