FPGA · RF signal processing · the seam where hardware meets DSP
Digital Hardware and DSP, in equal measure. Most of my repos sit somewhere on the path from an antenna to a register-transfer-level description: cardinal-cubic-spline pre-distortion for power amplifiers, LTE signal analysis (ACPR, PAPR, PSD), Verilog and VHDL labs targeting Intel/Altera boards, AMS boards, TI/ADi, and the occasional reusable IP core. I care about reference implementations that other engineers can actually run end-to-end, not just read.
| Repo | What it is |
|---|---|
| digital_lab | Verilog laboratory design files for digital signal generation on the DE-10 Lite. The single most-reused thing I've shipped. |
| Crypto | Synthesizable RC6 iterative cipher in VHDL — pipe controllers, round keys, register delays, port-mapped top-level. |
| matlab_codes | LTE signal analysis routines: ACPR, PAPR, PSD, formatting, data signals. |
| Cores | Reusable VHDL IP cores for Intel/Altera rapid prototyping. |
| clock-digital | VHDL digital-clock reference design. |
| TinyFPGA_labs | TinyFPGA BX labs — synthesizable code driving an HD44780 LCD. |
- Cardinal-cubic-spline DPD — Python ports of MATLAB
allPAPDiter.mand NARMA reference implementations for power-amplifier linearization, with an FPGA reference target on the way. - Teaching FPGA labs — synthesizable Verilog/VHDL for DE-10 Lite, TinyFPGA BX, and Altera Cyclone II boards.
