[cjfields]

Part of #31. This adds a Chip-specific optimizations subsection under Building and splits the testing, parity, benchmarking and CI notes into their own subsection.

Background, measured on the cluster nodes with an A/B build at the same commit:

• Xeon Gold 6150 (Skylake-SP): after Remove the AVX2 gather extend kernels (x86 stalls); race-safe bench runs #48, some cases ran 8–24% slower at an unchanged instruction count. This is the JCC-erratum microcode, which makes run time depend on code alignment. Building with -C llvm-args=-x86-branches-within-32B-boundaries made the affected cases 7–17% faster (edit, indel, gap-linear, X-drop/Z-drop, banded edit), back to their pre-Remove the AVX2 gather extend kernels (x86 stalls); race-safe bench runs #48 times. Gap-affine was 4% slower. Output was identical.
• EPYC 7713 (Zen 3): not affected. The op cache already served 95–99% of instructions without the flag. With it, times ranged from neutral to 7% slower, since the padding adds 1–4% more instructions.

The flag isn't set in .cargo/config.toml, because it would slow down other CPUs and wouldn't reach downstream crates anyway. The README documents it as an opt-in for Skylake-family Intel CPUs.

Docs only, no code changes.

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