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1 change: 1 addition & 0 deletions docs/reference-matrix.md
Original file line number Diff line number Diff line change
Expand Up @@ -55,6 +55,7 @@ Reading rules:
| vllm-project/vllm @ `7f730b4cea9a66520a9200265928ebe016b48a39` (Apache-2.0) | Dot bundle-mediated; `scheduler.py` admission/budgets/preemption/deferred frees and connector `v1/base.py` contracts/consumers; concrete connector, worker, cache-manager internals, config schema and tests unread | mined — independent admission budgets and async-KV readiness → `diagnose-vllm-admission-pressure`; completion/retention/failure ownership → `audit-vllm-kv-lifetimes`; conditional proposals and unrun verification only | out-of-scope — device KV is not host RAM | out-of-scope — external-hit API establishes no physical tier | out-of-scope — connector contract is not transport implementation | out-of-scope — engine scheduling is not OS priority control |
| vllm-project/vllm-ascend @ `8a8e1e05ecb64a30804c99c8f362909f9a0cb5bf` (Apache-2.0; separate runtime pin) | Dot bundle-mediated; `compilation/acl_graph.py`, pinned graph-mode guide and selected `test_acl_graph.py` cases; tests inspected by supplier, not run; caller/ENPU ordering and helpers untraced; native single-tier spec/worker, registration and DMA binding read directly ([seven-file ledger](../src/inferrsi/data/skill_library/hardware/host/host-memory-management/references/vllm-ascend-native-offload-readset.json)); external vLLM dependencies unpinned; [separate model-adapter routing](../src/inferrsi/data/skill_library/README.md#vllm-ascend-version-and-responsibility-routing) | mined — effective dispatch, caller-owned stable inputs, branch-specific replay/update order and capture-resource failures → `ascend-aclgraph-capture-replay`; separate from the older skill-doc pin | mined — normal event-query-gated CPU descriptor-pool ownership and wait/recycle distinction → [host-memory-management](../src/inferrsi/data/skill_library/hardware/host/host-memory-management/SKILL.md); source candidate, native tests not run; shared/tiering and allocator behavior excluded | out-of-scope | out-of-scope — offloader synchronization is not network evidence | out-of-scope — ACLGraph runtime supplies no new OS-control evidence; older Dockerfile/thread-env defaults remain scoped to bc8115ed |
| Ascend/pytorch (TorchNPU) @ `67511c53cd4c88014f6123de7097677e60e85faa` (upstream attribution notices retained in source notes) | Dot bundle-mediated; device/host allocators and bounded copy/record-stream/config/stats/binding/test paths in linked ledgers; underlying ATen host allocator and broader capture/IPC/driver behavior unread | mined — stream-use lifetime versus ordering, HBM counters/fragmentation and feature-gated controls → `torchnpu-device-memory-lifecycle`; tests unrun | mined — owned/external pinned buffers, host-specific counters, default/expandable paths and unresolved registration-version warning → `torchnpu-pinned-host-memory-lifecycle`; tests unrun | out-of-scope | out-of-scope — H2D/D2H, registration and IPC are not network coverage | out-of-scope — no OS-priority implementation |
| Dao-AILab/causal-conv1d @ `cd81f0413cad2fc1e6f17e785ac39f59aae690cd` (BSD-3-Clause) | Bounded source distillation, 2026-10-27; 10 retained files / 119,136 bytes matched to Git blobs; forward/update wrappers, compiled gates, selected packed/state branches, CUDA build/binding paths and test intent; [readset/notice](../src/inferrsi/data/skill_library/methods/kernel-writing-guide/references/causal-conv1d-contract.md#source-ledger) | mined (narrow) — forward versus in-place update, dtype/layout/packed history, gathered state rows and circular cursors; build targets versus observed dispatch → [kernel-writing-guide](../src/inferrsi/data/skill_library/methods/kernel-writing-guide/SKILL.md); native/integration/numerical/performance not_run; sm_89 compatibility unqualified | out-of-scope — device convolution state is not host RAM | out-of-scope — wheel retrieval is not storage optimization | out-of-scope — no transport implementation extracted | out-of-scope — request-state ownership is not OS scheduling |
| mindspore-ai/akg @ `5aa15f3fe4d856eb60cd3b27447e04f5f1fb4dff` (Apache-2.0) | Earlier discovery retained; 2026-10-23 bounded AKG-MLIR CUDA Affine tiling pass/options/pipeline/driver and one static elementwise FileCheck fixture; [readset](../src/inferrsi/data/skill_library/methods/kernel-writing-guide/references/akg-affine-tail-guards.md#source-ledger) | mined (narrow) — target/option/loop gates, full point-loop bounds and guarded body placement → [kernel-writing-guide](../src/inferrsi/data/skill_library/methods/kernel-writing-guide/SKILL.md); compiler/device execution and gains unverified; no Ascend qualification | unknown — host implementation not extracted | negative — scanned 2026-10-15, no LLM storage material (carried finding, not rescanned) | unknown — transport not extracted | negative — 2026-10-15 OS scan: identifier false-positives only (carried finding, not rescanned) |
| mindie-agent/mindie-agent @ 6a81b41 | full | out-of-scope — agent tooling, not serving performance | out-of-scope | mined (narrow) — logical-vs-physical I/O + cache-flush measurement caveat → `weight-loading-optimization` | out-of-scope | out-of-scope |
| hahnyuan/LLM-Viewer @ 1893e4b | full | mined — roofline model + hardware params → `performance-ceiling-analysis` (L1) | out-of-scope | out-of-scope | out-of-scope | out-of-scope |
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1 change: 1 addition & 0 deletions docs/searchspace-matrix.md
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Expand Up @@ -40,6 +40,7 @@ The primary compute and HBM resource. Most current work lives here.
| **Configure** | Parallelism strategy (USP/CP/TP/PP), topology-aware card-group selection | `ascend-distributed-parallel` | USP activation requirement, masking upper-bound formula, AlltoAllV workaround | MindIE-SD dit-parallel-opt @ 8481d39b (9 reference files) | 🟢 |
| **Configure** | Model adapter: FP8 dequantization, KV-head replication, multimodal feature validation order | `ascend-model-adaptation` | vllm-ascend FP8/multimodal lessons; [separate runtime-wrapper route](../src/inferrsi/data/skill_library/README.md#vllm-ascend-version-and-responsibility-routing) | vllm-ascend @ bc8115ed | 🟢 |
| **Optimize** | Kernel-level: Triton/CuTe/TileIR writing, kernel tuning, fusion scope analysis | `kernel-writing-guide` | Framework routing (Triton vs CuTe vs AscendC), 6 universal correctness rules, verify-before-benchmark workflow | TRT-LLM kernel-triton-writing + kernel-cute-writing @ f33e0e5f | 🟢 |
| **Diagnose / Configure / Verify** | Existing causal depthwise convolution: API/state ownership, dtype/layout/packed boundaries, gathered rows, circular cursor and build/binding evidence | [kernel-writing-guide](../src/inferrsi/data/skill_library/methods/kernel-writing-guide/SKILL.md) | [Five forward/update decision cases](../src/inferrsi/data/skill_library/methods/kernel-writing-guide/cases/causal-conv1d-dispatch-state.md); invalid layout/state and unproved dispatch stop qualification | Dao-AILab/causal-conv1d @ cd81f0413cad2fc1e6f17e785ac39f59aae690cd; [contract/readset](../src/inferrsi/data/skill_library/methods/kernel-writing-guide/references/causal-conv1d-contract.md); source and test intent only | Candidate; native/build/binary compatibility, downstream readiness, numerics, performance and efficacy not evaluated; no new measured coverage |
| **Diagnose / Configure / Verify** | AKG static CUDA Affine loop tails: effective target/option gates, full point-loop bounds and protected input/output accesses | [kernel-writing-guide](../src/inferrsi/data/skill_library/methods/kernel-writing-guide/SKILL.md) | [Tail-guard reference](../src/inferrsi/data/skill_library/methods/kernel-writing-guide/references/akg-affine-tail-guards.md): separation precedence, non-divisible fixture and diagnostic boundary | AKG @ 5aa15f3fe4d856eb60cd3b27447e04f5f1fb4dff; source + FileCheck expectations only | Candidate; compiler/IR command, CUDA runtime and agent efficacy not run; no new measured coverage |
| **Optimize** | Operator-level: staged accuracy-gated tuning campaign (code-level → scheduling → instruction-level), metric→action routing; AscendC tiling design per operator class (reduction/broadcast/elewise/matmul/conversion) | `ascend-operator-tuning`, `ascendc-tiling-design` | PyPTO frontend/swimlane/incore playbooks; fullload-vs-split, four-element tiling template, chip-generation (DAV_2201/3510) routing | awesome-ascend-skills pypto-op-perf-tune + ascendc-tiling-design @ 75ec89c | 🟢 |
| **Optimize** | Casebook of past NPU optimization decisions: AI-CPU fallback, memory-bound, comm-exposed, graph-compilation, scheduling idle gaps | `ascend-optimization-casebook`, `inference-optimization-casebook` | Five bottleneck classes with symptom→diagnosis→action→evidence schema | MindIE-SD profiling-analyze + dit-perf-opt + perf-gate + dit-parallel-opt @ 8481d39b | 🟢 |
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4 changes: 2 additions & 2 deletions docs/skill-coverage.md
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Expand Up @@ -4,7 +4,7 @@ Generated from the registry, the skill sidecars and the two maintained
matrices. **Do not edit by hand**; regenerate after any registry, skill,
matrix or frozen-plan change.

- Input digest: `sha256:25b6af447e0145ceb987e965515e6d48f3fbcefd56c6effb08129d0278f4616d`
- Input digest: `sha256:20625ca481a285ea88cff5a2e7cdccecd0b2a28a09eb1a43243d97d84731c444`
- Regenerate: `python tools/build_skill_coverage.py`
- Verify without writing: `python tools/build_skill_coverage.py --check`

Expand Down Expand Up @@ -125,7 +125,7 @@ optimization is fully covered or that any procedure has measured benefit.
| [evaluate-elastic-serving-placement](../src/inferrsi/data/skill_library/methods/evaluate-elastic-serving-placement/SKILL.md) | common | Compare migrating an LLM request between model replicas with changing its sequence-parallel execution group, including ... | 1 Accelerator · Diagnose / Configure / Optimize / Verify<br>2 RAM/Host · Diagnose / Configure / Optimize / Verify<br>4 Network · Diagnose / Configure / Optimize / Verify | 1 · Systems sources (Llumnix — [2406.03243v1](https://arxiv.org/abs/2406.03243v1)) | candidate · not_run · 1 readset(s) | no-eval |
| [inference-benchmark-design](../src/inferrsi/data/skill_library/methods/inference-benchmark-design/SKILL.md) | common | Select task quality gates, reference parity checks and performance workloads for text, agentic coding, work agents ... | — | 2 · Methodology and corpus references (JiusiServe/vllm-evolve @ 43cc82c)<br>Task-specific benchmark selection (issue #60) ([Issue #60 report](https://github.com/InferMatrixLab/InferRSI/issues/6 ...) | candidate · not_run · 2 readset(s) | no-SearchSpace-layer |
| [inference-optimization-casebook](../src/inferrsi/data/skill_library/methods/inference-optimization-casebook/SKILL.md) | common | How to structure and use a casebook of past optimization decisions as a decision-support tool. Extracts the casebook ... | 1 Accelerator · Optimize | 1 · Systems sources (NVIDIA/TensorRT-LLM @ f33e0e5fd) | candidate · not_run · 0 readset(s) | no-eval |
| [kernel-writing-guide](../src/inferrsi/data/skill_library/methods/kernel-writing-guide/SKILL.md) | common | Decision guide for writing custom inference kernels: when to write one, which framework to choose (Triton, CuTe DSL ... | 1 Accelerator · Optimize / Diagnose / Configure / Verify | 1 · Systems sources (NVIDIA/TensorRT-LLM @ f33e0e5fd)<br>1 · Systems sources (mindspore-ai/akg @ `5aa15f3fe4d856eb60cd3b27447e04f5f1fb4dff` ...) | candidate · not_run · 1 readset(s) | no-eval |
| [kernel-writing-guide](../src/inferrsi/data/skill_library/methods/kernel-writing-guide/SKILL.md) | common | Decision guide for writing custom inference kernels: when to write one, which framework to choose (Triton, CuTe DSL ... | 1 Accelerator · Optimize / Diagnose / Configure / Verify | 1 · Systems sources (Dao-AILab/causal-conv1d @ `cd81f0413cad2fc1e6f17e785ac39f59aae690cd` ...)<br>1 · Systems sources (NVIDIA/TensorRT-LLM @ f33e0e5fd)<br>1 · Systems sources (mindspore-ai/akg @ `5aa15f3fe4d856eb60cd3b27447e04f5f1fb4dff` ...) | candidate · not_run · 2 readset(s) | no-eval |
| [optimization-search-policy](../src/inferrsi/data/skill_library/methods/optimization-search-policy/SKILL.md) | common | Policy for how an optimization agent should select, order, and stop optimization experiments. Covers candidate ... | 1 Accelerator · Optimize | 2 · Methodology and corpus references (JiusiServe/vllm-evolve @ 43cc82c)<br>2 · Methodology and corpus references (RRSI — arXiv 2609.24972v3)<br>2 · Methodology and corpus references (arXiv 2608.01867 (CRISP))<br>2 · Methodology and corpus references (microsoft/SkillOpt @ 343db22) | candidate · not_run · 6 readset(s) | no-eval |
| [performance-ceiling-analysis](../src/inferrsi/data/skill_library/methods/performance-ceiling-analysis/SKILL.md) | common | Estimate optimization headroom before modifying an inference system. Produces a three-level ceiling model (analytical ... | 1 Accelerator · Diagnose / Verify<br>5 OS · Configure | 1 · Systems sources (NVIDIA/TensorRT-LLM @ f33e0e5fd)<br>1 · Systems sources (ebugger/Empirical-Roofline-Toolkit @ 0771fa9)<br>1 · Systems sources (hahnyuan/LLM-Viewer @ 1893e4b) | candidate · not_run · 16 readset(s) | no-eval |
| [plan-activation-residency](../src/inferrsi/data/skill_library/methods/plan-activation-residency/SKILL.md) | common | Propose training activation and gradient memory reductions by distinguishing lifetime reordering, address packing and ... | 1 Accelerator · Diagnose / Optimize / Verify | 1 · Systems sources (Checkmate — [1910.02653v3](https://arxiv.org/abs/1910.02653v3)) | candidate · not_run · 1 readset(s) | no-eval |
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4 changes: 2 additions & 2 deletions src/inferrsi/data/repo_packs/inferrsi/knowledge/README.md
Original file line number Diff line number Diff line change
Expand Up @@ -15,7 +15,7 @@ These are knowledge abstracts (`--kind knowledge`), with namespaced package
IDs distinct from explicitly selected `checkout_ref` skills. Ascend/CUDA
procedures use their corresponding backend; shared methods use `common`.

Source snapshot: [aafa181251043882546678920ae992498b405ffb](https://github.com/InferMatrixLab/InferRSI/tree/aafa181251043882546678920ae992498b405ffb/src/inferrsi/data/skill_library).
Source snapshot: [49335e0c388b84211364170daf3603525885eb28](https://github.com/InferMatrixLab/InferRSI/tree/49335e0c388b84211364170daf3603525885eb28/src/inferrsi/data/skill_library).

```bash
inferrsi knowledge search 'profiling' --repo-type inferrsi --limit 50
Expand All @@ -29,7 +29,7 @@ contain the current input paths and bytes (Git checkout filters are respected).

```bash
python tools/build_skill_index.py --source-revision <committed-source-revision>
python tools/build_skill_index.py --source-revision aafa181251043882546678920ae992498b405ffb --check
python tools/build_skill_index.py --source-revision 49335e0c388b84211364170daf3603525885eb28 --check
```

`--check` detects missing, stale and unexpected generated records without writing.
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Expand Up @@ -21,8 +21,8 @@
"sources": [
{
"type": "git",
"url": "https://github.com/InferMatrixLab/InferRSI/blob/aafa181251043882546678920ae992498b405ffb/src/inferrsi/data/skill_library/hardware/ascend/ascend-aclgraph-capture-replay/SKILL.md",
"commit": "aafa181251043882546678920ae992498b405ffb",
"url": "https://github.com/InferMatrixLab/InferRSI/blob/49335e0c388b84211364170daf3603525885eb28/src/inferrsi/data/skill_library/hardware/ascend/ascend-aclgraph-capture-replay/SKILL.md",
"commit": "49335e0c388b84211364170daf3603525885eb28",
"paths": [
"src/inferrsi/data/skill_library/hardware/ascend/ascend-aclgraph-capture-replay/SKILL.md",
"src/inferrsi/data/skill_library/hardware/ascend/ascend-aclgraph-capture-replay/metadata.json",
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Original file line number Diff line number Diff line change
Expand Up @@ -23,8 +23,8 @@
"sources": [
{
"type": "git",
"url": "https://github.com/InferMatrixLab/InferRSI/blob/aafa181251043882546678920ae992498b405ffb/src/inferrsi/data/skill_library/hardware/ascend/ascend-device-health/SKILL.md",
"commit": "aafa181251043882546678920ae992498b405ffb",
"url": "https://github.com/InferMatrixLab/InferRSI/blob/49335e0c388b84211364170daf3603525885eb28/src/inferrsi/data/skill_library/hardware/ascend/ascend-device-health/SKILL.md",
"commit": "49335e0c388b84211364170daf3603525885eb28",
"paths": [
"src/inferrsi/data/skill_library/hardware/ascend/ascend-device-health/SKILL.md",
"src/inferrsi/data/skill_library/hardware/ascend/ascend-device-health/metadata.json",
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Expand Up @@ -24,8 +24,8 @@
"sources": [
{
"type": "git",
"url": "https://github.com/InferMatrixLab/InferRSI/blob/aafa181251043882546678920ae992498b405ffb/src/inferrsi/data/skill_library/hardware/ascend/ascend-distributed-parallel/SKILL.md",
"commit": "aafa181251043882546678920ae992498b405ffb",
"url": "https://github.com/InferMatrixLab/InferRSI/blob/49335e0c388b84211364170daf3603525885eb28/src/inferrsi/data/skill_library/hardware/ascend/ascend-distributed-parallel/SKILL.md",
"commit": "49335e0c388b84211364170daf3603525885eb28",
"paths": [
"src/inferrsi/data/skill_library/hardware/ascend/ascend-distributed-parallel/SKILL.md",
"src/inferrsi/data/skill_library/hardware/ascend/ascend-distributed-parallel/metadata.json",
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Expand Up @@ -22,8 +22,8 @@
"sources": [
{
"type": "git",
"url": "https://github.com/InferMatrixLab/InferRSI/blob/aafa181251043882546678920ae992498b405ffb/src/inferrsi/data/skill_library/hardware/ascend/ascend-graph-mode/SKILL.md",
"commit": "aafa181251043882546678920ae992498b405ffb",
"url": "https://github.com/InferMatrixLab/InferRSI/blob/49335e0c388b84211364170daf3603525885eb28/src/inferrsi/data/skill_library/hardware/ascend/ascend-graph-mode/SKILL.md",
"commit": "49335e0c388b84211364170daf3603525885eb28",
"paths": [
"src/inferrsi/data/skill_library/hardware/ascend/ascend-graph-mode/SKILL.md",
"src/inferrsi/data/skill_library/hardware/ascend/ascend-graph-mode/metadata.json",
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Original file line number Diff line number Diff line change
Expand Up @@ -22,8 +22,8 @@
"sources": [
{
"type": "git",
"url": "https://github.com/InferMatrixLab/InferRSI/blob/aafa181251043882546678920ae992498b405ffb/src/inferrsi/data/skill_library/hardware/ascend/ascend-model-adaptation/SKILL.md",
"commit": "aafa181251043882546678920ae992498b405ffb",
"url": "https://github.com/InferMatrixLab/InferRSI/blob/49335e0c388b84211364170daf3603525885eb28/src/inferrsi/data/skill_library/hardware/ascend/ascend-model-adaptation/SKILL.md",
"commit": "49335e0c388b84211364170daf3603525885eb28",
"paths": [
"src/inferrsi/data/skill_library/hardware/ascend/ascend-model-adaptation/SKILL.md",
"src/inferrsi/data/skill_library/hardware/ascend/ascend-model-adaptation/metadata.json",
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Expand Up @@ -23,8 +23,8 @@
"sources": [
{
"type": "git",
"url": "https://github.com/InferMatrixLab/InferRSI/blob/aafa181251043882546678920ae992498b405ffb/src/inferrsi/data/skill_library/hardware/ascend/ascend-operator-profiling/SKILL.md",
"commit": "aafa181251043882546678920ae992498b405ffb",
"url": "https://github.com/InferMatrixLab/InferRSI/blob/49335e0c388b84211364170daf3603525885eb28/src/inferrsi/data/skill_library/hardware/ascend/ascend-operator-profiling/SKILL.md",
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"src/inferrsi/data/skill_library/hardware/ascend/ascend-operator-profiling/SKILL.md",
"src/inferrsi/data/skill_library/hardware/ascend/ascend-operator-profiling/metadata.json",
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Expand Up @@ -24,8 +24,8 @@
"sources": [
{
"type": "git",
"url": "https://github.com/InferMatrixLab/InferRSI/blob/aafa181251043882546678920ae992498b405ffb/src/inferrsi/data/skill_library/hardware/ascend/ascend-operator-tuning/SKILL.md",
"commit": "aafa181251043882546678920ae992498b405ffb",
"url": "https://github.com/InferMatrixLab/InferRSI/blob/49335e0c388b84211364170daf3603525885eb28/src/inferrsi/data/skill_library/hardware/ascend/ascend-operator-tuning/SKILL.md",
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"src/inferrsi/data/skill_library/hardware/ascend/ascend-operator-tuning/metadata.json",
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