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Single-Cycle-RISC-V-Processor-Implementation

Utilized Icarus Verilog (iverilog) to compile the Verilog code and GTKWave to analyze waveform.

Integrated modules such as Program Counter (PC), ALU, Register File, Data Memory and Control Unit.

Executed RISC-V instructions for arithmetic logic, memory access, and branching, insuring ISA compliance.

Tested the design rigorously, validating correctness of instruction types (R, I, S, B).

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