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.qsys_edit
.qsys_edit
 
 
db
db
 
 
greybox_tmp
greybox_tmp
 
 
incremental_db
incremental_db
 
 
simulation
simulation
 
 
.gitattributes
.gitattributes
 
 
LFSR.bsf
LFSR.bsf
 
 
LFSR.sv
LFSR.sv
 
 
LFSR.sv.bak
LFSR.sv.bak
 
 
Lab 3 Report_EE4449_TT01_231_Nguyễn Trường Phú_2051058.docx
Lab 3 Report_EE4449_TT01_231_Nguyễn Trường Phú_2051058.docx
 
 
Lab 3 Report_EE4449_TT01_231_Nguyễn Trường Phú_2051058.pdf
Lab 3 Report_EE4449_TT01_231_Nguyễn Trường Phú_2051058.pdf
 
 
RTL.pdf
RTL.pdf
 
 
RTLW.pdf
RTLW.pdf
 
 
altera_mf.v
altera_mf.v
 
 
async_fifo_TB.sv.bak
async_fifo_TB.sv.bak
 
 
binto7seg.sv
binto7seg.sv
 
 
binto7seg.sv.bak
binto7seg.sv.bak
 
 
c5_pin_model_dump.txt
c5_pin_model_dump.txt
 
 
clock_1sec.bsf
clock_1sec.bsf
 
 
clock_1sec.sv
clock_1sec.sv
 
 
clock_1sec.sv.bak
clock_1sec.sv.bak
 
 
clock_2sec.bsf
clock_2sec.bsf
 
 
clock_2sec.sv
clock_2sec.sv
 
 
clock_2sec.sv.bak
clock_2sec.sv.bak
 
 
console.png
console.png
 
 
controller.bsf
controller.bsf
 
 
controller.sv
controller.sv
 
 
controller.sv.bak
controller.sv.bak
 
 
data.png
data.png
 
 
dataempty.png
dataempty.png
 
 
datafull.png
datafull.png
 
 
dual_RAM.bsf
dual_RAM.bsf
 
 
dual_RAM.v
dual_RAM.v
 
 
dual_RAM.v.bak
dual_RAM.v.bak
 
 
dual_RAM_8.bsf
dual_RAM_8.bsf
 
 
dual_RAM_8.v.bak
dual_RAM_8.v.bak
 
 
fFFf.bdf
fFFf.bdf
 
 
fFFf.bsf
fFFf.bsf
 
 
fFFf.v
fFFf.v
 
 
fFFf.v.bak
fFFf.v.bak
 
 
fFFf_8.bdf
fFFf_8.bdf
 
 
fFFf_8.v.bak
fFFf_8.v.bak
 
 
feeFIFOfum.asm.rpt
feeFIFOfum.asm.rpt
 
 
feeFIFOfum.cdf
feeFIFOfum.cdf
 
 
feeFIFOfum.done
feeFIFOfum.done
 
 
feeFIFOfum.eda.rpt
feeFIFOfum.eda.rpt
 
 
feeFIFOfum.fit.rpt
feeFIFOfum.fit.rpt
 
 
feeFIFOfum.fit.smsg
feeFIFOfum.fit.smsg
 
 
feeFIFOfum.fit.summary
feeFIFOfum.fit.summary
 
 
feeFIFOfum.flow.rpt
feeFIFOfum.flow.rpt
 
 
feeFIFOfum.jdi
feeFIFOfum.jdi
 
 
feeFIFOfum.map.rpt
feeFIFOfum.map.rpt
 
 
feeFIFOfum.map.smsg
feeFIFOfum.map.smsg
 
 
feeFIFOfum.map.summary
feeFIFOfum.map.summary
 
 
feeFIFOfum.pin
feeFIFOfum.pin
 
 
feeFIFOfum.qpf
feeFIFOfum.qpf
 
 
feeFIFOfum.qsf
feeFIFOfum.qsf
 
 
feeFIFOfum.qws
feeFIFOfum.qws
 
 
feeFIFOfum.sld
feeFIFOfum.sld
 
 
feeFIFOfum.sof
feeFIFOfum.sof
 
 
feeFIFOfum.sta.rpt
feeFIFOfum.sta.rpt
 
 
feeFIFOfum.sta.summary
feeFIFOfum.sta.summary
 
 
feeFIFOfum.sv.bak
feeFIFOfum.sv.bak
 
 
feeFIFOfum_assignment_defaults.qdf
feeFIFOfum_assignment_defaults.qdf
 
 
feeFIFOfum_nativelink_simulation.rpt
feeFIFOfum_nativelink_simulation.rpt
 
 
fifotb.sv.bak
fifotb.sv.bak
 
 
firsttestfirstbench.vcd
firsttestfirstbench.vcd
 
 
flags_handler.sv.bak
flags_handler.sv.bak
 
 
important info.txt
important info.txt
 
 
len.png
len.png
 
 
lenempty.png
lenempty.png
 
 
lenfull.png
lenfull.png
 
 
segsel.sv
segsel.sv
 
 
segssel.bsf
segssel.bsf
 
 
segssel.sv
segssel.sv
 
 
testFIFObench.sv
testFIFObench.sv
 
 
testFIFObench.sv.bak
testFIFObench.sv.bak
 
 
top_lab3.bdf
top_lab3.bdf
 
 
top_lab3.v
top_lab3.v
 
 
top_lab3.v.bak
top_lab3.v.bak
 
 
wave.png
wave.png
 
 

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My design of a hardware asynchronous FIFO.

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