Firmware V2 (same V1 board) + V2 hardware warning

[TheusHen]

Been running the V1 firmware for a while and it had a few things bothering me, so I finally sat down and reworked it properly. This is all still for the current board (XIAO RP2040 + ADS1299-4), nothing here needs new hardware.

What was actually wrong:

• sample_index reset to 0 on every START and on every auto-recovery, so captures had duplicate timelines
• INFO/REGS while streaming touched SPI inside RDATAC and returned garbage / could desync the ADC
• ASCII prints bypassed the TX ring and glued to the next COBS frame on the host side
• the sample packet buffer was 40 bytes but the frozen layout needs 44 (2 hdr + 40 payload + 2 crc)
• DRDY ISR did interval/jitter/division work, CSV blocked on Serial.print, 8K ring with no backpressure handling

What changed:

• sample_index is monotonic since boot now, session_id separates runs, recovery restarts without resetting the timeline
• REGS refuses while streaming (BUSY), INFO answers with events only in BIN+streaming, STATS stays always safe
• all output goes through a 16K ring with bounded CDC drains, CSV is throttled instead of stalling acquisition
• ISR only timestamps now, interval/missed/jitter math is deferred
• new commands: SPS 250/500/1000, GAIN 1/2/4/6/8/12/24, VREF 2400/4500, PING with seq echo
• SPI 1M to 2M, watchdog boot-cause event, HELLO packet on boot with sps/gain/vref, stronger SELFTEST, button short-press toggles stream and 1.5s hold runs self-test
• kept every old packet layout and flag bit intact so current Pendulum builds keep decoding everything

Docs/tests:

• added firmware/PROTOCOL_V2.md with the framing, flags, event/error codes and the register map I'm actually using
• added firmware/sim_v2_check.py which mirrors the encode path and runs it through the real Pendulum decoder (fragmentation, uV scales, 1kSPS budget, missed-DRDY math) - 20/20 passing here
• extended the native unity tests (COBS long run, frozen 44B size, uV scale)

Also put a visible warning at the top of the README: V2 hardware is under active development, don't fab V1. That one is just to save someone money.

How I checked it:

• python firmware/sim_v2_check.py -> ALL PASS
• source consistency pass on buffers, ring size, SPI, ISR, session handling
• still needs a real bench run: flash with pio, STOP/MODE BIN/INFO/STATS/SELFTEST/START for 60s at 250 SPS and confirm missed=0, tx_drop=0, then try VREF 2400 vs 4500 and compare noise

Next up after this merges: new board revision, then Pendulum updates to use the HELLO fields instead of assuming 250/G24/4.5V.