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1. RISC-V-Processor-Architecture RISC-V-Processor-Architecture Public

   64-bit 5-Stage Sequential & Pipelined RISC-V Processor Architecture in Verilog

   Verilog

2. BitNet-RISCV-Multicore BitNet-RISCV-Multicore Public

   Hardware-software co-design for BitNet inference on multicore RISC-V using CVA6, Ara (RVV), and a ternary-optimized Gemmini.

3. pulp-platform/ara pulp-platform/ara Public

   The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 core

   C 552 207

4. VLSI-Carry-Look-Ahead-Adder VLSI-Carry-Look-Ahead-Adder Public

   4-bit Carry Lookahead Adder (CLA) – transistor-level in Ngspice, post-layout in Magic, results verified via Verilog on FPGA

   Verilog

5. vroon33/simplified-scara-bot vroon33/simplified-scara-bot Public

   A simplified model of a SCARA bot by team PID for M24 Systems Thinking Project

   2

6. OpAmp_Design OpAmp_Design Public