[FengHeting]

Summary

The PATA driver sent SET FEATURES to put the drive into UDMA/MWDMA but never programmed the chipset timing registers, so DMA did not work on real hardware. This reuses the mode the firmware already paired between the drive and the host, without vendor-specific timing code.

• ATA/ATAPI drives with DMA in IDENTIFY and a bus-master BAR4 are DMA candidates.
• Each candidate is validated once at boot by reading the same sectors with PIO and DMA and comparing the buffers.
• A failed validation, missing BAR4, or runtime bus-master error permanently drops the drive to PIO. ATA retries the same request in PIO; ATAPI resumes READ(12) from the completed offset; a stuck BSY resets the channel and drops both drives on it.
• ATAPI capacity probing follows REQUEST SENSE retries and maps a missing medium to -ENOMEDIUM.

Scope

Only the PATA (IDE-interface) driver changes. There is no SET FEATURES, no UDMA/MWDMA negotiation, and no vendor timing programming; full-speed DMA still needs chipset-specific support.

Testing

• make -j$(nproc) passes.
• QEMU PIIX3 + OVMF: ATA disk and ATAPI CD are detected, partitions/files read correctly, and the [DMA]/[PIO] mode is logged.
• The DMA validation failure path was exercised; the same request completes through PIO.