VendingMachine is a hardware description (Verilog) project that implements a digital vending machine controller. The design models coin acceptance, product selection, inventory tracking, dispensing logic, and change calculation as a deterministic finite-state machine (FSM) suitable for simulation and FPGA implementation. The repository includes synthesizable RTL modules, a behavioral testbench to validate functionality, and example scripts for simulation and (optional) synthesis with common open-source and vendor tools. This project is useful as a learning example for state-machine design, I/O interfacing, and the RTL verification workflow.
- Verilog
- Quartus Prime Lite
- VHDL
- DE-10 Standard FPGA Board
- Coin handling & validation
- Accepts multiple coin denominations (configurable in RTL), debounces inputs, accumulates credit, and rejects invalid pulses.
- Product selection & inventory
- Users select product codes; the controller checks inventory counts and prevents selection if out-of-stock.
- Dispense & change logic
- FSM manages dispense cycle and computes change using available coin denominations; supports partial/over-payment detection.
- User feedback signals
- Outputs for LEDs / 7-seg / LCD signals and a "dispense" pulse allow easy hookup to external display/hardware.
- Testbench with stimulus
- Behavioral testbench exercises nominal and edge cases: coin bursts, rapid selections, refunds, restocks, and error conditions.
- Synthesizable implementation
- RTL written for synthesis; ready-to-run examples for both open-source and vendor flows are included or easy to add.
- Modular design
- Clear separation of submodules (coin-processor, selector, inventory, changer) makes it easy to extend or reuse parts.
The vending machine is implemented as modular Verilog RTL centered around an FSM that tracks user credit and transaction state. Inputs (coin pulses, selection codes, restock signals) are debounced and sampled synchronously to the system clock. Business logic lives in separate modules:
- coin_processor: debounces and converts pulses into credit increments,
- selector: decodes selection codes and requests inventory,
- inventory: maintains product counts and supports restock,
- change_manager: computes change and issues dispensable coin counts,
- top-level FSM: orchestrates user interactions, transitions between idle/waiting/dispense/refund/error states.
Verification begins with a behavioral testbench that drives signals to the top-level module, checks expected outputs, and optionally generates VCD traces for waveform inspection. For FPGA use, synthesis scripts (Yosys / Vivado) constrain IO and map logic to the target device, and a timing-driven P&R is performed. Documentation comments in RTL describe signal names, expected timing, and IO conventions to help integration with board-level hardware.