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1. nayem-j/RISC-cpu-16b-mcycle nayem-j/RISC-cpu-16b-mcycle Public

   A 16-bit RISC like CPU design [RTL to GDS2] for IC Physical Design [PnR] training

   SystemVerilog

2. gowin-nongui-mint gowin-nongui-mint Public

   Tcl

3. PicoRV-SoC-Tang-Nano-9k PicoRV-SoC-Tang-Nano-9k Public

   Using the Gowin GW1NR-9 FPGA to prototype a simple RISC-V SOC with SRAM, LED driver, countdown timer and UART controller for education purposes with Gowin EDA tools and Verilog

   Verilog 2

4. vivado_tools_win11 vivado_tools_win11 Public

   Typical usage of vivado tools (xvlog, xelab and xsim) via GNU make on win11

   SystemVerilog

5. gw-dpb-infer gw-dpb-infer Public

   Verilog

6. apb-memory-sv-verif apb-memory-sv-verif Public

   Developed a generic memory module and implemented a protocol-compliant wrapper to interface with the AMBA APB standard. Verified the design with a layered testbench with coverage in Systemverilog

   SystemVerilog