config: enable Wildcat Lake in LPMD

[karanshukla]

Summary

Closes #123.

Add Wildcat Lake (family 6, model 0xD5/213) support: id_table[] entry plus a tuned config, same shape as #121 for Arrow Lake-H. This processor just released on the Dell XPS 13 2026, and the LPMD kept silently crashing at boot. The original workaround was to use --ignore-platform-check but I saw a PR and decided I could contribute as well to give the device a bit of a boost.

Topology: trust detect_cpu_topo(), not /sys/devices or lscpu -e

Verified on an Intel Core 5 320 (2 P-cores, 15W TDP). lscpu -e's L2-instance grouping (4 non-P cores sharing one L2 cluster) looks like a single Skymont-style E-core module, and /sys/devices/cpu_core/cpus / cpu_atom/cpus only give the P/atom split, not E vs L. Both are misleading here. Intel Reference for the CPU here.

Ran the daemon's own CPUID-based detection and it says otherwise:

Detected 2 Pcores, 0 Ecores, 4 Lcores, TDP 15W
CPU Config: 2P0E4L-15W

All 4 non-P cores fail is_cpu_in_l3() (no L3 in their CPUID leaf 4), so they classify as L, not E. There is no E-core tier on this platform, only P + L (Intel refers to them as Low Power Efficient or LP-E cores). A first draft of this config used ActiveEcores=ALL, which resolves to an empty CPU set on this topology and would leave Balanced/Powersaver mode with zero active cores. Caught by actually running it, not by reading the source.

Design

Same pattern as #121: WLT-driven core parking and EPP/EPB, with the L-core set as the low-power tier.

Profile	Def	Mode	Active cores
Performance	-1	LPMD OFF	All (P+L)
Balanced	0	AUTO	Varies by WLT state, see below
Power Saver	1	Force ON	L only, pinned

Balanced is opportunistic, not a static floor. choose_next_state() re-evaluates on every WLT notification, so the P-cores are parked only while the hardware reports idle or battery-life, and are released again for sustained and bursty work. Power Saver is the hard pin to the L-core set.

WLT states:

State	WLT	Active cores	EPP	EPB
UTIL_IDLE	0+1 (WLTTypeMask=3)	L only (ActiveLcores=ALL)	192 "balance_power"	8
UTIL_IDLE_SUSTAIN	2	full set (ActiveCPUs=*)	64	4
UTIL_IDLE_BURSTY	3	full set (ActiveCPUs=*)	128 "balance_performance"	6

Unparking on both 2 and 3 follows F6_M181 (Lunar Lake) and F6_M204 (Panther Lake). Every upstream config that varies the CPU set by WLT state unparks for both; none unparks for one alone.

WLTTypeMask=3 merges WLT 0/1 for the same reason as #121: this class of hardware oscillates between them fast enough that splitting them into separate EPP/EPB states is pure sysfs write churn for no benefit.

SoC Power Slider config omitted, not yet confirmed present on this sample via the int340x thermal driver.

Known limitation

Because every state defines a WLTType or WLTTypeMask, utilization-based entry triggers are disabled per intel_lpmd_config.xml(5), so entry and exit ride entirely on the hardware WLT hint. Measured 0.69s from load start to unpark and 0.64s from load stop to re-park, see the test plan below.

If the hint ever lands on a value no state matches (e.g. WLT_INVALID=4), choose_next_state() returns STATE_NONE and lpmd_enter_next_state() holds the previous state rather than falling back to the full CPU set, so it would stay parked. Happy to add a wildcard fallback state if that is the preferred handling.

Note for reviewers

Every merged F6_M* config sets all three of PerformanceDef/BalancedDef/PowersaverDef to -1, which leaves the WLT state table inert unless something drives the daemon over D-Bus. This config uses 0/1 so the states actually apply under power-profiles-daemon. Say the word if -1 across the board is deliberate policy for new platforms and I will match it.

Files changed

• src/lpmd_cpu.c - add model 0xD5 to id_table[]
• data/intel_lpmd_config_F6_M213.xml - new platform config
• data/Makefile.am - register config for install

Test plan

• Built from source (upower-devel, libnl3-devel needed, not in this repo's docs)

• Verified on Intel Core 5 320 (2P+4L, 15W TDP)

• Confirmed config file is found and parses (Found 3 config states)

• Confirmed Balanced mode parks P-cores via cgroup isolation while idle (0,1 moved to isolated partition, 2-5 remain schedulable)

• Confirmed WLT hint moves to 2 within ~1s of sustained load and UTIL_IDLE_SUSTAIN is entered

• Confirmed P-cores unpark on WLT 2 and re-park on WLT 1 under Balanced. Sampling /sys/fs/cgroup/cpuset.cpus.effective against the raw hint at workload_hint/workload_type_index every 250ms, with 6 busy workers as the load:

    0.00  raw=17  wlt=1  effective_cpus=2-5
    5.02  >>> LOAD START (6 workers)
    5.71  raw=18  wlt=2  effective_cpus=0-5
   25.16  >>> LOAD STOP
   25.80  raw=1   wlt=1  effective_cpus=2-5
  

  Note the raw hint reads 17/18 rather than 1/2, so WLTHintMask=15 is load-bearing on this platform, not just documentation.

• Confirmed EPP/EPB apply per WLT state on transition (Set CPU2 EPP to 0xc0, etc.)

• Confirmed clean shutdown: EPP/EPB restored, cgroup partition reset to member, full CPU set restored

[simiscoool-afk]

should 0 for automatic not reflect how automatic should be? aka switching between p and lp cores as needed.

i would assume usability would become quite bad, i have a 258v myself and i like going down to power save but responsiveness for anything but media is too bad. While on balanced i do have higher power draw but it is far more usable as the system can use the P cores for what they are meant for.

[karanshukla]

@simiscoool-afk hey sorry, the table in the PR description is a bit out of date, I'll update it shortly.