feat(synth): zero-multiplier proof and area stats (M4 Task 6) - #20
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zero_mult.ys: hierarchy -check + assert-count 0 on $mul/$div/$mod/$pow - passes. synth_xilinx stat: LUT 63697 (45181 LUT6), FF 11624, RAMB36E1 24, DSP 0, MUXF7/8 20133, CARRY4 3894. LUTs land ~3x the plan estimate: the per-tap dynamic weight-code part-selects synthesize as 144 parallel byte-mux trees per layer. M5 note: reorganizing weight ROMs as C_OUT-indexed wide-word BRAM reads should reclaim most of the LUT6/MUXF budget. Also fixes the plan's DSP guard (anchored grep - the yosys log mentions DSP48 while loading the cell library - and if/exit instead of a subshell exit that || silently swallowed).
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Task 6, executed inline by the planner per Bahadir (formal review skipped for Tasks 5-6). Netlist assertion: zero mul/div/mod/pow cells with hierarchy -check. synth_xilinx: LUT 63697, FF 11624, BRAM36 24, DSP 0. The LUT overshoot vs the plan estimate is diagnosed in the commit body (weight-ROM mux trees) with the M5 remediation path. Two guard bugs in the plan recipe found and fixed during execution.