soc: apple: add Apple SEP driver

Documentation/devicetree/bindings/input/apple,mesa-fingerprint.yaml

@@ -0,0 +1,77 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/input/apple,mesa-fingerprint.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Apple Mesa fingerprint sensor
+
+maintainers:
+  - Chromatischer <dominik@hildania.de>
+
+description: |
+  Fingerprint sensor on an SPI bus of an Apple SoC, normally owned by the
+  Secure Enclave Processor.  The chip-select setup and hold delays have to be
+  produced by the controller, so the device must use the native chip select of
+  its parent controller and not a GPIO one.
+
+  The SPI mode is not given a default here because the boards that carry this
+  sensor have not been observed to agree on one, so each board description has
+  to state the mode it needs.
+
+allOf:
+  - $ref: /schemas/spi/spi-peripheral-props.yaml#
+
+properties:
+  compatible:
+    const: apple,mesa-fingerprint
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+    description: Data-ready line from the sensor.
+
+  enable-gpios:
+    maxItems: 1
+    description: Power line to the sensor, asserted to power it up.
+
+  firmware-name:
+    maxItems: 1
+    description:
+      Calibration blob for this sensor.  It is per-device factory data written
+      at manufacture, so it is neither redistributable nor derivable from the
+      compatible; the board description has to name it.
+
+  spi-cpha: true
+
+  spi-cpol: true
+
+required:
+  - compatible
+  - reg
+  - enable-gpios
+  - firmware-name
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/gpio/gpio.h>
+
+    spi {
+        #address-cells = <1>;
+        #size-cells = <0>;
+
+        fingerprint@0 {
+            compatible = "apple,mesa-fingerprint";
+            reg = <0>;
+            spi-max-frequency = <8000000>;
+            spi-cpha;
+            spi-cs-setup-delay-ns = <20>;
+            spi-cs-hold-delay-ns = <20>;
+            enable-gpios = <&pinctrl_ap 108 GPIO_ACTIVE_HIGH>;
+            firmware-name = "apple/mesacal-j313.bin";
+        };
+    };

Documentation/devicetree/bindings/iommu/apple,dart.yaml

@@ -54,6 +54,15 @@ properties:
   power-domains:
     maxItems: 1
 
+  apple,dma-range:
+    description: |
+      The DART's IOVA aperture as one 64-bit base address followed by one
+      64-bit size.  Present when the device only translates IOVAs inside a
+      limited range, for example the SEP which only accepts IOVAs below 4 GiB.
+    $ref: /schemas/types.yaml#/definitions/uint32-array
+    minItems: 4
+    maxItems: 4
+
 required:
   - compatible
   - reg

MAINTAINERS

@@ -2534,6 +2534,7 @@ F:	Documentation/devicetree/bindings/gpio/apple,smc-gpio.yaml
 F:	Documentation/devicetree/bindings/gpu/apple,agx.yaml
 F:	Documentation/devicetree/bindings/hwmon/apple,smc-hwmon.yaml
 F:	Documentation/devicetree/bindings/i2c/apple,i2c.yaml
+F:	Documentation/devicetree/bindings/input/apple,mesa-fingerprint.yaml
 F:	Documentation/devicetree/bindings/input/touchscreen/apple,z2-multitouch.yaml
 F:	Documentation/devicetree/bindings/interrupt-controller/apple,*
 F:	Documentation/devicetree/bindings/iommu/apple,dart.yaml

arch/arm64/boot/dts/apple/t8103-j313.dts

@@ -94,6 +94,34 @@
 	};
 };
 
+/*
+ * Mesa fingerprint sensor on SPI2. The power line (pin 108, active high) comes
+ * from the J313 platform device tree, which also lists an interrupt on pin 104. The
+ * interrupt is left out on purpose: the driver polls, and the trigger flags in
+ * the ADT (3) are not decoded with any certainty here. Pin 104 reads back as a
+ * plain input with a pull-down, which rules out the two active-low readings of
+ * that value but does not decide between the remaining ones.
+ *
+ * Do not add cs-gpios. The sensor needs the controller's native chip select,
+ * otherwise the SPI core skips the hardware CS timing.
+ */
+&spi2 {
+	status = "okay";
+};
+
+&mesa {
+	status = "okay";
+	enable-gpios = <&pinctrl_ap 108 GPIO_ACTIVE_HIGH>;
+	spi-cs-setup-delay-ns = <20>;
+	spi-cs-hold-delay-ns = <20>;
+	/*
+	 * Per-device factory data written at manufacture.  It is not
+	 * redistributable and has to be extracted from the machine's own macOS
+	 * install, so the name only fixes where the driver looks for it.
+	 */
+	firmware-name = "apple/mesacal-j313.bin";
+};
+
 &i2c1 {
 	speaker_left: codec@31 {
 		compatible = "ti,tas5770l", "ti,tas2770";

arch/arm64/boot/dts/apple/t8103.dtsi

@@ -861,6 +861,51 @@
 			status = "disabled";
 		};
 
+		/*
+		 * The J313 platform device tree puts the Mesa fingerprint sensor
+		 * on SPI2.  The 120 MHz parent was confirmed by timing transfers:
+		 * a 22158-byte transfer requested at 8 MHz, divider 15, ran at
+		 * 7.45 Mbit/s.  A 200 MHz parent would make that divider
+		 * 13.3 MHz, and the measurement could not then have come out
+		 * below 8 MHz.
+		 *
+		 * The pin group was read out of the hardware rather than taken
+		 * from a schematic.  iBoot leaves every SPI pad it uses at
+		 * peripheral function 1, and the three buses whose groups are
+		 * already described here have the same register signature: two
+		 * pads with no pull for CLK and MOSI, one with a pull-down for
+		 * MISO.  Pins 128, 129 and 130 are the only remaining pads with
+		 * that signature, and they are contiguous, so they are SPI2.
+		 * Pin 131 is a different pad type and is not part of the group.
+		 *
+		 * There is no chip-select pin.  The platform device tree gives
+		 * SPI1, SPI3 and SPI4 a GPIO chip select (pins 45, 49 and 24, each the
+		 * last pad of its group) and gives SPI2 the string "null", so
+		 * SPI2 uses the controller's own chip select.  That is also why
+		 * SPI0, which has no GPIO chip select either, lists three pins.
+		 */
+		spi2: spi@235108000 {
+			compatible = "apple,t8103-spi", "apple,spi";
+			reg = <0x2 0x35108000 0x0 0x4000>;
+			interrupt-parent = <&aic>;
+			interrupts = <AIC_IRQ 616 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clk_120m>;
+			pinctrl-0 = <&spi2_pins>;
+			pinctrl-names = "default";
+			power-domains = <&ps_spi2>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+
+			mesa: fingerprint@0 {
+				compatible = "apple,mesa-fingerprint";
+				reg = <0>;
+				spi-max-frequency = <8000000>;
+				spi-cpha;
+				status = "disabled";
+			};
+		};
+
 		spi3: spi@23510c000 {
 			compatible = "apple,t8103-spi", "apple,spi";
 			reg = <0x2 0x3510c000 0x0 0x4000>;
@@ -1120,6 +1165,12 @@
 					<APPLE_PINMUX(45, 1)>;
 			};
 
+			spi2_pins: spi2-pins {
+				pinmux = <APPLE_PINMUX(128, 1)>, /* CLK */
+					<APPLE_PINMUX(129, 1)>, /* MOSI */
+					<APPLE_PINMUX(130, 1)>; /* MISO */
+			};
+
 			spi3_pins: spi3-pins {
 				pinmux = <APPLE_PINMUX(46, 1)>,
 					<APPLE_PINMUX(47, 1)>,

arch/arm64/boot/dts/apple/t8112.dtsi

@@ -888,6 +888,20 @@
 			status = "disabled";
 		};
 
+		spi2: spi@235108000 {
+			compatible = "apple,t8112-spi", "apple,spi";
+			reg = <0x2 0x35108000 0x0 0x4000>;
+			interrupt-parent = <&aic>;
+			interrupts = <AIC_IRQ 750 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clkref>;
+			pinctrl-0 = <&spi2_pins>;
+			pinctrl-names = "default";
+			power-domains = <&ps_spi2>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
 		spi3: spi@23510c000 {
 			compatible = "apple,t8112-spi", "apple,spi";
 			reg = <0x2 0x3510c000 0x0 0x4000>;
@@ -1291,6 +1305,13 @@
 					<APPLE_PINMUX(49, 1)>;
 			};
 
+			spi2_pins: spi2-pins {
+				/* Three signal pads; SPI2 uses the controller's native chip select. */
+				pinmux = <APPLE_PINMUX(64, 1)>,
+					<APPLE_PINMUX(65, 1)>,
+					<APPLE_PINMUX(66, 1)>;
+			};
+
 			spi3_pins: spi3-pins {
 				pinmux = <APPLE_PINMUX(93, 1)>,
 					<APPLE_PINMUX(94, 1)>,

block/blk-crypto.c

@@ -116,6 +116,7 @@ void bio_crypt_set_ctx(struct bio *bio, const struct blk_crypto_key *key,
 
 	bio->bi_crypt_context = bc;
 }
+EXPORT_SYMBOL_GPL(bio_crypt_set_ctx);
 
 void __bio_crypt_free_ctx(struct bio *bio)
 {
@@ -186,6 +187,7 @@ bool bio_crypt_dun_is_contiguous(const struct bio_crypt_ctx *bc,
 	/* If the DUN wrapped through 0, don't treat it as contiguous. */
 	return carry == 0;
 }
+EXPORT_SYMBOL_GPL(bio_crypt_dun_is_contiguous);
 
 /*
  * Checks that two bio crypt contexts are compatible - i.e. that
@@ -349,6 +351,7 @@ int blk_crypto_init_key(struct blk_crypto_key *blk_key,
 
 	return 0;
 }
+EXPORT_SYMBOL_GPL(blk_crypto_init_key);
 
 bool blk_crypto_config_supported_natively(struct block_device *bdev,
 					  const struct blk_crypto_config *cfg)
@@ -399,6 +402,7 @@ int blk_crypto_start_using_key(struct block_device *bdev,
 	}
 	return blk_crypto_fallback_start_using_mode(key->crypto_cfg.crypto_mode);
 }
+EXPORT_SYMBOL_GPL(blk_crypto_start_using_key);
 
 /**
  * blk_crypto_evict_key() - Evict a blk_crypto_key from a block_device

drivers/nvme/host/Kconfig

@@ -127,6 +127,7 @@ config NVME_APPLE
 	depends on OF && BLOCK
 	depends on APPLE_RTKIT && APPLE_SART
 	depends on ARCH_APPLE || COMPILE_TEST
+	select BLK_INLINE_ENCRYPTION
 	select NVME_CORE
 	help
 	  This provides support for the NVMe controller embedded in Apple SoCs