Popular repositories Loading
-
npu-aware-engineering
npu-aware-engineering PublicHW-SW Co-Design framework for custom NPU: Parameterized systolic array RTL verification via cocotb and multi-objective design space exploration (DSE) with analytical performance modeling.
Python
-
tessellate
tessellate PublicClosed-loop HW/SW co-design for compute-in-memory accelerators — NSGA-II searches per-layer weight precision and column pruning, verified by real PyTorch QAT and physics simulation. The LLM explain…
Python
Something went wrong, please refresh the page to try again.
If the problem persists, check the GitHub status page or contact support.
If the problem persists, check the GitHub status page or contact support.