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QCLINUX: arm64: dts: qcom: lemans and monaco: Rework RTSS Mailbox DT to use syscon and staging overlays #1042

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QCLINUX: arm64: dts: qcom: lemans and monaco: Rework RTSS Mailbox DT to use syscon and staging overlays #1042

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69b3cfe
Revert "QCLINUX: arm64: dts: qcom: lemans: Add RTSS Mailbox device tr…
sargarram7 Sep 5, 2026
1c11382
Revert "QCLINUX: arm64: dts: qcom: Monaco: Add RTSS Mailbox device tr…
sargarram7 Sep 5, 2026
85b8978
QCLINUX: arm64: dts: qcom: lemans: Add IPCC and syscon nodes for RTSS…
sargarram7 Sep 5, 2026
82b77ee
QCLINUX: arm64: dts: qcom: lemans: Add RTSS Mailbox device tree node
sargarram7 Sep 5, 2026
1704c1e
QCLINUX: arm64: dts: qcom: Monaco: Add SAIL/RTSS mailbox reserved-mem…
sargarram7 Sep 5, 2026
4d7b44a
QCLINUX: arm64: dts: qcom: Monaco: Add IPCC and syscon nodes for RTSS…
sargarram7 Sep 5, 2026
81fbcfc
QCLINUX: arm64: dts: qcom: Monaco: Add RTSS Mailbox device tree node
sargarram7 Sep 5, 2026
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2 changes: 0 additions & 2 deletions arch/arm64/boot/dts/qcom/Makefile
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Original file line number Diff line number Diff line change
Expand Up @@ -488,7 +488,6 @@ dtb-$(CONFIG_ARCH_QCOM) += lemans-camx-el2.dtb

dtb-$(CONFIG_ARCH_QCOM) += lemans-evk-staging.dtbo

dtb-$(CONFIG_ARCH_QCOM) += lemans-rtss-mb.dtbo
dtb-$(CONFIG_ARCH_QCOM) += lemans-staging.dtbo

monaco-evk-camx-dtbs := monaco-evk.dtb monaco-evk-camx.dtbo
Expand All @@ -501,7 +500,6 @@ monaco-camx-el2-dtbs := monaco-evk-el2.dtb monaco-evk-camx.dtbo monaco-camx-el2.
dtb-$(CONFIG_ARCH_QCOM) += monaco-camx-el2.dtb

dtb-$(CONFIG_ARCH_QCOM) += monaco-evk-staging.dtbo
dtb-$(CONFIG_ARCH_QCOM) += monaco-rtss-mb.dtbo

dtb-$(CONFIG_ARCH_QCOM) += monaco-staging.dtbo

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65 changes: 0 additions & 65 deletions arch/arm64/boot/dts/qcom/lemans-rtss-mb.dtso
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49 changes: 49 additions & 0 deletions arch/arm64/boot/dts/qcom/lemans-staging.dtso
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Expand Up @@ -8,9 +8,58 @@
/dts-v1/;
/plugin/;
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/clock/qcom,sa8775p-gcc.h>
#include <dt-bindings/mailbox/qcom-ipcc.h>

&soc {
rtss_mailbox: rtss-mailbox {
compatible = "qcom,rtss-mailbox";
qcom,syscon-tcsr-req = <&apss_tcsr_req>;
qcom,req-tcsr-offset = <0x0>;
qcom,syscon-tcsr-resp = <&apss_tcsr_resp>;
qcom,resp-tcsr-offset = <0x0>;
qcom,syscon-ipc = <&apss_shared_ipc>;
qcom,ipc-offset = <0x0>;
qcom,handshake-magic = <0xD0000000 0xD0020000 0xD0030000>;
qcom,handshake-delay = <0x0000C350>;
qcom,handle-offset = <0x80000 0x80000>;
qcom,client-lut = <0x488000 0x8>, <0x4a1000 0x21>, <0x4a2000 0x22>, <0x4a3000 0x23>;
mboxes = <&ipcc1 IPCC_CLIENT_RTSS0 0x2>,
<&ipcc1 IPCC_CLIENT_RTSS1 0x3>,
<&ipcc1 IPCC_CLIENT_RTSS0 0x4>,
<&ipcc1 IPCC_CLIENT_RTSS0 0x5>,
<&ipcc1 IPCC_CLIENT_RTSS0 0x6>,
<&ipcc1 IPCC_CLIENT_RTSS0 0x7>,
<&ipcc1 IPCC_CLIENT_RTSS2 0x8>,
<&ipcc1 IPCC_CLIENT_RTSS1 0x9>,
<&ipcc1 IPCC_CLIENT_RTSS2 0xa>,
<&ipcc1 IPCC_CLIENT_RTSS1 0xb>,
<&ipcc1 IPCC_CLIENT_RTSS0 0xc>,
<&ipcc1 IPCC_CLIENT_RTSS0 0xd>,
<&ipcc1 IPCC_CLIENT_RTSS1 0xe>,
<&ipcc1 IPCC_CLIENT_RTSS2 0xf>,
<&ipcc1 IPCC_CLIENT_RTSS3 0x10>;
interrupts-extended = <&ipcc1 IPCC_CLIENT_RTSS0 0x2 IRQ_TYPE_EDGE_RISING>,
<&ipcc1 IPCC_CLIENT_RTSS1 0x3 IRQ_TYPE_EDGE_RISING>,
<&ipcc1 IPCC_CLIENT_RTSS0 0x4 IRQ_TYPE_EDGE_RISING>,
<&ipcc1 IPCC_CLIENT_RTSS0 0x5 IRQ_TYPE_EDGE_RISING>,
<&ipcc1 IPCC_CLIENT_RTSS0 0x6 IRQ_TYPE_EDGE_RISING>,
<&ipcc1 IPCC_CLIENT_RTSS0 0x7 IRQ_TYPE_EDGE_RISING>,
<&ipcc1 IPCC_CLIENT_RTSS2 0x8 IRQ_TYPE_EDGE_RISING>,
<&ipcc1 IPCC_CLIENT_RTSS1 0x9 IRQ_TYPE_EDGE_RISING>,
<&ipcc1 IPCC_CLIENT_RTSS2 0xa IRQ_TYPE_EDGE_RISING>,
<&ipcc1 IPCC_CLIENT_RTSS1 0xb IRQ_TYPE_EDGE_RISING>,
<&ipcc1 IPCC_CLIENT_RTSS0 0xc IRQ_TYPE_EDGE_RISING>,
<&ipcc1 IPCC_CLIENT_RTSS0 0xd IRQ_TYPE_EDGE_RISING>,
<&ipcc1 IPCC_CLIENT_RTSS1 0xe IRQ_TYPE_EDGE_RISING>,
<&ipcc1 IPCC_CLIENT_RTSS2 0xf IRQ_TYPE_EDGE_RISING>,
<&ipcc1 IPCC_CLIENT_RTSS3 0x10 IRQ_TYPE_EDGE_RISING>;
memory-region = <&sail_mailbox_mem>,
<&sail_ota_mem>;
status = "okay";
};

tgu@4b0e000 {
compatible = "qcom,tgu", "arm,primecell";
reg = <0x0 0x4b0e000 0x0 0x1000>;
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51 changes: 51 additions & 0 deletions arch/arm64/boot/dts/qcom/lemans.dtsi
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Expand Up @@ -1130,6 +1130,57 @@
#mbox-cells = <2>;
};

ipcc1: mailbox@488000 {
compatible = "qcom,sa8775p-ipcc", "qcom,ipcc";
reg = <0x0 0x00488000 0x0 0x1000>;
interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <3>;
#mbox-cells = <2>;
};

ipcc2: mailbox@4a1000 {
compatible = "qcom,sa8775p-ipcc", "qcom,ipcc";
reg = <0x0 0x004a1000 0x0 0x1000>;
interrupts = <GIC_SPI 553 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <3>;
#mbox-cells = <2>;
};

ipcc3: mailbox@4a2000 {
compatible = "qcom,sa8775p-ipcc", "qcom,ipcc";
reg = <0x0 0x004a2000 0x0 0x1000>;
interrupts = <GIC_SPI 554 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <3>;
#mbox-cells = <2>;
};

ipcc4: mailbox@4a3000 {
compatible = "qcom,sa8775p-ipcc", "qcom,ipcc";
reg = <0x0 0x004a3000 0x0 0x1000>;
interrupts = <GIC_SPI 555 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <3>;
#mbox-cells = <2>;
};

apss_tcsr_req: syscon@1ffe02c {
compatible = "qcom,sa8775p-tcsr", "syscon";
reg = <0x0 0x1ffe02c 0x0 0x10>;
};

apss_tcsr_resp: syscon@1ffd018 {
compatible = "qcom,sa8775p-tcsr", "syscon";
reg = <0x0 0x1ffd018 0x0 0x10>;
};

apss_shared_ipc: syscon@17c0000c {
compatible = "qcom,sa8775p-tcsr", "syscon";
reg = <0x0 0x17c0000c 0x0 0x4>;
};

qfprom: efuse@784000 {
compatible = "qcom,sa8775p-qfprom", "qcom,qfprom";
reg = <0x0 0x00784000 0x0 0x3000>;
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65 changes: 0 additions & 65 deletions arch/arm64/boot/dts/qcom/monaco-rtss-mb.dtso
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50 changes: 50 additions & 0 deletions arch/arm64/boot/dts/qcom/monaco-staging.dtso
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Original file line number Diff line number Diff line change
Expand Up @@ -7,8 +7,58 @@

/dts-v1/;
/plugin/;
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/mailbox/qcom-ipcc.h>

&soc {
rtss_mailbox: rtss-mailbox {
compatible = "qcom,rtss-mailbox";
qcom,syscon-tcsr-req = <&apss_tcsr_req>;
qcom,req-tcsr-offset = <0x0>;
qcom,syscon-tcsr-resp = <&apss_tcsr_resp>;
qcom,resp-tcsr-offset = <0x0>;
qcom,syscon-ipc = <&apss_shared_ipc>;
qcom,ipc-offset = <0x0>;
qcom,handshake-magic = <0xD0000000 0xD0020000 0xD0030000>;
qcom,handshake-delay = <0x0000C350>;
qcom,handle-offset = <0x80000 0x80000>;
qcom,client-lut = <0x488000 0x8>, <0x4a1000 0x21>, <0x4a2000 0x22>, <0x4a3000 0x23>;
mboxes = <&ipcc1 IPCC_CLIENT_RTSS0 0x2>,
<&ipcc1 IPCC_CLIENT_RTSS1 0x3>,
<&ipcc1 IPCC_CLIENT_RTSS0 0x4>,
<&ipcc1 IPCC_CLIENT_RTSS0 0x5>,
<&ipcc1 IPCC_CLIENT_RTSS0 0x6>,
<&ipcc1 IPCC_CLIENT_RTSS0 0x7>,
<&ipcc1 IPCC_CLIENT_RTSS2 0x8>,
<&ipcc1 IPCC_CLIENT_RTSS1 0x9>,
<&ipcc1 IPCC_CLIENT_RTSS2 0xa>,
<&ipcc1 IPCC_CLIENT_RTSS1 0xb>,
<&ipcc1 IPCC_CLIENT_RTSS0 0xc>,
<&ipcc1 IPCC_CLIENT_RTSS0 0xd>,
<&ipcc1 IPCC_CLIENT_RTSS1 0xe>,
<&ipcc1 IPCC_CLIENT_RTSS2 0xf>,
<&ipcc1 IPCC_CLIENT_RTSS3 0x10>;
interrupts-extended = <&ipcc1 IPCC_CLIENT_RTSS0 0x2 IRQ_TYPE_EDGE_RISING>,
<&ipcc1 IPCC_CLIENT_RTSS1 0x3 IRQ_TYPE_EDGE_RISING>,
<&ipcc1 IPCC_CLIENT_RTSS0 0x4 IRQ_TYPE_EDGE_RISING>,
<&ipcc1 IPCC_CLIENT_RTSS0 0x5 IRQ_TYPE_EDGE_RISING>,
<&ipcc1 IPCC_CLIENT_RTSS0 0x6 IRQ_TYPE_EDGE_RISING>,
<&ipcc1 IPCC_CLIENT_RTSS0 0x7 IRQ_TYPE_EDGE_RISING>,
<&ipcc1 IPCC_CLIENT_RTSS2 0x8 IRQ_TYPE_EDGE_RISING>,
<&ipcc1 IPCC_CLIENT_RTSS1 0x9 IRQ_TYPE_EDGE_RISING>,
<&ipcc1 IPCC_CLIENT_RTSS2 0xa IRQ_TYPE_EDGE_RISING>,
<&ipcc1 IPCC_CLIENT_RTSS1 0xb IRQ_TYPE_EDGE_RISING>,
<&ipcc1 IPCC_CLIENT_RTSS0 0xc IRQ_TYPE_EDGE_RISING>,
<&ipcc1 IPCC_CLIENT_RTSS0 0xd IRQ_TYPE_EDGE_RISING>,
<&ipcc1 IPCC_CLIENT_RTSS1 0xe IRQ_TYPE_EDGE_RISING>,
<&ipcc1 IPCC_CLIENT_RTSS2 0xf IRQ_TYPE_EDGE_RISING>,
<&ipcc1 IPCC_CLIENT_RTSS3 0x10 IRQ_TYPE_EDGE_RISING>;
memory-region = <&sail_mailbox_mem>,
<&sail_ota_mem>;
status = "okay";
};

tgu@4b0e000 {
compatible = "qcom,tgu", "arm,primecell";
reg = <0x0 0x4b0e000 0x0 0x1000>;
Expand Down
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