RISC-V: Add Zmmul target feature - #162552
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cc @rust-lang/rust-analyzer Target features are being changed; ensure all ABI effects are being accounted for cc @RalfJung Some changes occurred in cc @Amanieu, @folkertdev, @sayantn |
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Thanks for the pull request, and welcome! The Rust Project has assigned @Darksonn (or someone else) to review your changes, you should hear from them (or someone else) within the next two weeks. Please see the contribution instructions and our LLM policy for more information. Why was this reviewer chosen?The reviewer was selected based on:
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LLVM can change their implications, we cannot. So we better be sure if we want to have this implication.
It's too early to worry about this. Add it unstably first. |
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Hey RISC-V Group! This issue has been identified as a good "RISC-V candidate". |
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r? compiler |
While the |
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That sounds reasonable, but we should make sure it is documented.
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I've put a comment explaining the difference between the ISA extension and the target feature in |
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Since "m" is stable it should be mentioned in the reference. Though having a comment in the code, at least a brief one saying that "m" also means that we assume that the bit is actually set at runtime, is still also a good idea. |
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r? @beetrees |
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Thanks. @bors r+ |
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…beetrees RISC-V: Add Zmmul target feature Zmmul is a ratified subset of the M extension that only supports multiplication, but not division ([spec](https://docs.riscv.org/reference/isa/v20260120/unpriv/m-st-ext.html#11-1-3-zmmul-extension-version-1-0)). LLVM already supports the extension under the same name, so until rust-lang#162235 I'd just been using it directly. There are two things I would particularly appreciate input on: - Should M imply Zmmul? - From the [Machine-Level ISA spec](https://docs.riscv.org/reference/isa/v20260120/priv/machine.html) and [this discussion](riscv/riscv-isa-manual#869) in the RISC-V ISA Manual repo, it seems that Zmmul means all multiplication instructions are always supported, whereas M means they're only supported if the M bit is set in the `misa` register. - On the other hand, LLVM has M imply Zmmul ([RISCVFeatures.td](https://github.com/llvm/llvm-project/blob/f6f71edb4346d586bb97485116175efd9a696ee8/llvm/lib/Target/RISCV/RISCVFeatures.td#L214-L229)), so it feels nice to match that. - How might I go about stabilizing this? - Can it be done right away? - Should it wait a few releases? - Is it better to batch it with the stabilization of other RISC-V target features, similarly to how it was done in rust-lang#145948? No LLMs were used in the making of this PR, and all mistakes are those of a first-time rustc contributor.
…uwer Rollup of 10 pull requests Successful merges: - #161987 (fix `is_single_fp_element` for `s390x` and `x86`) - #162366 (Replace hard linked `metadata.rmeta` with a copy when finalizing the incremental compilation session dir fails) - #162552 (RISC-V: Add Zmmul target feature) - #162602 (Ensure concurrent rustc instances in the same process correctly lock the session dir) - #162885 (Remove one remaining use of `Level::Help`) - #162606 (c-b: Export `fmaf16` now that we have an implementation) - #162817 (rustc_{codegen_,}llvm: adapt to new ThreadModel API) - #162860 (offload: add libLLVM rpath for libomptarget) - #162895 (Avoid derive edits on macro-generated types) - #162899 (Error on invalid placements of the `cfi_encoding` attribute.)
Rollup merge of #162552 - TechnoPorg:riscv-feature-zmmul, r=beetrees RISC-V: Add Zmmul target feature Zmmul is a ratified subset of the M extension that only supports multiplication, but not division ([spec](https://docs.riscv.org/reference/isa/v20260120/unpriv/m-st-ext.html#11-1-3-zmmul-extension-version-1-0)). LLVM already supports the extension under the same name, so until #162235 I'd just been using it directly. There are two things I would particularly appreciate input on: - Should M imply Zmmul? - From the [Machine-Level ISA spec](https://docs.riscv.org/reference/isa/v20260120/priv/machine.html) and [this discussion](riscv/riscv-isa-manual#869) in the RISC-V ISA Manual repo, it seems that Zmmul means all multiplication instructions are always supported, whereas M means they're only supported if the M bit is set in the `misa` register. - On the other hand, LLVM has M imply Zmmul ([RISCVFeatures.td](https://github.com/llvm/llvm-project/blob/f6f71edb4346d586bb97485116175efd9a696ee8/llvm/lib/Target/RISCV/RISCVFeatures.td#L214-L229)), so it feels nice to match that. - How might I go about stabilizing this? - Can it be done right away? - Should it wait a few releases? - Is it better to batch it with the stabilization of other RISC-V target features, similarly to how it was done in #145948? No LLMs were used in the making of this PR, and all mistakes are those of a first-time rustc contributor.
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Zmmul is a ratified subset of the M extension that only supports multiplication, but not division (spec). LLVM already supports the extension under the same name, so until #162235 I'd just been using it directly.
There are two things I would particularly appreciate input on:
misaregister.riscv_ratified_v2) #145948?No LLMs were used in the making of this PR, and all mistakes are those of a first-time rustc contributor.