make memory encryption bit an upper limit for physical address bits - #603
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The failing CI jobs will be addressed by #604. |
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Looks good overall, thanks a lot! I would update the safety docs in two places, but otherwise this looks ready to be merged.
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We should document here that no bits above the encryption bit must be set if memory encryption is enabled.
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| let c_bit_mask = 1u64 << bit_position; | ||
| let addr_mask = u64::MAX << bit_position; | ||
| PHYSICAL_ADDRESS_MASK.fetch_and(!addr_mask, Ordering::Relaxed); |
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This assumes that the method is only called once, right? We should add that to the safety docs of the method?
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Yes. I update the doc comment.
Ensure that no bit above the C-bit/S-bit is set: - TDX already requires this: "GPA bits higher than the SHARED bit are considered reserved and must be 0. Address translation with any of the reserved bits set to 1 cause a #PF with PFEC (Page Fault Error Code) RSVD bit set." (Architecture Specification: Intel® Trust Domain Extensions (Intel® TDX) Module, 13.11.1. GPAW-Relate EPT Violations). - AMD CPUs don't have the same restriction, however in practice, the C-bit is always the upmost supported physical adddress bit. Client parts and server parts up until Rome support 48 physical address bits and use bit 47 as the C-bit. Server parts starting with Milan support 52 physical address bits and always use bit 51 as the C-bit. Thinking about this, this makes sense: If the CPU allowed bits higher than the C-bit to be used for address bits, this would fragment the physical address space and make large parts of it effectively unusable.
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Ensure that no bit above the C-bit/S-bit is set: