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tharinduSamare/README.md

Hello, I am Tharindu 👋

I am a Master’s student in Embedded Computing Systems at RPTU Kaiserslautern, Germany. I was an FPGA Design Engineer (contract) at Integrated Automotive (UK). Previously, I worked as an Electronics Engineer at Paraqum Technologies and served as a Verification Engineer for SiFive, Inc. (US)(contract). I am passionate about digital electronics and robotics. I completed my Bachelor’s degree in Electronics and Telecommunication Engineering at the University of Moratuwa, Sri Lanka.

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  1. RV32I-Processor_with_UVM_TB RV32I-Processor_with_UVM_TB Public

    RISCV 32I simplified core + UVM testbench to support running (simplified) riscv-tests

    Scala 1

  2. RISCV_processor_design RISCV_processor_design Public

    This is a RISC-V 32I processor which also supports the M extension.

    SystemVerilog

  3. Multicore_processor_SystemVerilog_design Multicore_processor_SystemVerilog_design Public

    This is a multicore processor specially designed for matrix multiplication.

    SystemVerilog

  4. entc17fyp6/ROS_system entc17fyp6/ROS_system Public

    Static object detection full system.

    Python

  5. entc17fyp6/camera-ros-connect entc17fyp6/camera-ros-connect Public

    Jupyter Notebook 1

  6. UVM_switch_test UVM_switch_test Public

    This is a UVM test bench for a simple combinational switch, designed for learning purposes.

    SystemVerilog 1 1