#
anlogic
Here are 17 public repositories matching this topic...
AI-assisted FPGA development across AMD Vivado, Anlogic TangDynasty, and Intel Quartus.
ai fpga mcp vhdl eda verilog xilinx cursor vivado claude quartus intel-fpga anlogic fpga-design model-context-protocol
-
Updated
Aug 17, 2026
Stereo digital 2-way crossover filters processing I2S audio (16bit or 24bit) streams
primer fpga esp32 altera iir i2s tang anlogic sipeed crossover-filter biquad-filter cyclone4 linkwitz-riley
-
Updated
May 13, 2024 - C++
USB-PD-3.1-Verilog
-
Updated
Apr 22, 2024 - Verilog
MLK-L1-CZ06-DR1M90G HDMI Audio
-
Updated
Dec 7, 2024 - Verilog
Eagle-4-MIPI-DSI-5.5-inch-LCD
-
Updated
Jun 24, 2025
Dragon 1 MIPI DSI 5.5 inch LCD
-
Updated
Jul 24, 2025
Codex FPGA/SoC FPGA 多角色且基于证据工程工作流：逐拍 RTL、CDC/RDC、STA、官方 IP、三厂商原生脚本、单一实现者与独立签核。
fpga vhdl multi-agent rtl verilog vivado systemverilog cdc modelsim codex pango sta anlogic timing-closure soc-fpga
-
Updated
Aug 31, 2026 - PowerShell
Turn AI-assisted RTL into a reviewable FPGA engineering flow with 13 focused roles, live contracts, and evidence-triggered P&R.
fpga vhdl verification eda multi-agent rtl verilog chinese vivado systemverilog cdc modelsim codex pango anlogic timing-closure soc-fpga hardware-design
-
Updated
Sep 3, 2026 - PowerShell
Add this topic to your repo
To associate your repository with the anlogic topic, visit your repo's landing page and select "manage topics."