RTL to GDSII flow of a low Power configurable multi clock digital system
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Updated
Mar 3, 2024 - Verilog
RTL to GDSII flow of a low Power configurable multi clock digital system
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VSDIAT Documentation- Openlane/Sky130- MIT
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Repository for my hobby VHDL projects for self-learning purposes.
RTL implementation of a synchronous FIFO in Verilog with comprehensive testbench and waveform verification
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