一个FPGA核心板设计,体积小、低成本、易用、扩展性强。
-
Updated
Sep 14, 2023 - Verilog
一个FPGA核心板设计,体积小、低成本、易用、扩展性强。
SCH, PIN assignment and example programs for EP4CE6E22C8 with 5 LED, 5 Keys, EPCS4 and W25Q64
RISC-V (Nios V) SoC para placas genéricas Cyclone IV (EP4CE6, EP4CE10, EP4CE15) com controlador SDRAM, bootloader via SPI e módulo PWM (com Testbench) em VHDL
EP4CE6E22C8 board with 50 & 27 MHz implementation along with W25Q64. PIC18F14K50 used as byte blaster
DE0-NANO EP4CE22F256 running BASIC-52 with I2C, SFR extensions at 50MHz. Tested with both USB-TTL CH341T and HC-06 Bluetooth module.
To associate your repository with the ep4ce6 topic, visit your repo's landing page and select "manage topics."