kintex-7

Python client and getting-started examples for SK-RAFT EDA tool, the SolidKosmos fault-injection server for AMD-Xilinx FPGAs. Emulate single-event upsets (SEUs) through JTAG: inject into the configuration memory, BRAM, flip-flops and LUTRAM of 7 series, UltraScale and UltraScale+ devices (Versal device support coming soon).

A complete custom implementation of the 10GBASE-R Physical Layer (PHY) in VHDL. This implementation provides full control over the 10 Gigabit Ethernet physical layer without relying on encrypted vendor IP.

Implements multi-protocol market data parsing supporting NASDAQ (UDP/MoldUDP64), ASX (TCP/SoupBinTCP), and B3 Brazilian Exchange (UDP/SBE) market data feeds. Integrates with Project 33's 10GBASE-R PHY for 10GbE reception and outputs parsed messages via Aurora to FPGA2 (order book engine).

Flappy Bird in bare-metal Verilog RTL for the Xilinx Kintex-7 KC705 - 1080p60 HDMI via ADV7511, no processor, no video IP

SDR B210 Kintex-7 FPGA

Kintex 7 accelerator card, getting started guide

This project implements a 10 Gigabit Ethernet (10GbE) interface using the Kintex-7 GTX transceivers on the ALINX AX7325B board. It uses the open-source [verilog-ethernet](https://github.com/alexforencich/verilog-ethernet) library for the MAC/PHY layers.

Python-driven EDA automation framework for parameterized FPGA adder generation, synthesis, and design space exploration using Xilinx Vivado

This KiCad project implements the PCB design for the Standalone 3-FPGA Trading Appliance

Order Book 10GbE - FPGA Order Book with UDP TX and Latency Measurement

Independent research notes on the unannounced USRP B310, reconstructed entirely from the public EttusResearch/uhd source tree at v4.11.0.0-rc2 — every claim cited path:line, graded STATED/INFERRED/ESTIMATED

MEGA65 + C64 cores on the QMTech XC7K325T CM4 carrier with a Luckfox Core3566: build/test harness, Rockchip daemons (SD, USB input, monitor, Ethernet, RTC, flash), docs

RISC-V-controlled INT8 acceleration with a synthesizable CiM macro proxy, open Ibex simulation, and a K7-validated KWS subgraph.

Fork of MEGA65/mega65-core: qmtech-k325t-cm4 target (QMTech XC7K325T CM4 carrier + Rockchip bridge, DDR3 attic RAM, 1 MB chip RAM, raster DMA list)