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vsdip / vsdflow

Star 19

VSDFLOW is an automated solution to programmers, hobbyists and small scale semiconductor technology entrepreneurs who can craft their ideas in RTL language, and convert the design to hardware using VSD (RTL-to-GDS) FLOW. VSDFLOW is completely build using OPHW tools, where the user gives input RTL in verilog. From here on the VSDFLOW takes contro…

opensource magic static tcl scripting-language rtl programmer synthesis yosys semiconductor netgen sta opensta qflow vsdip graywolf qrouter opentimer blifffanout physicaldesign
  • Updated Jul 21, 2020
  • Coq

Olajide-Badejo / Low-Power-Async-CDC-FIFO-IP

Star 0

Parameterized asynchronous CDC FIFO IP: gray-code pointers, a sweepable N-flop synchronizer, IEEE 1801 UPF low-power intent, SymbiYosys formal proofs, and a 60-config Yosys/OpenSTA PPA sweep on SkyWater Sky130. Fully open-source and reproducible.

asic rtl systemverilog fifo cdc formal-verification yosys digital-design low-power upf clock-domain-crossing static-timing-analysis opensta symbiyosys open-source-eda sky130
  • Updated Jul 16, 2026
  • SystemVerilog

Brafamous / uart-safety-controller-synthesis-sta

Star 0

UART Safety Controller ASIC implementation project demonstrating RTL synthesis, SKY130 technology mapping, multi-corner static timing analysis (TT/SS/FF), timing closure, CDC/RDC review, and implementation readiness for ASIC physical design.

asic eda rtl verilog uart cdc vlsi yosys semiconductor digital-design ic-design static-timing-analysis physical-design rdc timing-closure opensta openlane sky130
  • Updated Jun 26, 2026
  • Verilog

ubyhzargam / OpenSTA

Star 0

Timing reports are generated for various circuits using an open source tool OpenSTA. Both min and max timing reports are generated. The commands are given using a tcl script and I have used a 45nm pdk for technology mapping. The circuit is described using Verilog language. We can also generate or report power dissipated by design. MMMC is performed

electronics hdl vlsi sta opensta veilog
  • Updated Dec 4, 2024
  • Verilog

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