Open JSON format and community-driven library of Modbus device register maps, with validation and firmware compatibility.
AXI4-Lite slave in SystemVerilog that exposes control, configuration, status and data registers to a bus master. It handles the five independent channels with proper VALID and READY handshakes, decodes addresses, and returns OKAY or error responses. A master model and protocol assertions verify it in Verilator.
APB4 slave peripheral block in SystemVerilog that puts a GPIO controller and a programmable timer behind one register map. A bus master configures pins and the timer with ordinary read and write transfers, and protocol assertions check every transaction. Simulated with Verilator and GTKWave, synthesized with Yosys.
Register-mapped programmable timer in SystemVerilog: set load and reload values, start it, and receive an interrupt request on every overflow. Supports start, stop, enable, disable and interrupt masking. Simulated with Verilator and GTKWave, synthesizable with Yosys.
Tapeout Object Format (.tapeout) - flat-text hardware integration contract (parser + emitter)
Read-only Modbus engineering skills and workflows for Codex, Claude Code, Cursor, and other Agent Plugins clients.
Read-only Modbus register map, scanner and Home Assistant package for the Marstek Jupiter C Plus
Turn a sensor datasheet PDF into a verified register map and a page-cited C driver. Every generated line traces back to the datasheet page it came from.
An interactive web tool for decoding and encoding hardware register values
Searchable public JSON previews for Modbus register maps, built for Modbus Monitor XPF.
[stable] A zero-cost, type-safe DSL for MMIO and volatile register mapping in Rust.
Compatibility gate for CMSIS-SVD register maps. Detect breaking register-map changes in CI before they reach firmware.
Read registers from any Modbus device over TCP or RTU (RS-485) – read-only by design, raw words always shown, addresses never converted. Single Go binary, no device knowledge built in.
Access device's physical memory (configuration registers).
Open-source, local-first SoC collateral consistency checker for RTL, Liberty, LEF/DEF, IP-XACT, SystemRDL, SDC, UPF, connectivity CSV, package maps, CDL/GDS, and C headers.
Turn a datasheet into a verified register map and driver code.
Open, machine-readable Modbus register maps for energy meters, inverters, drives and other field devices
Register & protocol maps for the Barnex solar-surplus controller: inverters (Deye, Growatt, Victron, Luxpower, Huawei, SMA…) and EV chargers (Eveus). https://barnex.io
An ESP32 acting as a Modbus server: plant points published in a documented register map (scaling, status bitfields, function codes, exceptions) for a CODESYS soft-PLC, a Trend controller or any Modbus client, the reverse of the earlier client-side Modbus projects.
To associate your repository with the register-map topic, visit your repo's landing page and select "manage topics."