single-cycle-mips-processor

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Here are 7 public repositories matching this topic...

anirudh-bijay / IITK-Mini-MIPS

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Repository for project work for the course CS220: Computer Organisation.

python mips assembler university-project verilog vivado single-cycle-mips-processor

Updated May 15, 2026
Tcl

Arshanhp / verilog-16bit-single-cycle-mips-processor

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A 16-bit single-cycle MIPS-like processor implemented in Verilog. Features an 8-register file (with R0 as accumulator), 4KB addressable memory, and 4 instruction formats (Types A-D).

processor-architecture mips processor verilog computer-architecture mips-architecture single-cycle-processor single-cycle-mips-processor

Updated Jun 12, 2026
Verilog

4lac1vica / MIPS-UNIC-CYCLE

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Here are the source codes for MIPS Unic Cycle. Written in VHDL

vhdl mips-assembly mips-architecture single-cycle-mips-processor

Updated Feb 15, 2026
VHDL

duxeph / single-cycle-mips-processor

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Building a Single-Cycle Processor Using MIPS Architecture (VHDL & Xilinx ISE)

vhdl xilinx mips-architecture xilinx-ise mips-processor xilinx-vivado single-cycle-processor single-cycle-mips-processor

Updated Oct 1, 2024
VHDL

SUHANI102003 / 32-bit-Pipelined-MIPS-Processor

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Designed the ISA for RISC based pipelined 32-bit MIPS processor and implemented a subset of instructions to verify the functionality. Tested the operation using 3 testcases and observed the dataflow between stages.

pipeline verilog assembly-language risc-v mips32 single-cycle-mips-processor

Updated Aug 30, 2025
Verilog

NoumanZahid-85 / MARS-Plus

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This repository supports students taking Dr. Mehmood Qureshi’s Computer Architecture course. It enhances the open-source MARS simulator, simplifies the X-Ray Tool for register-level instructions, and includes an AI assistant to aid lab comprehension.

mars mips-architecture r-type computer-architecture-lab single-cycle-mips-processor datapath-control i-type j-type x-ray-tool