two changes: support for smem atomics, moving the dxa to socket level - #390
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symmetryyyyy wants to merge 5 commits into
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two changes: support for smem atomics, moving the dxa to socket level#390symmetryyyyy wants to merge 5 commits into
symmetryyyyy wants to merge 5 commits into
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Route AMO metadata into the local/shared-memory path and implement an aligned 32-bit AMOADD.W at the LMEM banks, returning the old word. RTL: - VX_lmem_switch: stop stripping the per-lane AMO attr bits on the local path and drop the unsupported-AMO assertion, so bank-side logic can see amo_valid. - VX_local_mem: carry attr through the request crossbar into each bank; add a per-bank single-slot read-modify-write context (read, compute via VX_amo_alu, write back, return old value) that serializes against ordinary LMEM traffic while other banks progress independently; extend the read-during-write hazard to AMOs; block DMA while any bank has an RMW or response in flight; merge the AMO response with the load response ahead of the bank response port. SimX: - local_mem_switch: stop asserting on shared-memory AMO; forward flags and tids on the local path. - local_mem: commit AMO through the shared AmoUnit and return the old word; abort on any request that is not an aligned full-word AMOADD. Tests: - tests/regression/smem_amo_mlp: four-mode oracle covering same-bank contention, independent-bank, a non-atomic private RMW control, and a directed add-zero/add-one/add-minus-one sequence checking exact old values. Scope: only aligned AMOADD.W is implemented; CAS, LR/SC, AMOSWAP and other RISC-V AMOs on LMEM fail closed, as do unsupported widths and misalignment. Acquire/release ordering is not added: this establishes serialized RMW atomicity at a bank, matching the existing global-cache AMO contract. (cherry picked from commit aa075f7)
- one DXA engine per socket; NUM_DXA_CORES now means workers per engine - GMEM: socket-local 2:1 priority arb (L1 over DXA) per L2-facing port, replacing the cluster-level LSU+DXA arb; sockets emit L2_TAG_WIDTH tags - LMEM: engine->per-core switch inside the socket (no cluster hop) - DCR: socket dcr arb gains a DXA endpoint; cluster DXA endpoint removed - perf: dxa counters are socket-owned to avoid multi-socket double count - busy: socket_active includes dxa engine + in-flight lmem writes; VX_dxa_core tracks ingress/worker/lmem-arb-output occupancy - tests: dxa_copy refresh, new dxa_copy_persist and sgemm_tcu_wg_dxa_db Note: the earlier internal version of this change also carried a top-level busy-handoff shim in hw/rtl/Vortex.sv for the KMU->core false-idle window; it is intentionally left out here because PR #387 (fixes #386) addresses that root cause in VX_kmu_arb. Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
- amo.yaml: add smem_amo_mlp lanes — bank-contention and directed old-value checks on simx+rtlsim (xlen 32/64), per-bank spread and 8-warp contention in the full tier. - dxa.yaml: register dxa_copy_persist and sgemm_tcu_wg_dxa_db added by the socket-level move, plus a two-workers/two-sockets dxa_copy lane. - dxa.yaml: the sgemm2_dxa-6/7/8 lanes passed -DVX_CFG_NUM_DXA_UNITS=4, a config key that has never existed (configure silently ignores unknown defines), so they always ran a default-sized engine. Retarget to -DVX_CFG_NUM_DXA_CORES=2: under the socket-level scheme that is 2 workers per socket engine, and both lane shapes instantiate two sockets (cores:2 = 2x1-core sockets; cores:4 + SOCKET_SIZE=2), so the total is 2x2 = 4 workers — preserving the original "4 units" intent. Core counts (shape.cores) are unchanged. All three retargeted lanes re-validated locally (simx + rtlsim). Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
The bank AMO read-modify-write can now stall the LMEM DMA port, so dxa_bank_wr_fire must qualify with req_ready: a DMA write held at a busy bank would otherwise fire the completion detector early — and repeatedly for every stalled cycle — releasing the transaction barrier before the data is actually committed (found by review of the AMO-vs-DXA interaction; the pre-AMO code was safe because DMA writes were unconditionally accepted). SimX releases the barrier when LocalMem receives the final write; it does not model the AMO-vs-DMA interlock, so acceptance cannot stall there. Annotate that release point; aligning it with the actual bank write belongs to the SimX AMO timing-model work. Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
The contention oracles summed the returned old values per hart and
compared against a triangular number; distinct wrong multisets can
alias to the same sum (e.g. {0,0,3,3} vs {0,1,2,3}), hiding duplicated,
lost, or mis-routed AMO responses. Record every returned old value and
verify the multiset is exactly {0..N-1}: report out-of-range values,
duplicates, and missing values separately.
Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
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