[ruslan-splynx]

The single-threadgroup Metal MPS SVD is slow, but replacing it with a faster GPU factorization alone does not establish a useful CPU crossover. This PR records the scoped NO-GO from a frozen M5 experiment and keeps production MPS routing, guards and f64 fallback unchanged.

Closes #561. Refs #550.

The explicit factorization-research feature provides a multi-threadgroup round-robin Jacobi prototype, reusable stage probes and a real-device campaign example. Independent column pairs run in parallel; separate encoders order rounds, and per-sweep completion/rotation counts bound convergence. It retains FP32, the existing complex rotation/tolerance and the 60-sweep cap. Research code is not called by normal Metal execution.

On an M5 MacBook Air (10 CPU/10 GPU cores, 32 GiB, four Rayon workers), 240 receipts cover chi 32/64/128/256/512, square/tall/wide matrices and well/clustered/ill/rank-deficient spectra. One warmup per method, then two observations per method in ABBA order; source and protocol were committed before the full campaign. Shared desktop CPU idle was 53.93–95.70% (median 87.80%); GPU/thermals were not isolated and no programs/services were stopped.

Square well-conditioned matrix	Old GPU factor	Prototype factor	Mandatory guard/finalize	Full CPU split
64×64	13.075 ms	3.433 ms	0.300 ms	0.675 ms
256×256	405.415 ms	19.024 ms	7.954 ms	13.777 ms
1024×1024	16144.694 ms	1784.881 ms	780.530 ms	416.014 ms

The current reconstruction guard becomes a separate serial bottleneck. Instrumented stage sums are research budgets, not fused production or end-to-end MPS times. Criterion pack/factor controls (10 samples, 1 s warmup, 2 s requested measurement) show 13.311 → 2.885 ms at chi32 and 68.748 → 4.424 ms at chi64; this improves old GPU factorization, not overall CPU competitiveness.

The actual guard declined 8/120 reference and 8/120 candidate probes on large rank-deficient matrices. Stronger frozen accuracy gates rejected 26/120 reference and 32/120 candidate observations; clustered-cutoff observable sensitivity and ill-conditioned canonical/norm cases remain visible. No tolerance was widened and no failing fixture was removed. None of the 15 shape regimes passed the necessary integration gate, so no production integration is proposed. CPU QR timing is explicitly labeled an implicit-factor diagnostic; no matched full-Q speed ratio is claimed.

Validation: 83 release Metal-suite tests passed (four ignores: two research hardware tests plus two existing long cases); all 3 research tests separately passed with --include-ignored, including real-Metal hard fixtures and an independent large rank-deficient guard regression. Existing CPU/FP64 MPS, capped-bond truncation/norm, canonical, large-n readout and routing oracles passed. Research all-target Clippy, workspace all-target Clippy, formatting, 15 CI policy contracts, report/checksums and deterministic summary replay passed. The long chi512 n16/20 circuit test was not executed; this is a matrix-level no-go, with no end-to-end speed claim.

Metal CI also compiles/lints the explicit feature and tests pure schedule coverage. Actual-device tests are explicitly ignored in headless CI and backed by separate local receipts. Phase 8 documentation now records #551 as merged and this P8-11 no-go; #562 and the final #550 exit report remain outstanding.

Report: docs/perf/p8-11-metal-factorization.md. Frozen protocol, all raw rows/failures, Criterion samples/intervals, telemetry, executable/source identities, summary and test logs: docs/perf/data/p8-11-metal-factorization/. Reproduce with the committed example, Criterion bench and scripts/python/summarize_metal_factorization.py.