A Framework for Design and Verification of Image Processing Applications using UVM
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Nov 27, 2017 - SystemVerilog
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functional-verification
Here are 46 public repositories matching this topic...
A simple UVM example with DPI
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Aug 7, 2017 - SystemVerilog
Designing means to communicate as an SPI master, being a part of AXI interface
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Sep 14, 2023 - Verilog
UVM-based functional verification of an APB-based UART Master Core RTL. Includes multi-agent environment, assertions, coverage collection, and multiple test scenarios (full/half duplex, parity, framing, timeout errors) achieving 100% functional coverage and protocol compliance.
fpga eda uart systemverilog vlsi uvm testbench digital-design serial-communication apb functional-verification hardware-verification rtl-design rtl-verification uvm-environment
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Nov 1, 2025 - SystemVerilog
Implements a simple UVM based testbench for a simple memory DUT.
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Oct 26, 2019 - SystemVerilog
A simple UVM testbench using UVM Connect and Octave
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Aug 7, 2017 - SystemVerilog
This repository is meant for learning UVM using SystemVerilog. Through a verification environment, some hardware verification concepts are applied for a calculator with the four basic operations.
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May 14, 2026 - SystemVerilog
Apply dataclasses concept to testbench automation in Python
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Oct 9, 2022 - Python
A simple testbench with two refmods using UVM Connect
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Aug 7, 2017 - SystemVerilog
UVM VIP for Single Port RAM Synchronous Read/Write
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Jul 15, 2020 - SystemVerilog
A complete UVM-based verification environment for validating YAPP Router functionality using SystemVerilog and Cadence Xcelium, featuring advanced sequences, virtual interfaces, and coverage analysis.
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Jun 27, 2025 - SystemVerilog
UVM 1.2 Verification of Dual Clock Asynchronous FIFO
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Jul 25, 2026 - SystemVerilog
UVM testbench for verifying a packet router using the YAPP (Yet Another Packet Protocol)
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Jun 24, 2025 - SystemVerilog
SystemVerilog AXI4-Lite Slave IP with Hazard-Stalled FSM. Verified with 2M+ cycle randomized regression and 'Snoop & Serialize' collision handling.
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Feb 5, 2026 - SystemVerilog
Verification of Advanced Encryption Standard (AES-128) Using UVM
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Oct 6, 2024 - SystemVerilog
Layered SystemVerilog testbench for verifying a parameterized Synchronous FIFO. Includes directed and constrained-random tests, functional coverage, assertions, and scoreboard-based checking.
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Jun 24, 2025 - SystemVerilog
Simplified Advanced Encryption Standard (S-AES) Design and Verification Using System Verilog and UVM.
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Oct 6, 2024 - SystemVerilog
Automated machine-learning verification framework using cocotb, cocotb-coverage, and UCB1 Multi-Armed Bandit algorithm to accelerate functional coverage closure on a 5-stage pipelined RV32I CPU. Closes 100% functional coverage 4.9× faster than uniform random stimulus and speeds up microarchitectural RTL bug discovery by up to 16.4×.
reinforcement-learning riscv verilog multi-armed-bandit rv32i functional-verification cocotb hardware-verification cocotb-coverage
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Jul 22, 2026 - Verilog
UVM verification of an 8×8 INT8 weight-stationary systolic-array ML accelerator — closed to 100% functional coverage on an open-source Verilator + UVM toolchain.
coverage rtl systemverilog uvm verilator sva functional-verification asic-verification axi4 design-verification ml-accelerator stolic-array
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Jun 11, 2026 - SystemVerilog
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