UVM verification of an 8×8 INT8 weight-stationary systolic-array ML accelerator — closed to 100% functional coverage on an open-source Verilator + UVM toolchain.
coverage rtl systemverilog uvm verilator sva functional-verification asic-verification axi4 design-verification ml-accelerator stolic-array
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Updated
Jun 11, 2026 - SystemVerilog