intel-max10

Here are 7 public repositories matching this topic...

Galaviz1 / clock-digital

24-hour digital clock in VHDL for the Terasic DE10-Lite (Intel MAX 10), displayed on the board's six seven-segment displays with hour/minute set inputs.

fpga vhdl digital-clock seven-segment quartus de10-lite intel-max10

Updated Sep 20, 2026
VHDL

BJaideep18 / FPGA-chess-DE10lite

Star

Developed a fully functional chess game on an Intel MAX10 FPGA using System Verilog. The game runs on a VGA monitor at 640×480, accepts input via a matrix keypad, enforces all official chess rules in hardware, and renders the board and pieces procedurally at the pixel level all without a soft-core processor or external memory.

chess fpga systemverilog vga digital-design de10-lite hardware-design intel-max10

Updated Jun 28, 2026
SystemVerilog

aryand-2006 / accelerometer-digital-spirit-level

Star

Real-time digital spirit level on the DE10-Lite FPGA (VHDL). Reads the ADXL345 accelerometer over I2C and shows tilt on the seven-segment displays and an LED bar graph. IIT Goa EE232 project.

fpga i2c vhdl accelerometer adxl345 quartus de10-lite spirit-level intel-max10

Updated Sep 24, 2026
VHDL

avaamar / f1-reaction-timer-fpga

Star

F1 starting light reaction timer on Intel MAX10 FPGA. SystemVerilog FSM, LFSR random delay, hierarchical clock management. Imperial College London (Grade: A).

fsm fpga hardware systemverilog digital-design lfsr quartus imperial-college-london rtl-design intel-max10

Updated Aug 31, 2026
SystemVerilog

mohamedAziz-bousbih / fpga-ip-cores-vhdl

Star

Synthesizable VHDL-2008 IP cores for the Terasic DE10-Lite (MAX 10): UART with 16x oversampling, SPI master (all 4 modes), FIFO, PWM, 7-segment, BCD clock, FSM code lock. Self-checking GHDL testbenches, a board-level system test and mutation testing.

fpga vhdl spi finite-state-machine uart ghdl testbench digital-design de10-lite intel-max10

Updated Oct 2, 2026
VHDL

ShayanKhoshkeifi / FPGA-Memory-SqrtUnit

Star

Verilog implementation of an integer square root FSM and dual M9K RAM system on the Intel MAX10 FPGA, verified in ModelSim and demonstrated on the DE10-Lite board.

fpga verilog finite-state-machine modelsim digital-design quartus de10-lite m9k integer-square-root embedded-memory intel-max10

Updated Sep 10, 2026
HTML

lruizleonardo1 / FPGA-SPWM-Sine-Wave-Inverter

Star

FPGA-based single-phase SPWM sine-wave inverter using an Intel MAX 10, VHDL, H-bridge power stage, step-up transformer, and experimental validation at 120 V RMS / 60 Hz.

fpga vhdl pwm power-electronics digital-design quartus spwm h-bridge intel-max10 sine-wave-inverter dc-ac-inverter

Updated Sep 9, 2026
VHDL

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